storage device

Abstract

Embodiments provide a storage device with a smaller area. In the storage device of the embodiments, a plurality of first conductors are arranged along a first axis while being separated from each other. A storage pillar extends along the first axis, faces the plurality of first conductors, and includes a semiconductor and a film that surrounds the semiconductor. A plurality of contact plugs extend along the first axis, each including a second conductor and a first insulator that surrounds the second conductor. The first insulator is positioned between the plurality of first conductors and the second conductor. Each of the plurality of contact plugs interfaces a lower surface with an upper surface of a non-repeating one of the plurality of first conductors. The plurality of contact plugs includes a first contact plug to a third contact plug. The first contact plug and the second contact plug are adjacently arranged along a second axis that intersects the first axis. The third contact plug is positioned between the first contact plug and the second contact plug on the second axis and is arranged at a different position on a third axis that is orthogonal to the first axis and the second axis.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2022-048579 (filed on March 24, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] The implementation methods generally involve storage devices. Background Technology

[0003] A storage device is known to have storage cells configured in a three-dimensional manner. The storage device is required to have a smaller area. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a storage device with a smaller area.

[0005] One embodiment of a storage device includes a plurality of first conductors, storage pillars, and a plurality of contact plugs. The plurality of first conductors are arranged separately along a first axis. The storage pillars extend along the first axis, facing the plurality of first conductors, and include a semiconductor and a film surrounding the semiconductor. The plurality of contact plugs extend along the first axis. Each of the plurality of contact plugs includes a second conductor and a first insulator surrounding the second conductor. The first insulator is located between the plurality of first conductors and the second conductors. Each of the plurality of contact plugs has its lower surface in contact with the upper surface of one non-repeating first conductor among the plurality of first conductors. The plurality of contact plugs includes a first contact plug, a second contact plug, and a third contact plug. The first contact plugs and the second contact plugs are arranged adjacent to each other along a second axis intersecting the first axis. The third contact plug is located on the second axis between the first contact plug and the second contact plug, and is arranged at different positions on the third axis, which is orthogonal to the first axis and the second axis. Attached Figure Description

[0006] Figure 1 Examples of the components and connections of the storage device according to the first embodiment are shown.

[0007] Figure 2 This describes the constituent elements of a block of the storage device according to the first embodiment and the connections between the constituent elements.

[0008] Figure 3 An example of a planar layout representing a portion of the storage cell array of the storage device of the first embodiment.

[0009] Figure 4 An example of a planar layout showing a portion of the storage area of ​​the storage device of the first embodiment.

[0010] Figure 5 The structure shows a cross-sectional view of a portion of the storage area of ​​the storage device according to the first embodiment.

[0011] Figure 6 An example of the structure of a cross-section of the storage column of the storage device of the first embodiment.

[0012] Figure 7 An example of a planar layout showing a portion of the lead-out area of ​​the storage device in the first embodiment.

[0013] Figure 8 and Figure 9 The structure of cross-sections showing a portion of the storage area and a portion of the lead-out area of ​​the storage device of the first embodiment are shown respectively.

[0014] Figures 10-27 Examples of cross-sectional structures during a step in the manufacturing process of the storage device according to the first embodiment are shown.

[0015] Figure 28 An example of a planar layout representing a portion of the lead-out area of ​​a storage device for reference.

[0016] Figure 29 and Figure 30 Examples of planar layouts showing a portion of the lead-out area of ​​the storage device in the second embodiment.

[0017] Label Explanation

[0018] 1. Storage device, 10. Memory cell array, 11. Row decoder, 12. Register, 13. Sequencer, 14. Driver, 15. Sensing amplifier, BLK block, WL word line, BL bit line, MT memory cell transistor, MA memory region, HA1 lead-out region, HA2 lead-out region, SLT component, SHE component, MP memory pillar, CV contact plug, 22. Conductor, 23. Conductor, 24. Conductor. Detailed Implementation

[0019] In the following description, embodiments following a previously described embodiment are primarily described in terms of their differences from the previously described embodiment. Any description of a particular embodiment, unless explicitly stated or obviously excluded, is also applicable as a description of other embodiments. Therefore, the description of a particular embodiment, except where necessary, generally does not include the same content as the description of a prior embodiment. For multiple components having substantially the same function and structure in a particular embodiment or in different embodiments, numbers or characters are sometimes appended to the end of the reference numerals to distinguish them.

[0020] The accompanying drawings are schematic; the relationship between thickness and planar dimensions, the ratio of thicknesses of different layers, etc., may differ from reality. The drawings may also include dimensional relationships and ratios between different elements. In the top view, shading lines are sometimes added to improve visual clarity. The shading lines added to the top view are not necessarily related to the material and / or characteristics of the elements to which the shading lines are added.

[0021] In this specification and claims, a first element being "connected" to another second element includes the first element being directly or always or temporarily connected to the second element via an element that is conductive.

[0022] The following description uses an orthogonal xyz coordinate system. Sometimes the positive direction of the vertical axis in the figures is referred to as the upper side, and the negative direction as the lower side. Sometimes the positive direction of the horizontal axis in the figures is referred to as the right side, and the negative direction as the left side.

[0023] 1. First Implementation Method

[0024] 1.1. Composition (Structure)

[0025] 1.1.1. Storage device

[0026] Figure 1 This illustrates the constituent elements and connections of the storage device according to the first embodiment. Storage device 1 is a device that uses storage cells to store data. Storage device 1 is controlled by an external storage controller. Storage device 1 operates, for example, based on commands CMD and address information ADD received from the storage controller. Storage device 1 accepts data DAT to be written and outputs the data stored in storage device 1. Storage device 1 is configured, for example, as a semiconductor chip.

[0027] The storage device 1 includes components such as a storage cell array 10, a row decoder 11, a register 12, a sequencer 13, a driver 14, and a sensing amplifier 15.

[0028] The memory cell array 10 is a collection of memory cell transistors and components connected to them. The memory cell array 10 includes multiple memory blocks (BLKs) (BLK_0, BLK_1, ...). Each BLK includes multiple memory cell transistors MTs (not shown). Word lines WL (not shown) and bit lines BL (not shown), as well as wiring connected to the memory cell transistors MTs, are also located in the memory cell array 10.

[0029] The row decoder 11 is a circuit used to select a block BLK. The row decoder 11 transmits the voltage supplied from the driver 14 to a block BLK selected based on the block address received from the register 12.

[0030] Register 12 is a circuit that holds the command CMD and address information ADD received from storage device 1. The command CMD instructs sequencer 13 on various actions including data reading, data writing, and data erasure. The address information ADD specifies the access object in storage cell array 10.

[0031] The sequencer 13 is a circuit that controls the overall operation of the storage device 1. The sequencer 13 controls the row decoder 11, driver 14 and sense amplifier 15 based on the command CMD received from the register 12, and performs various operations including data reading, data writing and data erasure.

[0032] Driver 14 is a circuit that generates multiple voltages of different magnitudes to apply the various voltages required for the operation of storage device 1 to several components. The row decoder 11 is supplied with the voltage selected by the sequencer 13 based on the control and address information ADD.

[0033] The sense amplifier 15 is a circuit that outputs a signal based on the data stored in the memory cell array 10. The sense amplifier 15 senses the state of the memory cell transistor MT and generates read data or sends write data to the memory cell transistor MT based on the sensed state.

[0034] 1.1.2. Circuit Structure of Memory Cell Array

[0035] Figure 2 This describes the constituent elements of a block BLK in the storage device of the first embodiment and the connections between these constituent elements. Multiple block BLKs, such as all block BLKs, are included. Figure 2 The constituent elements and connections are shown.

[0036] A block BLK consists of multiple string units SU. Figure 2 This represents an example of four string units SU_0 to SU_3.

[0037] Each of the m bit lines BL_0 to BL_m-1 is connected in its respective BLK block to a NAND string NS from each of the string units SU_0 to SU_3. m is a positive integer.

[0038] Each NAND string NS includes a select gate transistor ST, multiple memory cell transistors MT, and a select gate transistor DT (DT0, DT1, DT2, or DT3). Figure 2An example based on eight memory cell transistors MT0 to MT7. The memory cell transistor MT is a component comprising a control gate electrode and a charge storage film insulated from the surroundings, storing data in a non-volatile manner based on the amount of charge in the charge storage film. The select gate transistor ST, the memory cell transistor MT, and the select gate transistor DT are connected in series in this order between the source line SL and a bit line BL.

[0039] Multiple NAND strings NS, each connected to different bit lines BL, constitute a string unit SU. In each string unit SU, the control gate electrodes of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The group of memory cell transistors MT that share word line WL in a string unit SU is called a cell unit CU.

[0040] Gate transistors DT0 to DT3 are selected to belong to series units SU_0 to SU_3, respectively. Figure 2 The gate selection transistors DT2 and DT3 are not shown in the diagram. The gates of the gate selection transistors DT0 of the multiple NAND strings NS in string unit SU_0 are connected to the gate selection line SGDL0. Similarly, the gates of the gate selection transistors DT1, DT2, and DT3 of the multiple NAND strings NS in string units SU_1, SU_2, and SU_3 are connected to the gate selection lines SGDL1, SGDL2, and SGDL3, respectively.

[0041] The gate of the select gate transistor ST is connected to the select gate line SGSL.

[0042] 1.1.3. Planar Layout of Storage Cell Array

[0043] Figure 3 An example of a planar layout representing a portion of the storage cell array of the storage device of the first embodiment. Figure 3 The xy plane represents a region consisting of four blocks, BLK_0 to BLK_3. These blocks are repeatedly set along the y-axis. Figure 3 The structure shown.

[0044] like Figure 3 As shown, the memory cell array 10 includes a memory region MA and lead-out regions HA1 and HA2. Lead-out region HA1, memory region MA, and lead-out region HA2 are arranged in this order along the x-axis. Multiple components SLT and SHE are disposed in the memory cell array 10.

[0045] The storage region MA is a region that includes multiple NAND strings NS. The lead-out region HA is a region with contact plugs that are connected to the stacked structure in which memory cell transistors are formed.

[0046] Multiple component SLTs extend along the x-axis and are arranged along the y-axis. Each component SLT is located at the boundary between adjacent block BLKs. Component SLTs traverse storage region MA and lead-out regions HA1 and HA2. Each component SLT has, for example, a structure with embedded insulators and / or plate-like contacts. Each component SLT is truncated across its adjacent stack-up structure.

[0047] Multiple components SHE extend along the x-axis and are arranged along the y-axis. Multiple components SHE are located between each pair of adjacent components SLT. Figure 4 This example illustrates four select gate units (SHEs). Each SHE traverses the memory region MA along the x-axis. The two ends of each SHE are located in the lead-out regions HA1 and HA2, respectively. Each SHE may contain an insulator. Each SHE is truncated across its adjacent select gate line SGDL. The regions defined by SLT and SHE form a region containing a single string cell SU.

[0048] 1.1.4. Floor plan layout of storage area

[0049] Figure 4 An example of a planar layout showing a portion of the storage area of ​​the storage device of the first embodiment. Figure 4 This indicates a block BLK, comprising the region of string units SU0 to SU4, and two components SLT sandwiching this block. For example... Figure 4 As shown, the memory cell array 10 includes multiple memory pillars MP, multiple contact plugs CV, and multiple conductors 25 in the memory region MA. Each component SLT includes a contact portion LI and a spacer SP.

[0050] A memory column (MP) is a structure in which memory cell transistors (MTs) are formed internally. The memory column (MP) comprises one or more of a semiconductor, a conductor, and an insulator. The memory column (MP) functions as a NAND string (NS). Multiple memory columns (MPs) are arranged in an alternating pattern in the region between two component segments (SLTs). That is, multiple memory columns (MPs) are configured as multiple columns along the y-axis, and each column of memory columns (MPs) is arranged in a zigzag (Z) shape along the y-axis. In other words, each column comprises two sub-columns. The y-axis coordinates of the memory columns (MPs) in one sub-column are located at the y-axis coordinates between two adjacent memory columns (MPs) in the other sub-column. Each column may, for example, comprise 24 memory columns (MPs).

[0051] For example from Figure 4 The top number of components SHE overlaps with the 5th, 10th, 15th, and 20th storage columns MP, respectively.

[0052] Each conductor 25 functions as a bit line BL. The conductors 25 extend along the y-axis and are arranged along the x-axis. Each conductor 25 is configured to overlap with at least one memory column MP in a string cell SU. Figure 4 This illustrates an example where two conductors 25 are configured to overlap with a memory column MP. Each memory column MP is electrically connected via a contact plug CV to one of the plurality of conductors 25 overlapping the memory column MP.

[0053] The contact portion LI is formed of a conductor. The contact portion LI extends along the xz plane and has a plate-like shape. The spacer SP is an insulator and is located on the side of the contact portion LI, for example, covering the side of the contact portion LI.

[0054] 1.1.5. Cross-sectional structure of the storage area

[0055] Figure 5 This diagram shows a cross-sectional view of a portion of the storage area of ​​the storage device according to the first embodiment. Specifically, Figure 5 Indicates along Figure 4 The cross-section of the VV line.

[0056] like Figure 5 As shown, the memory cell array 10 also includes a substrate 20, conductors 21 and 22, multiple conductors 23, conductors 24 and 25, and insulators 30 to 37. Figure 5 This example shows eight conductors 23. Insulators 30 to 37, in addition to insulator 31, include, for example, silicon oxide.

[0057] The substrate 20 is, for example, a p-type semiconductor substrate. An insulator 30 is located on the upper surface of the substrate 20. Circuitry (not shown) is formed in the semiconductor substrate 20 and the insulator 30. The circuitry includes, for example, a line decoder 11, a driver 14, and / or a sense amplifier 15, including transistors (not shown).

[0058] Insulator 31 is located on the upper surface of insulator 30. Insulator 31, for example, inhibits the intrusion of hydrogen from the structure above insulator 31 into substrate 20 and the transistor contained in insulator 30. Insulator 31, for example, comprises silicon nitride.

[0059] Insulator 32 is located on the upper surface of insulator 31.

[0060] Conductor 21 is located on the upper surface of insulator 32. Conductor 21 extends along the xy plane and has a plate-like shape. Conductor 21 functions as at least part of source line SL. Conductor 21 may contain, for example, phosphorus-doped silicon.

[0061] Insulator 33 is located on the upper surface of conductor 21.

[0062] Conductor 22 is located on the upper surface of insulator 33. Conductor 22 extends along the xy plane and has a plate-like shape. Conductor 22 functions as at least a portion of the select gate line SGSL. Conductor 22 contains, for example, tungsten.

[0063] Multiple insulators 34 and multiple conductors 23 are alternately located one after another along the z-axis on the upper surface of conductor 22. Thus, the conductors 23 are either separated from each other or arranged at intervals along the z-axis. The insulators 34 and conductors 23 extend along the xy-plane, having a plate-like shape. The multiple conductors 23, starting from one side of the substrate 20, function sequentially as word lines WL0 to WL7. The conductors 23 may contain, for example, tungsten.

[0064] Insulator 35 is located on the upper surface of the uppermost conductor 23.

[0065] Conductor 24 is located on the upper surface of insulator 35. Conductor 24 extends along the xy plane and has a plate-like shape. Conductor 24 functions as at least a portion of the select gate line SGDL. Conductor 24 contains, for example, tungsten.

[0066] Insulator 36 is located on the upper surface of conductor 24.

[0067] Conductor 25 is located on the upper surface of insulator 36. Conductor 25 has a linear shape and extends along the y-axis. Conductor 25 functions as at least a portion of a bit line BL. Figure 5 Conductors 25 are also provided in different yz planes shown, and thus the conductors 25 are arranged at intervals along the x-axis. The conductors 25 contain, for example, copper.

[0068] Insulator 37 is located on the upper surface of conductor 25.

[0069] Each storage pillar MP extends along the z-axis and has a pillar shape. The storage pillar MP is located within a stacked structure formed by insulators 33-35 and conductors 22-24, penetrating or passing through insulators 33-35 and conductors 22-24. The upper surface of the storage pillar MP is located above conductor 24. The lower surface of the storage pillar MP is located within conductor 21. The portion of the storage pillar MP connected to conductor 22 functions as a select gate transistor ST. The portion of the storage pillar MP connected to a conductor 23 functions as a storage cell transistor MT. The portion of the storage pillar MP connected to conductor 24 functions as a select gate transistor DT.

[0070] The storage column MP includes, for example, a core 50, a semiconductor 51, and a stack 52. The core 50 is formed of an insulator, such as silicon oxide. The core 50 extends along the z-axis and has a column shape. The semiconductor 51 includes, for example, silicon. The semiconductor 51 covers the surface of the core 50. The stack 52 covers the sides and bottom surface of the semiconductor 51. The stack 52 has an opening in a conductor 21, which is partially located within the opening. The conductor 21 and the semiconductor 51 are connected within the opening.

[0071] As described above, a storage column MP and a conductor 25 are connected by a contact plug CV.

[0072] Component SLT interrupts conductors 22-24. The upper surface of component SLT is positioned above the upper surface of storage column MP. The lower surface of contact LI is in contact with conductor 21. Spacer SP is located between contact LI and conductors 22-24, insulating contact LI from conductors 22-24. Contact LI functions as part of source line SL.

[0073] The component SHE cuts off the conductor 24. The lower surface of the component SHE is located within the insulator 35. The component SHE may contain an insulator such as silicon oxide.

[0074] Figure 6 An example showing the cross-sectional structure of the storage column of the storage device according to the first embodiment. Specifically, Figure 6 Indicates along Figure 5 The cross-section of the VI-VI line. For example... Figure 6 As shown, the laminate 52 includes, for example, a tunnel insulator 53, a charge storage film 54, and a barrier insulator 55.

[0075] Tunnel insulator 53 surrounds the sides of semiconductor 51. Charge storage film 54 surrounds the sides of tunnel insulator 53. Barrier insulator 55 surrounds the sides of charge storage film 54. Conductor 23 surrounds the sides of barrier insulator 55.

[0076] Semiconductor 51 functions as the channel (current path) for memory cell transistors MT0 to MT7 and gate select transistors DT and ST. Tunnel insulator 53 and barrier insulator 55 each comprise, for example, silicon oxide. Charge storage film 54 stores charge. Charge storage film 54 comprises, for example, silicon nitride.

[0077] 1.1.6. Construction of the Lead-Out Region

[0078] Figure 7 An example of a planar layout showing a portion of the lead-out area of ​​the storage device in the first embodiment. Figure 7 The xy plane represents a portion of the area between the two SLT components. Figure 7This shows the layout when viewed from above on the z-axis, considering the layer containing conductor 24.

[0079] like Figure 7 As shown, the lead-out area HA1 includes multiple support posts HR and multiple contact plugs CC.

[0080] Support pillars HR are distributed throughout the entire lead-out area HA1. Support pillars HR are formed of an insulator, such as silicon oxide. Support pillars HR have a pillar shape and extend along the z-axis. See below for further details. Figure 8 As described, the support posts HR extend from the layer of insulator 36 to the layer of conductor 22. Several support posts HR at least partially overlap with contact plugs CC. The portion of the support post HR that overlaps with the contact plug CC is in contact with the contact plug CC on its upper surface and is not located within insulator 36. The support posts HR are not located at the center of one or more contact plugs CC, for example, each contact plug CC, but in a region off-center.

[0081] The contact plug CC has, for example, a quadrilateral shape. The contact plug CC forms multiple rows along the x-axis. Figure 7 As an example, three rows of contact plugs (CC) are shown. Rows of contact plugs (CC) are sometimes referred to as contact plug groups. The contact plugs (CC) are arranged in an alternating pattern, meaning that adjacent rows of contact plugs (CC) are staggered. Specifically, as described below: Two contact plugs (CC) belonging to two adjacent rows are located at different coordinates on the x-axis. For example, the x-axis coordinates of each contact plug (CC) in one row of two rows are the same as the x-axis coordinates of the region between two adjacent contact plugs (CC) in the other row of two rows. For example, the x-axis coordinates of each contact plug (CC) in one row are substantially the same as the coordinates of the center of the region between two adjacent contact plugs (CC) in the other row. On the other hand, the x-axis coordinates of the two rows of contact plugs (CC) sandwiching another row are substantially the same. That is, the x-axis coordinates of each contact plug (CC) in one row of two rows sandwiching another row are substantially the same as the x-axis coordinates of each contact plug (CC) in the other row. In this specification and claims, "substantially identical" means that although they are identical in meaning, errors due to the limitations of manufacturing and / or measurement techniques are permissible.

[0082] In other words, the two rows include contact plugs CC configured in a zigzag pattern along the x-axis.

[0083] The configuration of the contact plug CC described using rows also applies to the description using columns. The description of columns is equivalent to replacing "rows" with "columns" and "x-axis" with "y-axis" in the description above.

[0084] The contact plug CC is connected to the upper surface of different conductors 23 on each of its lower surfaces. Specific examples are described below.

[0085] The bottom row of contact plugs CC are named CC0, CC3, and CC6 from left to right. The lower surface of contact plug CC0 is in contact with the upper surface of conductor 23, which functions as word line WL0. The lower surface of contact plug CC3 is in contact with the upper surface of conductor 23, which functions as word line WL3. The lower surface of contact plug CC6 is in contact with the upper surface of conductor 23, which functions as word line WL6.

[0086] The contact plugs CC in the second row from the bottom are named CC1, CC4, and CC7 from left to right. The lower surface of contact plug CC1 is in contact with the upper surface of conductor 23, which functions as word line WL1. The lower surface of contact plug CC4 is in contact with the upper surface of conductor 23, which functions as word line WL4. The lower surface of contact plug CC7 is in contact with the upper surface of conductor 23, which functions as word line WL7.

[0087] The topmost contact plugs CC are named CC2, CC5, and CC8 from left to right. The lower surface of contact plug CC2 is in contact with the upper surface of conductor 23, which functions as word line WL2. The lower surface of contact plug CC5 is in contact with the upper surface of conductor 23, which functions as word line WL5. The lower surface of contact plug CC8 is in contact with the upper surface of conductor 23, which functions as word line WL8.

[0088] For reference Figure 5 As described, the conductors 23, which function as different word lines WL, are located at different heights or layers. Therefore, the contact plug CC has a lower surface positioned based on the location of the conductor 23 it contacts.

[0089] For reference Figure 7 As described above, the upper surface of the portion of the support post HR that overlaps with the contact plug CC at least partially contacts the lower surface of the contact plug CC. Thus, the support post HR has an upper surface based on the position of the contact plug CC that partially overlaps with the support post HR.

[0090] Figure 8 and Figure 9 This diagram shows a cross-sectional view of a portion of the storage region and lead-out region of the storage device according to the first embodiment. Specifically, Figure 8 Along Figure 7 The VIII-VIII line represents the section of region HA1, and indicates... Figure 5 This is a portion of the storage area MA shown. Figure 9 Indicates along Figure 7 The cross section of the IX-IX line.

[0091] like Figure 8 and Figure 9 As shown, each contact plug CC penetrates the conductor 24 and the insulator 35. Several contact plugs CC further penetrate one or more conductors 23 and one or more insulators 34. Each contact plug CC includes a conductor 61 and a spacer 62.

[0092] Conductor 61 has a downward protrusion on its lower surface facing the z-axis. The lower surface of the protrusion is in contact with the upper surface of a conductor 23. Additionally, the lower surface of the protrusion may be in contact with the upper surfaces of one or more support posts HR. The sides of the contact plug CC are covered by spacers 62. Spacers 62 are, for example, silicon oxide. The sides of spacers 62 are in contact with conductors 24 and insulators 35. The spacers 62 of several contact plugs CC are further in contact with one or more conductors 23 and one or more insulators 34. Through the spacers 62, conductor 61 is insulated from conductors 23 other than those contacted on its lower surface.

[0093] For reference Figure 7 As described, different contact plugs CC are connected to different conductors 23 on their lower surfaces. The lower surface of contact plug CC0 is connected to the upper surface of conductor 23, which functions as word line WL0. The lower surface of contact plug CC1 is connected to the upper surface of conductor 23, which functions as word line WL1. The lower surface of contact plug CC2 is connected to the upper surface of conductor 23, which functions as word line WL2. The lower surface of contact plug CC3 is connected to the upper surface of conductor 23, which functions as word line WL3. The lower surface of contact plug CC6 is connected to the upper surface of conductor 23, which functions as word line WL6.

[0094] A conductor 60 is provided on the upper surface of the contact plug CC.

[0095] Reference Figures 7-9 The description includes the lead-out region HA1, which also describes contact plugs CC0 to CC8. Information regarding other contact plugs CC and the lead-out region HA2 is also provided in the reference section. Figures 7-9 The described lead-out region HA1 and contact plugs CC0 to CC8 are the same. That is, lead-out region HA2 has a planar layout obtained by reversing the planar layout of lead-out region HA1 along the y-axis. Contact plugs CC other than contact plugs CC0 to CC8 are in contact with a conductor 23 on their lower surface that is different from the conductor 23 that the other contact plugs CC are in contact with.

[0096] 1.2. Manufacturing Method

[0097] Figures 10-27Examples of cross-sectional structures are shown in one step of the manufacturing process of the storage device according to the first embodiment. Figures 10-12 , Figures 14-16 , Figure 18 , Figure 20 as well as Figures 22-27 The components in the manufacturing process are represented sequentially. Figures 10-12 , Figures 14-16 , Figure 18 , Figure 20 as well as Figures 22-27 Indicates and Figure 8 The cross-section shown is a cross-section of the same region. Figure 13 , Figure 17 , Figure 19 as well as Figure 21 Respectively represent and Figure 12 , Figure 16 , Figure 18 as well as Figure 20 The same steps. Figure 12 , Figure 16 , Figure 18 as well as Figure 20 Indicates and Figure 9 The cross-section shown is a cross-section of the same region.

[0098] like Figure 10 As shown, after a circuit (not shown) is formed on the substrate 20, insulators 31 and 32, conductors 61, 62, 63 and 64, and conductor 65 are stacked on the upper surface of the substrate 20 in this order. The group of conductors 61, insulators 62, 63 and 64, and conductor 65 occupies the area where conductor 21 is to be formed.

[0099] An insulator 33 is formed on the upper surface of the conductor 65.

[0100] Multiple insulators SM and multiple insulators 34 are alternately stacked one on one on the upper surface of insulator 33. The lowest insulator SM occupies the area where conductor 22 is to be formed. The remaining insulators SM are located in the area where conductor 23 is to be formed. The insulators SM contain, for example, silicon nitride.

[0101] On the upper surface of the uppermost insulator SM, insulators 35, SM2, and 71 are stacked in this order. Insulator SM2 is located in the region where conductor 24 is to be formed. Insulator 71 forms part of insulator 36. Insulator SM2, for example, contains silicon nitride.

[0102] like Figure 11As shown, a memory pillar MP is formed. However, the stack 52 of the memory pillar MP has no opening at this stage. Specifically, it is as follows: That is, a memory hole is formed by photolithography and anisotropic etching. The memory hole is located in the area where the memory pillar MP is to be formed. The memory hole passes through insulators 71, SM2, 35, SM3, 34, 33, conductors 65, insulators 64, 63, and 62. The bottom of the memory hole is located in conductor 61. A stack 52, namely a tunnel insulator 53, a charge storage film 54, and a barrier insulator 55, are formed on the surface of the memory hole. A semiconductor 51 is formed on the surface of the stack 52. By forming a core 50 on the surface of the semiconductor 51, the center of the memory hole is filled by the core 50. Then, the upper part of the core 50 is removed, and the semiconductor 51 is formed in the removed portion. The memory pillar MP is thus formed, and then an insulator is formed on the upper surface of the memory pillar MP. Figure 11 In the diagram, the insulator is depicted as part of insulator 71.

[0103] Support posts HR are formed. Each support post HR penetrates insulators 71, SM2, 35, SM, and 34. Each support post HR extends from the upper surface of insulator 71 to the upper surface of insulator 33.

[0104] exist Figure 12 and Figure 13 In the steps and subsequent steps, a contact hole CH for contacting the plug CC is formed. See reference... Figures 7-9 As described, the contact plug CC has a bottom at different heights depending on the position of the conductor 23 it contacts. Consequently, the contact hole CH also has a bottom at different depths during the stage before being filled by the conductor 61. Therefore, the contact hole CH with a bottom at a deeper position is connected to... Figure 14 In the steps shown, the base is further etched in the subsequent steps. By... Figure 12 and Figure 13 The etching process begins with etching each contact hole CH to achieve its inherent target depth. Contact holes CH that should have a deeper target depth are etched repeatedly. Meanwhile, contact holes CH that have reached the target depth are filled with the filling material NG, described later, during the further etching of other contact holes CH.

[0105] like Figure 12 and Figure 13 As shown, this forms a portion of the contact hole CH. The contact hole CH is the region where the contact plug CC is formed. Specifically, it is formed as described below.

[0106] A mask is formed on the upper surface of insulator 71 by photolithography. The mask has an opening above the area where contact plugs CC0 to CC8 are to be formed. Contact holes CH0 to CH8 are formed by anisotropic etching through the mask. Contact holes CH0 to CH8 penetrate insulator 71 and SM2 and reach the upper surface of insulator 35.

[0107] like Figure 14 As shown, by reference Figure 14 In the steps described later, the bottoms of contact holes CH7 and CH8 (not shown) are lowered to the target depth. At this time, contact holes CH, which have a target depth shallower than that of contact holes CH7 and CH8, are filled with a filling material NG (not shown). On the other hand, the bottoms of contact holes CH, which have a deeper target depth than contact holes CH7 and CH8, i.e., contact holes CH0 to CH5, are etched to a deeper position. As a result, contact holes CH0 to CH6 reach the upper surface of the insulator 34 on the upper surface of the insulator SM, which is located in the area where the conductor 23 is to be formed as the word line WL6.

[0108] like Figure 15 As shown, contact hole CH6 is filled with a filler material NG. The filler material NG is, for example, a negative resist. Specifically, a negative resist is coated on the upper surface of the structure obtained through the processes up to this point. Next, a mask with an opening is formed on the upper surface of the structure in the area where the filler material NG is to be filled, i.e., above the contact hole CH6. The negative resist is exposed to light through the opening of the mask. As a result, the portion of the negative resist below the opening of the mask, i.e., the portion in the contact hole CH6, cures. Then, the uncured portion of the negative resist is removed.

[0109] like Figure 16 and Figure 17 As shown, anisotropic etching is performed on the structure obtained through the processes up to this point. Etching is performed under conditions with a high selectivity between the insulator SM and 34 and the filler material NG. As a result, the bottoms of the contact holes CH0 to CH5 that are not filled by the filler material NG are etched. Through etching, the bottoms of the contact holes CH0 to CH5 reach the upper surface of the insulator 34 on the upper surface of the insulator SM, which is located in the region where the conductor 23, which functions as the word line WL5, is to be formed.

[0110] like Figure 18 and Figure 19 As shown, through repeated practice and reference Figures 15-17The same steps described are followed, in which the bottoms of contact holes CH0 to CH4 are etched. During this process, after contact hole CH4 reaches the target depth, it is filled with filler material NG. Through etching performed simultaneously with the filling of contact holes CH at the target depth, the bottoms of contact holes CH0 to CH3 reach the upper surface of insulator 34 on the upper surface of insulator SM, which is located in the region where the conductor 23 is to be formed as the word line WL3.

[0111] like Figure 20 and Figure 21 As shown, through repeated practice and reference Figures 15-17 The same steps described are performed simultaneously with the filling of the contact holes CH to the target depth, etching is performed on the bottom of the contact holes CH0 to CH2. As a result, the bottoms of the contact holes CH0 to CH2 reach the upper surface of the insulator 34 on the upper surface of the insulator SM, which is located in the region where the conductor 23 is formed to function as word lines WL0, WL1, and WL2.

[0112] like Figure 22 As shown, the filler material NG in each contact hole CH is removed. Removal can be performed by wet etching or ashing. Insulator 62 is deposited over the entire surface of the upper surface of the structure obtained by the steps so far. Insulator 62 covers the sides and bottom of each contact hole CH. Insulator 62 further covers the upper surface of insulator 71 and the upper surface of the support post HR that does not overlap with the contact hole CH.

[0113] The contact hole CH is filled with filler material 72. Filler material 72 is, for example, amorphous silicon.

[0114] like Figure 23 As shown, the slotted SLI is formed by photolithography and anisotropic etching. The slotted SLI is located in the region where the component SLT is to be formed. The slotted SLI extends to the upper surface of the insulator 64 at its bottom. An insulator 75 is formed on the surface of the slotted SLI. The bottom portion of the slotted SLI in the insulator 75 and the lower portion of the slotted SLI in the insulator 64 are removed. As a result, the insulator 63 is exposed at the bottom of the slotted SLI.

[0115] like Figure 24 As shown, the bottom of the SLI gap, i.e., the insulator 63, is exposed to the chemical solution through wet etching. The insulator 63 is removed by the chemical solution. At this time, the portion of the layer located in the insulator 63 in the stack 52 of the storage pillar MP is removed, and the semiconductor 51 is exposed in the removed portion.

[0116] like Figure 25As shown, by wet etching, the chemical solution travels from the bottom of the slit SLI, where the insulator 63 was previously located. The insulators 62 and 64 are removed by the chemical solution. Conductor 21 is formed by embedding a conductor in the spaces previously occupied by insulators 62 and 64.

[0117] Insulator 75 is removed. With the removal of insulator 75, insulators SM and SM2 are exposed in the slot SLI. Through wet etching, the exposed portions of insulators SM and SM2 are exposed to the etching solution. As the etching solution travels, insulators SM and SM2 are removed, and the areas previously occupied by insulators SM and SM2 open in the slot SLI. During this process, spaces are formed in the areas previously occupied by insulators SM and SM2. This weakens the structure of the storage device 1 during this period of manufacturing, particularly destabilizing high aspect ratio sections of the structure. In contrast, by providing a large number of support pillars HR, shape deformation of the structure can be suppressed.

[0118] Conductors 22, 23 and 24 are formed by embedding conductors into the regions that were previously insulators SM and SM2 through openings in the slot SLI.

[0119] like Figure 26 As shown, the sides of the Slit SLI are covered by spacers SP. The component SLT is formed by filling the Slit SLI with conductive material.

[0120] The landfill material 72 is removed. A portion of the upper surface of the insulator 71 in the insulator 62 and the upper surface of the support post HR that does not overlap with the contact hole CH are removed. As a result, insulator 62 remains on the sides and bottom of the contact hole CH. Anisotropic etching is performed on the bottom surface of the contact hole CH. Thus, a portion of the bottom surface of the contact hole CH in the insulator 62 is removed. As a result, insulator 34 is partially exposed on the bottom surface of each contact hole CH.

[0121] Further anisotropic etching is performed on the bottom of the contact hole CH. As a result, the portion below each contact hole CH in each insulator 34 is removed. Thus, the conductor 23 is exposed at the bottom of each contact hole CH. During this etching, the support pillar HR overlapping with the contact hole CH is also partially removed. The upper surface of the partially removed support pillar HR is adjacent to the upper surface of one of the conductors 23.

[0122] For reference Figure 7 As described, the support post HR is not located in the center of the contact plug CC. Therefore, during the etching process used to connect the bottom of the contact hole CH to the conductor 23, the area of ​​contact between the bottom of the contact hole CH and the support post HR can be suppressed.

[0123] like Figure 27 As shown, the contact hole CH is filled with a conductor. This forms the contact plug CC.

[0124] The remaining portion of insulator 36, conductor 60, contact plug CV, conductor 25, and insulator 37 are formed to complete the process. Figure 8 and Figure 9 The structure shown.

[0125] 1.3. Advantages (Effects)

[0126] According to the first embodiment, as described below, it is possible to provide a storage device including a lead-out area with a small area.

[0127] Figure 28 The reference storage device has a lead-out area 101. In the lead-out area 101, contact plugs 103, intended to connect to the conductors 102 corresponding to the conductors 23 in the first embodiment, are arranged in a matrix. However, when a large number of conductors are provided for the purpose of increasing the storage device's capacity, a large number of contact plugs are required to match the large number of conductors. Therefore, the lead-out area needs to have a large area.

[0128] According to the first embodiment, the contact plugs CC are arranged in an alternating pattern. Therefore, the contact plugs CC are arranged more densely than the contact plugs 103. As a result, when the dimensions of the contact plugs 103 and the contact plugs CC are the same, especially the cross-sectional area along the xy plane, the area of ​​the lead-out region HA1 required to arrange the same number of contact plugs 103 or CC is smaller than the area of ​​the lead-out region 101.

[0129] According to the first embodiment, the support post HR is not located at the center of the contact plug CC. Therefore, during etching to connect the bottom of the contact hole CH to the conductor 23, the area where the bottom of the contact hole CH contacts the support post HR can be suppressed. This reduces the size of the portion of the area of ​​the bottom of the contact hole CH along the xy plane that contacts the conductor 23. This minimizes the resistance between the contact plug CC and the conductor 23.

[0130] 2. Second Implementation Method

[0131] The second embodiment differs from the first embodiment in the shape of the contact plug CC along the xy plane.

[0132] Figure 29 An example of a planar layout showing a portion of the lead-out area of ​​the storage device in the second embodiment. Figure 29 Indicates and Figure 7 The same region, that is, a portion of the region between the two SLT components along the xy plane. Figure 29 This shows the layout of the layer containing conductor 24 as viewed from above along the z-axis.

[0133] like Figure 29 As shown, each contact plug CC has a hexagonal shape. For example, two opposite (substantially parallel) sides of each contact plug CC extend along the x-axis. The remaining four sides intersect both the x-axis and the y-axis. In other words, each contact plug CC has the shape of a quadrilateral contact plug CC in the first embodiment with its four corners cut off. Therefore, the vertices of each contact plug CC are closer to the center than the vertices of a quadrilateral contact plug CC. Based on this shape, the minimum spacing between adjacent contact plug CCs is large. The minimum spacing between adjacent contact plug CCs is the length of the shortest imaginary line among multiple imaginary lines connecting the edges of two adjacent contact plug CCs. Based on the contact plug CCs being configured the same as in the first embodiment and having a hexagonal shape, the minimum spacing between two contact plug CCs in the second embodiment is the distance between the opposite vertices of the two contacts.

[0134] The contact plugs CC are configured the same as in the first embodiment, i.e., they are arranged in an alternating pattern.

[0135] The support post HR comprises the area near the four vertices VX of one or more contact plugs CC. The four vertices VX are the two vertices VX formed by one of the two sides of the contact plug CC extending along the x-axis and the other two vertices VX formed by the other side of the two sides of the contact plug CC extending along the x-axis. The support post HR is, for example, located in the area near the four vertices VX of each contact plug CC.

[0136] For example, when viewed along the xy plane, the support post HR is located near 1 to 4 of the 4 vertices VX, in an area that does not overlap with the contact plug CC. Alternatively, when viewed along the xy plane, the support post HR is positioned to include 1 to 4 of the 4 vertices VX. Figure 29 This example illustrates the concept. Alternatively, when viewed along the xy plane, the support post HR is located near vertices 1 to 4 of the 4 vertices VX, in an area that completely overlaps with the contact plug CC.

[0137] The support post HR is not located at the center of more than one contact plug CC, for example, at the center of each contact plug CC.

[0138] For the configuration of support posts HR, support posts HR located in any other region are allowed as long as they are located near one or more of the four vertices VX of one or more contact plugs CC, and not located in the center of one or more contact plugs CC, such as the center of each contact plug CC. Figure 29 This represents an example of a matrix configuration for the support columns HR.

[0139] According to the second embodiment, the contact plug CC is configured the same as in the first embodiment. Furthermore, according to the second embodiment, similarly to the first embodiment, the support post HR is not located at the center of the contact plug CC. Therefore, the same advantages as in the first embodiment can be obtained.

[0140] Furthermore, according to the second embodiment, as described below, a storage device having a structure that suppresses differences from the designed and envisioned structure can be provided. (Referring to the first embodiment...) Figures 12-21 When the described method is used to form the contact hole CH, during the formation process, a portion of the structure of insulators 34, SM, and SM2 (hereinafter sometimes referred to as the "layered structure") may produce a state with a high aspect ratio. For example, Figure 19 The state conforms to this condition; when more conductors 23 are provided for the purpose of increasing the capacity of the storage device, the aspect ratio is higher. The aspect ratio depends on the distance between adjacent contact holes CH.

[0141] According to the second embodiment, each contact plug CC has a hexagonal shape. The minimum spacing between the contact plugs CC is the distance between the vertices VX of one contact plug CC and the vertices VX of the other contact plug CC. Therefore, the minimum spacing between adjacent contact plugs CC is large, which is larger than the minimum spacing between adjacent contact plugs CC when the contact plugs CC are quadrilateral. Therefore, the aspect ratio of a portion of the laminated structure generated during the formation of the contact hole CH is smaller than the aspect ratio of a portion of the laminated structure when the contact plugs CC are quadrilateral. As a result, a portion of the laminated structure is stable, at least more stable than when the contact plugs CC are quadrilateral. This can suppress structural collapse during the manufacturing of the storage device 1, and as a result, it can prevent the completed storage device 1 from deviating from the design and the envisioned structure.

[0142] As described above, according to the second embodiment, the contact plugs CC are configured in the same way as in the first embodiment, and the minimum spacing of the contact plugs CC is the distance between the opposite vertices of two obliquely arranged contact portions. Therefore, the distance between two adjacent rows of contact plugs CC is smaller than the distance between two adjacent rows in the reference storage device. Here, the distance between two adjacent rows of contact plugs is the difference between the center coordinate of the y-axis of one row of contact plugs CC and the center coordinate of the y-axis of the other row of contact plugs CC. Based on the oblique arrangement of the minimum spacing of the contact plugs CC, even if the distance between two adjacent rows of contact plugs CC is smaller than the distance between adjacent rows of contact plugs 103 in the reference storage device, the same minimum spacing as the minimum spacing of contact plugs 103 in the reference storage device can be maintained. Thus, according to the second embodiment, the contact plugs CC can have the same minimum spacing as the minimum spacing of contact plugs 103 in the reference storage device, and are configured to be denser than the contact plugs 103 in the reference storage device. That is, according to the second embodiment, it is possible to achieve both the same structural strength as the reference storage device and the lead-out region HA having an area smaller than the lead-out region 101 of the reference storage device.

[0143] like Figure 30 As shown, the contact plug CC in the second embodiment can also be circular along the xy plane.

[0144] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and also within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage device comprising: Multiple first conductors are arranged separately along the first axis; A storage column, extending along the first axis and facing the plurality of first conductors, includes a semiconductor and a film surrounding the semiconductor; and Multiple contact plugs extending along the first axis, Each of the plurality of contact plugs includes a second conductor and a first insulator surrounding the second conductor. The first insulator is located between the plurality of first conductors and the second conductor. Each of the plurality of contact plugs is connected on its lower surface to the upper surface of one of the plurality of first conductors, which are non-repeating. The plurality of contact plugs includes a first contact plug, a second contact plug, and a third contact plug. The first contact plug and the second contact plug are arranged adjacent to each other along a second axis that intersects the first axis. The third contact plug is located on the second axis between the first contact plug and the second contact plug, and is configured at different positions on the third axis, which is orthogonal to both the first and second axes. Each of the plurality of contact plugs has a hexagonal shape along a first surface including the second axis and the third axis, and the plurality of contact plugs are arranged in an alternating pattern on the first surface. The storage device also includes a plurality of insulators extending along the first axis and passing through the plurality of first conductors. The plurality of insulators are located in regions offset from the center of the respective shapes of the plurality of contact plugs. One of the plurality of insulators overlaps at least partially with one of the plurality of contact plugs along the first surface. One of the plurality of insulators overlaps at least partially with the vertex of one of the plurality of contact plugs along the first surface.

2. The storage device according to claim 1, The plurality of contact plugs also includes a fourth contact plug. The third contact plug and the fourth contact plug are arranged adjacent to each other along the second axis. The second contact plug is located on the second shaft between the third contact plug and the fourth contact plug.

3. The storage device according to claim 1, further comprising: A second insulator extends along the first axis, with its upper end positioned above the uppermost conductor among the plurality of first conductors, and its lower end connected to the lowermost conductor among the plurality of first conductors; and A plurality of third insulators, extending along the first axis, have their upper ends in contact with the lower surface of one of the plurality of contact plugs, and their lower ends in contact with the lowest-ranking conductor among the plurality of first conductors. The plurality of third insulators are located in regions offset from the center of the respective shapes of the plurality of contact plugs.

4. The storage device according to claim 3, One of the plurality of third insulators overlaps at least partially with one of the plurality of contact plugs along the first surface.

5. The storage device according to claim 4, One of the plurality of third insulators overlaps at least partially with the vertex of one of the plurality of contact plugs along the first surface.

6. The storage device according to claim 1, Each of the plurality of contact plugs has a circular shape along a first surface including the second axis and the third axis.

7. The storage device according to claim 6, It also includes a plurality of insulators extending along the first axis and passing through the plurality of first conductors. The plurality of insulators are located in regions offset from the center of the respective shapes of the plurality of contact plugs.

8. The storage device according to claim 7, One of the plurality of insulators overlaps at least partially with one of the plurality of contact plugs along the first surface.

9. The storage device according to claim 6, further comprising: A second insulator extends along the first axis, with its upper end positioned above the uppermost conductor among the plurality of first conductors, and its lower end connected to the lowermost conductor among the plurality of first conductors; and A plurality of third insulators, extending along the first axis, have their upper ends in contact with the lower surface of one of the plurality of contact plugs, and their lower ends in contact with the lowest-ranking conductor among the plurality of first conductors. The plurality of third insulators are located in regions offset from the center of the respective shapes of the plurality of contact plugs.

10. The storage device according to claim 9, One of the plurality of third insulators overlaps at least partially with one of the plurality of contact plugs along the first surface.

11. The storage device according to claim 1, It also includes a plurality of insulators extending along the first axis and passing through the plurality of first conductors. The plurality of insulators are located in regions offset from the center of the respective shapes of the plurality of contact plugs.

12. The storage device according to claim 1, The membrane of the storage column comprises: A fourth insulator is disposed between the semiconductor and the first conductor; A charge storage film is disposed between the fourth insulator and the first conductor; as well as A fifth insulator is disposed between the charge storage film and the first conductor.

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