Test structures and methods of manufacturing the same

Abstract

The present disclosure provides a test structure and a method for manufacturing the same. The test structure includes a substrate, a transistor formed on the substrate, the transistor including a gate structure, a plurality of metal layers above the transistor including a top metal layer, and a gate pad and an antenna structure formed on the top metal layer and electrically connected to the gate structure of the transistor through the plurality of metal layers and conductive plugs between adjacent metal layers of the plurality of metal layers. The antenna structure collects free charges generated during the manufacturing of the top metal layer and transmits the free charges to the gate pad. When the charge accumulation of the gate pad reaches a certain level, the gate pad causes damage to the gate structure. The gate structure includes a gate oxide layer. By electrically detecting the damage to the gate structure, plasma-induced damage during the manufacturing of the top metal layer can be determined, and the impact of the related process on a device corresponding to the test structure can be monitored, which is beneficial to improving the yield and reliability of the manufactured chips.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a test structure and its manufacturing method. Background Technology

[0002] In deep submicron integrated circuit fabrication processes, high-density plasma-enhanced chemical vapor deposition (HDPECVD) and plasma etching techniques are typically used extensively. These techniques can meet the demands of continuously shrinking dimensions and increasing mask etching resolution.

[0003] However, during high-density plasma-enhanced vapor deposition or plasma etching, free charges are generated, and these free charges collect on the exposed conductor surface. If the conductor with accumulated charge is directly connected to the gate structure of the device, gate leakage current will form in the gate oxide layer beneath the gate structure, affecting the turn-on voltage Vt of the semiconductor device. When the accumulated charge exceeds a certain amount, this gate leakage current will damage the gate oxide layer, causing circuit failure and severely reducing the reliability and lifespan of the device and even the entire chip. This situation is usually called plasma-induced damage (PID), also known as the process antenna effect (PAE). Summary of the Invention

[0004] This disclosure provides a test structure and its manufacturing method to solve the problem that plasma-induced damage to the gate oxide layer cannot be determined during the manufacturing of the top metal layer.

[0005] A test structure, comprising:

[0006] Base;

[0007] A transistor formed on a substrate, the transistor including a gate structure;

[0008] Multiple metal layers are located above the transistor, including a top metal layer; and

[0009] The gate pad and antenna structure are formed on the top metal layer and electrically connected to the gate structure of the transistor through the plurality of metal layers and conductive plugs located between adjacent metal layers.

[0010] In an optional embodiment, the test structure further includes:

[0011] A passivation layer, located above the plurality of metal layers, includes at least one of a first opening exposing a gate pad and a second opening exposing an antenna structure.

[0012] In an optional embodiment, the test structure further includes:

[0013] A dielectric layer is located between adjacent metal layers of the plurality of metal layers;

[0014] The conductive plug is located in a via of the dielectric layer.

[0015] In an optional embodiment, the transistor further includes a source structure and a drain structure, and the test structure further includes:

[0016] A source pad is formed in any one of the plurality of metal layers and is electrically connected to the source structure through at least one of the plurality of metal layers; and

[0017] The drain pad is formed in any one of the plurality of metal layers and is electrically connected to the drain structure through at least one of the plurality of metal layers.

[0018] In an optional embodiment, the test structure further includes:

[0019] The substrate pad is formed in any one of the plurality of metal layers and is electrically connected to the substrate through at least one of the plurality of metal layers.

[0020] In an optional embodiment, the dielectric layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a low-k dielectric layer.

[0021] In an optional embodiment, the gate structure includes:

[0022] A gate oxide layer is located on the substrate; and

[0023] A gate layer is located on the surface of the gate oxide layer.

[0024] In an optional embodiment, the thickness of the gate oxide layer is 1 nm to 20 nm.

[0025] In an optional embodiment, the gate layer includes:

[0026] Gate polysilicon layer; and,

[0027] A gate metal layer is located on the surface of the gate polysilicon layer.

[0028] On the other hand, this application provides a method for manufacturing a test structure, comprising:

[0029] A substrate is provided on which a transistor is formed, the transistor including a gate structure;

[0030] Multiple metal layers are formed above the transistor;

[0031] The plurality of metal layers include a top metal layer, which includes a gate pad and an antenna structure. The gate pad and the antenna structure are electrically connected to the gate structure of the transistor through the plurality of metal layers and conductive plugs located between adjacent metal layers.

[0032] In an optional embodiment, the method further includes:

[0033] A passivation layer is formed over the plurality of metal layers, the passivation layer including at least one of a first opening exposing a gate pad and a second opening exposing an antenna structure.

[0034] In an optional embodiment, the method further includes:

[0035] A dielectric layer is formed between adjacent metal layers of multiple metal layers;

[0036] The conductive plug is located in a via of the dielectric layer.

[0037] In an optional embodiment, the transistor further includes a source structure and a drain structure;

[0038] Each of the plurality of metal layers includes a source structure, and the source structure is electrically connected to the source structure through at least one of the plurality of metal layers; and

[0039] The plurality of metal layers includes a drain structure, and the drain structure is electrically connected to the drain structure through at least one of the plurality of metal layers.

[0040] In an optional embodiment, any one of the plurality of metal layers includes a substrate pad, the substrate pad being electrically connected to the substrate through at least one of the plurality of metal layers.

[0041] In an optional embodiment, the dielectric layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a low-k dielectric layer.

[0042] In an optional embodiment, the gate structure includes:

[0043] A gate oxide layer is located on the substrate; and

[0044] A gate layer is located on the surface of the gate oxide layer.

[0045] In an optional embodiment, the thickness of the gate oxide layer is 1 nm to 20 nm.

[0046] In an optional embodiment, the gate layer includes:

[0047] Gate polysilicon layer; and,

[0048] A gate metal layer is located on the surface of the gate polysilicon layer.

[0049] The test structure provided in the embodiments of this application includes a substrate, a transistor, multiple metal layers, a gate pad, and an antenna structure. The transistor is formed on the substrate and includes a gate structure. The multiple metal layers are located above the transistor, including a top metal layer. The gate pad and antenna structure are formed on the top metal layer and are electrically connected to the gate structure of the transistor through the multiple metal layers and conductive plugs located between adjacent metal layers. Thus, the antenna structure and gate pad can collect free charges generated during the fabrication of the top metal layer. Since they are electrically connected to the gate structure, when the charge accumulates to a certain level, it may damage the gate structure (e.g., damage to the gate oxide layer included in the gate structure). By electrically detecting the damage to the gate structure, plasma-induced damage during the fabrication of the top metal layer can be determined, thereby monitoring the impact of related processes on the device corresponding to the test structure, which is beneficial for improving the yield and reliability of the manufactured chip. Attached Figure Description

[0050] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0051] Figure 1 This is a schematic diagram of a test structure;

[0052] Figure 2 This is a schematic diagram of a jumper structure in a test setup.

[0053] Figure 3 Schematic diagram of the test structure provided for some embodiments of this disclosure;

[0054] Figure 4 Partial schematic diagram of the test structure provided for some embodiments of this disclosure;

[0055] Figure 5 Schematic diagram of the passivation layer of the test structure provided for some embodiments of this disclosure;

[0056] Figure 6 A schematic flowchart illustrating a method for manufacturing a test structure provided for some embodiments of this disclosure.

[0057] Explanation of reference numerals in the attached figures:

[0058] Test Structure 101

[0059] Gate pad 1011

[0060] Source pad 1012

[0061] Drain pad 1013

[0062] Substrate pad 1014

[0063] 1015 substrate

[0064] Jumper structure 102

[0065] Top metal layer 103

[0066] Protection diode 104

[0067] Antenna structure 105

[0068] Non-top metal layer 106

[0069] Transistor 107

[0070] First passivation layer 108

[0071] Second passivation layer 109

[0072] Test Structure 10

[0073] 100 base

[0074] Transistor 200

[0075] Gate structure 210

[0076] Gate oxide layer 211

[0077] Gate layer 212

[0078] Source structure 220

[0079] Drain structure 230

[0080] Metal layer 300

[0081] Top metal layer 310

[0082] Gate pad 400

[0083] Source pad 410

[0084] Drain pad 420

[0085] Base pad 430

[0086] Antenna structure 500

[0087] passivation layer 600

[0088] First passivation layer 610

[0089] Second passivation layer 620

[0090] Conductive plug 20

[0091] Dielectric layer 30

[0092] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0093] The exemplary embodiments will now be described in detail herein, and these embodiments are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0094] When manufacturing chips based on deep submicron integrated circuit processing technology, it is necessary to assess plasma-induced damage to the gate oxide layer, especially when manufacturing metal layers.

[0095] Figure 1 This is a schematic diagram of a test structure 101. Figure 2 for Figure 1 The diagram shows a jumper structure 102 in the test structure. The test structure 101 includes a jumper structure 102, a top metal layer 103 (M4), a protection diode 104, an antenna structure 105, non-top metal layers 106 (M1-M3), and a transistor 107. It also includes dielectric layers (V1, V2, V3, and V4) between the metal layers, a gate pad 1011, a source pad 1012, a drain pad 1013, and a base pad 1014.

[0096] The gate of transistor 107 is connected to gate pad 1011, the source of transistor 107 is connected to source pad 1012, the drain is connected to drain pad 1013, and the substrate pad 1014 is connected to substrate 1015. Antenna structure 105 is formed based on a single or multiple metal layers when forming the non-top metal layer 106, and antenna structure 105 is also connected to the gate of transistor 107. Therefore, based on this test structure 101, the antenna effect of a single metal layer in the non-top metal layer 106 (excluding the top metal layer 103), or the cumulative antenna effect of multiple metal layers, can be monitored, but the antenna effect of the top metal layer 103 cannot be monitored.

[0097] like Figure 1 As shown, the jumper structure 102 connects the gate of the transistor 107 to the gate pad 1011. When the top metal layer 103 is formed, the jumper structure 102 is turned on. The top metal layer 103 has a large critical dimension and thickness, resulting in a strong antenna effect during the manufacturing process. Figure 1 In the test structure, the antenna effect of the top metal layer 103 is reduced by the jumper structure 102 and the protection diode 104. On the one hand, the jumper structure 102 can shorten the length of the metal trace, thereby reducing the antenna effect; on the other hand, the gate pad 1011 is grounded through the protection diode 104. Thus, after the jumper structure 102 is turned on, the gate of the transistor 107 is also grounded through the protection diode 104. When the charge on the top metal layer 103 accumulates to a certain level, the protection diode 104 will turn on to form a path to ground, thereby also reducing the antenna effect. Therefore, the antenna effect of the top metal layer 103 cannot be monitored based on this test structure 101.

[0098] However, since the protection diode 104 increases the chip area, it is often not included in the fabrication of the device corresponding to test structure 101. The protection diode 104 is only present during plasma damage testing. Therefore, plasma-induced damage to the gate oxide layer of transistor 107 is an objective reality when fabricating the top metal layer of the device corresponding to test structure 101, making it necessary to monitor the antenna effect of the top metal layer.

[0099] In addition, such as Figure 1As shown in the figure below, the test structure 101 also includes a first passivation layer 108 and a second passivation layer 109. Openings in the first passivation layer 108 and the second passivation layer 109 are used to expose the gate pad 1011, source pad 1012, drain pad 1013, and base pad 1014 for relevant electrical tests. During the fabrication of the device corresponding to the test structure 101, etching the openings of the first passivation layer 108 and the second passivation layer 109 (such as exposing the opening of the gate pad 1011) will also cause plasma-induced damage to the gate oxide layer in the transistor 107. Figure 1 The test structure shown is also unable to detect plasma-induced damage when an opening is formed.

[0100] In conclusion, Figure 1 The test structure shown can only be used to detect plasma-induced damage to the gate oxide layer during the fabrication of the non-top metal layer. It cannot detect plasma-induced damage to the gate oxide layer during the fabrication of the top metal layer or during the etching of the passivation layer opening. Therefore, during chip manufacturing, it is impossible to accurately implement countermeasures based on plasma-induced damage to improve chip yield, potentially leading to a decrease in chip yield.

[0101] Therefore, how to determine the plasma-induced damage to the gate oxide layer during the fabrication of the top metal layer in order to improve the yield of manufactured chips remains an urgent problem to be solved.

[0102] Based on this, this disclosure provides a test structure and its manufacturing method. The test structure includes a substrate, a transistor, multiple metal layers, a gate pad, and an antenna structure. The transistor is formed on the substrate and includes a gate structure. The multiple metal layers are located above the transistor, including a top metal layer. The gate pad and antenna structure are formed on the top metal layer and are electrically connected to the gate structure of the transistor through the multiple metal layers and conductive plugs located between adjacent metal layers. Thus, the antenna structure and gate pad can collect free charges generated during the manufacturing of the top metal layer. Since they are electrically connected to the gate structure, when the charge accumulates to a certain level, it may damage the gate structure (e.g., damage the gate oxide layer included in the gate structure). By electrically detecting the damage to the gate structure, plasma-induced damage during the manufacturing of the top metal layer can be determined, thereby monitoring the impact of related processes on the device corresponding to the test structure, which is beneficial to improving the yield and reliability of the manufactured chip.

[0103] Please see Figure 3One embodiment of this disclosure provides a test structure 10, including a substrate 100, a transistor 200, a plurality of metal layers 300, a gate pad 400, and an antenna structure 500. The transistor 200 is formed on the substrate 100, the plurality of metal layers 300 are located above the transistor 200, and the gate pad 400 and the antenna structure 500 are both formed on the top metal layer 310.

[0104] The substrate 100 may be made of one or more of the following materials: silicon (Si), silicon carbide (SiC), aluminum oxide (Al2O3), gallium arsenide (GaAs), etc. The thickness, formation method, and material of the substrate 100 can be selected according to actual needs, and this embodiment does not limit them.

[0105] The transistor 200 is formed on the substrate 100. The transistor 200 includes a gate structure 210, a source structure 220, and a drain structure 230. The shape and position of the gate structure 210, the source structure 220, and the drain structure 230 can be set according to actual needs, and are not limited in this embodiment.

[0106] Please see Figure 4 In an optional embodiment, the gate structure 210 includes a gate oxide layer 211 and a gate layer 212.

[0107] The gate oxide layer 211 is located on the substrate 100, and the gate layer 212 is located on the surface of the gate oxide layer 211. The thickness of the gate oxide layer 211 can be set according to actual needs. For example, the thickness of the gate oxide layer 211 can be 1 nm to 20 nm. For example, the thickness of the gate oxide layer 211 can be 1 nm to 10 nm. For example, the thickness of the gate oxide layer 211 can be 1 nm to 5 nm. Specifically, the thickness of the gate oxide layer 211 is, for example, 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, 15 nm, or 20 nm.

[0108] The thickness of the gate layer 212 can be set according to actual needs. For example, the thickness of the gate layer 212 can include 1000 angstroms to 5000 angstroms. Specifically, the thickness of the gate layer 212 can be 1000 angstroms, 1500 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms or 5000 angstroms.

[0109] The gate layer 212 may include a gate polysilicon layer (not shown) and a gate metal layer (not shown). The gate metal layer is located on the surface of the gate polysilicon layer. The dielectric layer 30 is located on the surface of the gate metal layer, and leads out electrodes that are electrically connected to the gate metal layer.

[0110] In another alternative embodiment, the gate layer 212 may include a gate metal layer, that is, the gate layer 212 is a metal gate layer.

[0111] In yet another alternative embodiment, the gate layer 212 may also be a polysilicon layer.

[0112] It should be noted that the polysilicon layer or gate polysilicon layer in the gate layer 212 in the above embodiments are all doped polysilicon layers.

[0113] The plurality of metal layers 300 are located above the transistor 200, including a top metal layer 310 and non-top metal layers 310 (e.g., including a second-top metal layer, intermediate metal layers, and a bottom metal layer, wherein the bottom metal layer covers the transistor 200). The specific number of metal layers 300 can be set according to actual needs, for example, two, three, four, six, seven, or even more layers. The material of the metal layers 300 can be copper, tungsten, aluminum, etc. There is also a dielectric layer 30 between adjacent metal layers 300. When forming the plurality of metal layers 300 and the dielectric layer 30, the metal layers 300 can be deposited on the dielectric layer 30 using high-density plasma-enhanced vapor deposition, and then the metal layers 300 can be etched using plasma etching to form a pattern. In addition, the dielectric layer 30 can be etched using plasma etching to form vias for setting conductive plugs 20 in the dielectric layer 30.

[0114] During high-density plasma-enhanced vapor deposition or plasma etching, free charges are generated, and these free charges are collected on the surface of the exposed metal layer 300. If the metal layer 300 with accumulated charge is directly connected to the gate structure 210 of the transistor 200, gate leakage current will form in the gate oxide layer 211 under the gate structure 210, thereby affecting the turn-on voltage Vt of the semiconductor device in the chip. When the accumulated charge exceeds a certain amount, this gate leakage current will damage the gate oxide layer 211, causing circuit failure, which will severely reduce the reliability and lifespan of the semiconductor device and even the entire chip.

[0115] Please see Figures 3 to 4The gate pad 400 and the antenna structure 500 are formed on the top metal layer 310 and are electrically connected to the gate structure 210 of the transistor 200 through the plurality of metal layers 300 and the conductive plugs 20 located between adjacent metal layers 300. Thus, the antenna structure 500 and the gate pad 400 can collect ionized charges generated during the fabrication of the top metal layer 310. Since they are electrically connected to the gate structure, when the charge accumulates to a certain level, it may damage the gate structure (e.g., damage the gate oxide layer included in the gate structure). Specifically, the antenna structure 500 and the gate pad 400 transfer ionized charges to the gate structure 210 of the transistor 200 through leads. When the accumulated charge in the gate structure 210 exceeds a certain amount, it will damage the gate oxide layer 211 in the gate structure 210, resulting in gate leakage. By performing electrical testing on the damage to the gate structure 210, plasma-induced damage during the manufacturing of the top layer metal can be identified. This allows for monitoring of the impact of related processes on the devices corresponding to the test structure, which is beneficial for improving the yield and reliability of the manufactured chips.

[0116] Please see Figure 5 In an optional embodiment, the test structure 10 further includes a passivation layer 600. The passivation layer 600 is located above the plurality of metal layers 300 and includes a first opening exposing the gate pad 400. Figure 5 The test structure 10 contains at least one of the openings in the passivation layer 600 and the second opening (not shown in the figure) of the exposed antenna structure 500. Thus, the test structure 10 can also be used to determine plasma-induced damage to the gate oxide layer 211 when the first opening and / or the second opening is etched in the passivation layer 600 to form it.

[0117] For example, the passivation layer 600 may include a first passivation layer 610 and a second passivation layer 620 stacked together. For example, the material of the first passivation layer 610 may be silicon oxide, and the material of the second passivation layer 620 may be silicon nitride.

[0118] The passivation layer 600 may also include openings exposing the source pad 410, drain pad 420, and base pad 430 (see subsequent description). Thus, the transistor 200 can be electrically tested through the gate pad 400, source pad 410, drain pad 420, and base pad 430; that is, the gate structure 210 of the transistor 200 can be electrically inspected.

[0119] Please see Figure 4 and Figure 5The test structure 10 further includes a dielectric layer 30 located between adjacent metal layers 300 of the plurality of metal layers 300. The dielectric layer 30 can be made of at least one of silicon nitride, silicon oxynitride, silicon oxide, or other low-k (dielectric constant) layers; that is, the dielectric layer 30 can be a silicon nitride layer, silicon oxynitride layer, silicon oxide layer, or other low-k dielectric layer, or it can be a stacked structure of at least two of silicon nitride, silicon oxynitride, silicon oxide, and other low-k dielectric layers. In an optional embodiment, the dielectric layer 30 can be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Silicon nitride and silicon oxynitride layers have higher capture capabilities for free charges and can have higher sensitivity than the dielectric layer 30 with a silicon oxide layer. In an optional embodiment, the dielectric layer 30 can be a stacked structure comprising sequentially stacked silicon oxide, silicon nitride, and silicon oxide layers, or it can be a stacked structure comprising sequentially stacked silicon nitride, silicon oxide, and silicon nitride layers. Since a thick silicon nitride layer will result in large residual stress, while a thin silicon nitride layer will result in too large parasitic capacitance between the upper and lower metal layers 300, by setting the dielectric layer 30 as a stacked structure including a silicon oxide layer, a silicon nitride layer and a silicon oxide layer or a stacked structure including a silicon nitride layer, a silicon oxide layer and a silicon nitride layer, it is possible to reduce the thickness of the silicon nitride layer to reduce residual stress, while ensuring the thickness of the dielectric layer 30 and reducing the parasitic capacitance between the upper and lower metal layers 300.

[0120] Specifically, the silicon nitride and silicon oxide layers in the dielectric layer 30 can be formed using PECVD (plasma-enhanced chemical vapor deposition). Silicon nitride or silicon oxide layers formed using PECVD have lower film quality but are more prone to trapping free charges. The growth pressure in the PECVD process cannot be too high or too low. If the growth pressure is too high, the dielectric layer 30 will grow too quickly, resulting in poor quality. If the growth pressure is too low, the dielectric layer 30 will grow too slowly, leading to a longer growth cycle and lower production efficiency. Specifically, in this embodiment, the growth pressure can be 1 Torr to 10 Torr, or more specifically, 1 Torr, 5 Torr, or 10 Torr, etc. The growth temperature in the PECVD process cannot be too high or too low. If the growth temperature is too high, the dielectric layer 30 will grow too fast, resulting in poor quality of the dielectric layer 30. If the growth temperature is too low, the dielectric layer 30 will grow too slowly, resulting in a longer growth cycle and lower production efficiency. Specifically, in this embodiment, the growth stability can be 300℃~500℃. More specifically, the growth temperature can be 300℃, 400℃, or 500℃, etc.

[0121] In an optional embodiment, the multilayer metal layers 300 are stacked sequentially with intervals, and the area of ​​the top metal layer 300 can be larger than the areas of the other metal layers 300. The larger the area of ​​the metal layer 300, the stronger the ability of the antenna structure 500 on the metal layer 300 to collect free charge; that is, the larger the area of ​​the metal layer 300, the more free charge it collects. Therefore, by setting the area of ​​the top metal layer 310 to be larger than the areas of the other metal layers 300, the gate structure leakage current induced by free charge can more easily damage the gate oxide layer 211 of the gate structure 210 in the transistor 200, thereby making it easier to determine the plasma-induced damage caused by the top metal layer 310.

[0122] Adjacent metal layers 300 are electrically connected via conductive plugs 20. The gate pad 400 and antenna structure 500 are electrically connected to the gate structure 210 of the transistor 200 through the plurality of metal layers 300 and the conductive plugs 20 located between adjacent metal layers 300. It should be noted that an interlayer dielectric layer 30 is provided between adjacent metal layers 300, and the conductive plugs 20 are located in vias of the interlayer dielectric layer 30.

[0123] When forming the gate pad 400 and the antenna structure 500, the position of the gate pad 400 on the top metal layer 310 and the position of the antenna structure 500 on the top metal layer 310 can be selected according to actual needs, and this embodiment does not limit them.

[0124] Please see Figure 3 In an optional embodiment, the transistor 200 further includes a source structure 220 and a drain structure 230, and the test structure 10 further includes a source pad 410 and a drain pad 420. The source pad 410 is formed in any one of the plurality of metal layers 300 and is electrically connected to the source structure 220 of the transistor 200 through at least one of the plurality of metal layers 300. The drain pad 420 is formed in any one of the plurality of metal layers 300 and is electrically connected to the drain structure 230 of the transistor 200 through at least one of the plurality of metal layers 300. The source pad 410 and the drain pad 420 may be formed on the top metal layer 310 and are electrically connected to the source structure 220 of the transistor 200 through the top metal layer 310 and other metal layers 300.

[0125] In an optional embodiment, the test structure 10 further includes a base pad 430 formed in any one of the plurality of metal layers 300 and electrically connected to the substrate 100 through at least one of the plurality of metal layers 300. The base pad 430 may be formed on the top metal layer 310 and electrically connected to the substrate 100 of the transistor 200 through the top metal layer 310.

[0126] In summary, the test structure 10 provided in this embodiment includes a substrate 100, a transistor 200, multiple metal layers 300, a gate pad 400, and an antenna structure 500. The transistor 200 is formed on the substrate 100 and includes a gate structure 210. The multiple metal layers 300 are located above the transistor 200 and include a top metal layer 310. The gate pad 400 and the antenna structure 500 are formed on the top metal layer 310 and are electrically connected to the gate structure 210 of the transistor 200 through the multiple metal layers 300 and conductive plugs 20 located between adjacent metal layers 300. Therefore, the antenna structure 500 and the gate pad 400 can collect free charges generated during the manufacturing of the top metal layer 310. Since they are electrically connected to the gate structure, when the charge accumulates to a certain level, it may damage the gate structure (e.g., damage to the gate oxide layer included in the gate structure). By performing electrical testing on the damage to the gate structure 210, plasma-induced damage during the manufacturing of the top layer metal can be identified. This allows for monitoring of the impact of related processes on the devices corresponding to the test structure, which is beneficial for improving the yield and reliability of the manufactured chips.

[0127] Please see Figure 6 One embodiment of this disclosure also provides a method for manufacturing a test structure, including the following steps S610 to S630.

[0128] S610 provides a substrate on which a transistor is formed, the transistor including a gate structure.

[0129] Please see Figure 3 The substrate 100 may be made of one or more of the following materials: silicon (Si), silicon carbide (SiC), aluminum oxide (Al2O3), gallium arsenide (GaAs), etc. The thickness, formation method, and material of the substrate 100 can be selected according to actual needs, and this embodiment does not limit them.

[0130] The transistor 200 is formed on the substrate 100. The transistor 200 includes a gate structure 210, a source structure 220, and a drain structure 230. The shape and position of the gate structure 210, the source structure 220, and the drain structure 230 can be set according to actual needs, and are not limited in this embodiment.

[0131] Please see Figure 4 In an optional embodiment, the gate structure 210 includes a gate oxide layer 211 and a gate layer 212.

[0132] The gate oxide layer 211 is located on the substrate 100, and the gate layer 212 is located on the surface of the gate oxide layer 211. The thickness of the gate oxide layer 211 can be set according to actual needs. For example, the thickness of the gate oxide layer 211 can include 1 nm to 20 nm. For example, the thickness of the gate oxide layer 211 can be 1 nm to 10 nm. For example, the thickness of the gate oxide layer 211 can be 1 nm to 5 nm. Specifically, the thickness of the gate oxide layer 211 is, for example, 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, 15 nm, or 20 nm.

[0133] The thickness of the gate layer 212 can be set according to actual needs. For example, the thickness of the gate layer 212 can include 1000 angstroms to 5000 angstroms. Specifically, the thickness of the gate layer 212 can be 1000 angstroms, 1500 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms or 5000 angstroms.

[0134] The gate layer 212 may include a gate polysilicon layer (not shown) and a gate metal layer (not shown). The gate metal layer is located on the surface of the gate polysilicon layer. The dielectric layer 30 is located on the surface of the gate metal layer, and leads out electrodes that are electrically connected to the gate metal layer.

[0135] In another alternative embodiment, the gate layer 212 may include a gate metal layer, that is, the gate layer 212 is a metal gate layer.

[0136] In yet another alternative embodiment, the gate layer 212 may also be a polysilicon layer.

[0137] It should be noted that the polysilicon layer or gate polysilicon layer in the gate layer 212 in the above embodiments are all doped polysilicon layers.

[0138] S620, a plurality of metal layers are formed above the transistor; wherein the plurality of metal layers include a top metal layer, the top metal layer includes a gate pad and an antenna structure, the gate pad and the antenna structure are electrically connected to the gate structure of the transistor through the plurality of metal layers and conductive plugs 20 located between adjacent metal layers of the plurality of metal layers.

[0139] Please see Figure 3 and Figure 4The plurality of metal layers 300 are located above the transistor 200, including a top metal layer 310 and non-top metal layers (including a second-to-top metal layer, intermediate metal layers, and a bottom metal layer, wherein the bottom metal layer covers the transistor 200). The specific number of metal layers 300 can be set according to actual needs, for example, two, three, four, six, seven, or even more layers. The material of the metal layers 300 can be copper, tungsten, aluminum, etc. There is also a dielectric layer 30 between adjacent metal layers 300. When forming the plurality of metal layers 300 and the dielectric layer 30, the metal layers 300 can be deposited on the dielectric layer 30 using high-density plasma-enhanced vapor deposition, and then the metal layers 300 can be etched using plasma etching to form a pattern. In addition, the dielectric layer 30 can be etched using plasma etching to form vias for setting conductive plugs 20 in the dielectric layer 30.

[0140] During high-density plasma-enhanced vapor deposition or plasma etching, free charges are generated, and these free charges are collected on the surface of the exposed metal layer 300. If the metal layer 300 with accumulated charge is directly connected to the gate structure 210 of the transistor 200, gate leakage current will form in the gate oxide layer 211 under the gate structure 210, thereby affecting the turn-on voltage Vt of the semiconductor device in the chip. When the accumulated charge exceeds a certain amount, this gate leakage current will damage the gate oxide layer 211, causing circuit failure, which will severely reduce the reliability and lifespan of the semiconductor device and even the entire chip.

[0141] Please see Figures 3 to 4 The gate pad 400 and the antenna structure 500 are formed on the top metal layer 310 and are electrically connected to the gate structure 210 of the transistor 200 through the plurality of metal layers 300 and the conductive plugs 20 located between adjacent metal layers 300. The antenna structure 500 and the gate pad 400 can collect free charges generated during the manufacturing of the top metal layer 310. Since they are electrically connected to the gate structure, when the charge accumulates to a certain level, it may cause damage to the gate structure (for example, damage to the gate oxide layer included in the gate structure). By electrically detecting the damage to the gate structure 210, plasma-induced damage during the manufacturing of the top metal layer can be determined, thereby monitoring the impact of related processes on the device corresponding to the test structure, which is beneficial to improving the yield and reliability of the manufactured chip.

[0142] Please see Figures 3 to 4 The method of manufacturing the test structure further includes forming a dielectric layer 30 between adjacent metal layers 300 of a plurality of metal layers 300, wherein the conductive plug 20 is located in a via of the dielectric layer 30.

[0143] The dielectric layer 30 can be made of at least one of silicon nitride, silicon oxynitride, silicon oxide, or other low-k (dielectric constant) layers. Specifically, the dielectric layer 30 can be one of silicon nitride, silicon oxynitride, silicon oxide, or other low-k dielectric layers, or it can be a stacked structure of at least two of these low-k dielectric layers. In an optional embodiment, the dielectric layer 30 can be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Silicon nitride and silicon oxynitride layers have higher capture capabilities for free charges and can exhibit higher sensitivity compared to a silicon oxide layer. In an optional embodiment, the dielectric layer 30 can be a stacked structure comprising sequentially stacked silicon oxide, silicon nitride, and silicon oxide layers, or it can be a stacked structure comprising sequentially stacked silicon nitride, silicon oxide, and silicon nitride layers. Since a thick silicon nitride layer will result in large residual stress, while a thin silicon nitride layer will result in too large parasitic capacitance between the upper and lower metal layers 300, by setting the dielectric layer 30 as a stacked structure including a silicon oxide layer, a silicon nitride layer and a silicon oxide layer or a stacked structure including a silicon nitride layer, a silicon oxide layer and a silicon nitride layer, it is possible to reduce the thickness of the silicon nitride layer to reduce residual stress, while ensuring the thickness of the dielectric layer 30 and reducing the parasitic capacitance between the upper and lower metal layers 300.

[0144] Specifically, the silicon nitride and silicon oxide layers in the dielectric layer 30 can be formed using PECVD (plasma-enhanced chemical vapor deposition). Silicon nitride or silicon oxide layers formed using PECVD have lower film quality but are more prone to trapping free charges. The growth pressure in the PECVD process cannot be too high or too low. If the growth pressure is too high, the dielectric layer 30 will grow too quickly, resulting in poor quality. If the growth pressure is too low, the dielectric layer 30 will grow too slowly, leading to a longer growth cycle and lower production efficiency. Specifically, in this embodiment, the growth pressure can be 1 Torr to 10 Torr, or more specifically, 1 Torr, 5 Torr, or 10 Torr, etc. The growth temperature in the PECVD process cannot be too high or too low. If the growth temperature is too high, the dielectric layer 30 will grow too fast, resulting in poor quality of the dielectric layer 30. If the growth temperature is too low, the dielectric layer 30 will grow too slowly, resulting in a longer growth cycle and lower production efficiency. Specifically, in this embodiment, the growth stability can be 300℃~500℃. More specifically, the growth temperature can be 300℃, 400℃, or 500℃, etc.

[0145] In an optional embodiment, the multilayer metal layers 300 are stacked sequentially with intervals between them, and the area of ​​the top metal layer 310 can be larger than the areas of the other metal layers 300. The larger the area of ​​the metal layer 300, the stronger the ability of the antenna structure 500 on the metal layer 300 to collect ionized charges; that is, the larger the area of ​​the metal layer 300, the more ionized charges it collects. Therefore, by setting the area of ​​the top metal layer 310 to be larger than the area of ​​the other metal layers 300, the gate structure leakage current induced by ionized charges can more easily damage the gate oxide layer 211 of the gate structure 210 in the transistor 200, thereby making it easier to determine the plasma-induced damage caused by the top metal layer 310.

[0146] Adjacent metal layers 300 are electrically connected via conductive plugs 20. The gate pad 400 and antenna structure 500 are electrically connected to the gate structure 210 of the transistor 200 through the plurality of metal layers 300 and the conductive plugs 20 located between adjacent metal layers 300. It should be noted that an interlayer dielectric layer 30 is provided between adjacent metal layers 300, and the conductive plugs 20 are located in vias of the interlayer dielectric layer 30.

[0147] When forming the gate pad 400 and the antenna structure 500, the position of the gate pad 400 on the top metal layer 310 and the position of the antenna structure 500 on the top metal layer 310 can be selected according to actual needs, and this embodiment does not limit them.

[0148] Please see Figure 3 In an optional embodiment, the transistor 200 further includes a source structure 220 and a drain structure 230, and the test structure 10 further includes a source pad 410 and a drain pad 420. The source pad 410 is formed in any one of the plurality of metal layers 300 and is electrically connected to the source structure 220 of the transistor 200 through at least one of the plurality of metal layers 300. The drain pad 420 is formed in any one of the plurality of metal layers 300 and is electrically connected to the drain structure 230 of the transistor 200 through at least one of the plurality of metal layers 300. The source pad 410 and the drain pad 420 may be formed on the top metal layer 310 and are electrically connected to the source structure 220 of the transistor 200 through the top metal layer 310 and other metal layers 300.

[0149] In an optional embodiment, the test structure 10 further includes a base pad 430 formed in any one of the plurality of metal layers 300 and electrically connected to the substrate 100 through at least one of the plurality of metal layers 300. The base pad 430 may be formed on the top metal layer 310 and electrically connected to the substrate 100 of the transistor 200 through the top metal layer 310.

[0150] S630, a passivation layer and an opening in the passivation layer are formed in the test structure.

[0151] Please see Figure 5 The passivation layer 600 is located above the plurality of metal layers 300, including a first opening exposing the gate pad 400. Figure 5 The test structure 10 contains at least one of the openings in the passivation layer 600 and the second opening (not shown in the figure) of the exposed antenna structure 500. Thus, the test structure 10 can also be used to determine plasma-induced damage to the gate oxide layer 211 when the first opening and / or the second opening is etched in the passivation layer 600 to form it.

[0152] For example, the passivation layer 600 may include a first passivation layer 610 and a second passivation layer 620 stacked together. For example, the material of the first passivation layer 610 may be silicon oxide, and the material of the second passivation layer 620 may be silicon nitride.

[0153] The passivation layer 600 may also include openings exposing the source pad 410, drain pad 420, and base pad 430. Thus, the transistor 200 can be electrically tested through the gate pad 400, source pad 410, drain pad 420, and base pad 430; that is, the gate structure 210 of the transistor 200 can be electrically inspected.

[0154] In summary, the method for manufacturing the test structure provided in this embodiment includes a substrate 100, on which a transistor 200 is formed, the transistor 200 including a gate structure 210. A plurality of metal layers 300 are then formed above the transistor 200, wherein the plurality of metal layers 300 includes a top metal layer 310, the top metal layer 310 including a gate pad 400 and an antenna structure 500. The gate pad 400 and the antenna structure 500 are electrically connected to the gate structure 210 of the transistor 200 through the plurality of metal layers 300 and conductive plugs 20 located between adjacent metal layers 300. Therefore, the antenna structure 500 and the gate pad 400 can collect free charges generated during the manufacturing of the top metal layer 310. Since they are electrically connected to the gate structure, when the charge accumulates to a certain level, it may damage the gate structure (e.g., damage to the gate oxide layer included in the gate structure). By performing electrical testing on the damage to the gate structure 210, plasma-induced damage during the manufacturing of the top layer metal can be identified. This allows for monitoring of the impact of related processes on the devices corresponding to the test structure, which is beneficial for improving the yield and reliability of the manufactured chips.

[0155] The above are merely embodiments of this disclosure and do not limit the patent scope of this disclosure. Any equivalent structural or procedural transformations made using the content of this disclosure and its drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this disclosure.

[0156] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the applications disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0157] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A test structure, characterized in that, include: Base; A transistor formed on a substrate, the transistor including a gate structure; Multiple metal layers are located above the transistor, including a top metal layer; as well as The gate pad and antenna structure are formed on the top metal layer and electrically connected to the gate structure of the transistor through the plurality of metal layers and conductive plugs located between adjacent metal layers.

2. The test structure according to claim 1, characterized in that, The test structure also includes: A passivation layer, located above the plurality of metal layers, includes at least one of a first opening exposing a gate pad and a second opening exposing an antenna structure.

3. The test structure according to claim 1 or 2, characterized in that, The test structure also includes: A dielectric layer is located between adjacent metal layers of the plurality of metal layers; The conductive plug is located in a via of the dielectric layer.

4. The test structure according to claim 3, characterized in that, The transistor further includes a source structure and a drain structure, and the test structure further includes: A source pad is formed in any one of the plurality of metal layers and is electrically connected to the source structure through at least one of the plurality of metal layers; and The drain pad is formed in any one of the plurality of metal layers and is electrically connected to the drain structure through at least one of the plurality of metal layers.

5. The test structure according to claim 4, characterized in that, The test structure also includes: The substrate pad is formed in any one of the plurality of metal layers and is electrically connected to the substrate through at least one of the plurality of metal layers.

6. The test structure according to claim 3, characterized in that, The dielectric layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a low-k dielectric layer.

7. The test structure according to claim 1 or 2, characterized in that, The gate structure includes: A gate oxide layer is located on the substrate; and A gate layer is located on the surface of the gate oxide layer.

8. The test structure according to claim 7, characterized in that, The thickness of the gate oxide layer is 1 nm to 20 nm.

9. The test structure according to claim 7, characterized in that, The gate layer includes: Gate polysilicon layer; and, A gate metal layer is located on the surface of the gate polysilicon layer.

10. A method for manufacturing a test structure, characterized in that, include: A substrate is provided on which a transistor is formed, the transistor including a gate structure; Multiple metal layers are formed above the transistor; The plurality of metal layers include a top metal layer, which includes a gate pad and an antenna structure. The gate pad and the antenna structure are electrically connected to the gate structure of the transistor through the plurality of metal layers and conductive plugs located between adjacent metal layers.

11. The method according to claim 10, characterized in that, The method further includes: A passivation layer is formed over the plurality of metal layers, the passivation layer including at least one of a first opening exposing a gate pad and a second opening exposing an antenna structure.

12. The method according to claim 10 or 11, characterized in that, The method further includes: A dielectric layer is formed between adjacent metal layers of multiple metal layers; The conductive plug is located in a via of the dielectric layer.

13. The method according to claim 12, characterized in that, The transistor further includes a source structure and a drain structure; Each of the plurality of metal layers includes a source pad, and the source pad is electrically connected to the source structure through at least one of the plurality of metal layers. as well as The plurality of metal layers includes a drain pad, which is electrically connected to the drain structure through at least one of the plurality of metal layers.

14. The method according to claim 13, characterized in that, Each of the plurality of metal layers includes a substrate pad, which is electrically connected to the substrate through at least one of the plurality of metal layers.

15. The method according to claim 12, characterized in that, The dielectric layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and a low-k dielectric layer.

16. The method according to claim 10 or 11, characterized in that, The gate structure includes: A gate oxide layer is located on the substrate; and A gate layer is located on the surface of the gate oxide layer.

17. The method according to claim 16, characterized in that, The thickness of the gate oxide layer is 1 nm to 20 nm.

18. The method according to claim 16, characterized in that, The gate layer includes: Gate polysilicon layer; and, A gate metal layer is located on the surface of the gate polysilicon layer.

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