A three-level hybrid isolated DC-DC converter

Abstract

This invention discloses a three-level hybrid isolated DC-DC converter, belonging to the field of power electronics, comprising: a three-level unit, an isolation unit, and a control unit; the three-level unit adopts a three-level half-bridge topology, and the isolation unit adopts an isolated full-bridge topology; the midpoint of the three-level half-bridge topology is connected to the midpoint of the full-bridge on the primary side of the isolated full-bridge topology through a first inductor L1; an input capacitor C is connected in parallel on the input side of the three-level unit. in An intermediate capacitor C is connected in parallel on both the input and output sides of the isolation unit. m Output capacitor C o The control unit is used to control the three-level hybrid isolated DC-DC converter using a two-level modulation method when the voltage of the input three-level unit is less than the set value; otherwise, it controls the three-level hybrid isolated DC-DC converter using a three-level modulation method. This enables a wider gain adjustment range and soft-switching range, making it suitable for applications with wide voltage variations, such as photovoltaic systems, energy storage batteries, and electric vehicle chargers.

Description

Technical Field

[0001] This invention belongs to the field of power electronics, and more specifically, relates to a three-level hybrid isolated DC-DC converter. Background Technology

[0002] With the goal of carbon neutrality being set, the penetration rate of renewable energy power generation is increasing year by year. Photovoltaic power generation, as an important form of renewable energy power generation, has been vigorously promoted. However, the output voltage of photovoltaic power generation is greatly affected by environmental factors such as light intensity and temperature, resulting in a large range of output voltage fluctuations. Centralized photovoltaic power plants often use photovoltaic modules connected in series to improve power generation efficiency; however, this series connection leads to a higher peak output voltage, further expanding the output voltage range. The peak output voltage of photovoltaic power plants can typically reach over 1700V, while the minimum output voltage can reach 250V. Voltages above 1700V exceed the withstand voltage of common silicon or silicon carbide devices.

[0003] Common isolated DC-DC converters, such as dual active bridge converters, possess zero-voltage turn-on and electrical isolation characteristics. However, traditional dual active bridge converters suffer from drawbacks under wide input voltage ranges, including excessive return power and loss of zero-voltage turn-on characteristics. Furthermore, the two-level modulation design makes the switching transistors insufficient to withstand high input voltages. Therefore, designing a wide-range, high-voltage-resistance multilevel isolated converter is of significant research importance. Summary of the Invention

[0004] In view of the shortcomings of the existing technology and the need for improvement, the present invention provides a three-level hybrid isolated DC-DC converter, which aims to solve the problem of poor performance of existing isolated DC-DC converters under conditions of high input voltage and wide input voltage range.

[0005] To achieve the above objectives, the present invention provides a three-level hybrid isolated DC-DC converter, comprising: a three-level unit, an isolation unit, and a control unit; the three-level unit adopts a three-level half-bridge topology, and the isolation unit adopts an isolated full-bridge topology; the midpoint of the three-level half-bridge topology is connected to the midpoint of the full-bridge on the primary side of the isolated full-bridge topology through a first inductor L1; an input capacitor C is connected in parallel on the input side of the three-level unit. in The isolation unit has an intermediate capacitor C connected in parallel on its input side. m The isolation unit has a parallel output capacitor C connected to its output side. o The control unit is used to control the three-level hybrid isolated DC-DC converter using a two-level modulation method when the input voltage of the three-level unit is less than a set value; otherwise, it controls the three-level hybrid isolated DC-DC converter using a three-level modulation method.

[0006] Furthermore, the three-level half-bridge topology includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4 connected in sequence, and the connection point of the second switch S2 and the third switch S3 is the midpoint of the three-level half-bridge topology; the isolated full-bridge topology includes a primary-side full-bridge, a secondary-side full-bridge, and a transformer connecting the primary-side full-bridge and the secondary-side full-bridge.

[0007] Furthermore, the two-level modulation method includes: controlling the first switch S1 and the fourth switch S4 to be in the on state, controlling the second switch S2 and the third switch S3 to be alternately turned on, and controlling the three-level hybrid isolation DC-DC converter to realize the DC-DC conversion function; controlling T s1 =T s2 , among which, T s1 T s2 These are the switching cycles of the switching transistors whose switching states change in the three-level half-bridge topology and the isolated full-bridge topology, respectively.

[0008] Furthermore, the three-level modulation method includes: controlling the first switch S1 and the fourth switch S4 to conduct complementaryly, controlling the second switch S2 and the third switch S3 to conduct complementaryly, controlling the duty cycles of the first switch S1 and the second switch S2 to be the same, and the phase shift duty cycle between them to be 0.5, controlling the three-level hybrid isolation DC-DC converter to realize the DC-DC conversion function; controlling T s1 =2T s2 , among which, T s1 T s2 These are the switching cycles of the switching transistors whose switching states change in the three-level half-bridge topology and the isolated full-bridge topology, respectively.

[0009] Furthermore, the control unit is also used to: control the phase shift duty cycle between the primary side full bridge of the isolated full bridge topology and the three-level half bridge, so as to adjust the freewheeling current of the first inductor L1, such that the freewheeling current is equal to the soft-switching critical current.

[0010] Furthermore, the control unit is also configured to: control the phase shift duty cycle between the primary side full bridge of the isolated full bridge topology and the secondary side full bridge of the isolated full bridge topology, so that the output voltage of the secondary side full bridge of the isolated full bridge topology is equal to the output voltage command value.

[0011] Furthermore, the control unit is also used to: control the duty cycle of the three-level half-bridge to adjust the intermediate capacitor C. m The intermediate voltage on both sides is such that it matches the output voltage of the secondary side of the isolated full-bridge topology.

[0012] Furthermore, the three-level half-bridge topology can be a diode-clamped three-level topology, a switch-clamped three-level topology, a flying capacitor-type three-level topology, a hybrid three-level topology of clamping and flying capacitor, or a T-type three-level half-bridge topology.

[0013] Furthermore, the isolated full-bridge topology can be a dual active bridge topology, LLC resonant topology, CLLC resonant topology, CLLLC resonant topology, isolated series resonant topology, isolated parallel resonant topology, phase-shifted full-bridge topology, isolated half-bridge topology, or dual-transistor forward topology.

[0014] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0015] (1) The structure of the isolated DC-DC converter is optimized by setting a three-level structure on its input side to perform multi-level conversion, which improves the peak input voltage of the converter. Furthermore, two different modulation methods are proposed for different operating conditions to optimize its efficiency under wide input voltage conditions. It can still maintain extremely high DC-DC conversion accuracy under low input voltage conditions and reduce the voltage applied across the switching transistor under high input voltage conditions, making it suitable for high voltage applications.

[0016] (2) The proposed segmented modulation method can achieve soft switching across the entire operating range, and the current ripple does not increase significantly with the increase of voltage, making the current stress of the switching transistor relatively balanced across the entire voltage range, which is beneficial for the selection of switching transistors and the design of circuit parameters.

[0017] (3) The soft switching of the switching transistor is achieved by using the phase shift duty cycle between the three-level unit and the isolation unit. Continuous frequency conversion is not required, which improves stability and reduces the difficulty of electromagnetic compatibility design. It can achieve a wider gain adjustment range and soft switching range, and is suitable for photovoltaic systems, energy storage batteries, electric vehicle chargers and other occasions with wide voltage range changes. In addition, it maintains the simplicity of traditional control methods, without complex algorithms or large data lookup operations, and is easy to implement on digital controllers. Attached Figure Description

[0018] Figure 1 This is a topology diagram of a three-level hybrid isolated DC-DC converter provided in an embodiment of the present invention;

[0019] Figure 2A , Figure 2B , Figure 2C , Figure 2D The circuit diagrams are respectively provided in the embodiments of the present invention for the flying capacitor type three-level topology, diode clamp type three-level topology, switch clamp type three-level topology, and clamp and flying capacitor hybrid three-level topology;

[0020] Figure 3A , Figure 3B , Figure 3C The circuit diagrams are respectively provided in the embodiments of the present invention for the dual active bridge topology, LLC resonant topology, and CLLLC resonant topology;

[0021] Figure 4 The waveform diagram provided for the two-level modulation method in the embodiments of the present invention;

[0022] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E The circuit diagrams for stages I, II, III, IV, and V of the two-level modulation method provided in the embodiments of the present invention are as follows:

[0023] Figure 6 The waveform diagram provided for the use of the three-level modulation method in the embodiments of the present invention;

[0024] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E The circuit diagrams for stages I, II, III, IV, and V of the three-level modulation method provided in the embodiments of the present invention are shown. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0026] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] Figure 1 This is a topology diagram of a three-level hybrid isolated DC-DC converter provided in an embodiment of the present invention. (See also...) Figure 1 , combined Figures 2A-7E The three-level hybrid isolated DC-DC converter in this embodiment will be described in detail.

[0028] See Figure 1 The three-level hybrid isolated DC-DC converter includes: a three-level unit, an isolation unit, and a control unit (not shown in the figure).

[0029] The three-level unit adopts a three-level half-bridge topology, and the isolation unit adopts an isolation full-bridge topology; the midpoint of the three-level half-bridge topology is connected to the midpoint of the full-bridge on the original side of the isolation full-bridge topology through the first inductor L1; the input capacitor C is connected in parallel on the input side of the three-level unit. in An intermediate capacitor C is connected in parallel on the input side of the isolation unit. m The output capacitor C is connected in parallel on the output side of the isolation unit. o .

[0030] The control unit is used to control the three-level hybrid isolated DC-DC converter using a two-level modulation method when the voltage of the input three-level unit is less than a set value; otherwise, it controls the three-level hybrid isolated DC-DC converter using a three-level modulation method. This set value is designed according to the specific application scenario.

[0031] According to an embodiment of the present invention, the three-level half-bridge topology is a diode-clamped three-level topology (circuit shown in Figure 1). Figure 2B As shown), a switching transistor clamping three-level topology (circuit shown) Figure 2C As shown), flying capacitor type three-level topology (circuit as shown) Figure 2A (As shown), a hybrid three-level topology of clamping and flying capacitor (circuit shown) Figure 2D (as shown) or a T-type three-level half-bridge topology.

[0032] According to an embodiment of the present invention, the isolated full-bridge topology is a dual active bridge topology (circuit as follows). Figure 3A As shown), LLC resonant topology (circuit as shown) Figure 3B As shown), CLLC resonant topology, CLLLC resonant topology (circuit shown) Figure 3C (As shown), isolated series resonant topology, isolated parallel resonant topology, phase-shifted full-bridge topology, isolated half-bridge topology, or dual-tube forward topology.

[0033] See Figure 1 The three-level unit has three external connection points: connection point N1, connection point N2, and connection point N3. Connection point N1 is connected to the input capacitor C. in The positive terminal is connected, and the connection point N2 is connected to the input capacitor C. in The negative terminal is connected, and connection point N3 is connected to the isolation unit as the output point.

[0034] According to an embodiment of the present invention, the three-level half-bridge topology includes a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4 connected in sequence, and the connection point of the second switch S2 and the third switch S3 is the midpoint of the three-level half-bridge topology.

[0035] The transistors are connected in the following order: positive terminal of the input power supply, drain of the first switch S1, source of the first switch S1, drain of the second switch S2, source of the second switch S2, drain of the third switch S3, source of the third switch S3, drain of the fourth switch S4, source of the fourth switch S4, and negative terminal of the input power supply. The first switch S1 and the second switch S2 form the upper half-bridge, and the third switch S3 and the fourth switch S4 form the lower half-bridge. Connection point N1 is connected to the positive terminal of the bridge arm of the three-level half-bridge topology (i.e., the drain of S1); connection point N2 is connected to the negative terminal of the bridge arm of the three-level half-bridge topology (i.e., the source of S4); and connection point N3 is the connection point between the first inductor L1 and the isolation unit.

[0036] See Figure 1 The isolation unit has five external connection points: connection point P1, connection point P2, connection point P3, connection point P4, and connection point P5. Connection point P1 and the intermediate capacitor C... m The positive terminal is connected, connection point P2 is connected to connection point N3, and connection point P3 is connected to the intermediate capacitor C. m The negative terminal is connected, and the connection point P4 is connected to the output capacitor C. o The positive terminal is connected, and the connection point P5 is connected to the output capacitor C. o The negative terminal connection.

[0037] According to an embodiment of the present invention, the isolated full-bridge topology includes a primary-side full-bridge, a secondary-side full-bridge, and a transformer T connecting the primary-side full-bridge and the secondary-side full-bridge.

[0038] Connection point P1 is connected to the positive terminal of the primary side full bridge, connection point P2 is connected to the midpoint of the primary side full bridge, connection point P3 is connected to the negative terminal of the primary side full bridge, connection point P4 is connected to the positive terminal of the secondary side full bridge, and connection point P5 is connected to the negative terminal of the secondary side full bridge.

[0039] The primary-side full bridge includes the fifth switch Q1, the sixth switch Q2, the seventh switch Q3, and the eighth switch Q4. The source of the fifth switch Q1 and the drain of the sixth switch Q2 are connected to form the first half-bridge, with the intermediate capacitor C. m The first half-bridge is connected in parallel, with the midpoint of its arm connected to the first inductor L1. The midpoint of the first half-bridge arm is also connected to the intermediate inductor L2, and then to the same-name terminal of the first winding n1 of transformer T. The source of the seventh switch Q3 and the drain of the eighth switch Q4 are connected to form the second half-bridge, with the midpoint of its arm connected to the non-same-name terminal of the first winding n1 of transformer T. The sources of the fourth switch S4, the sixth switch Q2, and the eighth switch Q4 are connected; the drain of the fifth switch Q1 and the drain of the seventh switch Q3 are connected.

[0040] The secondary-side full bridge includes the ninth switch Q5, the tenth switch Q6, the eleventh switch Q7, and the twelfth switch Q8. The source of the ninth switch Q5 and the drain of the tenth switch Q6 are connected to form the third half-bridge, and the source of the eleventh switch Q7 and the drain of the twelfth switch Q8 are connected to form the fourth half-bridge. The midpoint of the bridge arm of the third half-bridge is connected to the same-name terminal of the second winding n2 of transformer T, and the midpoint of the bridge arm of the fourth half-bridge is connected to the non-same-name terminal of the second winding n2 of transformer T. The drain of the ninth switch Q5 and the drain of the eleventh switch Q7 are connected, and the source of the tenth switch Q6 and the source of the twelfth switch Q8 are connected.

[0041] by Figure 2A The flying capacitor three-level topology shown in the figure and Figure 3A Taking the dual active bridge topology shown in the figure as an example, the circuit structure of the three-level unit and the isolation unit in this embodiment is explained.

[0042] See Figure 2A The circuit of the three-level unit includes an upper half-bridge, a lower half-bridge, a first inductor L1, and a flying capacitor C. f Input capacitor C in Parallel to a three-level half-bridge; flying capacitor C f The positive terminal is connected to the midpoint of the upper half-bridge, and the flying capacitor C... f The negative terminal is connected to the midpoint of the lower half-bridge.

[0043] See Figure 3A For the isolation unit, the two ends of its secondary side full bridge are used as output terminals, and an output filter capacitor C is connected in parallel. o The intermediate capacitor C is connected in parallel across both ends of the original side of the full bridge. m The isolation unit also includes a high-frequency link, which consists of a second inductor L2 and a transformer T. The midpoint of the first half-bridge of the primary-side full bridge is connected to the second inductor L2 and then to the same-name terminal of the first winding n1 of the transformer T.

[0044] In this embodiment, the control unit uses a segmented modulation method and / or a closed-loop control method to control each switching transistor. The segmented modulation method refers to: when the per-unit input voltage is small (e.g., less than 1.66), a two-level modulation method is used; when the per-unit input voltage is large (e.g., greater than 1.66), a three-level modulation method is used.

[0045] According to an embodiment of the present invention, the two-level modulation method includes: controlling the first switch S1 and the fourth switch S4 to be in the on state, controlling the second switch S2 and the third switch S3 to be alternately turned on, and controlling the three-level hybrid isolation DC-DC converter to realize the DC-DC conversion function; controlling T s1 =T s2 , among which, T s1 T s2These represent the switching cycles of the switching transistors whose switching states change in a three-level half-bridge topology and an isolated full-bridge topology, respectively.

[0046] According to an embodiment of the present invention, the three-level modulation method includes: controlling the first switch S1 and the fourth switch S4 to conduct complementaryly, controlling the second switch S2 and the third switch S3 to conduct complementaryly, controlling the duty cycles of the first switch S1 and the second switch S2 to be the same and the phase shift duty cycle between them to be 0.5, controlling the three-level hybrid isolation DC-DC converter to realize the DC-DC conversion function; controlling T s1 =2T s2 , among which, T s1 T s2 These represent the switching cycles of the switching transistors whose switching states change in a three-level half-bridge topology and an isolated full-bridge topology, respectively.

[0047] In three-level modulation, Q1 and Q2 conduct complementaryly, Q3 and Q4 conduct complementaryly, Q5 and Q6 conduct complementaryly, and Q7 and Q8 conduct complementaryly. There is a certain dead time between the drive pulses of the complementary conducting switching transistors.

[0048] The control unit is also used to: control the phase shift duty cycle between the primary side of the isolated full-bridge topology and the three-level half-bridge, so as to adjust the freewheeling current i of the first inductor L1. fw This causes the freewheeling current i fw Equal to the soft-switching critical current I ZVS .

[0049] The control unit is also used to: control the phase shift duty cycle between the primary side of the isolated full-bridge topology and the secondary side of the isolated full-bridge topology, so as to adjust the output voltage V of the secondary side of the isolated full-bridge topology. o Equal to the output voltage command value V oref .

[0050] The control unit is also used to: control the duty cycle of the three-level half-bridge to adjust the intermediate capacitor C. m The intermediate voltage V on both sides m This makes the intermediate voltage V m The output voltage V of the full bridge on the secondary side of the isolated full bridge topology o Matching, that is, satisfying V m / V o = n1 / n2.

[0051] In this embodiment, the duty cycle of the primary-side full bridge refers to the duty cycle of Q1 and Q3; the duty cycle of the secondary-side full bridge refers to the duty cycle of Q5 and Q7; the phase-shifting duty cycle D1 between the primary-side full bridge and the three-level half-bridge refers to the phase-shifting duty cycle of the turn-on time of Q1 relative to the turn-on time of S3; the phase-shifting duty cycle D2 between the secondary-side full bridge and the primary-side full bridge refers to the phase-shifting duty cycle of the turn-on time of Q5 relative to the turn-on time of Q7; the phase-shifting duty cycle refers to the ratio of the difference in turn-on time to the switching cycle of the dual active bridge.

[0052] by Figure 1 The diagram illustrates the working process of the three-level hybrid isolation DC-DC converter in this embodiment, using the example of a flying capacitor three-level topology for the three-level unit and a dual active bridge topology for the isolation unit.

[0053] When operating in the two-level modulation method, the typical operating waveform is as follows: Figure 4 As shown, there are 5 operating stages within half a switching cycle of the dual active bridge. Due to symmetry, the boost and buck processes of the converter are similar; this embodiment uses the boost mode as an example for analysis. To simplify the analysis, it is assumed that the transformer turns ratio n1 / n2 = N = 1. The operational analysis of each operating stage is as follows.

[0054] Phase I [t0-t1]: such as Figure 5A As shown, before time t0, the current of L1 is negative and the current of L2 is positive. At time t0, S2 of the three-level half-bridge is off and S3 is on; Q2 and Q3 of the primary-side full-bridge are on as zero-voltage switches (ZVS), and Q1 and Q4 are off; the current of L1 is approximately constant and freewheels through S3, S4, and Q2; correspondingly, Q5 and Q8 of the secondary-side full-bridge are on, and Q6 and Q7 are off. As time progresses, the current of L2 decreases linearly. During this stage, the current of L2 is expressed as:

[0055] i L2 (t)=i L2 (t0)-(V m +Vo / N)(t-t0) / L2

[0056] Phase II [t1-t2]: such as Figure 5B As shown, at time t1, the switching states of the three-level half-bridge and the primary-side full-bridge are the same as in stage I. The current of L2 decreases linearly and then reverses. Q5 and Q8 are turned off. This stage is the dead time of Q5 and Q6, as well as Q7 and Q8. The current of the secondary winding n2 freewheels through the body diodes of Q6 and Q7, providing the conditions for ZVS of Q6 and Q7.

[0057] Phase III [t2-t3]: such as Figure 5CAs shown, at time t2, the switching states of the three-level half-bridge and the primary-side full-bridge are the same as in stage II. Q6 and Q7 are turned on with ZVS. L1 Keeping it approximately constant, the voltage across L2 is 0, i L2 Approximately constant. The primary winding n1 transfers power to the secondary winding n2 through L2.

[0058] Phase IV [t3-t4]: such as Figure 5D As shown, at time t3, the switching states of the primary and secondary full-bridge circuits are the same as in stage III. S3 of the three-level half-bridge is turned off. This stage is the dead time of S2 and S3, and the current in L1 freewheels through the body diode of S2, providing the conditions for ZVS of S2.

[0059] Stage V[t4-t5]: As shown in E of Figure 5, at time t4, the switching states of the primary and secondary full-bridge circuits are the same as in Stage III. S2 of the three-level half-bridge is turned on with ZVS. L1 is controlled by voltage V. in Linear current, i L1 The voltage increases linearly. The voltage across L2 is 0, i L2 It is approximately constant. During this stage, the current in L1 is expressed as:

[0060] i L1 (t)=i L1 (t4)+V in (t-t4) / L1

[0061] When operating in the three-level modulation method, the typical operating waveform is as follows: Figure 6 As shown, there are 5 operating stages within half a switching cycle of the dual active bridge. Due to symmetry, the boost and buck processes of the converter are similar; this embodiment takes the boost mode as an example for analysis. To simplify the analysis, it is assumed that the transformer turns ratio n1 / n2 = N = 1. The operational analysis of each stage is as follows.

[0062] Phase I [t0-t1]: such as Figure 7A As shown, before time t0, the current of L1 is negative and the current of L2 is positive. At time t0, S1 and S2 of the three-level half-bridge are off, S3 and S4 are on; Q2 and Q3 of the primary side full-bridge are on as zero-voltage switches, and Q1 and Q4 are off; the current of L1 is approximately constant and freewheels through S3, S4 and Q2; correspondingly, Q5 and Q8 of the secondary side full-bridge are on, and Q6 and Q7 are off. With time, the current of L2 decreases linearly. During this stage, the current of L2 is expressed as:

[0063] i L2 (t)=i L2 (t0)-(V m +Vo / N)(t-t0) / L2

[0064] Phase II [t1-t2]: such as Figure 7B As shown, at time t1, the switching states of the three-level half-bridge and the primary-side full-bridge are the same as in stage I. The current of L2 decreases linearly and then reverses. Q5 and Q8 are turned off. This stage is the dead time of Q5 and Q6, as well as Q7 and Q8. The current of the secondary winding n2 freewheels through the body diodes of Q6 and Q7, providing the conditions for ZVS of Q6 and Q7.

[0065] Phase III [t2-t3]: such as Figure 7C As shown, at time t2, the switching states of the three-level half-bridge and the primary-side full-bridge are the same as in stage II. Q6 and Q7 are turned on with ZVS. L1 Keeping it approximately constant, the voltage across L2 is 0, i L2 Approximately constant. The primary winding n1 transfers power to the secondary winding n2 through L2.

[0066] Phase IV [t3-t4]: such as Figure 7D As shown, at time t3, the switching states of the primary and secondary full-bridge circuits are the same as in stage III. S4 of the three-level half-bridge is turned off. This stage is the dead time of S1 and S4, and the current in L1 freewheels through the body diode of S1, which provides the conditions for ZVS of S1.

[0067] Stage V[t4-t5]: such as Figure 7E As shown, at time t4, the switching states of the primary and secondary full-bridge circuits are the same as in stage III. S1 of the three-level half-bridge is ZVS enabled. L1 is controlled by voltage V. in Linear current, i L1 The voltage increases linearly. The voltage across L2 is 0, i L2 It is approximately constant. During this stage, the current in L1 is expressed as:

[0068] i L1 (t)=i L1 (t4)+V in (t-t4) / 2L1

[0069] contrast Figure 4 and Figure 6 As can be seen, when the input voltage doubles, the three-level modulation method still ensures that the current flowing through the switching transistor maintains its original variation and magnitude, giving the converter higher voltage withstand capability. When the input voltage is low, a two-level modulation method is used to ensure the converter's conversion accuracy under low input voltage conditions.

[0070] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A three-level hybrid isolated DC-DC converter, characterized in that, include: Three-level unit, isolation unit, and control unit; The three-level unit adopts a three-level half-bridge topology, and the isolation unit adopts an isolation full-bridge topology. The isolation full-bridge topology includes a primary-side full-bridge, a secondary-side full-bridge, and a transformer connecting the primary-side and secondary-side full-bridges. The midpoint of the three-level half-bridge topology is connected to the midpoint of the primary-side full-bridge of the isolation full-bridge topology through a first inductor L1. An input capacitor C is connected in parallel on the input side of the three-level unit. in The isolation unit has an intermediate capacitor C connected in parallel on its input side. m The isolation unit has a parallel output capacitor C connected to its output side. o ; The control unit is used to control the three-level hybrid isolated DC-DC converter using a two-level modulation method when the voltage input to the three-level unit is less than a set value; otherwise, it controls the three-level hybrid isolated DC-DC converter using a three-level modulation method. The three-level half-bridge topology includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4 connected in sequence, and the connection point between the second switch S2 and the third switch S3 is the midpoint of the three-level half-bridge topology. The two-level modulation method includes: The first switch S1 and the fourth switch S4 are controlled to be in the on state, and the second switch S2 and the third switch S3 are controlled to be turned on alternately, thereby controlling the three-level hybrid isolation DC-DC converter to realize the DC-DC conversion function. Control T s1 = T s2 , among which, T s1 T s2 These are the switching cycles of the switching transistors whose switching states change in the three-level half-bridge topology and the isolated full-bridge topology, respectively. The three-level modulation method includes: The first switch S1 and the fourth switch S4 are controlled to conduct complementaryly, the second switch S2 and the third switch S3 are controlled to conduct complementaryly, the duty cycles of the first switch S1 and the second switch S2 are the same, and the phase shift duty cycle between them is 0.5, so as to control the three-level hybrid isolation DC-DC converter to realize the DC-DC conversion function. Control T s1 = 2T s2 , among which, T s1 T s2 These are the switching cycles of the switching transistors whose switching states change in the three-level half-bridge topology and the isolated full-bridge topology, respectively.

2. The three-level hybrid isolated DC-DC converter as described in claim 1, characterized in that, The control unit is also used to: control the phase shift duty cycle between the full bridge on the primary side of the isolated full bridge topology and the three-level half bridge, so as to adjust the freewheeling current of the first inductor L1, so that the freewheeling current is equal to the soft-switching critical current.

3. The three-level hybrid isolated DC-DC converter as described in claim 1, characterized in that, The control unit is further configured to: control the phase shift duty cycle between the full bridge on the primary side of the isolated full bridge topology and the full bridge on the secondary side of the isolated full bridge topology, so that the output voltage of the full bridge on the secondary side of the isolated full bridge topology is equal to the output voltage command value.

4. The three-level hybrid isolated DC-DC converter as described in claim 1, characterized in that, The control unit is also used to: control the duty cycle of the three-level half-bridge to adjust the intermediate capacitor C. m The intermediate voltage on both sides is such that it matches the output voltage of the secondary side of the isolated full-bridge topology.

5. The three-level hybrid isolated DC-DC converter as described in claim 1, characterized in that, The three-level half-bridge topology is a diode-clamped three-level topology, a switch-clamped three-level topology, a flying capacitor three-level topology, a hybrid three-level topology of clamping and flying capacitor, or a T-type three-level half-bridge topology.

6. The three-level hybrid isolated DC-DC converter as described in claim 1, characterized in that, The isolated full-bridge topology can be a dual active bridge topology, LLC resonant topology, CLLC resonant topology, CLLLC resonant topology, isolated series resonant topology, isolated parallel resonant topology, phase-shifted full-bridge topology, isolated half-bridge topology, or dual-tube forward topology.

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