Switched capacitor circuit with comparator core

Abstract

The present disclosure provides a comparator-based switched-capacitor circuit. The comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter, a decoder, and a switched-capacitor network. The analog-to-digital converter is coupled to the first input terminal and the second input terminal, and includes a plurality of comparators. The decoder is coupled to the analog-to-digital converter. The switched-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. A voltage of the first output terminal and a voltage of the second output terminal do not exceed a target range.

Description

Technical Field

[0001] This disclosure relates to switching capacitor circuits, and more particularly to switching capacitor circuits centered around a comparator. Background Technology

[0002] Figure 1 This illustrates a conventional comparator-based switched-capacitor circuit (SC circuit) (also known as a zero-crossing-based circuit (ZCBC)). The switched-capacitor circuit 100 includes a comparator 110, a current source 120, capacitors C1 and C2, a load capacitor CL, and a switch SW. The switched-capacitor circuit 100 can be used to derive various circuits, such as a pipelined analog-to-digital converter (ADC) or a multiplying digital-to-analog converter (DAC).

[0003] Comparator 110 compares the voltage Vx at the positive input terminal with the reference voltage Vcm at the negative input terminal to generate a control signal Dc0. The control signal Dc0 controls the output current of the current source 120, thereby controlling the magnitude of the output voltage Vo (i.e., the terminal voltage of the load capacitor CL). When the switch SW is turned on, the output voltage Vo is reset to the power supply voltage VDD.

[0004] The current source 120 is typically implemented using a metal-oxide-semiconductor field-effect transistor (MOSFET), and the output voltage Vo is the drain voltage of this transistor. However, because the drain-source current (Ids, i.e., the output current of the current source 120) is dependent on the drain-source voltage (Vds), the output current of the current source 120 is affected by the output voltage Vo, resulting in a decrease in the linearity of the switching capacitor circuit 100. Summary of the Invention

[0005] In view of the shortcomings of the prior art, one object of this disclosure is to provide a switching capacitor circuit with a comparator as its core, so as to improve the shortcomings of the prior art.

[0006] One embodiment of this disclosure provides a comparator-based switching capacitor circuit. This comparator-based switching capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes: a comparator, an analog-to-digital converter (ADC), a decoder, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, a first current source, a second current source, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The ADC is coupled to the first input terminal and the second input terminal. The decoder is coupled to the ADC. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The first capacitor has a first terminal and a second terminal; the first terminal is coupled to the first input terminal via the first switch and to the first output terminal via the fourth switch; the second terminal is coupled to the comparator and to a reference voltage via the third switch. The second capacitor has a third terminal and a fourth terminal. The third terminal is coupled to the first input terminal via the second switch and to the decoder via the fifth switch. The fourth terminal is coupled to the comparator and to the reference voltage via the third switch. The third capacitor has a fifth terminal and a sixth terminal. The fifth terminal is coupled to the second input terminal via the sixth switch and to the second output terminal via the ninth switch. The sixth terminal is coupled to the comparator and to the reference voltage via the eighth switch. The fourth capacitor has a seventh terminal and an eighth terminal. The seventh terminal is coupled to the second input terminal via the seventh switch and to the decoder via the tenth switch. The eighth terminal is coupled to the comparator and to the reference voltage via the eighth switch.

[0007] The technical means embodied in the embodiments of this disclosure can improve at least one of the disadvantages of the prior art, and therefore this disclosure has better linearity than the prior art.

[0008] The features, implementation, and effects of this disclosure will be described in detail below with reference to the accompanying drawings. Attached Figure Description

[0009] Figure 1 This demonstrates a conventional switching capacitor circuit with a comparator as its core.

[0010] Figure 2 This is a circuit diagram of an embodiment of a switching capacitor circuit with a comparator as its core, as disclosed in this disclosure;

[0011] Figure 3 This is a timing diagram according to an embodiment of the present disclosure;

[0012] Figure 4 This is a circuit diagram of one embodiment of the analog-to-digital converter disclosed herein;

[0013] Figure 5 The relationship between the range of the display signal Vi and the output bits of the comparator;

[0014] Figure 6 Display the truth table of the decoder;

[0015] Figure 7 Display the relationship between the output signal and signal Vi;

[0016] Figure 8 This is a circuit diagram of another embodiment of the switching capacitor circuit with a comparator as its core disclosed in this disclosure;

[0017] Figure 9 This is a circuit diagram of another embodiment of the analog-to-digital converter disclosed herein;

[0018] Figure 10 Display the relationship between the output signal and signal Vi;

[0019] Figure 11 The relationship between the range of the display signal Vi and the output bits of the comparator;

[0020] Figure 12 Display the truth table of the decoder;

[0021] Figure 13 The relationship between the output signal and signal Vi is displayed; and

[0022] Figure 14 Display the truth table of the decoder. Detailed Implementation

[0023] The technical terms used in the following description are based on the customary terms in this technical field. If this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification.

[0024] This disclosure includes a switching capacitor circuit with a comparator at its core. Since some components of the comparator-based switching capacitor circuit of this disclosure may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention.

[0025] Figure 2 This is a circuit diagram of an embodiment of a switching capacitor circuit with a comparator as its core, as disclosed herein. The switching capacitor circuit 200 includes an analog-to-digital converter 210, a decoder 220, and a switched capacitor network 230. The switching capacitor circuit 200 has a first input terminal (i.e., for receiving input signals). One end), the second input end (i.e., the end that receives the input signal) One end), the first output end (i.e., the output signal) One end) and the second output end (i.e., the output signal) (one end).

[0026] The analog-to-digital converter 210 includes multiple comparators that convert the differential input signal V in (including input signals) and The signal is compared with multiple default voltages (Vs0 to Vs6) to obtain a digital signal b. Decoder 220 provides at least one of the multiple reference voltages (Vr0 to Vr3) to switched-capacitor network 230 (more specifically, to capacitors C1a and C1b) based on digital signal b. Switched-capacitor network 230 processes the differential input signal Vr... in Sampling is performed, and the sampled signal is compared and / or processed according to the target reference voltage provided by the decoder 220 to output a differential output signal V. out (including output signals) and ).

[0027] The output signal of the capacitor circuit 200 is switched by a carefully designed analog-to-digital converter 210 and decoder 220. (i.e., the voltage at the first output terminal) and the output signal (That is, the voltage at the second output terminal) is controlled within the target range. In other words, regardless of the differential input signal V... in What is the magnitude of the differential output signal V? out It does not exceed the target range. The analog-to-digital converter 210 and decoder 220 will be described in detail below.

[0028] The switched capacitor network 230 includes a comparator 232, capacitors C0a, C1a, C0b, and C1b, switches S0a to S5a, switches S0b to S5b, current source I1, and current source I2. The reference voltage Vcm is the input signal. and The common-mode voltage. Current source I1 is coupled between switch S5a and ground voltage GND; current source I2 is coupled between power supply voltage VDD and switch S5b. In some embodiments, the capacitance values ​​of capacitors C0a, C1a, C0b, and C1b are substantially the same.

[0029] One end of the capacitor C0a is coupled to the first input terminal via the switch S0a and coupled to the first output terminal via the switch S3a, and the other end of the capacitor C0a is coupled to the comparator 232 and coupled to the reference voltage Vcm via the switch S2a. One end of the capacitor C1a is coupled to the first input terminal via the switch S1a and coupled to the decoder 220 via the switch S4a, and the other end of the capacitor C1a is coupled to the comparator 232 and coupled to the reference voltage Vcm via the switch S2a. One end of the capacitor C0b is coupled to the second input terminal via the switch S0b and coupled to the second output terminal via the switch S3b, and the other end of the capacitor C0b is coupled to the comparator 232 and coupled to the reference voltage Vcm via the switch S2b. One end of the capacitor C1b is coupled to the second input terminal via the switch S1b and coupled to the decoder 220 via the switch S4b, and the other end of the capacitor C1b is coupled to the comparator 232 and coupled to the reference voltage Vcm via the switch S2b.

[0030] The switched-capacitor circuit 200 operates alternately in a sampling phase and an operation phase. In the sampling phase, the switch S0a, the switch S1a, the switch S2a, the switch S0b, the switch S1b and the switch S2b are turned on, and the switch S3a, the switch S4a, the switch S3b and the switch S4b are turned off; in the operation phase, the switch S3a, the switch S4a, the switch S3b and the switch S4b are turned on, and the switch S0a, the switch S1a, the switch S2a, the switch S0b, the switch S1b and the switch S2b are turned off.

[0031] Figure 3 is a timing diagram according to an embodiment of the present disclosure. The sampling phase corresponds to a frequency Φ1 being at a first level (e.g., a high level), and the operation phase corresponds to a frequency Φ2 being at the first level (e.g., between time point T1 and time point T4). The operation phase includes two sub-phases: phase P and phase E. The switch S5a and the switch S5b are turned on for a preset time (T2-T1) in phase P to reset the first output terminal and the second output terminal (the switch S5a and the switch S5b are turned off at other times), then the current source I1 and the current source I2 are turned on (i.e., supply current) in phase E (between time point T2 and time point T3) to charge or discharge the load capacitor CL. The voltage V+ and the voltage V- are input voltages of the comparator 232. The comparator 232 compares the voltage V+ and the voltage V- and outputs a control signal Dc1 and a control signal Dc2. When V+≧V-, the control signal Dc1 is at a first level (e.g., a high level or logic 1) and the control signal Dc2 is at a second level (e.g., a low level or logic 0); when V+<V-, the control signal Dc1 is at the second level and the control signal Dc2 is at the first level.

[0032] The voltage V+ varies with the output signal The voltage V- varies with the output signal change. Time point T3 corresponds to the voltage reversal at the input terminal of the comparator 232 (i.e., changing from V+≧V- to V+<V-, or vice versa); that is, the current source I1 and the current source I2 are turned off (stop supplying current) at time point T3. When the current source I1 and the current source I2 are implemented with MOSFETs, the output signal and the output signal are the drain voltages of the MOSFETs.

[0033] Figure 4 is a circuit diagram of an embodiment of the analog-to-digital converter 210 of the present disclosure. The analog-to-digital converter 210 includes 7 comparators (410, 420, 430, 440, 450, 460, 470), and one end of each comparator receives the signal Vi The 7 comparators respectively compare the signal Vi with 7 default voltages (-3Vr / 4, -2Vr / 4, -Vr / 4, 0, Vr / 4, 2Vr / 4, 3Vr / 4, corresponding to Vs0 to Vs6 respectively, and in general Vr may be between 0.5VDD and VDD) to output 7 bits (b0, b1, b2, b3, b4, b5, b6). The signal Vi is divided into 8 intervals (X0, X1, X2, X3, X4, X5, X6, X7) by the 7 default voltages, Figure 5 shows the relationship between the interval of the signal Vi and the output bits of the comparators. For example, when -Vr / 4<Vi<0 (corresponding to interval X3), the digital signal b output by the analog-to-digital converter 210 is (1110000) (corresponding to b0 to b6).

[0034] Figure 6 shows the truth table of the decoder 220. When the signal Vi is located in intervals X0, X1, X2, X3, X4, X5, X6, X7, the decoder 220 respectively outputs voltages Vr, Vr / 2, 0, Vr / 2, 0, Vr / 2, 0 and -Vr / 2 to the capacitor C1a and the capacitor C1b (i.e., Figure 2 the reference voltages Vr0 to Vr3 respectively correspond to -Vr / 2, 0, Vr / 2 and Vr). In some embodiments, the decoder 220 may be implemented by a logic circuit. In the operation phase, when the output voltage of the decoder 220 changes, the output signal and will also change accordingly.

[0035] Figure 7 shows the output signal (or ) and the signal Vi. As shown in Figure 7 , the output signal (or ) only falls within the range of 0 to Vr / 2. Although the current source I1 and the current source I2 will still be affected by the output signal and output signal The impact, but because of the output signal (or The change in the current source I1 is small (i.e., it is controlled within the target range), so the current source I2 is less affected. In other words, the linearity of the switching capacitor circuit 200 is good.

[0036] Figure 8 This is a circuit diagram of another embodiment of the switching capacitor circuit with a comparator at its core disclosed herein. The switching capacitor circuit 800 includes an analog-to-digital converter 810, a decoder 820, and a switched capacitor network 830.

[0037] The analog-to-digital converter 810 functions similarly to the analog-to-digital converter 210, but the analog-to-digital converter 810 includes more comparators (corresponding to reference voltages Vs0 to Vs14, not shown in the figure), which will be described in detail below.

[0038] Decoder 820 functions similarly to decoder 220, but decoder 820 can provide more reference voltages (7 in total: Vr0 to Vr6, not shown in the figure).

[0039] Compared to the switched capacitor network 230, the switched capacitor network 830 further includes capacitors C2a, C3a, C2b, and C3b. Switch groups S1A, S1B, S4A, and S4B each include three switches; all three switches in the same switch group may be simultaneously on or off. The on / off sequences of switch groups S1A, S1B, S4A, and S4B correspond to... Figure 2 The on / off sequence of switches S1a, S1b, S4a and S4b.

[0040] One end of capacitor C1a (and capacitors C2a and C3a) is coupled to the first input terminal via switch group S1A and to decoder 820 via switch group S4A. The other end of capacitor C1a (and capacitors C2a and C3a) is coupled to comparator 232 and to reference voltage Vcm via switch S2a. One end of capacitor C1b (and capacitors C2b and C3b) is coupled to the second input terminal via switch group S1B and to decoder 820 via switch group S4B. The other end of capacitor C1b (and capacitors C2b and C3b) is coupled to comparator 232 and to reference voltage Vcm via switch S2b.

[0041] Similarly, the output signal of the capacitor circuit 800 is switched by a carefully designed analog-to-digital converter 810 and decoder 820. (i.e., the voltage at the first output terminal) and the output signal (That is, the voltage at the second output terminal) is controlled within the target range.

[0042] Figure 9 This is a circuit diagram of one embodiment of the analog-to-digital converter 810 disclosed herein. The analog-to-digital converter 810 includes 15 comparators (910, 915, 920, 925, 930, 935, 940, 945, 950, 955, 960, 965, 970, 975, 980). The 15 comparators compare the signal Vi with 15 default voltages (-14Vr / 16, -12Vr / 16, -10Vr / 16, -8Vr / 16, -6Vr / 16, -4Vr / 16, -2Vr / 16, 0, 2Vr / 16, 4Vr / 16, 6Vr / 16, 8Vr / 16, 10Vr / 16, 12Vr / 16, 14Vr / 16, corresponding to reference voltages Vs0 to Vs14 respectively) to output 15 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14).

[0043] Figure 10 Display output signal (or The relationship between the signal and Vi is defined, where signal Vi is divided into 16 intervals (X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15) by the 15 default voltages. Similar to the previous embodiment, the output signal... (or The range of ) only falls between 0 and Vr / 2. Figure 11 Display the relationship between the range of signal Vi and the output bits of the comparator. Figure 12 Display the truth table of decoder 820.

[0044] In different embodiments, the output signal (or The range of ) is controlled within other target ranges, such as -Vr / 2 to 0, for example Figure 13 As shown. Figure 14 The display corresponds to Figure 13 The truth table of the decoder 820 (reference voltages Vr0 to Vr6 correspond to -3Vr / 2, -Vr, -Vr / 2, 0, Vr / 2, Vr, 3Vr / 2 respectively).

[0045] In summary, this disclosure utilizes control output signals and This disclosure is not limited to improving the linearity of switching capacitor circuits. Figure 2 and Figure 8 In the embodiments described above, those skilled in the art can apply this disclosure to switching capacitor circuits that include more capacitors.

[0046] Please note that the shapes, sizes, and proportions of the components in the foregoing figures are merely illustrative and intended for those skilled in the art to understand this disclosure, and are not intended to limit this disclosure.

[0047] Although the embodiments of this disclosure are described above, these embodiments are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on its explicit or implicit content. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the scope of the claims in this specification.

[0048] [Symbol Explanation]

[0049] 100, 200, 800: Switching capacitor circuit

[0050] 110, 232, 410, 420, 430, 440, 450, 460, 470, 910, 915, 920, 925, 930, 935, 940, 945, 950, 955, 960, 965, 970, 975, 980: Comparators; I1, I2: Current sources

[0051] C1, C2, C0a, C1a, C0b, C1b, C2a, C3a, C2b, C3b: Capacitors

[0052] CL: Load capacitance

[0053] SW, S0a, S1a, S2a, S3a, S4a, S5a, S0b, S1b, S2b, S3b, S4b, S5b: switches

[0054] Vx, V+, V-: Voltage

[0055] Vcm: Reference voltage

[0056] Dc0, Dc1, Dc2: Control signals

[0057] Vo: Output voltage

[0058] VDD: Power supply voltage

[0059] Input signal (first input terminal)

[0060] Input signal (second input terminal)

[0061] Output signal (first output terminal)

[0062] Output signal (second output terminal)

[0063] 210, 810: Analog-to-digital converters

[0064] 220, 820: Decoder

[0065] b: Digital signal

[0066] 230, 830: Switched capacitor networks

[0067] GND: Grounding voltage

[0068] Φ1, Φ2: Frequency

[0069] P, E: Stage

[0070] T1, T2, T3, T4: Time points

[0071] b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14: bits

[0072] X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15: Interval

[0073] Vi: Signal

[0074] S1A, S4A, S1B, S4B: Switching groups

Claims

1. A switching capacitor circuit with a comparator as its core, comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, characterized in that, This comparator-based switching capacitor circuit includes: Comparator; An analog-to-digital converter, coupled to the first input terminal and the second input terminal; A decoder, the input of which is coupled to the output of the analog-to-digital converter; First switch; Second switch; The third switch; Fourth switch; Fifth switch; Sixth switch; The seventh switch; Eighth switch; Ninth switch; Tenth switch; The first current source is coupled to the first output terminal of the comparator and the first output terminal of the switching capacitor circuit; The second current source is coupled to the second output terminal of the comparator and the second output terminal of the switching capacitor circuit; A first capacitor has a first terminal and a second terminal. The first terminal is coupled to the first input terminal of the switching capacitor circuit via the first switch and to the first output terminal of the switching capacitor circuit via the fourth switch. The second terminal is coupled to the first input terminal of the comparator and to the reference voltage via the third switch. The second capacitor has a third terminal and a fourth terminal. The third terminal is coupled to the first input terminal of the switching capacitor circuit through the second switch and to the first output terminal of the decoder through the fifth switch. The fourth terminal is coupled to the first input terminal of the comparator and to the reference voltage through the third switch. The third capacitor has a fifth terminal and a sixth terminal. The fifth terminal is coupled to the second input terminal of the switching capacitor circuit via the sixth switch and to the second output terminal of the switching capacitor circuit via the ninth switch. The sixth terminal is coupled to the second input terminal of the comparator and to the reference voltage via the eighth switch. The fourth capacitor has a seventh terminal and an eighth terminal. The seventh terminal is coupled to the second input terminal of the switching capacitor circuit via the seventh switch and to the second output terminal of the decoder via the tenth switch. The eighth terminal is coupled to the second input terminal of the comparator and to the reference voltage via the eighth switch. The comparator compares the voltage at its first input terminal and the voltage at its second input terminal, and outputs a high-level first control signal and a low-level second control signal, or outputs a low-level first control signal and a high-level second control signal.

2. The switching capacitor circuit with a comparator as its core as described in claim 1, characterized in that, The analog-to-digital converter includes N comparators, outputs an N-bit digital signal where N is a positive integer, and the decoder provides a target reference voltage to the third terminal of the second capacitor or the seventh terminal of the fourth capacitor; wherein the voltage of the first output terminal and the voltage of the second output terminal do not exceed the target range.

3. The switching capacitor circuit with a comparator as its core as described in claim 2, characterized in that, N equals 7, and the analog-to-digital converter includes 7 comparators.

4. The switching capacitor circuit with a comparator as its core as described in claim 3, characterized in that, The decoder receives a first reference voltage, a second reference voltage, a third reference voltage, and a fourth reference voltage. The target reference voltage is one of the first reference voltage, the second reference voltage, the third reference voltage, and the fourth reference voltage, and one of the first reference voltage, the second reference voltage, the third reference voltage, and the fourth reference voltage is substantially 0 volts.

5. The switching capacitor circuit with a comparator as its core as described in claim 2, characterized in that, N equals 15, and the analog-to-digital converter includes 15 comparators.

6. The switching capacitor circuit with a comparator as its core as described in claim 5, characterized in that, The decoder receives a first reference voltage, a second reference voltage, a third reference voltage, a fourth reference voltage, a fifth reference voltage, a sixth reference voltage, and a seventh reference voltage. The target reference voltage is one of the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage, the sixth reference voltage, and the seventh reference voltage, and one of the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage, the sixth reference voltage, and the seventh reference voltage is substantially 0 volts.

7. The switching capacitor circuit with a comparator as its core as described in claim 2, characterized in that, The upper or lower limit of the target range is essentially 0 volts.

8. The switching capacitor circuit with a comparator as its core as described in claim 1, characterized in that, The switching capacitor circuit operates in either a first stage or a second stage; in the first stage, the first switch, the second switch, the third switch, the sixth switch, the seventh switch, and the eighth switch are turned on, while the fourth switch, the fifth switch, the ninth switch, and the tenth switch are turned off; in the second stage, the first switch, the second switch, the third switch, the sixth switch, the seventh switch, and the eighth switch are turned off, while the fourth switch, the fifth switch, the ninth switch, and the tenth switch are turned on.

9. The switching capacitor circuit with a comparator as its core as described in claim 8, characterized in that, This comparator-based switching capacitor circuit also includes: The eleventh switch is coupled between the first output terminal and the power supply voltage; and The twelfth switch is coupled between the second output terminal and the ground voltage.

10. The switching capacitor circuit with a comparator as its core as described in claim 9, characterized in that, The second phase includes a sub-phase in which the eleventh and twelfth switches are turned on.

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