A phase detector, a phase detection unit, and a delay phase-locked loop circuit.

Abstract

This invention discloses a phase detector, a phase detection unit, and a delayed phase-locked loop (PLL) circuit, including a first phase detection unit and a second phase detection unit with identical circuit structures. The first or second phase detection unit consists of a dynamic phase detection structure and a falling-edge delayed inverter. This invention uses a falling-edge delayed inverter to delay the input signal, effectively extending the width of the phase detector's output pulse, thus solving the problem of phase detection dead time. Simultaneously, when the phase difference between the reference signal and the feedback signal is small, the first and second output pulses of this invention have significant differences in width and height, effectively overcoming the static phase deviation problem caused by the mismatch between the charge pump charging and discharging currents of the delayed PLL. Furthermore, the phase detector output of this invention does not contain slow pulses, ensuring that the charge pump switch is turned off promptly and preventing the introduction of additional leakage current. This invention effectively solves the problems of phase detection dead time and static phase deviation in existing phase detectors, and has broad application prospects and market demand.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop circuit technology, and in particular to a phase detector, a phase detection unit, and a delay phase-locked loop circuit. Background Technology

[0002] The phase detector is a key circuit structure in a delay-locked loop (DLL) circuit. Its main function is to convert the phase difference between the input reference clock signal (REF) and the feedback clock signal (FB) output from the last stage of the voltage-controlled delay line (VLDL) into a pulse signal of corresponding width. The polarity of the phase difference is reflected by the output path of the pulse signal. The charge pump uses the pulse signal to control the charging (or discharging) time of the loop filter capacitor each reference clock cycle. By changing the amount of charge on the loop filter capacitor, the voltage of the loop filter capacitor is changed, thereby controlling the delay of the entire VLDL (i.e., adjusting the phase of the FB signal relative to REF), ensuring that there is no phase error between the two signals (REF and FB) input to the phase detector.

[0003] However, when the phase error between the two input signals REF and FB of the phase detector becomes small enough, the output pulse of the phase detector is too narrow to properly activate the charge pump's charging or discharging switch. Consequently, the entire system cannot respond to or adjust to this small phase difference range, which is called the phase detector dead zone. The existence of the phase detector dead zone causes the phase of the voltage-controlled delay line output signal FB of the phase detector to fluctuate randomly within the dead zone, generating significant random phase noise.

[0004] A common method to overcome phase detection dead time is to introduce a reset path into the phase detector, using the delay generated by the reset path to extend the on-time of the charge pump branch. However, the delay-locked loop circuit with the reset path requires strict matching of the charge pump's charging and discharging currents. When the difference between the charging and discharging currents is too large, the voltage across the loop filter capacitor deviates from the correct value because the amount of charge entering and exiting the loop filter capacitor is different. Consequently, the phases of REF and FB can never be aligned, resulting in a static phase deviation. Currently, there is no phase detector that simultaneously overcomes both the phase detection dead time problem and the static phase deviation problem, necessitating optimization. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a phase detector, a phase detection unit, and a delay phase-locked loop circuit, which simultaneously overcome the phase detection dead zone problem and the static phase deviation problem, thereby improving the performance of the delay phase-locked loop system.

[0006] A first aspect of the present invention provides a phase detector, comprising a first phase detector unit and a second phase detector unit with identical circuit structures; the first phase detector unit receives a reference clock signal as a first clock signal at its first input terminal, receives a feedback clock signal as a second clock signal at its second input terminal, and outputs a first pulse signal at its output terminal; the second phase detector unit receives the feedback clock signal as a first clock signal at its first input terminal, receives the reference clock signal as a second clock signal at its second input terminal, and outputs a second pulse signal at its output terminal; the first phase detector unit or the second phase detector unit is composed of a dynamic phase detector structure and a falling edge delayed inverter, wherein the first clock signal is input to the falling edge delayed inverter to form a delayed inverted signal of the first clock signal, which is then input to the dynamic phase detector structure; the first clock signal, the second clock signal, and the delayed inverted signal of the first clock signal are input to the dynamic phase detector structure, and the dynamic phase detector structure outputs a first pulse signal or a second pulse signal.

[0007] Furthermore, the dynamic phase detector structure includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

[0008] The first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are connected in series between the power supply terminal and ground; the source of the first PMOS transistor is connected to the power supply terminal, and the drain is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded.

[0009] The third PMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected in series between the power supply terminal and ground; the source of the third PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is grounded.

[0010] The fourth PMOS transistor and the fourth NMOS transistor are connected in series between the power supply terminal and ground; the source of the fourth PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is grounded.

[0011] The gates of the first PMOS transistor and the first NMOS transistor are connected to a first clock signal input; the gates of the second PMOS transistor and the second NMOS transistor are connected to a second clock signal input; the gate of the third PMOS transistor is connected to a delayed inverted signal input of the first clock signal; the gate of the third NMOS transistor is connected to the drain of the second PMOS transistor and the drain of the first NMOS transistor; the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor and establishes an electrical connection with the drain of the third PMOS transistor and the drain of the second NMOS transistor; the pulse signal output terminal of the dynamic phase detection structure is connected to the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor.

[0012] Further, the falling-edge delayed inverter includes a fifth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; the fifth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are connected in series between the power supply terminal and ground; the source of the fifth PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the fifth NMOS transistor; the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor; the first clock signal is input to the gates of the fifth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor; the source of the sixth NMOS transistor is grounded; the source and drain of the seventh NMOS transistor are grounded, and its gate is connected to the drains of the fifth PMOS transistor and the fifth NMOS transistor, forming a delayed inverted signal output of the first clock signal.

[0013] Furthermore, the fifth NMOS transistor and the sixth NMOS transistor are in a stacked structure.

[0014] Furthermore, the seventh NMOS transistor constitutes a MOS capacitor, and the capacitance value C of the MOS capacitor is calculated using the following formula:

[0015]

[0016] In the formula ε ox It is the dielectric constant of the oxide layer, t ox It is the thickness of the transistor oxide layer, and W and L are the transistor length and width of the seventh NMOS transistor, respectively;

[0017] The falling edge delay time t of the inverter delay Calculated using the following formula:

[0018]

[0019] In the formula, i is the average current of the inverter discharge with falling edge delay; V DD This refers to the supply voltage at the power supply terminal.

[0020] Furthermore, when the first clock signal lags behind the second clock signal, the pulse width t of the first pulse signal or the second pulse signal is calculated using the following formula:

[0021] t=Δt+t delay

[0022] When the first clock signal leads the second clock signal, the pulse width t of the first pulse signal or the second pulse signal is calculated using the following formula:

[0023] t = t delay -|Δt|

[0024] Where Δt represents the phase difference between the first clock signal and the second clock signal.

[0025] Furthermore, when the first clock signal lags behind the second clock signal, the pulse height V of the first pulse signal or the second pulse signal... pulse Calculated using the following formula:

[0026]

[0027] The first clock signal lags behind the second clock signal and At that time, V pulse =V DD ;

[0028] When the first clock signal leads the second clock signal, the pulse height V of the first pulse signal or the second pulse signal pulse Calculated using the following formula:

[0029]

[0030] In the formula, C B This represents the parasitic capacitance formed by the gate of the fourth PMOS transistor, the gate of the fourth NMOS transistor, the drain of the third PMOS transistor, and the drain of the second NMOS transistor. The parasitic capacitance C at the junction of the gate of the fourth PMOS transistor, the gate of the fourth NMOS transistor, the drain of the third PMOS transistor, and the drain of the second NMOS transistor. B The average current during charging or discharging; t delay,3 This indicates the time it takes for the gate level of the third NMOS transistor to change.

[0031] Furthermore, when the first clock signal is synchronized with the second clock signal, the pulse widths of the first pulse signal and the second pulse signal are t. delay When there is a phase difference of Δt between the first clock signal and the second clock signal, the pulse width difference between the first pulse signal and the second pulse signal is 2Δt, and the pulse height difference is...

[0032] The second aspect of the present invention discloses a phase detector unit, which is applied in a phase detector and includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

[0033] The first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are connected in series between the power supply terminal and ground; the source of the first PMOS transistor is connected to the power supply terminal, and the drain is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded.

[0034] The third PMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected in series between the power supply terminal and ground; the source of the third PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is grounded.

[0035] The fourth PMOS transistor and the fourth NMOS transistor are connected in series between the power supply terminal and ground; the source of the fourth PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is grounded.

[0036] The gates of the first PMOS transistor and the first NMOS transistor are connected to a first clock signal input; the gates of the second PMOS transistor and the second NMOS transistor are connected to a second clock signal input; the gate of the third PMOS transistor is connected to a delayed inverted signal input of the first clock signal; the gate of the third NMOS transistor is connected to the drain of the second PMOS transistor and the drain of the first NMOS transistor; the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor and establishes an electrical connection with the drain of the third PMOS transistor and the drain of the second NMOS transistor; the pulse signal output terminal of the dynamic phase detection structure is connected to the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor.

[0037] A third aspect of the present invention discloses a delay phase-locked loop circuit, including the phase detector described above.

[0038] The embodiments of the present invention have the following beneficial effects: The phase detector, phase detection unit, and delayed phase-locked loop circuit of the present invention use a falling-edge delayed inverter to delay the input signal, effectively extending the width of the phase detector output pulse, thereby solving the problem of phase detection dead zone; simultaneously, when the phase difference between the reference signal and the feedback signal is small, the first and second output pulses of the phase detector in the present invention have significant differences in width and height, thus effectively overcoming the static phase deviation problem caused by the mismatch of the charge pump charging and discharging current in the delayed phase-locked loop; furthermore, the phase detector output of the present invention will not have slow pulses, thereby ensuring that the charge pump switch is turned off in a timely manner and without introducing additional leakage current problems. The present invention also effectively solves the problems of phase detection dead zone and static phase deviation in existing phase detectors, and has broad application prospects and market demand.

[0039] Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of an existing delay phase-locked loop circuit.

[0042] Figure 2 This is a schematic diagram of a traditional phase detector structure that incorporates a reset path.

[0043] Figure 3 This is a schematic diagram of the phase detector in the phase detector, phase detection unit, and delay phase-locked loop circuit of the present invention.

[0044] Figure 4 This is a schematic diagram of the circuit structure of the phase detection unit in the phase detector, phase detection unit and delay phase-locked loop circuit of the present invention.

[0045] Figure 5 The simulation test results are those of a phase detector, phase detection unit and delay phase-locked loop circuit of the present invention.

[0046] Figure 6 The present invention relates to the simulation test results of the transfer characteristics of a phase detector, a phase detector unit, a delayed phase-locked loop circuit, a phase detector combined with a charge pump, and a loop filter capacitor. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0048] Reference for the structure of delay phase-locked loop circuit in the prior art Figure 1 The phase detector in a delay-locked loop (PLL) converts the phase difference between the input reference clock (REF) and the clock output (FB) of the last stage of the voltage-controlled delay line into a pulse signal of corresponding width. The polarity of the phase difference is reflected by whether the pulse signal appears on the UP path or the DN path. The charge pump uses the pulse signal UP (or DN) to control the charging (or discharging) time of the loop filter capacitor each reference clock cycle. By changing the amount of charge on the loop filter capacitor, the voltage at point Vc is changed, thereby controlling the delay of the entire voltage-controlled delay line (i.e., adjusting the phase of the FB signal relative to REF). This ensures that there is no phase error between the two signals (REF and FB) input to the phase detector, and the FB signal is exactly FB delayed by one clock cycle.

[0049] When the phase error between the two input signals of a phase detector is small enough, the output pulse of the phase detector is too narrow to properly activate the charging or discharging switch of the charge pump. Consequently, the entire system cannot respond to or adjust to this small phase difference range. This small phase deviation range is called the phase detector's dead zone. A phase detector with a dead zone will cause the phase of the voltage-controlled delay line output signal FB to randomly jitter within the dead zone, resulting in significant random phase noise in FB.

[0050] A common method to eliminate phase detection dead zones is to use a reset path. (See reference) Figure 2 The phase detector, which includes a reset path, utilizes two phase detectors with reset (i.e., ...) Figure 2 The D flip-flop (DFF in the diagram) at the RST terminal, along with an AND gate (or other logic gate), feeds the output signals UP and DN back to the reset terminal of the D flip-flop, enabling the phase detector to reset. This is because the reset path itself introduces a certain delay t. on Both UP and DN produce values ​​with equal duration and width t. on The pulse width is such that pulses of this width can open the charge and discharge switches of the subsequent charge pump. Since the UP and DN pulse widths are equal, and the charge and discharge currents of the charge pump are also equal, the amount of charge charged into and discharged from the loop filter capacitor is equal, ensuring that the voltage across the loop filter capacitor remains constant. However, when REF and FB have a pulse width of t... err When the phase error is large and the REF phase leads, since DN still has ton The pulse width of UP is t. on +t err Therefore, the charging branch of the charge pump can open t more times than the discharging branch. err The time allowed for the voltage across the loop filter capacitor to rise, thus reducing the delay time of the voltage-controlled delay line. Conversely, when REF lags behind FB, DN is wider than UP, and the pulse width of DN is t. on +t err As can be seen from the above analysis, as long as t on The design is long enough that even with a small phase deviation between the input signals REF and FB, the pulse width generated by the phase detector output, including the reset path, ensures the charge pump switch is turned on, thus overcoming the phase detection dead time problem. However, the phase detector structure with a reset path requires strict matching of the charge pump charging and discharging currents. If the charging and discharging currents are mismatched, when REF and FB have no phase error, the phase detector generates UP and DN with the same width, ensuring that the charge pump charges and discharges the capacitor for the same time. However, if the charging and discharging currents are mismatched, the amount of charge entering and leaving the loop filter capacitor will be different, further causing the voltage Vc on the loop filter capacitor to deviate from the correct value. Therefore, the phases of REF and FB can never be aligned, resulting in a static phase deviation. Static phase deviation refers to a fixed phase deviation between the two clock signals REF and FB that cannot be eliminated when the entire delay-locked loop system stabilizes, caused by undesirable factors such as mismatched charging and discharging currents of the phase detector or charge pump. Existing technologies still lack a satisfactory solution to simultaneously address the problems of static phase deviation and phase detection dead time.

[0051] To overcome the problem that existing phase detectors cannot simultaneously solve the phase detection dead zone and static phase deviation, this invention proposes a phase detector, a phase detection unit, and a delayed phase-locked loop, which greatly reduces the requirements for the charge pump charging and discharging current matching degree and improves the performance of the phase detector and the entire system.

[0052] The phase detector structure provided by this invention is as follows: Figure 3As shown, a first phase detector unit and a second phase detector unit with identical circuit structures are included. The first phase detector unit receives a reference clock signal as its first input terminal and a feedback clock signal as its second input terminal, and outputs a first pulse signal. The second phase detector unit receives the feedback clock signal as its first input terminal and the reference clock signal as its second input terminal, and outputs a second pulse signal. Each phase detector unit consists of a dynamic phase detector structure and a falling-edge delayed inverter. The first clock signal is input to the falling-edge delayed inverter to form a delayed inverted signal of the first clock signal, which is then input to the dynamic phase detector structure. The first clock signal, the second clock signal, and the delayed inverted signal of the first clock signal are input to the dynamic phase detector structure, which outputs either a first pulse signal or a second pulse signal. Figure 3 It is evident that the phase detector provided in this embodiment of the invention does not have a reset path, thus overcoming the static phase deviation problem.

[0053] In the phase detector of this embodiment, the reference clock signal is called REF, the feedback clock signal is called FB, the first pulse signal output is called UP, and the second pulse signal output is called DN.

[0054] In this embodiment, the phase detection unit is as follows: Figure 4 As shown, it consists of a falling edge delayed inverter and a dynamic phase detector structure. The dynamic phase detector structure includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the falling edge delayed inverter includes a fifth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor.

[0055] In the phase detection unit of this embodiment, the first PMOS transistor is referred to as M1, the second PMOS transistor as M2, the first NMOS transistor as M3, the third PMOS transistor as M4, the second NMOS transistor as M5, the third NMOS transistor as M6, the fourth PMOS transistor as M7, the fourth NMOS transistor as M8, the fifth PMOS transistor as M9, the fifth NMOS transistor as M10, the sixth NMOS transistor as M11, and the seventh NMOS transistor as M12; the first clock signal input is referred to as CLK1, and the second clock signal input is referred to as CLK2.

[0056] In this embodiment, M1, M2, and M3 are connected in series between the power supply terminal and ground; the source of M1 is connected to the power supply terminal, and its drain is connected to the source of M2; the drain of M2 is connected to the drain of M3; the source of M3 is grounded; M4, M5, and M6 are connected in series between the power supply terminal and ground; the source of M4 is connected to the power supply terminal, and its drain is connected to the drain of M5; the source of M5 is connected to the drain of M6; the source of M6 is grounded; M7 and M8 are connected in series between the power supply terminal and ground; the source of M7 is connected to the power supply terminal, and its drain is connected to the drain of M8; the source of M8 is grounded.

[0057] The gates of M1 and M3 are connected to the first clock signal input; the gates of M2 and M5 are connected to the second clock signal input; the gate of M4 is connected to the delayed inverted signal input of the first clock signal; the gate of M6 is connected to the drain of M2 and the drain of M3; the gate of M7 is connected to the gate of M8 and establishes an electrical connection with the drain of M4 and the drain of M5; the pulse signal output terminal of the dynamic phase detection structure is connected to the drain of M7 and the drain of M8.

[0058] In this embodiment, the falling edge delayed inverter includes M9, M10, M11, and M12; M9, M10, and M11 are connected in series between the power supply terminal and ground; the source of M9 is connected to the power supply terminal, and its drain is connected to the drain of M10; the source of M10 is connected to the drain of M11; a first clock signal is input to the gates of M9, M10, and M11; the source of M11 is grounded; the source and drain of M12 are grounded, and its gate is connected to the drains of M9 and M10 to form a delayed inverted signal output of the first clock signal.

[0059] In this embodiment, M10 and M11 are designed as a stacked structure. This increases the delay of the inverter discharge branch under dynamic conditions and reduces the static leakage current of the circuit, effectively reducing the power consumption of the phase detector. M12 is a MOS capacitor, and the source, drain, and substrate of M12 are all grounded.

[0060] The signal conversion process of the phase detector unit in this embodiment is described with the case that the phase of CLK1 lags behind that of CLK2: Let the average current of the falling edge delayed inverter discharge in the figure be... The size is determined by the dimensions of M10 and M11. When the gate-source voltage of M12 is high enough, the MOS capacitance value C is calculated by the following formula:

[0061]

[0062] In the formula ε ox It is the dielectric constant of the oxide layer, t ox is the thickness of the transistor oxide layer, and W and L are the length and width of the M12 transistor, respectively.

[0063] The delay time t of the falling edge delayed inverter delay Calculated using the following formula:

[0064]

[0065] In the formula, i is the average current of the inverter discharge with falling edge delay; V DD This refers to the supply voltage at the power supply terminal.

[0066] Assuming that CLK1 and CLK2 are both low in the initial state, then Figure 4 Point A is at a high level. When the phase of CLK1 lags behind CLK2, at t clk2 At that moment, the high level of CLK2 arrives first, M2 is turned off, M5 is turned on, and since the initial state of point A is high, M6 is also turned on. Figure 4 Point B discharges to ground to a low level through M5 and M6, and Q outputs a high level. At t cld1 At that moment, the high level of CLK1 is also reached, turning on M3, discharging point A to a low level, and turning off M6. The rising edge of CLK1 is delayed by a time t by the falling edge delay inverter composed of M9 to M12. delay The output CLK1_D then goes low, which turns on PMOS transistor M4, thereby charging node B. Figure 4 The Q pulse pulls the signal back to low level. Let Δt = t clk1 -t clk2 When CLK1 lags behind CLK2, the pulse width of the output pulse Q, i.e., the high-level duration t, is... high Calculated using the following formula:

[0067] t=Δt+t delay

[0068] The phase detector structure design in this embodiment allows for easy adjustment of W and L of M12 during the layout design stage. This ensures that the delay unit still has a suitable delay when considering layout parasitic parameters, more closely resembling the actual situation of the manufactured circuit. Therefore, even when Δt is close to 0, the generated pulse width can guarantee that the charge pump is turned on, thus effectively eliminating the phase detector dead zone problem.

[0069] When the phase of CLK1 leads that of CLK2, t clk1 When the high level of CLK1 arrives, consider the time t it takes for point A to discharge to the low level through M3. delay,3 , then t clk1 +t delay,M3 At that moment, M6 was shut down. clk2 At that moment, CLK2 reaches M5, causing M5 to open. clk1 +t delay At that time, CLK1_D causes M4 to open. This causes t delay >>t delay,3 Then, the width and height of the output pulse of the phase detector unit can be in the following two cases:

[0070] (1): t clk2 <t clk1 +t delay,3 The discharge time at point B is t. delay,3 -|Δt|, assuming the parasitic capacitance is C B Parasitic capacitance C B The average current discharged at point B is The height of the generated pulse is calculated using the following formula:

[0071]

[0072] Pulse duration t high =t delay -|Δt|.

[0073] (2): t clk1 +t delay,3 <t clk2 B cannot discharge, and the output cannot generate a pulse of a certain height.

[0074] It can be seen that when the phase of CLK1 leads CLK2, as |Δt| increases, the duration of the generated pulse decreases continuously, and its amplitude also decreases continuously.

[0075] The output pulse width height of the phase detection unit in this embodiment is represented by Table 1:

[0076] Table 1

[0077]

[0078] In this embodiment, when there is no phase difference between the two input clock signals (Δt = 0), both UP and DN can output t. delay The pulse width allows the charge pump to turn on, thus eliminating the dead zone problem of traditional phase detectors. When there is a small phase difference Δt between the two input clocks, the two output pulses UP and DN differ not only in width 2Δt but also in pulse height. This overcomes the mismatch problem inherent in charge pumps and solves the static phase deviation problem. Furthermore, the output stage composed of transistors M7 and M8 in the phase detector unit has no clock edge delay circuit, thus overcoming the slow switching speed of charge pumps.

[0079] This embodiment also discloses a phase detector unit, which is applied in a phase detector, including a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

[0080] The first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are connected in series between the power supply terminal and ground; the source of the first PMOS transistor is connected to the power supply terminal, and the drain is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded.

[0081] The third PMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected in series between the power supply terminal and ground; the source of the third PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is grounded.

[0082] The fourth PMOS transistor and the fourth NMOS transistor are connected in series between the power supply terminal and ground; the source of the fourth PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is grounded.

[0083] The gates of the first PMOS transistor and the first NMOS transistor are connected to the first clock signal input; the gates of the second PMOS transistor and the second NMOS transistor are connected to the second clock signal input; the gate of the third PMOS transistor is connected to the delayed inverted signal input of the first clock signal; the gate of the third NMOS transistor is connected to the drain of the second PMOS transistor and the drain of the first NMOS transistor; the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor and establishes an electrical connection with the drain of the third PMOS transistor and the drain of the second NMOS transistor; the pulse signal output terminal of the dynamic phase detection structure is connected to the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor.

[0084] This embodiment also discloses a delayed phase-locked loop circuit, including the phase detector described above. The content of the phase detector in this embodiment is applicable to this delayed phase-locked loop embodiment. The specific functions implemented in this delayed phase-locked loop embodiment are the same as those in the aforementioned phase detector embodiment, and the beneficial effects achieved are also the same as those achieved by the aforementioned phase detector.

[0085] Figure 5 The embodiment of the present invention combines a phase detector with a charge pump and a loop filter capacitor, as shown in the figure. Figure 1 The simulation test results of the transmission characteristics of the delay-locked loop circuit shown are presented. In this embodiment, the circuit design and simulation were performed using SMIC's standard 0.18-micron CMOS process. Figure 5 As shown in (a), the clock signal REF is led by one nanosecond over the UP signal. Then, the output waveforms of UP and DN are observed. It can be seen that UP has a relatively wide pulse, while DN has no pulse. Figure 5As shown in (b), when the clock signal REF leads the UP signal by 10 ps, ​​it can be seen that under a relatively small phase error, the UP signal still has a relatively wide pulse, while the DN signal has no effective pulse. This indicates that the phase detector can still effectively distinguish the phase error between REF and DN; Figure 5 As shown in (c), by further leading the clock signal REF by as little as one picosecond before the UP signal, it can be observed that the output UP and DN pulses differ not only in width but also in pulse height. This significantly improves the phase detector's ability to distinguish very small phase errors and effectively avoids static phase deviations caused by mismatched charge pump charging and discharging currents. Figure 5 As shown in (d), the clock signal REF lags the UP signal by one picosecond, and the width and height of the output pulse DN are both greater than UP. The output result is the same as... Figure 5 (c) is the opposite, indicating that the phase detector's output can correctly reflect the polarity of the phase deviation whether the phase is leading or lagging.

[0086] To verify the phase detector's characteristics of having no dead-zone and effectively eliminating static phase deviation, the phase detector was connected to a charge pump and a 2pF loop filter capacitor C. A circuit simulation environment was set up, and the performance of the phase detector was simulated using circuit simulation software. The change in the output voltage Vc during each phase detection cycle was observed and plotted as follows: Figure 6 The curve shows that when the phase difference is close to 0, the curve still has a certain slope and passes through the origin, indicating that the combination of phase detector and charge pump in this embodiment has neither a phase detection dead zone nor a static phase deviation problem.

[0087] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0088] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the described functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0089] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0090] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0091] The above is a detailed description of the preferred embodiments of the present invention, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A phase detector, characterized in that, It includes a first phase detection unit and a second phase detection unit with the same circuit structure; the first phase detection unit inputs a reference clock signal as a first clock signal at its first input terminal, inputs a feedback clock signal as a second clock signal at its second input terminal, and outputs a first pulse signal at its output terminal. The second phase detector unit receives a feedback clock signal as a first clock signal at its first input terminal, a reference clock signal as a second clock signal at its second input terminal, and outputs a second pulse signal at its output terminal. The first phase detection unit or the second phase detection unit consists of a dynamic phase detection structure and a falling edge delayed inverter. The first clock signal is input to the falling edge delayed inverter to form a delayed inverted signal of the first clock signal, which is then input to the dynamic phase detection structure. The first clock signal, the second clock signal, and the delayed inverted signal of the first clock signal are input to the dynamic phase detection structure, and the dynamic phase detection structure outputs a first pulse signal or a second pulse signal. The dynamic phase detection structure includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are connected in series between the power supply terminal and ground; the source of the first PMOS transistor is connected to the power supply terminal, and the drain is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded. The third PMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected in series between the power supply terminal and ground; the source of the third PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is grounded. The fourth PMOS transistor and the fourth NMOS transistor are connected in series between the power supply terminal and ground; the source of the fourth PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is grounded. The gates of the first PMOS transistor and the first NMOS transistor are connected to a first clock signal input; the gates of the second PMOS transistor and the second NMOS transistor are connected to a second clock signal input; the gate of the third PMOS transistor is connected to a delayed inverted signal input of the first clock signal; the gate of the third NMOS transistor is connected to the drain of the second PMOS transistor and the drain of the first NMOS transistor; the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor and establishes an electrical connection with the drain of the third PMOS transistor and the drain of the second NMOS transistor; the pulse signal output terminal of the dynamic phase detection structure is connected to the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor.

2. A phase detector according to claim 1, characterized in that, The falling-edge delayed inverter includes a fifth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The fifth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are connected in series between the power supply terminal and ground. The source of the fifth PMOS transistor is connected to the power supply terminal, and its drain is connected to the drain of the fifth NMOS transistor. The source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor. The first clock signal is input to the gates of the fifth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor. The source of the sixth NMOS transistor is grounded. The source and drain of the seventh NMOS transistor are grounded, and its gate is connected to the drains of the fifth PMOS transistor and the fifth NMOS transistor, forming a delayed and inverted output of the first clock signal.

3. A phase detector according to claim 2, characterized in that, The fifth and sixth NMOS transistors are stacked.

4. A phase detector according to claim 2, characterized in that, The seventh NMOS transistor forms a MOS capacitor, and the capacitance value C of the MOS capacitor is calculated using the following formula: In the formula It is the dielectric constant of the oxide layer. It is the thickness of the transistor oxide layer, and W and L are the transistor length and width of the seventh NMOS transistor, respectively; The falling edge delay time of the inverter Calculated using the following formula: In the formula V is the average current of the inverter discharge with a falling edge delay. DD This refers to the supply voltage at the power supply terminal.

5. A phase detector according to claim 4, characterized in that, When the first clock signal lags behind the second clock signal, the pulse width t of the first pulse signal or the second pulse signal is calculated using the following formula: When the first clock signal leads the second clock signal, the pulse width t of the first pulse signal or the second pulse signal is calculated using the following formula: Where Δt represents the phase difference between the first clock signal and the second clock signal.

6. A phase detector according to claim 5, characterized in that, When the first clock signal lags behind the second clock signal, the pulse height V of the first pulse signal or the second pulse signal pulse Calculated using the following formula: The first clock signal lags behind the second clock signal and At that time, V pulse =V DD ; When the first clock signal leads the second clock signal, the pulse height V of the first pulse signal or the second pulse signal pulse Calculated using the following formula: In the formula, C B This represents the parasitic capacitance formed by the gate of the fourth PMOS transistor, the gate of the fourth NMOS transistor, the drain of the third PMOS transistor, and the drain of the second NMOS transistor. The parasitic capacitance C at the junction of the gate of the fourth PMOS transistor, the gate of the fourth NMOS transistor, the drain of the third PMOS transistor, and the drain of the second NMOS transistor. B The average current during charging or discharging; This indicates the time it takes for the gate level of the third NMOS transistor to change.

7. A phase detector according to claim 6, characterized in that, When the first clock signal is synchronized with the second clock signal, the pulse widths of the first pulse signal and the second pulse signal are: ; When there is a Δt between the first clock signal and the second clock signal ( When the phase difference is ), the pulse width difference between the first pulse signal and the second pulse signal is 2Δt, and the pulse height difference is... .

8. A phase detection unit, used in a phase detector, characterized in that, It includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are connected in series between the power supply terminal and ground; the source of the first PMOS transistor is connected to the power supply terminal, and the drain is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded. The third PMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected in series between the power supply terminal and ground; the source of the third PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is grounded. The fourth PMOS transistor and the fourth NMOS transistor are connected in series between the power supply terminal and ground; the source of the fourth PMOS transistor is connected to the power supply terminal, and the drain is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is grounded. The gates of the first PMOS transistor and the first NMOS transistor are connected to a first clock signal input; the gates of the second PMOS transistor and the second NMOS transistor are connected to a second clock signal input; the gate of the third PMOS transistor is connected to a delayed inverted signal input of the first clock signal; the gate of the third NMOS transistor is connected to the drain of the second PMOS transistor and the drain of the first NMOS transistor; the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor and establishes an electrical connection with the drain of the third PMOS transistor and the drain of the second NMOS transistor; the pulse signal output terminal of the dynamic phase detection structure is connected to the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor.

9. A delay phase-locked loop circuit, characterized in that, Includes the phase detector as described in any one of claims 1-7.

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