SRIO communication method and system based on FPGA and FPGA

Abstract

This invention discloses an FPGA-based SRIO communication method, system, and FPGA. The method includes: acquiring flow control data; adding routing information and memory addresses to the flow control data, and dividing the flow control data into packets according to the maximum SRIO transmission packet payload to obtain multiple sub-data packets with consecutive memory addresses; sending the multiple sub-data packets to a distribution module, and sending a packet interrupt signal to the distribution module after each transmission of multiple sub-data packets with a total length equal to a preset interrupt length; the distribution module distributing all sub-data packets and all packet interrupt signals to multiple SRIO controllers; and the multiple SRIO controllers packaging all sub-data packets and all packet interrupt signals into a three-layer data format and sending it to a host computer. The FPGA-based SRIO communication method of this invention not only increases SRIO data bandwidth but also simplifies host computer operation by eliminating the need for data splicing.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to an FPGA-based SRIO communication method, system, and FPGA. Background Technology

[0002] SRIO is a next-generation high-speed interconnect technology based on packet switching, offering high reliability and performance for embedded system development. It's a serial RapidIO interface for serial backplane, DSP, and related serial data plane connections. It comprises a three-layer protocol: physical layer, transport layer, and logic layer. In the communications field, besides interconnection between SRIO networks, there are various other data communication methods that convert various interfaces to SRIO interfaces. FPGAs, as programmable logic devices, offer greater convenience for protocol conversion across different interfaces.

[0003] Currently, implementing SRIO communication with other interfaces in FPGAs involves first converting front-end data into the SRIO protocol data format, adding a DMA address, and then packaging it into a three-layer data packet format via the SRIO controller. The data is then written to the host computer's memory via the SRIO transmission network. After each fixed-length data or data frame is written, a DOORBELL interrupt signal is sent to trigger an interrupt on the host computer to notify of data arrival. However, when the front-end data source bandwidth exceeds the SRIO interface bandwidth, the device's buffer module overflows, leading to data loss. Therefore, when encountering a data source bandwidth exceeding the SRIO interface bandwidth, the usual approach is to reduce the front-end data source bandwidth or use other faster communication interfaces. This limitation on front-end data source bandwidth also restricts the widespread application of the SRIO interface. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes an FPGA-based SRIO communication method that uses multiple SRIO interfaces to implement DMA communication, which can increase SRIO data bandwidth and eliminate the need for data splicing by the host computer, thus simplifying host computer operation.

[0005] The present invention also provides an FPGA-based SRIO communication system, an FPGA, a control device, and a computer-readable storage medium.

[0006] According to a first aspect of the present invention, an FPGA-based SRIO communication method is provided, wherein the FPGA includes a data forwarding module, a distribution module, and a plurality of SRIO controllers, the bandwidth of the data forwarding module is less than the sum of the bandwidths of the plurality of SRIO controllers, and the FPGA-based SRIO communication method includes the following steps:

[0007] Obtain the flow control data output by the caching module;

[0008] Routing information and memory addresses are added to the flow control data, and the flow control data is divided into packets according to the maximum packet payload of SRIO transmission to obtain multiple sub-data packets with consecutive memory addresses. The length of each sub-data packet does not exceed the maximum packet payload of SRIO transmission.

[0009] Multiple sub-data packets are sent to the distribution module, and a packet interrupt signal is sent to the distribution module after each set of multiple sub-data packets with a total length equal to the preset interrupt length and after all sub-data packets have been sent. The distribution module then distributes all sub-data packets and all packet interrupt signals to multiple SRIO controllers in a round-robin arbitration manner, so that the multiple SRIO controllers package all sub-data packets and all packet interrupt signals into a three-layer data format and send them to the host computer. The packet interrupt signal includes the memory start address of the multiple sub-data packets with the corresponding preset interrupt length.

[0010] The FPGA-based SRIO communication method according to embodiments of the present invention has at least the following beneficial effects:

[0011] By adding routing information and memory addresses to the flow control data, and dividing the flow control data into packets based on the maximum packet payload of SRIO transmission, the flow control data can be divided into multiple sub-data packets with consecutive memory addresses. A packet interruption signal is generated after each transmission of multiple sub-data packets with a total length equal to a preset interrupt length, and after all sub-data packets have been transmitted. The packet interruption signal includes the memory start address of the corresponding multiple sub-data packets with the preset interrupt length, which can be used to notify the host computer that the data has arrived in memory. The host computer then reads the corresponding multiple sub-data packets with a total length equal to the preset interrupt length from its memory based on the memory start address, until all the sub-data packets have been read. The host computer does not need to perform data concatenation. By dividing the flow control data into multiple sub-data packets with consecutive memory addresses and using multiple SRIO interfaces to transmit single-channel front-end data, although the transmission time of different SRIO interfaces in the SRIO transmission network is inconsistent, since the memory address and sub-data packet are one-to-one, the final data arriving in the host computer's memory is also a contiguous block of memory data. If one or more SRIO paths malfunction, the malfunctioning SRIO controller will be skipped during the polling and distribution of SRIO controllers, without affecting normal communication. The FPGA-based SRIO communication method of this invention can not only increase SRIO data bandwidth, but also simplify the operation of the host computer by eliminating the need for data splicing.

[0012] According to some embodiments of the present invention, the step of dividing the flow control data into packets based on the maximum packet payload transmitted via SRIO to obtain multiple sub-data packets with consecutive memory addresses includes the following steps:

[0013] The flow control data is divided into packets every SRIO transmission maximum packet payload, resulting in multiple fixed data packets with consecutive memory addresses, each the size of the SRIO transmission maximum packet payload, and an end data packet less than or equal to the SRIO transmission maximum packet payload.

[0014] According to some embodiments of the present invention, the method further includes the following steps:

[0015] Receive all the sub-data packets and all the packet interrupt signals output by the data forwarding module;

[0016] Multiple asynchronous FIFO buffer blocks are allocated one-to-one according to the multiple SRIO controllers, and the capacity of each asynchronous FIFO buffer block is greater than the maximum packet payload of SRIO transmission.

[0017] All the sub-data packets and all the packet interrupt signals are written one-to-one into multiple asynchronous FIFO buffer blocks. All the sub-data packets and all the packet interrupt signals are read asynchronously from the multiple asynchronous FIFO buffer blocks and sent to multiple SRIO controllers.

[0018] According to some embodiments of the present invention, the step of writing all the sub-data packets and all the packet interrupt signals one-to-one into multiple asynchronous FIFO buffer blocks, asynchronously reading all the sub-data packets and all the packet interrupt signals from the multiple asynchronous FIFO buffer blocks, and sending them to multiple SRIO controllers includes the following steps:

[0019] All the sub-data packets and all the packet interrupt signals are written into multiple asynchronous FIFO buffer blocks one-to-one according to a preset first clock;

[0020] All sub-data packets and all packet interrupt signals are read from multiple asynchronous FIFO buffer blocks according to a preset second clock and sent to multiple SRIO controllers.

[0021] According to some embodiments of the present invention, the method further includes the following steps:

[0022] Receive all the sub-data packets and all the packet interrupt signals output by the distribution module;

[0023] All the sub-data packets are packaged into a three-layer structured data format to obtain multiple SRIO interface data;

[0024] All the aforementioned packetized interrupt signals are packaged into a three-layer data format to obtain multiple SRIO interrupt signals;

[0025] Multiple SRIO interface data and multiple SRIO interrupt signals are sent to the host computer via the SRIO transmission network. Each SRIO interface data is stored in the corresponding memory of the host computer according to its corresponding memory address, and each SRIO interrupt signal is sent to the processor of the host computer.

[0026] According to some embodiments of the present invention, the method further includes the following steps:

[0027] Receive multiple SRIO interrupt signals output by multiple SRIO controllers;

[0028] Based on the memory start address of each SRIO interrupt signal, read multiple SRIO interface data with a total length equal to the preset interrupt length from the memory of the host computer until all SRIO interface data has been read.

[0029] According to some embodiments of the present invention, the flow control data is obtained by the following steps:

[0030] Obtain valid data, which is obtained by decoding the original front-end data corresponding to the non-SRIO interface;

[0031] The valid data is converted into flow control data for the flow control interface, wherein the flow control interface is a data interface type supported by the SRIO controller for transmitting data.

[0032] According to a second aspect embodiment of the present invention, an FPGA-based SRIO communication system is provided, wherein the FPGA includes a data forwarding module, a distribution module, and a plurality of SRIO controllers, the bandwidth of the data forwarding module is less than the sum of the bandwidths of the plurality of SRIO controllers, and the FPGA-based SRIO communication system includes:

[0033] The flow control data acquisition unit is used to acquire the flow control data output by the cache module.

[0034] The data processing unit is used to add routing information and memory address to the flow control data, and to divide the flow control data into packets according to the maximum packet payload of SRIO transmission to obtain multiple sub-data packets with consecutive memory addresses. The length of each sub-data packet does not exceed the maximum packet payload of SRIO transmission.

[0035] A data distribution unit is used to send multiple sub-data packets to the distribution module, and after each of the multiple sub-data packets with a total length equal to a preset interrupt length is sent, and after all the sub-data packets have been sent, a packet interrupt signal is sent to the distribution module. The distribution module then distributes all the sub-data packets and all the packet interrupt signals to multiple SRIO controllers in a round-robin arbitration manner, so that the multiple SRIO controllers package all the sub-data packets and all the packet interrupt signals into a three-layer data format and send them to the host computer. The packet interrupt signal includes the memory start address of the multiple sub-data packets corresponding to the preset interrupt length.

[0036] The FPGA-based SRIO communication system according to embodiments of the present invention has at least the following beneficial effects:

[0037] By adding routing information and memory addresses to the flow control data, and dividing the flow control data into packets based on the maximum packet payload of SRIO transmission, the flow control data can be divided into multiple sub-data packets with consecutive memory addresses. A packet interruption signal is generated after each transmission of multiple sub-data packets with a total length equal to a preset interrupt length, and after all sub-data packets have been transmitted. The packet interruption signal includes the memory start address of the corresponding multiple sub-data packets with the preset interrupt length, which can be used to notify the host computer that the data has arrived in memory. The host computer then reads the corresponding multiple sub-data packets with a total length equal to the preset interrupt length from its memory based on the memory start address, until all the sub-data packets have been read. The host computer does not need to perform data concatenation. By dividing the flow control data into multiple sub-data packets with consecutive memory addresses and using multiple SRIO interfaces to transmit single-channel front-end data, although the transmission time of different SRIO interfaces in the SRIO transmission network is inconsistent, since the memory address and sub-data packet are one-to-one, the final data arriving in the host computer's memory is also a contiguous block of memory data. If one or more SRIO paths malfunction, the malfunctioning SRIO controller will be skipped during the polling and distribution of SRIO controllers, without affecting normal communication. The FPGA-based SRIO communication system of this invention can not only increase SRIO data bandwidth, but also simplify the operation of the host computer by eliminating the need for data splicing.

[0038] An FPGA according to a third aspect of the present invention includes:

[0039] The data forwarding module is used to execute the FPGA-based SRIO communication method as described in the first aspect embodiment above;

[0040] The distribution module is used to receive all the sub-data packets and all the packet interruption signals output by the data forwarding module, and distribute all the sub-data packets and all the packet interruption signals in a round-robin arbitration manner;

[0041] Multiple SRIO controllers are used to receive all the sub-data packets and all the packet interrupt signals output by the distribution module, and to package all the sub-data packets and all the packet interrupt signals into a three-layer data format and send them to the host computer; the total bandwidth of the multiple SRIO controllers is greater than the bandwidth of the data forwarding module.

[0042] The FPGA according to embodiments of the present invention has at least the following beneficial effects:

[0043] By adding routing information and memory addresses to the flow control data, and dividing the flow control data into packets based on the maximum packet payload of SRIO transmission, the flow control data can be divided into multiple sub-data packets with consecutive memory addresses. A packet interruption signal is generated after each transmission of multiple sub-data packets with a total length equal to a preset interrupt length, and after all sub-data packets have been transmitted. The packet interruption signal includes the memory start address of the corresponding multiple sub-data packets with the preset interrupt length, which can be used to notify the host computer that the data has arrived in memory. The host computer then reads the corresponding multiple sub-data packets with a total length equal to the preset interrupt length from its memory based on the memory start address, until all the sub-data packets have been read. The host computer does not need to perform data concatenation. By dividing the flow control data into multiple sub-data packets with consecutive memory addresses and using multiple SRIO interfaces to transmit single-channel front-end data, although the transmission time of different SRIO interfaces in the SRIO transmission network is inconsistent, since the memory address and sub-data packet are one-to-one, the final data arriving in the host computer's memory is also a contiguous block of memory data. If one or more SRIO paths malfunction, the malfunctioning SRIO controller will be skipped during the polling and distribution of SRIO controllers, without affecting normal communication. The FPGA in this embodiment of the invention can not only increase the SRIO data bandwidth, but also simplify the operation of the host computer by eliminating the need for data splicing.

[0044] A control device according to a fourth aspect embodiment of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the FPGA-based SRIO communication method as described in the first aspect embodiment above. Since the control device employs all the technical solutions of the FPGA-based SRIO communication method of the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments.

[0045] According to a fifth aspect embodiment of the present invention, a computer-readable storage medium stores computer-executable instructions for performing the FPGA-based SRIO communication method as described in the first aspect embodiment above. Since the computer-readable storage medium employs all the technical solutions of the FPGA-based SRIO communication method of the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments.

[0046] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0047] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0048] Figure 1 This is a system block diagram of an FPGA according to an embodiment of the present invention;

[0049] Figure 2 This is a flowchart of an FPGA-based SRIO communication method according to an embodiment of the present invention.

[0050] Figure label:

[0051] Data forwarding module 100;

[0052] Distribution module 200;

[0053] SRIO controller 300;

[0054] Host computer 400;

[0055] Cache module 500. Detailed Implementation

[0056] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0057] In the description of this invention, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order of the technical features indicated.

[0058] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the drawings and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0059] In the description of this invention, it should be noted that, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0060] The following will combine Figure 1 and Figure 2 The FPGA-based SRIO communication method of the present invention will be clearly and completely described in the following embodiments. Obviously, the embodiments described below are some embodiments of the present invention, not all embodiments.

[0061] According to a first aspect embodiment of the FPGA-based SRIO communication method, the FPGA includes a data forwarding module 100, a distribution module 200, and a plurality of SRIO controllers 300. The bandwidth of the data forwarding module 100 is less than the sum of the bandwidths of the plurality of SRIO controllers 300. The FPGA-based SRIO communication method includes the following steps:

[0062] Obtain the flow control data output by the cache module 500;

[0063] Add routing information and memory address to the flow control data, and divide the flow control data into packets according to the maximum packet payload of SRIO transmission to obtain multiple sub-data packets with consecutive memory addresses. The length of each sub-data packet does not exceed the maximum packet payload of SRIO transmission.

[0064] Multiple sub-data packets are sent to the distribution module 200. After each sub-data packet with a total length equal to the preset interrupt length is sent, and after all sub-data packets have been sent, a packet interrupt signal is sent to the distribution module 200. The distribution module 200 then distributes all sub-data packets and all packet interrupt signals to multiple SRIO controllers 300 in a round-robin arbitration manner. This allows the multiple SRIO controllers 300 to package all sub-data packets and all packet interrupt signals into a three-layer data format and send it to the host computer 400. The packet interrupt signal includes the memory start address of the corresponding multiple sub-data packets with the preset interrupt length.

[0065] After decoding the front-end data corresponding to the original non-SRIO interface, valid data is obtained. This valid data is then converted into flow control data for the flow control interface by the caching module 500. Since the bandwidth of the flow control data is greater than that of a single SRIO interface, using a single SRIO interface in this case may result in data loss. In some embodiments of this invention, the flow control interface is an AXIS interface. The data forwarding module 100, distribution module 200, and multiple SRIO controllers 300 in these embodiments all use a data flow interface with a handshake protocol, namely the AXIS interface. The SRIO controller 300 can only transmit data through the AXIS interface.

[0066] It should be noted that the flow control interface can be not only the AXIS interface, but also other interfaces with flow control. The specific interface type is determined by the relevant data of the selected FPGA and should not be regarded as a limitation of the present invention.

[0067] Furthermore, it should be noted that the cache module 500 may be part of the FPGA in this embodiment of the invention or part of an external device, and should not be regarded as a limitation of the invention.

[0068] The maximum packet payload for SRIO transmission is 256 bytes, so the data forwarding module 100 performs packet splitting every 256 bytes or at the end of the current data frame to ensure maximum transmission efficiency.

[0069] The reason for sending a packet interrupt signal to the distribution module 200 after each transmission of multiple sub-data packets with a total length equal to the preset interrupt length, and after all sub-data packets have been sent, is that an interrupt signal needs to be sent to the host computer 400 after each transmission of a certain length of data packet to notify the host computer 400 of data arrival. This allows the host computer 400 to read the corresponding SRIO interface data with a total length equal to the preset interrupt length from its memory according to the memory start address of the packet interrupt signal, until all SRIO interface data has been read. The host computer 400 does not need to perform data concatenation, which simplifies its operation. A packet interrupt signal is also sent at the end of a data frame to prevent error accumulation caused by an error in one frame. When a frame ends, it jumps to the next preset interrupt length start address instead of continuing to the current address, thus preventing error accumulation.

[0070] It should be noted that the preset interrupt length can be adjusted according to actual conditions, and is not specifically limited here. In some embodiments, if a frame of flow control data is 512KB and the preset interrupt length is 1MB, a packet interrupt signal will be triggered at the end of the frame, and the preset interrupt length will be cleared, entering the starting address of the next preset interrupt length. For example, when the length of the flow control data is 0.5M, the end of this 0.5M flow control data will trigger a packet interrupt signal, and the memory starting address of the next frame of flow control data will jump to the starting position of the second 1M, that is, the beginning of each frame is aligned with the preset interrupt length.

[0071] The interrupt triggering mechanism is based on either reaching a preset interrupt length or the end of a data frame. If they overlap, only one is used. If there are concerns about interrupts being processed too quickly, since the memory start address carried on the interrupt is spaced at the preset interrupt length, it's sufficient to observe whether the received interrupt packets are continuous to determine if an interrupt has been lost. If an interrupt is lost, data is retrieved from the preceding memory address based on the difference. If there are concerns that interrupts might arrive before data during the transmission of small data frames, a transmission type with a reply mechanism (N_WRITE for large data frames) can be used to ensure that data has been delivered before transmitting the interrupt packet. It should be noted that N_WRITE_R and N_WRITE are existing technologies known to those skilled in the art and will not be elaborated upon here.

[0072] The distribution module 200 distributes all sub-data packets and all packet interrupt signals to multiple SRIO controllers 300 using a round-robin arbitration method, which can be implemented using an asynchronous FIFO buffer block. Specifically, the following steps are included:

[0073] Receive all sub-data packets and all packet interrupt signals output by the data forwarding module 100;

[0074] Multiple asynchronous FIFO buffer blocks are allocated one-to-one according to multiple SRIO controllers 300, and the capacity of each asynchronous FIFO buffer block is greater than the maximum packet payload of SRIO transmission.

[0075] All sub-data packets and all sub-packet interrupt signals are written into multiple asynchronous FIFO buffer blocks one by one according to a preset first clock;

[0076] All sub-data packets and all packet interrupt signals are read from multiple asynchronous FIFO buffer blocks according to a preset second clock and sent to multiple SRIO controllers 300.

[0077] In some embodiments, assuming there are two SRIO interfaces, there are two SRIO controllers 300 (hereinafter referred to as SRIO_CTRL). SRIO_CTRL_0 and SRIO_CTRL_1 both have a bit width of 64 bits and a clock speed of 125 MHz. The two asynchronous FIFO buffers in the distribution module 200 operate at 64 bits * 250 MHz for writing and 64 bits * 125 MHz for reading. This ensures that when writing a sub-data packet to the first asynchronous FIFO buffer and switching to the second asynchronous FIFO buffer, the first asynchronous FIFO buffer has not yet finished reading. The second asynchronous FIFO buffer finishes writing, and the first asynchronous FIFO buffer finishes reading, allowing writing to continue without overflow. Data read from the asynchronous FIFO buffer goes directly to the corresponding SRIO_CTRL. Furthermore, since the memory addresses of the sub-data packets are contiguous, when an SRIO_CTRL is not working, polling will skip that asynchronous FIFO buffer, preventing packet loss.

[0078] It should be noted that the specific values ​​of the first clock and the second clock need to be determined based on the data bandwidth of the flow control data, and should not be regarded as a limitation of the present invention.

[0079] Multiple SRIO controllers 300 package all sub-data packets and all packet interrupt signals into a three-layer data format and send them to the host computer 400 via the SRIO transmission network. Each sub-data packet is stored in the corresponding memory of the host computer 400 according to its memory address, and each packet interrupt signal is sent to the processor of the host computer 400. After receiving the multiple packet interrupt signals output by the multiple SRIO controllers 300, the processor of the host computer 400 reads multiple sub-data packets with a total length equal to the preset interrupt length from the memory of the host computer 400 according to the memory start address of each packet interrupt signal, until all sub-data packets have been read.

[0080] The FPGA-based SRIO communication method of this invention divides flow control data into multiple sub-data packets with contiguous memory addresses and uses multiple SRIO interfaces to transmit single-channel front-end data. Although the transmission time of different SRIO interfaces in the SRIO transmission network is inconsistent, since the memory address and sub-data packet are in one-to-one correspondence, the data ultimately arrives at the host computer 400 as a contiguous block of memory data. This not only increases SRIO data bandwidth but also simplifies host computer 400 operations by eliminating the need for data splicing. Furthermore, if one or more SRIO paths malfunction, the malfunctioning SRIO controller will be skipped during polling and distribution, without affecting normal communication.

[0081] According to the FPGA-based SRIO communication method of this invention, by adding routing information and memory addresses to the flow control data and packetizing the flow control data according to the maximum packet payload of SRIO transmission, the flow control data can be divided into multiple sub-data packets with consecutive memory addresses. A packet interrupt signal is generated after each transmission of multiple sub-data packets with a total length equal to a preset interrupt length, and after all sub-data packets have been transmitted. The packet interrupt signal includes the memory start address of the corresponding multiple sub-data packets with a preset interrupt length, which can be used to notify the host computer 400 that the data has arrived in memory. The host computer 400 then reads the corresponding multiple sub-data packets with a total length equal to the preset interrupt length from its memory according to the memory start address, until all sub-data packets have been read. The host computer 400 does not need to perform data concatenation. By dividing the flow control data into multiple sub-data packets with consecutive memory addresses and using multiple SRIO interfaces to transmit single-channel front-end data, although the transmission time of different SRIO interfaces in the SRIO transmission network is inconsistent, since the memory address and sub-data packet are one-to-one, the data ultimately arriving in the host computer 400's memory is also a continuous block of memory data. If one or more SRIO paths malfunction, the malfunctioning SRIO controller will be skipped during the polling and distribution of SRIO controllers, without affecting normal communication. The FPGA-based SRIO communication method of this invention not only increases SRIO data bandwidth but also simplifies the operation of the host computer 400 by eliminating the need for data splicing.

[0082] In some embodiments of the present invention, reference is made to Figure 1 and Figure 2 The flow control data is packetized according to the maximum SRIO transmission payload, resulting in multiple sub-data packets with consecutive memory addresses. This involves the following steps: The flow control data is packetized once every SRIO transmission maximum payload, resulting in multiple fixed data packets with consecutive memory addresses, each the size of the SRIO transmission maximum payload, and an ending data packet less than or equal to the SRIO transmission maximum payload. Since the SRIO transmission maximum payload is 256 bytes, the data forwarding module 100 performs packetization every 256 bytes or at the end of the current data frame to ensure maximum transmission efficiency.

[0083] In some embodiments of the present invention, the following steps are also included:

[0084] Receive all sub-data packets and all packet interrupt signals output by the distribution module 200;

[0085] All sub-data packets are packaged into a three-layer structured data format to obtain multiple SRIO interface data;

[0086] All sub-packed interrupt signals are packaged into a three-layer data format to obtain multiple SRIO interrupt signals;

[0087] Multiple SRIO interface data and multiple SRIO interrupt signals are sent to the host computer 400 through the SRIO transmission network. Each SRIO interface data is stored in the corresponding memory of the host computer 400 according to the corresponding memory address, and each SRIO interrupt signal is sent to the processor of the host computer 400.

[0088] The processor of host computer 400 performs the following steps:

[0089] Receives multiple SRIO interrupt signals output by multiple SRIO controllers 300;

[0090] Based on the memory start address of each SRIO interrupt signal, read multiple SRIO interface data with a total length equal to the preset interrupt length from the memory of the host computer 400 until all SRIO interface data has been read.

[0091] The data structure is a three-layer architecture: physical layer, transport layer, and logic layer. Multiple SRIO interface data have contiguous memory addresses. While different SRIO interfaces transmit single-channel front-end data at different times within the SRIO network, the memory addresses and SRIO interface data are in a one-to-one correspondence, resulting in a contiguous block of data reaching the host computer's 400 memory. This not only increases SRIO data bandwidth but also simplifies host computer 400 operations. It only requires reading data from multiple SRIO interfaces with a total length equal to the preset interrupt length based on the memory start address of each SRIO interrupt signal until all SRIO interface data has been read, eliminating the need for data concatenation.

[0092] It should be noted that the three-layer data format packaging and the working principle of data transmission via SRIO transmission network are existing technologies known to those skilled in the art, and will not be elaborated here.

[0093] In some embodiments of the present invention, flow control data is obtained by the following steps:

[0094] Obtain valid data, which is obtained by decoding the original front-end data corresponding to the non-SRIO interface.

[0095] The valid data is converted into flow control data by the flow control interface, which is the data interface type supported by the SRIO controller 300 for data transmission.

[0096] After decoding the front-end data corresponding to the original non-SRIO interface, valid data is obtained. This valid data is then converted into flow control data for the flow control interface by the caching module 500. Since the bandwidth of the flow control data is greater than that of a single SRIO interface, using a single SRIO interface in this case may result in data loss. In some embodiments of this invention, the flow control interface is an AXIS interface. The data forwarding module 100, distribution module 200, and multiple SRIO controllers 300 in these embodiments all use a data flow interface with a handshake protocol, namely the AXIS interface. The SRIO controller 300 can only transmit data through the AXIS interface.

[0097] To better demonstrate the advantages of the FPGA-based SRIO communication method of this invention, a specific embodiment will be described in detail below. In the following example, the data forwarding module 100 is represented as SRIO_DMA, the distribution module 200 is represented as SRIO_SEG, and the SRIO controller 300 is represented as SRIO_CTRL.

[0098] Suppose the front-end wants to transmit a data packet with a length of 5.5MB. After decoding, 5.5MB of valid data is obtained. This valid data is then converted into 5.5MB of flow control data by a buffer module 500 (usually using DDR as the buffer module 500). The valid data has a bit width of 64 bits and a clock speed of 250MHz. The bit width and clock speed of the flow control data after passing through the buffer module 500 remain unchanged.

[0099] The caching module 500 outputs 5.5MB of flow control data to SRIO_DMA. Routing information and memory addresses are added to SRIO_DMA, and the flow control data is packetized according to the maximum SRIO transmission payload. For example, if the device ID on the CPU is 0x10, then device ID information for 0x10 is added; if the transmission type is NWRITE, then NWRITE transmission information is added. The maximum SRIO transmission payload is 256 bytes, and the maximum transmission length is 256 bytes. Memory addresses sequentially proceed from 0x00 to the maximum memory space allocated on the CPU, then repeat. The base address can be pre-defined, and the offset address can increment in units of 0x100. This divides the 5.5MB flow control data into multiple sub-data packets with a maximum payload of no more than 256 bytes, with the bit width and clock remaining unchanged. Then, a doorbell data packet, i.e., a packet interrupt signal, is sent every time the total length of the multiple sub-data packets reaches 1MB. A packet interrupt signal is also sent at the end of the 5.5MB flow control data. The packet interrupt signal contains the address of the beginning of the 1MB data in memory.

[0100] SRIO_DMA outputs all sub-data packets and all packet interrupt signals to SRIO_SEG. This invention employs a multi-channel SRIO interface. Assuming there are two SRIO interfaces, there are two SRIO_CTRL channels. SRIO_CTRL_0 and SRIO_CTRL_1 both have a bit width of 64 bits and a clock speed of 125 MHz. The two asynchronous FIFO buffers in SRIO_SEG operate at 64 bits * 250 MHz for writing and 64 bits * 125 MHz for reading. This ensures that when writing a sub-data packet to the first asynchronous FIFO buffer and switching to the second, the first asynchronous FIFO buffer hasn't finished reading. By the time the second asynchronous FIFO buffer finishes writing, the first asynchronous FIFO buffer has finished reading, allowing writing to continue without overflow. Data read from the asynchronous FIFO buffer goes directly to the corresponding SRIO_CTRL. Furthermore, since the memory addresses of sub-data packets are contiguous, when a certain SRIO_CTRL is not working, the polling packet segmentation will skip that asynchronous FIFO buffer block, and no packet loss will occur.

[0101] After SRIO_SEG outputs all sub-data packets and all packet interrupt signals to multiple SRIO_CTRLs, it is converted into high-speed serial SRIO data. This data is then transmitted through the physical channel to the SRIO interface of the host computer 400 and written to the host computer 400's memory. Upon receiving a packet interrupt signal, the host computer 400 reads the corresponding 1MB of data from its memory based on the memory start address of each SRIO interrupt signal, until all SRIO interface data has been read. This achieves multi-channel SRIO transmission of single-channel front-end data. Although the transmission times of different SRIO interfaces in the SRIO transmission network are inconsistent, since the memory address and sub-data packet are one-to-one, the data that ultimately arrives in the host computer 400's memory is also a continuous block of memory data.

[0102] The FPGA-based SRIO communication system of this invention can not only increase SRIO data bandwidth, but also simplify the operation of the host computer 400 without requiring data splicing.

[0103] According to a second aspect embodiment of the present invention, the FPGA-based SRIO communication system includes a data forwarding module 100, a distribution module 200, and a plurality of SRIO controllers 300. The bandwidth of the data forwarding module 100 is less than the sum of the bandwidths of the plurality of SRIO controllers 300. The FPGA-based SRIO communication system includes a flow control data acquisition unit, a data processing unit, and a data distribution unit.

[0104] The flow control data acquisition unit is used to acquire the flow control data output by the cache module 500;

[0105] The data processing unit is used to add routing information and memory addresses to the flow control data, and to divide the flow control data into packets according to the maximum packet payload of SRIO transmission, so as to obtain multiple sub-data packets with consecutive memory addresses. The length of each sub-data packet does not exceed the maximum packet payload of SRIO transmission.

[0106] The data distribution unit is used to send multiple sub-data packets to the distribution module 200, and to send a packet interrupt signal to the distribution module 200 after each sub-data packet with a total length equal to a preset interrupt length and after all sub-data packets have been sent. The distribution module 200 then distributes all sub-data packets and all packet interrupt signals to multiple SRIO controllers 300 in a round-robin arbitration manner, so that the multiple SRIO controllers 300 can package all sub-data packets and all packet interrupt signals into a three-layer data format and send them to the host computer 400. The packet interrupt signal includes the memory start address of the corresponding multiple sub-data packets with a preset interrupt length, where the preset interrupt length is less than the total length of all sub-data packets.

[0107] The FPGA-based SRIO communication system of this invention adopts all the technical solutions of the FPGA-based SRIO communication method of the first aspect embodiment described above, and the specific details will not be repeated here.

[0108] According to the FPGA-based SRIO communication system of this invention, by adding routing information and memory addresses to the flow control data and packetizing the flow control data according to the maximum packet payload of SRIO transmission, the flow control data can be divided into multiple sub-data packets with consecutive memory addresses. A packet interrupt signal is generated after each transmission of multiple sub-data packets with a total length equal to a preset interrupt length, and after all sub-data packets have been transmitted. The packet interrupt signal includes the memory start address of the corresponding multiple sub-data packets with a preset interrupt length, which can be used to notify the host computer 400 that the data has arrived in memory. The host computer 400 then reads the corresponding multiple sub-data packets with a total length equal to the preset interrupt length from its memory according to the memory start address, until all sub-data packets have been read. The host computer 400 does not need to perform data concatenation. By dividing the flow control data into multiple sub-data packets with consecutive memory addresses and using multiple SRIO interfaces to transmit single-channel front-end data, although the transmission time of different SRIO interfaces in the SRIO transmission network is inconsistent, since the memory address and sub-data packet are one-to-one, the data ultimately arriving in the host computer 400's memory is also a continuous block of memory data. If one or more SRIO paths malfunction, the malfunctioning SRIO controller will be skipped during the polling and distribution of SRIO controllers, without affecting normal communication. The FPGA-based SRIO communication system of this invention not only increases SRIO data bandwidth but also simplifies the operation of the host computer 400 by eliminating the need for data splicing.

[0109] An FPGA according to a third aspect embodiment of the present invention includes a data forwarding module 100, a distribution module 200, and a plurality of SRIO controllers 300.

[0110] The data forwarding module 100 is used to execute the FPGA-based SRIO communication method as described in the first aspect embodiment above;

[0111] The distribution module 200 is used to receive all sub-data packets and all sub-packet interrupt signals output by the data forwarding module 100, and distribute all sub-data packets and all sub-packet interrupt signals in a round-robin arbitration manner;

[0112] Multiple SRIO controllers 300 are used to receive all sub-data packets and all packet interrupt signals output by the distribution module 200, and package all sub-data packets and all packet interrupt signals into a three-layer data format before sending them to the host computer 400; the total bandwidth of the multiple SRIO controllers 300 is greater than the bandwidth of the data forwarding module 100.

[0113] The FPGA in this embodiment of the invention adopts all the technical solutions of the FPGA-based SRIO communication method described in the first aspect of the invention, and the specific details will not be repeated here. Furthermore, the circuit structure and working principle of the FPGA are existing technologies known to those skilled in the art, and will not be described further here.

[0114] According to the FPGA of this embodiment, by adding routing information and memory addresses to the flow control data and packetizing the flow control data according to the maximum packet payload of SRIO transmission, the flow control data can be divided into multiple sub-data packets with consecutive memory addresses. A packet interrupt signal is generated after each transmission of multiple sub-data packets with a total length equal to a preset interrupt length, and after all sub-data packets have been transmitted. The packet interrupt signal includes the memory start address of the corresponding multiple sub-data packets with a preset interrupt length, which can be used to notify the host computer 400 that the data has arrived in memory. The host computer 400 then reads the corresponding multiple sub-data packets with a total length equal to the preset interrupt length from its memory according to the memory start address, until all sub-data packets have been read. The host computer 400 does not need to perform data concatenation. By dividing the flow control data into multiple sub-data packets with consecutive memory addresses and using multiple SRIO interfaces to transmit single-channel front-end data, although the transmission time of different SRIO interfaces in the SRIO transmission network is inconsistent, since the memory address and sub-data packet are one-to-one, the final data arriving in the host computer 400's memory is also a continuous block of memory data. If one or more SRIO paths malfunction, the malfunctioning SRIO controller will be skipped during the polling and distribution of SRIO controllers, without affecting normal communication. The FPGA in this embodiment of the invention not only increases SRIO data bandwidth but also simplifies the operation of the host computer 400 by eliminating the need for data splicing.

[0115] Furthermore, a fourth aspect of the present invention provides a control device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and the memory may be connected via a bus or other means.

[0116] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0117] The non-transient software program and instructions required to implement the FPGA-based SRIO communication method of the above embodiments are stored in memory. When executed by the processor, the FPGA-based SRIO communication method of the above embodiments is executed.

[0118] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0119] Furthermore, a fifth aspect embodiment of the present invention provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor or controller, for example, by a processor of the aforementioned control device, such that the processor performs the FPGA-based SRIO communication method described in the above embodiments.

[0120] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0121] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. An FPGA-based SRIO communication method, characterized in that, The FPGA includes a data forwarding module, a distribution module, and multiple SRIO controllers. The bandwidth of the data forwarding module is less than the sum of the bandwidths of the multiple SRIO controllers. The FPGA-based SRIO communication method includes the following steps: Obtain the flow control data output by the caching module; Routing information and memory addresses are added to the flow control data, and the flow control data is divided into packets according to the maximum packet payload of SRIO transmission to obtain multiple sub-data packets with consecutive memory addresses. The length of each sub-data packet does not exceed the maximum packet payload of SRIO transmission. Multiple sub-data packets are sent to the distribution module, and a packet interrupt signal is sent to the distribution module after each of the multiple sub-data packets with a total length equal to the preset interrupt length or after all the sub-data packets have been sent. The distribution module then distributes all the sub-data packets and all the packet interrupt signals to multiple SRIO controllers in a round-robin arbitration manner, so that the multiple SRIO controllers package all the sub-data packets and all the packet interrupt signals into a three-layer data format and send it to the host computer. The packet interrupt signal includes the memory start address of the multiple sub-data packets with the corresponding preset interrupt length.

2. The FPGA-based SRIO communication method according to claim 1, characterized in that, The step of dividing the flow control data into packets based on the maximum packet payload transmitted via SRIO to obtain multiple sub-data packets with consecutive memory addresses includes the following steps: The flow control data is divided into packets every SRIO transmission maximum packet payload, resulting in multiple fixed data packets with consecutive memory addresses, each the size of the SRIO transmission maximum packet payload, and an end data packet less than or equal to the SRIO transmission maximum packet payload.

3. The FPGA-based SRIO communication method according to claim 1, characterized in that, It also includes the following steps: Receive all the sub-data packets and all the packet interrupt signals output by the data forwarding module; Multiple asynchronous FIFO buffer blocks are allocated one-to-one according to the multiple SRIO controllers, and the capacity of each asynchronous FIFO buffer block is greater than the maximum packet payload of SRIO transmission. All the sub-data packets and all the packet interrupt signals are written one-to-one into multiple asynchronous FIFO buffer blocks. All the sub-data packets and all the packet interrupt signals are read asynchronously from the multiple asynchronous FIFO buffer blocks and sent to multiple SRIO controllers.

4. The FPGA-based SRIO communication method according to claim 3, characterized in that, The step of writing all the sub-data packets and all the packet interrupt signals into multiple asynchronous FIFO buffer blocks in a one-to-one correspondence, asynchronously reading all the sub-data packets and all the packet interrupt signals from the multiple asynchronous FIFO buffer blocks, and sending them to multiple SRIO controllers includes the following steps: All the sub-data packets and all the packet interrupt signals are written into multiple asynchronous FIFO buffer blocks one-to-one according to a preset first clock; All sub-data packets and all packet interrupt signals are read from multiple asynchronous FIFO buffer blocks according to a preset second clock and sent to multiple SRIO controllers.

5. The FPGA-based SRIO communication method according to claim 1, characterized in that, It also includes the following steps: Receive all the sub-data packets and all the packet interrupt signals output by the distribution module; All the sub-data packets are packaged into a three-layer structured data format to obtain multiple SRIO interface data; All the aforementioned packetized interrupt signals are packaged into a three-layer data format to obtain multiple SRIO interrupt signals; Multiple SRIO interface data and multiple SRIO interrupt signals are sent to the host computer via the SRIO transmission network. Each SRIO interface data is stored in the corresponding memory of the host computer according to its corresponding memory address, and each SRIO interrupt signal is sent to the processor of the host computer.

6. The FPGA-based SRIO communication method according to claim 5, characterized in that, It also includes the following steps: Receive multiple SRIO interrupt signals output by multiple SRIO controllers; Based on the memory start address of each SRIO interrupt signal, read multiple SRIO interface data with a total length equal to the preset interrupt length from the memory of the host computer until all SRIO interface data has been read.

7. The FPGA-based SRIO communication method according to claim 1, characterized in that, The flow control data is obtained through the following steps: Obtain valid data, which is obtained by decoding the original front-end data corresponding to the non-SRIO interface; The valid data is converted into flow control data for the flow control interface, wherein the flow control interface is a data interface type supported by the SRIO controller for transmitting data.

8. An FPGA-based SRIO communication system, characterized in that, The FPGA includes a data forwarding module, a distribution module, and multiple SRIO controllers. The bandwidth of the data forwarding module is less than the sum of the bandwidths of the multiple SRIO controllers. The FPGA-based SRIO communication system includes: The flow control data acquisition unit is used to acquire the flow control data output by the cache module. The data processing unit is used to add routing information and memory address to the flow control data, and to divide the flow control data into packets according to the maximum packet payload of SRIO transmission to obtain multiple sub-data packets with consecutive memory addresses. The length of each sub-data packet does not exceed the maximum packet payload of SRIO transmission. A data distribution unit is used to send multiple sub-data packets to the distribution module, and to send a packet interrupt signal to the distribution module after each of the multiple sub-data packets with a total length equal to a preset interrupt length or after all the sub-data packets have been sent. The distribution module then distributes all the sub-data packets and all the packet interrupt signals to multiple SRIO controllers in a round-robin arbitration manner, so that the multiple SRIO controllers package all the sub-data packets and all the packet interrupt signals into a three-layer data format and send it to the host computer. The packet interrupt signal includes the memory start address of the multiple sub-data packets with the corresponding preset interrupt length.

9. An FPGA, characterized in that, include: A data forwarding module is used to execute the FPGA-based SRIO communication method as described in any one of claims 1 to 7; The distribution module is used to receive all the sub-data packets and all the packet interruption signals output by the data forwarding module, and distribute all the sub-data packets and all the packet interruption signals in a round-robin arbitration manner; Multiple SRIO controllers are used to receive all the sub-data packets and all the packet interrupt signals output by the distribution module, and to package all the sub-data packets and all the packet interrupt signals into a three-layer data format and send them to the host computer; the total bandwidth of the multiple SRIO controllers is greater than the bandwidth of the data forwarding module.

10. A computer-readable storage medium storing computer-executable instructions, characterized in that, The computer-executable instructions are used to execute the FPGA-based SRIO communication method as described in any one of claims 1 to 7.

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