Memory and its manufacturing method

Abstract

This disclosure provides a memory and its fabrication method, relating to the field of semiconductor technology, to solve the technical problem of difficult word line fabrication. The fabrication method includes: forming a stacked structure on a substrate, the stacked structure including sacrificial layers and active layers alternately stacked along a first direction; removing a portion of the stacked structure located in a first region to form multiple spaced-apart first trenches extending along a second direction, the first trenches exposing the substrate to separate the active layer in the first region into multiple spaced-apart active pillars; removing the sacrificial layer located in the first region and a second region; removing a portion of the active layer located in the second region to form multiple stepped interconnect layers at the end of the second region away from the first region; and forming a gate material layer covering the interconnect layers and active pillars. The gate material layer serves as the word line, and the interconnect layers facilitate the fabrication of the word line and its routing.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and a method for manufacturing the same. Background Technology

[0002] With the development of semiconductor technology, memory, especially dynamic random access memory (DRAM), is widely used in various electronic devices due to its high storage density and fast read / write speed.

[0003] Dynamic random access memory (DRAM) typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line (WL) of the DRAM, and the voltage on the word line controls the transistor's on and off states. One of the transistor's source and drain terminals is electrically connected to the bit line (BL), and the other of the source and drain terminals is electrically connected to the capacitor. Data information is stored or output through the bit line.

[0004] To further reduce the size of memory and increase its storage density, capacitors are usually placed horizontally to facilitate the fabrication of capacitors with a larger aspect ratio; however, the word lines that are compatible with them are difficult to manufacture. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a memory and a method for manufacturing the same, which reduces the difficulty of manufacturing word lines.

[0006] According to some embodiments, a first aspect of this disclosure provides a method for manufacturing a memory, comprising:

[0007] Provide substrate;

[0008] A stacked structure is formed on the substrate, the stacked structure comprising a sacrificial layer and an active layer alternately stacked along a first direction;

[0009] A portion of the stacked structure located in the first region is removed to form a plurality of spaced first trenches extending in a second direction, the first trenches exposing the substrate to divide the active layer located in the first region into a plurality of spaced active pillars;

[0010] Using the first trench, the sacrificial layer located in the first region and the second region is removed, so that the active pillar located in the first region and the active layer located in the second region are both spaced apart along the first direction, wherein the second region is adjacent to the first region;

[0011] Remove a portion of the active layer located in the second region to form a plurality of stepped connection layers at one end of the second region away from the first region;

[0012] A gate material layer is formed to cover the connection layer and the active pillar, and the gate material layers formed on the connection layer and the active pillar located on the same layer are interconnected, while the gate material layers formed on the connection layer and the active pillar located on different layers are isolated from each other.

[0013] In some possible embodiments, the lengths of the plurality of interconnect layers decrease sequentially along a direction away from the substrate, such that one end of the plurality of interconnect layers away from the first region is formed in a stepped shape.

[0014] In some possible embodiments, a stacked structure is formed on the substrate, including:

[0015] One sacrificial layer and one active layer are sequentially and alternately formed on the substrate until the stacked structure is formed, wherein the innermost layer of the stacked structure closest to the substrate is the sacrificial layer, and the outermost layer of the stacked structure furthest from the substrate is the active layer.

[0016] In some possible embodiments, the sacrificial layer and the active layer are formed from the substrate by an epitaxial growth process.

[0017] In some possible embodiments, the active layer is made of N-type doped silicon, and the sacrificial layer is made of germanium-silicon.

[0018] In some possible embodiments, a portion of the stacked structure located in the first region is removed to form a plurality of spaced-apart first trenches extending along the second direction, including:

[0019] The stacked structure located in the first region is etched to form the first trench, which penetrates the stacked structure.

[0020] In some possible embodiments, the stacked structure located in the first region is etched to form the first trench, the first trench penetrating the stacked structure, including:

[0021] A first mask layer is formed on the stacked structure, and the first mask layer located in the first region has a first pattern;

[0022] Using the first mask layer as a mask, the stacked structure located in the first region is etched to form the first trench.

[0023] In some possible embodiments, using the first trench to remove the sacrificial layer located in the first region and the second region includes:

[0024] The sidewalls of the sacrificial layer are exposed using the first trench, and the sacrificial layer located in the first region and the second region is removed by a wet etching process.

[0025] In some possible embodiments, the first mask layer is formed on the stacked structure, including:

[0026] A protective layer is formed on the stacked structure, and the first mask layer is formed on the protective layer.

[0027] In some possible embodiments, using the first mask layer as a mask, etching the stacked structure located in the first region includes:

[0028] Using the first mask layer as a mask, the protective layer located in the first region is etched to transfer the first pattern into the protective layer;

[0029] Remove the first mask layer and continue etching the stacked structure with the patterned protective layer.

[0030] In some possible embodiments, a portion of the active layer located in the second region is removed to form a plurality of stepped connection layers at the end of the second region away from the first region, including:

[0031] A second mask layer is formed on the active layer, and the second mask layer located in the second region has a second pattern;

[0032] Using the second mask layer as a mask, the active layer located in the second region is etched to form a plurality of stepped connection layers at one end of the second region away from the first region;

[0033] Remove the second mask layer.

[0034] In some possible embodiments, a gate material layer is formed to cover the interconnect layer and the active pillar, including:

[0035] A gate dielectric layer is formed to cover the surfaces of the interconnecting layers and the active pillars, and there are gaps between the gate dielectric layers on the surfaces of each interconnecting layer and each active pillar;

[0036] A deposited gate conductive layer covers the surface of the gate dielectric layer.

[0037] In some possible embodiments, the gate conductive layers on the gate dielectric layers disposed in the same layer are interconnected, while the gate conductive layers on the gate dielectric layers disposed in different layers are isolated from each other.

[0038] In some possible embodiments, while forming a gate material layer covering the interconnect layer and the active pillar, the method further includes:

[0039] The gate material layer is formed on the substrate located in the first region and the second region, and the gate material layer on the substrate is isolated from the gate material layer on the active pillar and the gate material layer on the interconnect layer.

[0040] In some possible embodiments, a gate material layer is formed to cover the interconnect layer and the active pillar, and the gate material layers formed on the interconnect layer and the active pillar located on the same layer are interconnected, while the gate material layers formed on the interconnect layer and the active pillar located on different layers are isolated from each other, further comprising:

[0041] A plurality of spaced contact plugs extending along the first direction are formed, each contact plug being in contact with one of the gate material layers located in the second region.

[0042] The method for manufacturing the memory provided in this disclosure has at least the following advantages:

[0043] In the memory fabrication method provided in this disclosure, a stacked structure is formed on a substrate. The stacked structure includes sacrificial layers and active layers alternately stacked along a first direction. The sacrificial layers and part of the active layers are removed, such that the active layers in the first region form multiple spaced active pillars, and the active layers in the second region form multiple stepped interconnect layers. Gate material layers are then formed on the interconnect layers and active pillars. The gate material layers formed on the interconnect layers and active pillars in the same layer are interconnected, while the gate material layers formed on the interconnect layers and active pillars in different layers are isolated from each other. The gate material layers are used as word lines. By setting the interconnect layers, it is convenient to fabricate word lines and lead them out. In addition, since the ends of the multiple interconnect layers away from the first region are stepped, the ends of the gate material layers covering the active pillars and interconnect layers away from the first region are also stepped, i.e., the word lines are stepped, which facilitates the fabrication of other structures on the word lines to achieve electrical connection between the word lines and peripheral circuits.

[0044] According to some embodiments, a second aspect of this disclosure provides a memory having adjacent first and second regions. The memory includes: a plurality of interconnect layers located in the second region and spaced apart along a first direction, wherein one end of the plurality of interconnect layers away from the first region is stepped; a plurality of active pillar layers located in the first region and spaced apart along the first direction, wherein each active pillar layer is co-located with one of the interconnect layers; each active pillar layer has a plurality of spaced active pillars, and each active pillar extends along a second direction; and gate material layers located on the interconnect layers and the active pillars, wherein the gate material layers formed on the interconnect layers and the active pillars on the same layer are interconnected, and the gate material layers formed on the interconnect layers and the active pillars on different layers are isolated from each other.

[0045] In some possible embodiments, the memory further has a third region adjacent to the first region, and the memory further includes a plurality of spaced capacitors located in the third region, the capacitors extending along the second direction, and each of the capacitors being electrically connected to one of the active posts.

[0046] In some possible embodiments, the memory further includes a plurality of spaced-apart contact plugs extending along the first direction, each of the contact plugs being in contact with one of the gate material layers located in the second region.

[0047] The memory provided in this disclosure has at least the following advantages:

[0048] The memory provided in this disclosure comprises gate material layers disposed on the interconnect layers and the active pillars. The gate material layers formed on the interconnect layers and the active pillars on the same layer are interconnected, while those on different layers are isolated from each other. The gate material layers serve as word lines. The interconnect layers facilitate the fabrication of word lines and their routing. Furthermore, since the ends of the multiple interconnect layers away from the first region are stepped, the ends of the gate material layers covering the active pillars and interconnect layers away from the first region are also stepped, resulting in stepped word lines. This facilitates the fabrication of other structures on the word lines to achieve electrical connections between the word lines and peripheral circuits. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is an architectural diagram of a memory according to an embodiment of the present disclosure;

[0051] Figure 2 This is a flowchart of a method for manufacturing a memory according to an embodiment of the present disclosure;

[0052] Figure 3 This is a schematic diagram of the first and second regions after forming a stacked structure in one embodiment of the present disclosure;

[0053] Figure 4 This is a schematic diagram of a first region and a second region after the formation of a first trench in one embodiment of the present disclosure;

[0054] Figure 5 This is another schematic diagram of the first and second regions after the formation of the first trench in one embodiment of the present disclosure;

[0055] Figure 6 This is a schematic diagram of a first region and a second region after the formation of a protective layer in one embodiment of the present disclosure;

[0056] Figure 7 This is a schematic diagram of a first region and a second region after the formation of a first mask layer in one embodiment of the present disclosure;

[0057] Figure 8 This is a schematic diagram of the first and second regions after removing the sacrificial layer in one embodiment of the present disclosure;

[0058] Figure 9 This is a schematic diagram of a first region and a second region after the formation of a connecting layer in one embodiment of the present disclosure;

[0059] Figure 10 This is a schematic diagram of a first region and a second region after the formation of a gate material layer in one embodiment of the present disclosure;

[0060] Figure 11 This is a schematic diagram of the first and second regions after the formation of the contact plug in one embodiment of the present disclosure;

[0061] Figure 12 This is a schematic diagram of a third region after the formation of a stacked structure in one embodiment of the present disclosure;

[0062] Figure 13 This is a schematic diagram of a third region after the formation of a protective layer in one embodiment of the present disclosure;

[0063] Figure 14 This is a schematic diagram of a third region after the formation of the first mask layer in one embodiment of the present disclosure. Detailed Implementation

[0064] In related technologies, to further increase the storage capacity of memory, capacitors are typically placed horizontally, meaning their extension direction is parallel to the substrate, to facilitate capacitor fabrication. However, when capacitors are placed horizontally, the corresponding word lines need to be rearranged, making word line fabrication more difficult.

[0065] In view of this, embodiments of the present disclosure provide a memory and a method for manufacturing the same. The method involves forming an interconnect layer and active pillars, with the end of the interconnect layer away from the active pillars forming a stepped shape. Gate material layers are formed on the gate material layers of the interconnect layer and the active pillars. The gate material layers formed on the interconnect layer and the active pillars on the same layer are interconnected, while the gate material layers formed on the interconnect layer and the active pillars on different layers are isolated from each other. The gate material layers serve as word lines, facilitating fabrication and output. The stepped shape of the word lines facilitates the fabrication of other structures on the word lines to achieve electrical connections between the word lines and peripheral circuits.

[0066] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0067] The first aspect of this disclosure provides a method for manufacturing a memory, which includes Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Flash Memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM), etc. This disclosure uses DRAM as an example for illustration.

[0068] See Figure 1The memory includes word line 4, bit line 1, transistor 2, and capacitor 3. The gate of transistor 2 is electrically connected to word line 4, and one of the source and drain of transistor 2 is electrically connected to bit line 1, while the other is electrically connected to capacitor 3. Word line 4 is used to control the on / off state of transistor 2, and bit line 1 is used to write data to capacitor 3 or read data from capacitor 3. Figure 1 As shown, both transistor 2 and capacitor 3 extend along the second direction. Figure 1 (As shown in the Z direction), this direction is parallel to the substrate, that is, both transistor 2 and capacitor 3 are arranged parallel to the substrate, so as to facilitate the fabrication of capacitor 3 with a larger aspect ratio, thereby increasing the storage capacity of the memory.

[0069] See Figure 2 , Figure 2 This is a flowchart of a method for manufacturing a memory according to an embodiment of the present disclosure. The method may include:

[0070] Step S10: Provide a substrate.

[0071] See Figure 3 The substrate 10 can provide a supporting foundation for the structural layers on the substrate 10. The substrate 10 can be made of semiconductor, such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanium (SiGe), germanium on insulator (GOI) or silicon on insulator (SOI), etc.

[0072] In some possible embodiments, the substrate 10 includes a first region and a second region, the first region being as follows: Figure 3 As shown at point B, the second region is as follows: Figure 3 As shown at point A, the first region and the second region are adjacent, for example, the first region and the second region are adjacent and connected. A semiconductor device, such as a transistor 2, may be disposed on the first region, and a connection structure, such as a connection layer 60, may be disposed on the second region (see Figure *). The semiconductor device on the first region is brought out through the structure on the second region to electrically connect the semiconductor device to peripheral circuitry. The substrate 10 located in the first region and the substrate 10 located in the second region are integrated as a single unit to facilitate the provision of substrate 10.

[0073] Step S20: Form a stacked structure on the substrate, the stacked structure including a sacrificial layer and an active layer alternately stacked along a first direction.

[0074] See Figure 3The stacked structure 20 includes multiple sacrificial layers 21 and multiple active layers 22, which are alternately stacked along a first direction. The first direction is perpendicular to the substrate 10, such as... Figure 3 The Y direction is shown. Along the first direction, an active layer 22 is disposed between two adjacent sacrificial layers 21, or a sacrificial layer 21 is disposed between two adjacent active layers 22, so that the sacrificial layer 21 and the active layer 22 are disposed alternately. In this arrangement, the sacrificial layer 21 can isolate two adjacent active layers 22, so as to electrically isolate the active layers 22 along the first direction.

[0075] Specifically, forming a stacked structure 20 on the substrate 10 includes: sequentially and alternately forming a sacrificial layer 21 and an active layer 22 on the substrate 10 until the stacked structure 20 is formed, wherein the innermost layer of the stacked structure 20 closest to the substrate 10 is the sacrificial layer 21, and the outermost layer of the stacked structure 20 furthest from the substrate 10 is the active layer 22. Specifically, when forming the stacked structure 20, a sacrificial layer 21 is formed on the substrate 10, then an active layer 22 is formed on the sacrificial layer 21, then a sacrificial layer 21 is formed on the active layer 22, and the formation process of the active layer 22 and the sacrificial layer 21 is repeated until the required number of sacrificial layers 21 and active layers 22 are formed.

[0076] like Figure 3 As shown, the innermost layer of the stacked structure 20 closest to the substrate 10 is a sacrificial layer 21, which separates the active layers 22 on the sacrificial layer 21 from the substrate 10. Each active layer 22 can subsequently form a transistor 2, increasing the number of transistors 2 and thus improving the storage capacity of the semiconductor structure. The outermost layer of the stacked structure 20 furthest from the substrate 10 is an active layer 22. With this configuration, when the stacked structure 20 has the same number of active layers 22, the height of the stacked structure 20 is reduced, which facilitates subsequent etching of the stacked structure 20.

[0077] In some possible implementations, a sacrificial layer 21 and an active layer 22 are formed on the substrate 10 by a deposition process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0078] In some possible implementations, a sacrificial layer 21 and an active layer 22 are formed on a substrate 10 using an epitaxial growth process (EPI). Specifically, the substrate 10, active layer 22, and sacrificial layer 21 are all made of the same element, such as silicon, to epitaxially grow the sacrificial layer 21 on the substrate 10, the active layer 22 on the sacrificial layer 21, and the sacrificial layer 21 on the active layer 22. For example, the substrate 10 is made of silicon, the active layer 22 is made of silicon, and the sacrificial layer 21 is made of germanium-silicon. This facilitates the epitaxial growth of the active layer 22 and the sacrificial layer 21, and also allows for a higher selectivity between the sacrificial layer 21 and the active layer 22, enabling the sacrificial layer 21 to be removed separately, thus reducing damage to the active layer 22 during removal. Preferably, the active layer 22 is made of doped silicon, for example, N-type doped silicon, to improve its electrical performance.

[0079] Step S30: Remove part of the stacked structure located in the first region to form multiple spaced first trenches extending along the second direction. The first trenches expose the substrate to divide the active layer located in the first region into multiple spaced active pillars.

[0080] See Figure 4 Multiple first grooves 51 are formed in the stacked structure 20 located in the first region. The multiple first grooves 51 are spaced apart and extend along a second direction, which is... Figure 1 The horizontal direction (Z direction) shown is parallel to the substrate 10 and perpendicular to the first direction. The first trench 51 penetrates the stacked structure 20 located in the first region to expose the substrate 10.

[0081] In some possible embodiments, see Figure 5 The first trench 51 can extend into the substrate 10, that is, the bottom of the first trench 51 is located in the substrate 10. This configuration ensures that the first trench 51 divides the stacked structure 20 into multiple parts, thereby dividing each active layer 22 in the stacked structure 20 into multiple spaced active pillars 50, increasing the number of active pillars 50 and increasing the storage capacity of the semiconductor structure.

[0082] like Figure 4 and Figure 5 As shown, multiple active pillars 50 are arranged in an array, extending along a second direction. The multiple active pillars 50 are spaced apart along a first direction and also spaced apart along a third direction, which intersects the first direction and is perpendicular to the second direction. The third direction is parallel to the substrate 10; for example, the third direction is... Figure 4 and Figure 5As shown in the horizontal direction (X direction), the first direction, the second direction, and the third direction are perpendicular to each other. This arrangement allows for a more compact arrangement of the active posts 50, maximizing the number of active posts 50. Each active post 50 includes a source, a drain, and a channel between the source and drain. The shape of the active post 50 can be a cylinder, prism, cuboid, or other shape, and is not limited in this embodiment.

[0083] Specifically, removing a portion of the stacked structure 20 located in the first region to form multiple spaced first trenches 51 extending along the second direction includes: etching the stacked structure 20 located in the first region to form the first trenches 51, the first trenches 51 penetrating the stacked structure 20.

[0084] See Figures 4 to 7 In some possible implementations, the stacked structure 20 located in the first region is etched to form a first trench 51, the first trench 51 penetrating the stacked structure 20, including:

[0085] A first mask layer 40 is formed on the stacked structure 20. The first mask layer 40 located in a first region has a first pattern. The first mask layer 40 is formed on the stacked structure 20 and covers both the stacked structure 20 located in the first region and the stacked structure 20 located in the second region. The first mask layer 40 located in the first region has the first pattern to expose a portion of the stacked structure 20 located in the first region, while the stacked structure 20 located in the second region is not exposed.

[0086] Using the first mask layer 40 as a mask, the stacked structure 20 located in the first region is etched to form the first trench 51. By etching the stacked structure 20 using the first mask layer 40 as a mask, the first pattern is transferred to the stacked structure 20 located in the first region to form the first trench 51 in the stacked structure 20.

[0087] In some other possible implementations, forming a first mask layer 40 on the stacked structure 20 includes: forming a protective layer 30 on the stacked structure 20, and forming the first mask layer 40 on the protective layer 30. See also Figure 4 and Figure 6 A protective layer 30 covers the stacked structure 20. The protective layer 30 can oxidize the silicon layer to reduce or prevent oxidation of the active layer 22. (See also...) Figure 6 and Figure 7 The protective layer 30 is covered with a first mask layer 40, and the first mask layer 40 located in the first region has a first pattern.

[0088] Accordingly, see Figure 7 and Figure 5Using the first mask layer 40 as a mask, etching the stacked structure 20 located in the first region includes: using the first mask layer 40 as a mask, etching the protective layer 30 located in the first region to transfer the first pattern to the protective layer 30; removing the first mask layer 40, and continuing to etch the stacked structure 20 with the patterned protective layer 30. That is, firstly, the first pattern of the first mask layer 40 is transferred to the protective layer 30 located in the first region; then the first mask layer 40 is removed to expose the protective layer 30; and then the stacked structure 20 is etched with the patterned protective layer 30 as a mask to form a first trench 51 in the stacked structure 20.

[0089] Step S40: Using the first trench, remove the sacrificial layer located in the first region and the second region, so that the active pillars located in the first region and the active layer located in the second region are both spaced apart along the first direction, wherein the second region is adjacent to the first region.

[0090] See Figure 5 and Figure 8 The sacrificial layers 21 in the first and second regions are completely removed. Active pillars 50 in the first region are spaced apart along a first direction, and active layers 22 in the second region are spaced apart along the first direction. In some possible implementations, the sacrificial layers 21 in the first and second regions are removed using a first trench 51, including: exposing the sidewalls of the sacrificial layers 21 using the first trench 51, and removing the sacrificial layers 21 in the first and second regions using a wet etching process. The wet etching process has a better selectivity; when removing the sacrificial layers 21 using wet etching, damage to the exposed active layers 22, active pillars 50, and substrate 10 can be avoided.

[0091] Step S50: Remove a portion of the active layer located in the second region to form a plurality of stepped connecting layers at the end of the second region away from the first region.

[0092] See Figure 9 The active layer 22 located in the second region is removed, and the remaining active layer 22 in the second region forms a connecting layer 60. Along the direction away from the substrate 10, the lengths of the multiple connecting layers 60 decrease sequentially, so that the ends of the multiple connecting layers 60 away from the first region form a stepped shape. Figure 9 As shown, the step-like shape extends upwards along a first direction and upwards along a third direction, where the first direction is perpendicular to the substrate 10. Figure 9 As shown, the Y direction is the direction parallel to the substrate 10, as... Figure 9 The X direction is shown. A portion of the surface of each connecting layer 60 is exposed to facilitate the formation of other structures on the connecting layer 60. Specifically, a portion of the surface of each connecting layer 60 facing away from the substrate 10, away from the first region, is exposed, i.e., the left end of the upper surface of each connecting layer 60 is exposed.

[0093] In some possible embodiments, removing a portion of the active layer 22 located in the second region to form a plurality of stepped interconnecting layers 60 at the end of the second region away from the first region includes: forming a second mask layer on the active layer 22, the second mask layer located in the second region having a second pattern; using the second mask layer as a mask, etching the active layer 22 located in the second region to form a plurality of stepped interconnecting layers 60 at the end of the second region away from the first region; and removing the second mask layer.

[0094] In the above embodiments, each active layer 22 corresponds to a second mask layer of different sizes. By successively shrinking the second mask layer and etching down to the corresponding active layer 22, the desired connection layer 60 is formed. Specifically, a second mask layer is first formed on the active layer 22. Using this as a mask, etching is performed down to the bottommost active layer 22, so that the bottommost active layer 22 forms the connection layer 60. Then, a portion of the second mask layer away from the first region is removed. Using the removed second mask layer as a mask, etching is performed down to the second-to-last active layer 22, so that the second-to-last active layer 22 forms the connection layer 60; ...; and so on, until the topmost active layer 22 forms the connection layer 60. Here, the bottommost layer refers to the active layer 22 closest to the substrate 10, and the topmost layer refers to the active layer 22 furthest from the substrate 10.

[0095] Step S60: Form a gate material layer covering the interconnect layer and the active pillar, wherein the gate material layers formed on the interconnect layer and the active pillar located on the same layer are interconnected, and the gate material layers formed on the interconnect layer and the active pillar located on different layers are isolated from each other.

[0096] See Figure 10 After the gate material layer 70 is formed, the gate material layer 70 on the interconnect layer 60 and the active pillar 50 disposed on the same layer are interconnected, while the gate material layer 70 on the interconnect layer 60 and the active pillar 50 disposed on different layers are isolated from each other, so that the gate material layer 70 is electrically isolated along the first direction. The multiple gate material layers 70 are stepped, and their lengths vary stepwise. Specifically, along the direction away from the substrate 10, the length of the gate material layer 70 gradually decreases.

[0097] The gate material layer 70 includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers the outer peripheral surface of the source pillar 50, and the gate conductive layer covers the outer peripheral surface of the gate dielectric layer and is integrally formed along the second direction. This portion of the gate conductive layer can be used as the gate of the transistor 2. Figure 10As shown, the gate conductive layer also extends to the connection layer 60, covering at least two opposing surfaces of the connection layer 60 along the first direction. A gate dielectric layer may also be disposed between the gate conductive layer and the connection layer 60, so that the connection layer 60 and the gate dielectric layer on the active pillar 50 are formed together, facilitating the fabrication of the gate dielectric layer. The gate dielectric layer can be made of silicon oxide, and the gate conductive layer can be made of titanium nitride. The gate conductive layer serves as word line 4, which is easy to fabricate and easy to lead out.

[0098] In some possible embodiments, a gate material layer 70 is formed to cover the interconnect layer 60 and the active pillar 50, including:

[0099] A gate dielectric layer is formed covering the surfaces of the interconnect layer 60 and the active pillar 50, with gaps between the gate dielectric layers on the surfaces of each interconnect layer 60 and each active pillar 50. Exemplarily, a gate dielectric layer is deposited on the surfaces of the interconnect layer 60 and the active pillar 50, covering the outer peripheral surface of the active pillar 50 and at least covering two surfaces of the interconnect layer 60 opposite each other along a first direction, as well as the surface facing the active pillar 50. In embodiments where the active pillar 50 includes a source, a channel, and a drain, the gate dielectric layer is opposite the channel.

[0100] A gate conductive layer is deposited to cover the surface of the gate dielectric layer. Gate conductive layers on the same layer of the gate dielectric layer are interconnected, while gate conductive layers on different layers of the gate dielectric layer are isolated from each other. That is, multiple gate conductive layers are formed, and the multiple gate conductive layers are spaced apart along a first direction. Each gate conductive layer covers the surface of the gate dielectric layer on the same layer and fills the spaces between the gate dielectric layers. The gate conductive layers form word lines 4. The gate conductive layer located in the first region serves as the gate, which is part of the word line 4. The gate conductive layer located in the second region serves as the lead-out terminal of the gate to connect to the peripheral circuit.

[0101] It should be noted that, while forming the gate material layer 70 covering the interconnect layer 60 and the active pillar 50, the process also includes: forming the gate material layer 70 on the substrate 10 located in the first region and the second region, wherein the gate material layer 70 on the substrate 10 is isolated from the gate material layer 70 on the active pillar 50 and the gate material layer 70 on the interconnect layer 60. Figure 10 As shown, there is a gap between the active pillar 50 in the first region and the substrate 10, and there is a gap between the interconnect layer 60 in the second region and the substrate 10. Therefore, when depositing the gate material layer 70, the gate material layer 70 will also cover the substrate 10 in the first and second regions. The gate material layer 70 on the substrate 10 is spaced apart from the gate material layer 70 on the active pillar 50 and spaced apart from the gate material layer 70 on the interconnect layer 60, so that each gate material layer 70 is isolated from each other.

[0102] In some possible embodiments, after forming a gate material layer 70 covering the connection layer 60 and the active pillar 50, and the gate material layers 70 formed on the connection layer 60 and the active pillar 50 located on the same layer are interconnected, and the gate material layers 70 formed on the connection layer 60 and the active pillar 50 located on different layers are isolated from each other (step S60), the method further includes: forming a plurality of spaced contact plugs 80 extending along a first direction, each contact plug 80 contacting a gate material layer 70 located in a second region.

[0103] See Figure 11 Multiple contact plugs 80 are used to connect the gate material layer 70 to the peripheral circuit. The multiple contact plugs 80 are spaced apart to ensure insulation and isolation between them, thereby avoiding mutual interference between the gate material layers 70. The multiple contact plugs 80 correspond one-to-one with the multiple gate material layers 70 and are in contact with each other, so that each gate material layer 70 can be electrically connected to the peripheral circuit, and the transistor 2 corresponding to the gate material layer 70 can be controlled by the peripheral circuit.

[0104] The contact plug 80 may include a first conductive portion and a second conductive portion disposed on the first conductive portion. The first conductive portion is the portion closer to the substrate 10, and the second conductive portion is the portion farther from the substrate 10, i.e., the second conductive portion is located on the side of the first conductive portion away from the substrate 10. Both the first and second conductive portions may include a core layer and an outer layer covering the sides and bottom of the core layer. The core layer may be an insulating layer, and its material may be silicon nitride or silicon oxide. The outer layer may be a metal layer, and its material may be tungsten or titanium nitride. This configuration reduces the thickness of the metal layer while maintaining the electrical performance of the first and second conductive portions, thus saving costs.

[0105] It should be noted that the substrate 10 in this embodiment further has a third region, which is adjacent to the first region, as shown in the figure. Figure 11 As shown at point C, capacitor 3 can be formed on the third region. Capacitor 3 is typically fabricated after the gate material layer 70 is formed.

[0106] For details, please refer to Figure 12 When a stacked structure 20 is formed on a substrate 10, the stacked structure 20 includes a sacrificial layer 21 and an active layer 22 that are alternately stacked along a first direction. The stacked structure 20 is formed on a first region, a second region and a third region of the substrate 10. The stacked structure 20 located in the first region is subsequently formed into an active pillar 50. The stacked structure 20 located in the second region is subsequently formed into a connecting layer 60. The stacked structure 20 located in the third region is subsequently formed into a support layer for a capacitor 3.

[0107] See Figure 13 and Figure 14A protective layer 30 is formed on the stacked structure 20. When a first mask layer 40 is formed on the protective layer 30, both the protective layer 30 and the first mask layer 40 are formed on the stacked structures 20 located in the first, second, and third regions. Furthermore, the protective layer 30 and the first mask layer 40 located in the third region are retained throughout the subsequent fabrication process until the gate material layer 70 is formed. This arrangement prevents damage to the active layer 22 in the third region during the fabrication of the word line 4.

[0108] In summary, in the memory fabrication method provided in this embodiment, a stacked structure 20 is formed on a substrate 10. The stacked structure 20 includes a sacrificial layer 21 and an active layer 22 alternately stacked along a first direction. The sacrificial layer 21 and part of the active layer 22 are removed, so that the active layer 22 in the first region forms a plurality of spaced active pillars 50, and the active layer 22 in the second region forms a plurality of stepped interconnect layers 60. Gate material layers 70 are then formed on the interconnect layers 60 and the active pillars 50. The gate material layers 70 formed on the interconnect layers 60 and the active pillars 50 on the same layer are interconnected, while the gate material layers 70 formed on the interconnect layers 60 and the active pillars 50 on different layers are isolated from each other. The gate material layer 70 is used as a word line 4. By setting the interconnect layers 60, it is convenient to fabricate the word line 4 and lead it out. Furthermore, since the ends of the multiple interconnect layers 60 away from the first region are stepped, the ends of the gate material layer 70 covering the active pillar 50 and the interconnect layers 60 away from the first region are also stepped, that is, the word line 4 is stepped, which makes it easier to fabricate other structures on the word line 4 to realize the electrical connection between the word line 4 and the peripheral circuit.

[0109] A second aspect of this disclosure provides a memory, see [reference] Figure 1 and Figure 11 The memory has an adjacent first region and a second region, the first region being as follows: Figure 11 As shown at point B, the second region is as follows: Figure 11 As shown at point A, the first region and the second region are adjacent, for example, the first region and the second region are adjacent and connected. A semiconductor device, such as a transistor 2, can be disposed on the first region, and a connection structure, such as a connection layer 60, can be disposed on the second region. The semiconductor device on the first region is led out through the structure on the second region so that the semiconductor device is electrically connected to a peripheral circuit. The memory includes: a plurality of connection layers 60 located in the second region and spaced apart along a first direction, with one end of each connection layer 60 away from the first region forming a stepped shape.

[0110] See Figure 11 Multiple connecting layers 60 are located in the second region and are stacked along the first direction, with the multiple connecting layers 60 spaced apart to ensure electrical isolation between them. A step is formed at the end of each connecting layer 60 away from the first region, such as... Figure 11 As shown, the left ends of the multiple interconnect layers 60 are stepped. Specifically, the stepped shape extends upwards along a first direction and upwards along a third direction, the first direction being perpendicular to the substrate 10, as shown below. Figure 11 As shown, the Y direction is the direction parallel to the substrate 10, as... Figure 11 The X direction is shown.

[0111] See some possible examples. Figure 11 Along the direction away from the substrate 10, the lengths of the plurality of interconnecting layers 60 decrease sequentially, so that the ends of the plurality of interconnecting layers 60 away from the first region form a stepped shape. Figure 11 As shown, a portion of the surface of the interconnect layer 60 in each layer is exposed to facilitate the formation of other structures on the interconnect layer 60. Specifically, a portion of the surface of the interconnect layer 60 facing away from the substrate 10, away from the first region, is exposed.

[0112] Continue reading Figure 11 The memory further includes: a plurality of active pillar layers located in the first region and spaced apart along the first direction, each active pillar layer being disposed on the same layer as a connection layer 60; each active pillar layer having a plurality of spaced active pillars 50, and each active pillar 50 extending along the second direction.

[0113] like Figure 11 As shown, multiple active pillar layers are located in the first region and are stacked along the first direction. The multiple active pillar layers 50 are spaced apart to ensure electrical isolation between them. Each of the multiple active pillar layers corresponds to a multiple interconnecting layer 60, and the corresponding active pillar layer and interconnecting layer 60 are disposed on the same layer to facilitate the formation of a gate material layer 70 on the active pillar layer and interconnecting layer 60.

[0114] like Figure 11 As shown, each active pillar layer includes a plurality of spaced-apart active pillars 50 extending along a second direction. The plurality of active pillars 50 are arranged in an array; specifically, the plurality of active pillars 50 are spaced-apart along a first direction and also spaced-apart along a third direction, which intersects the first direction and is perpendicular to the second direction. The second direction is parallel to the substrate 10; for example, the second direction is... Figure 1 As shown in the horizontal direction (Z direction), the first direction, the second direction, and the third direction are perpendicular to each other. This arrangement allows for a more compact arrangement of the active pillars 50, maximizing the number of active pillars 50 that can be arranged. The shape of the active pillars 50 can be a cylinder, prism, cuboid, or other shape, and is not limited in this embodiment.

[0115] Continue reading Figure 11The memory also includes a gate material layer 70 located on the interconnect layer 60 and the active pillar 50, wherein the gate material layers 70 formed on the interconnect layer 60 and the active pillar 50 located on the same layer are interconnected, and the gate material layers 70 formed on the interconnect layer 60 and the active pillar 50 located on different layers are isolated from each other.

[0116] like Figure 11 As shown, the interconnect layer 60 and the gate material layer 70 on the active pillar 50 are interconnected, while the interconnect layer 60 and the gate material layer 70 on the active pillar 50 are isolated from each other, so that the gate material layer 70 is electrically isolated along the first direction. Since the interconnect layer 60 is stepped, the multiple gate material layers 70 are also stepped, with their lengths varying in a stepped manner, to facilitate the formation of other structures on the gate material layer 70, thereby leading out the gate material layer 70. Specifically, the length of the gate material layer 70 gradually decreases along the direction away from the substrate 10.

[0117] The gate material layer 70 includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers the outer peripheral surface of the source pillar 50, and the gate conductive layer covers the outer peripheral surface of the gate dielectric layer and is integrally formed along the second direction. This portion of the gate conductive layer can be used as the gate of the transistor 2. Figure 11 As shown, the gate conductive layer also extends to the connection layer 60, covering at least two opposing surfaces of the connection layer 60 along the first direction. A gate dielectric layer may also be disposed between the gate conductive layer and the connection layer 60, so that the connection layer 60 and the gate dielectric layer on the active pillar 50 are formed together, facilitating the fabrication of the gate dielectric layer. The gate dielectric layer can be made of silicon oxide, and the gate conductive layer can be made of titanium nitride. The gate conductive layer serves as word line 4, which is easy to fabricate and easy to lead out.

[0118] In some possible embodiments, the memory further includes a plurality of spaced contact plugs 80 extending along a first direction, each contact plug 80 being in contact with a gate material layer 70 located in a second region.

[0119] For details, please refer to Figure 11 Multiple contact plugs 80 are used to connect the gate material layer 70 to the peripheral circuit. The multiple contact plugs 80 are spaced apart to ensure insulation and isolation between them, thereby avoiding mutual interference between the gate material layers 70. The multiple contact plugs 80 correspond one-to-one with the multiple gate material layers 70 and are in contact with each other, so that each gate material layer 70 can be electrically connected to the peripheral circuit, and the transistor 2 corresponding to the gate material layer 70 can be controlled by the peripheral circuit.

[0120] The contact plug 80 may include a first conductive portion and a second conductive portion disposed on the first conductive portion. The first conductive portion is the portion closer to the substrate 10, and the second conductive portion is the portion farther from the substrate 10, i.e., the second conductive portion is located on the side of the first conductive portion away from the substrate 10. Both the first and second conductive portions may include a core layer and an outer layer covering the sides and bottom of the core layer. The core layer may be an insulating layer, and its material may be silicon nitride or silicon oxide. The outer layer may be a metal layer, and its material may be tungsten or titanium nitride. This configuration reduces the thickness of the metal layer while maintaining the electrical performance of the first and second conductive portions, thus saving costs.

[0121] In some possible embodiments, the memory further includes a third region adjacent to the first region. The memory also includes a plurality of spaced capacitors 3 located in the third region, the capacitors 3 extending along a second direction, and each capacitor 3 being electrically connected to an active post 50. Specifically, the third region and the first region may be along the second direction (…). Figure 11 As shown in the Z direction, the third region is provided with multiple capacitors 3 spaced apart, and the multiple capacitors 3 correspond one-to-one with and are electrically connected to multiple active columns 50.

[0122] The memory provided in this embodiment of the present disclosure has gate material layers 70 disposed on the interconnect layer 60 and the active pillar 50. The gate material layers 70 formed on the interconnect layer 60 and the active pillar 50 located on the same layer are interconnected, while the gate material layers 70 formed on the interconnect layer 60 and the active pillar 50 located on different layers are isolated from each other. The gate material layer 70 serves as a word line 4. By providing the interconnect layer 60, it is convenient to fabricate the word line 4 and lead it out. In addition, since the ends of the multiple interconnect layers 60 away from the first region are formed in a stepped shape, the ends of the gate material layers 70 covering the active pillar 50 and the interconnect layer 60 away from the first region are also formed in a stepped shape, that is, the word line 4 is stepped, which facilitates the fabrication of other structures on the word line 4 to realize the electrical connection between the word line 4 and the peripheral circuit.

[0123] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method of fabricating a memory, comprising: The method comprises the following steps: providing a substrate; forming a stack structure on the substrate, the stack structure comprising sacrificial layers and active layers alternately stacked along a first direction; removing part of the stack structure in a first region to form a plurality of first trenches spaced apart and extending along a second direction, the first trenches exposing the substrate to separate the active layers in the first region into a plurality of active pillars spaced apart; using the first trenches, removing the sacrificial layers in the first region and a second region to make the active pillars in the first region and the active layers in the second region spaced apart along the first direction, wherein the second region is adjacent to the first region; removing part of the active layers in the second region to form a plurality of connection layers in a stepped manner at an end of the second region away from the first region; forming a gate material layer covering the connection layers and the active pillars, and the gate material layers formed on the connection layers and the active pillars in the same layer are connected to each other, and the gate material layers formed on the connection layers and the active pillars in different layers are isolated from each other.

2. The method of manufacturing according to claim 1, wherein, The lengths of the plurality of connection layers gradually decrease in a direction away from the substrate, so that the plurality of connection layers form a stepped manner at an end away from the first region.

3. The method of making of claim 1, wherein, forming a stack structure on the substrate comprises: alternately repeating the formation of one layer of the sacrificial layer and one layer of the active layer on the substrate until the stack structure is formed, and the innermost layer of the stack structure close to the substrate is the sacrificial layer, and the outermost layer of the stack structure away from the substrate is the active layer.

4. The method of making of claim 1, wherein, The sacrificial layers and the active layers are formed by an epitaxial growth process from the substrate.

5. The method of manufacturing according to claim 4, wherein, The material of the active layer comprises N-doped silicon, and the material of the sacrificial layer comprises germanium silicon.

6. The method of making of claim 1, wherein, The method for removing part of the stack structure in the first region to form a plurality of first trenches spaced apart and extending along the second direction comprises: etching the stack structure in the first region to form the first trenches, the first trenches penetrating through the stack structure.

7. The method of manufacturing according to claim 6, wherein, The method for etching the stack structure in the first region to form the first trenches, the first trenches penetrating through the stack structure, comprises: forming a first mask layer on the stack structure, the first mask layer in the first region having a first pattern; using the first mask layer as a mask, etching the stack structure in the first region to form the first trenches.

8. The method of manufacturing according to claim 7, wherein, The method for removing the sacrificial layers in the first region and the second region using the first trenches comprises: exposing the side walls of the sacrificial layers using the first trenches, and removing the sacrificial layers in the first region and the second region by a wet etching process.

9. The method of manufacturing according to claim 7, wherein, The method for forming the first mask layer on the stack structure comprises: forming a protection layer on the stack structure, and forming the first mask layer on the protection layer.

10. The method of manufacturing according to claim 9, wherein, The method for etching the stack structure in the first region using the first mask layer as a mask comprises: Etching the protection layer in the first region as a mask to transfer the first pattern to the protection layer; Removing the first mask layer to continue etching the stack structure with the patterned protection layer.

11. The method of making according to any one of claims 1-10, wherein, Removing part of the active layer in the second region to form a plurality of connection layers in a stepped shape at an end of the second region away from the first region, comprising: Forming a second mask layer on the active layer, the second mask layer in the second region having a second pattern; Etching the active layer in the second region as a mask to form a plurality of connection layers in a stepped shape at an end of the second region away from the first region; Removing the second mask layer.

12. The method of making according to any one of claims 1-10, wherein, Forming a gate material layer covering the connection layers and the active columns, comprising: Forming a gate dielectric layer covering the surfaces of the connection layers and the active columns, the gate dielectric layers on the surfaces of each of the connection layers and each of the active columns having gaps therebetween; Depositing a gate conductive layer covering the surfaces of the gate dielectric layers.

13. The method of manufacturing according to claim 12, wherein, The gate conductive layers on the gate dielectric layers arranged in the same layer are in communication with each other, and the gate conductive layers on the gate dielectric layers arranged in different layers are isolated from each other.

14. The method of manufacturing according to claim 12, wherein, Simultaneously with forming the gate material layer covering the connection layers and the active columns, further comprising: Forming the gate material layer on the substrate in the first region and the second region, the gate material layer on the substrate being isolated from the gate material layer on the active columns and the gate material layer on the connection layers.

15. The method of making according to any one of claims 1-10, wherein, After forming the gate material layer covering the connection layers and the active columns, and the gate material layers formed on the connection layers and the active columns in the same layer being in communication with each other and the gate material layers formed on the connection layers and the active columns in different layers being isolated from each other, further comprising: Forming a plurality of contact plugs arranged at intervals and extending along the first direction, each of the contact plugs being in contact with one of the gate material layers in the second region.

16. A memory, comprising: The memory has adjacent first and second regions, and the memory comprises: A plurality of connection layers in the second region and arranged at intervals along a first direction, and a plurality of the connection layers forming a stepped shape at an end away from the first region; A plurality of active column layers in the first region and arranged at intervals along the first direction, each of the active column layers being arranged in the same layer as one of the connection layers; each of the active column layers having a plurality of active columns arranged at intervals, and each of the active columns extending along a second direction; A gate material layer on the connection layers and on the active columns, and the gate material layers formed on the connection layers and the active columns in the same layer being in communication with each other and the gate material layers formed on the connection layers and the active columns in different layers being isolated from each other.

17. The memory of claim 16, wherein, The memory further has a third region adjacent to the first region, and the memory further comprises: A plurality of capacitors arranged at intervals in the third region, the capacitors extending along the second direction, and each of the capacitors being electrically connected to one of the active columns.

18. The memory of claim 16 or 17, wherein, The memory also includes: a plurality of contact plugs spaced apart and extending along the first direction, each of the contact plugs being in contact with one of the gate material layers located in the second region.

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