storage device

Abstract

A storage device of one embodiment includes a first conductor, a first memory pillar, a second conductor, a third conductor, a second memory pillar, a fourth conductor, and a fifth conductor. The first conductor extends along a first axis and a second axis. The first memory pillar is provided inside the first conductor and includes a first semiconductor and a charge accumulation layer around the first semiconductor. The second conductor extends along the second axis and is connected to the first memory pillar. The third conductor extends along the first axis and the second axis and is arranged apart from the first conductor along the second axis. The second memory pillar is provided inside the third conductor and includes a second semiconductor and a charge accumulation layer around the second semiconductor. The fourth conductor extends along the second axis and is connected to the second memory pillar. The fifth conductor extends along the second axis and is connected to the first memory pillar and the second memory pillar.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-47429 (filed on March 23, 2022). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation generally relates to a storage device. Background Technology

[0004] A storage device is known to contain storage cells arranged in three dimensions. The storage device needs to operate at high speed. Summary of the Invention

[0005] The embodiment provides a storage device capable of high-speed operation.

[0006] A storage device according to one embodiment includes a first conductor, a first memory pillar, a second conductor, a third conductor, a second memory pillar, a fourth conductor, and a fifth conductor. The first conductor extends along a first axis and a second axis. The first memory pillar is disposed inside the first conductor and includes a first semiconductor and a charge accumulation layer surrounding the first semiconductor. The second conductor extends along the second axis and is in contact with the first memory pillar. The third conductor extends along the first axis and is arranged at a distance from the first conductor along the second axis. The second memory pillar is disposed inside the third conductor and includes a second semiconductor and a charge accumulation layer surrounding the second semiconductor. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is connected to the first memory pillar and the second memory pillar. Attached Figure Description

[0007] Figure 1 Examples of the constituent elements and connections of the storage device according to the first embodiment are shown.

[0008] Figure 2 This describes the constituent elements of a block of the storage device according to the first embodiment and the connections between the constituent elements.

[0009] Figure 3 The components of the drive of the storage device in the first embodiment are shown.

[0010] Figure 4 The components of the sensing amplifier of the storage device according to the first embodiment and the connections of the components are shown.

[0011] Figure 5The layout of the storage device in the first embodiment is shown.

[0012] Figures 6 to 10 The layout and several constituent elements of a portion of the storage device according to the first embodiment are shown respectively.

[0013] Figure 11 An example of a planar layout representing a portion of the storage cell array of the storage device of the first embodiment.

[0014] Figures 12 to 14 The images show cross-sectional views of a portion of the storage device according to the first embodiment.

[0015] Figure 15 An example of the detailed structure of a cross-section of a portion of the storage device according to the first embodiment.

[0016] Figure 16 This shows a cross-sectional structure of the storage cell array of the storage device according to the first embodiment.

[0017] Figure 17 This section illustrates the constituent elements of the storage device according to the first embodiment and an example of assigning addresses to the constituent elements.

[0018] Figure 18 This section illustrates the constituent elements in the storage cell array of the storage device according to the first embodiment, and an example of assigning addresses to the constituent elements.

[0019] Figure 19 This section illustrates an example of the selection of constituent elements in the storage cell array of the storage device according to the first embodiment.

[0020] Figure 20 This describes the constituent elements of the line decoder of the storage device according to the first embodiment, and the connections between these constituent elements.

[0021] Figure 21 The components of the line decoder of the storage device of the first embodiment and the connections of the components are shown in more detail.

[0022] Figure 22 This describes the constituent elements of the line decoder of the storage device according to the first embodiment, and the connections between these constituent elements.

[0023] Figure 23 This indicates a state during operation of the storage device in the first embodiment.

[0024] Figure 24 The cross-sectional structure of the storage device is shown in the first variation of the first embodiment.

[0025] Figure 25 The cross-sectional structure of the storage device is shown in the second variation of the first embodiment.

[0026] Figure 26 The cross-sectional structure of the storage device is shown in the third variation of the first embodiment.

[0027] Figure 27 The cross-sectional structure of the storage device is shown in the third variation of the first embodiment.

[0028] Figure 28 The layout and several constituent elements of a portion of the storage device of the fourth variation of the first embodiment are shown.

[0029] Figure 29 The cross-sectional structure of the storage device is shown in the fourth variation of the first embodiment.

[0030] Figure 30 The layout and several constituent elements of a portion of the storage device of the fifth variation of the first embodiment are shown.

[0031] Figure 31 The cross-sectional structure of the storage device is shown in the fifth variation of the first embodiment.

[0032] Figure 32 The layout and several constituent elements of a portion of the storage device of the sixth variation of the first embodiment are shown.

[0033] Figure 33 The cross-sectional structure of the storage device in the sixth variation of the first embodiment is shown.

[0034] Figures 34 to 39 Examples of signals transmitted and received between the storage device and the memory controller in the second embodiment are shown respectively.

[0035] Figure 40 This indicates a state during operation of the storage device in the second embodiment.

[0036] Figure 41 This indicates a state during operation of the storage device in the second embodiment.

[0037] Figure 42 This describes the constituent elements of the line decoder of the storage device according to the third embodiment, and the connections between these constituent elements.

[0038] Figure 43 The components of the drive of the storage device according to the third embodiment and the connections of the components are shown.

[0039] Figure 44 This indicates a state during operation of the storage device in the third embodiment.

[0040] Figure 45 The components of the drive of the storage device according to the fourth embodiment and the connections of the components are shown.

[0041] Figure 46 and Figure 47 The layout and several constituent elements of a portion of the storage device according to the fifth embodiment are shown respectively.

[0042] Figure 48 This shows a cross-sectional view of a portion of the storage device according to the fifth embodiment.

[0043] Figure 49 This section illustrates the constituent elements in the storage cell array of the storage device according to the fifth embodiment, and an example of assigning addresses to the constituent elements.

[0044] Figure 50 This describes the constituent elements of the line decoder of the storage device according to the fifth embodiment, and the connections between these constituent elements.

[0045] Figure 51 and Figure 52 Examples of signals transmitted and received between the storage device and the memory controller in the fifth embodiment are shown respectively.

[0046] Figure 53 This indicates a state during operation of the storage device in the fifth embodiment. Detailed Implementation

[0047] In the following description, in embodiments following a previously described embodiment, the differences from the previously described embodiment will be primarily described. Unless explicitly or obviously excluded, a description of a particular embodiment is also suitable as a description of another embodiment. Therefore, a description of a particular embodiment, except where necessary, will generally not include the same content as a description of previous embodiments. Multiple constituent elements having substantially the same function and structure in a particular embodiment or across different embodiments are sometimes distinguished by appending numbers or words to the end of the reference numerals.

[0048] The accompanying drawings are schematic; the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc., may differ from the actual object. The drawings may also contain parts with different dimensional relationships or ratios.

[0049] In this specification and claims, a first element being "connected" to another second element includes the first element being directly connected to the second element, or being connected to the second element always or temporarily via a conductive element.

[0050] The following description uses an orthogonal xyz coordinate system. Sometimes the positive direction of the vertical axis of the graph is called the top, and the negative direction is called the bottom. Sometimes the positive direction of the horizontal axis of the graph is called the right side, and the negative direction is called the left side.

[0051] 1. First Implementation Method

[0052] 1.1. Composition (Structure)

[0053] 1.1.1. Storage device

[0054] Figure 1 This illustrates the constituent elements of the storage device 1 according to the first embodiment and examples of the connections between these elements. Additionally, Figure 1 It also refers to the memory controller 2 that controls the storage device 1.

[0055] Storage device 1 is connected to memory controller 2 via a NAND (Not AND) interface-based wiring. The NAND interface-based wiring transmits multiple control signals and 8-bit input / output signals DQ. The control signals include signal... - CE, CLE, ALE - WE - RE、 - WP, DQS, - DQS and the Standby / Busy signal RB. Symbol " - "" indicates inversion logic. Storage device 1 receives input / output signal DQ and sends input / output signal DQ. Input / output signal DQ contains instruction (CMD), data (DAT), and address information (ADD).

[0056] Signal - CE activates storage device 1. The CLE signal instructs storage device 1 to send the input / output signal DQ. The ALE signal instructs storage device 1 to send the address information for the input / output signal DQ. The WE signal instructs storage device 1 to capture the input / output signal DQ. The RE signal instructs storage device 1 to output the input / output signal DQ. The standby / busy signal RB indicates whether storage device 1 is in standby or busy mode; a low level indicates busy mode. Storage device 1 accepts commands when in standby mode and does not accept commands when in busy mode.

[0057] The storage device 1 is configured as a single chip, for example. The storage device 1 includes multiple memory planes PLN, registers 12, sequencers 13, voltage generation circuits 14, and drivers 15, etc. The multiple memory planes PLN are, for example, four memory planes PLN_0, PLN_1, PLN_2, and PLN_3.

[0058] Each memory surface PLN is a collection of multiple components. A memory surface PLN is a unit (memory area) for writing and reading data. Memory surfaces PLN_0 to PLN_3 can operate independently of each other. Memory surfaces PLN_0 to PLN_3 can also operate in parallel. In other words, the storage device 1 has multiple memory areas that can be controlled independently of each other. Each memory surface PLN contains a group of the same components, including the memory cell array 10, the line decoder 11, and the sense amplifier 17.

[0059] Register 12 is a circuit that stores the instruction CMD and address information ADD received by storage device 1. The instruction CMD instructs storage device 1 to perform various operations, including data reading, data writing, and data erasure. The address information ADD specifies the object of the data reading, data writing, and data erasure. The address information ADD may include, for example, a memory plane address, a block address, a page address, and a column address. The memory plane address specifies a memory plane PLN. The block address specifies a block BLK. The page address specifies a string component SU, a word line WL, and a page. The page address specifies the string component SU, the word line WL, and the page in different parts. The part of the page address specifying the word line WL is called the word line address. The column address specifies a bit line BL.

[0060] The sequencer 13 is a circuit that controls the overall operation of the storage device 1. Based on the instruction CMD received from the register 12, the sequencer 13 controls the voltage generation circuit 14, the line decoder 11, and the sensing amplifier 17 to perform various operations including data reading, data writing, and data erasure.

[0061] The voltage generation circuit 14 is a circuit that generates multiple voltages of different magnitudes. The voltage generation circuit 14 receives a power supply voltage from an external source of the storage device 1 and generates multiple voltages from that power supply voltage. The generated voltages are supplied to components such as the storage cell array 10 and the driver 15.

[0062] The driver 15 is a circuit that applies various voltages required for the storage device 1 to operate to several components. The driver 15 receives multiple voltages from the voltage generation circuit 14 and supplies a selected voltage from the multiple voltages to one or more line decoders 11.

[0063] The memory cell array 10 of each memory plane PLN is a collection of arranged memory cells. The memory cell array 10 contains n blocks BLK, namely BLK_0, BLK_1, ..., BLK_n-1. Each block BLK contains multiple memory cell transistors MT (not shown). Word lines WL (not shown) and bit lines BL (not shown) are also located in the memory cell array 10.

[0064] The row decoder 11 is a circuit used to select a block BLK. The row decoder 11 of each memory plane PLN functions to operate on the memory plane PLN containing the row decoder 11. The row decoder 11 transmits the voltage supplied by the driver 15 to one block BLK selected based on the block address received from register 12.

[0065] The sense amplifier 17 is a circuit that outputs a signal based on data stored in the memory cell transistor MT. The sense amplifier 17 of each memory plane PLN functions to operate in the memory plane PLN containing the memory cell array 10. The sense amplifier 17 senses the state of the memory cell transistor MT and generates read data or transmits write data to the memory cell transistor MT based on the sensed state.

[0066] 1.1.2. Storage Cell Array

[0067] Figure 2 This represents the constituent elements of a block BLK_0 in the first embodiment and the connections between these constituent elements. Multiple blocks BLK, for example, all blocks BLK contain... Figure 2 The constituent elements and connections are shown.

[0068] One block BLK contains multiple string components SU, such as four string components SU_0 to SU_3.

[0069] Each of the m bit lines BL_0 to BL_m-1 is connected in each block BLK to one NAND string NS from each of the string components SU_0 to SU_3. m is a positive integer, for example, 16kB, which is 16 × 1024 × 8. The following description is based on this example.

[0070] Each NAND string NS includes one select-gate transistor ST, multiple memory cell transistors MT, and one select-gate transistor DT. The multiple memory cell transistors MT are, for example, eight memory cell transistors MT0 to MT7. Each memory cell transistor MT is a device that includes a control gate electrode and a charge accumulation layer insulated from the surroundings, and non-volatilely stores data based on the amount of charge in the charge accumulation layer. Transistors ST, MT, and DT are connected in series between the source line SL and a bit line BL.

[0071] Multiple different bit lines BL and their respective connected NAND strings NS constitute a string assembly SU. In each string assembly SU, the control gate electrodes of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. A group of memory cell transistors MT sharing a word line WL in a string assembly SU is called a cell assembly CU. Each cell assembly CU stores one or more pages of data. If each memory cell transistor MT of a cell assembly CU stores 1 bit of data, that cell assembly CU stores 1 page of data. Similarly, if each memory cell transistor MT of a cell assembly CU stores p bits of data, that cell assembly CU stores p pages of data. Here, p is an integer greater than 2. An example of storing 1 bit of data per memory cell transistor MT is described below for ease of understanding. Therefore, one cell assembly CU is allocated only one page address.

[0072] If we take an example where the number of bit lines m is 16kB, then the size of one page is 16kB.

[0073] In each block BLK, the memory cell transistors MT0 to MT7 of any string component SU are connected to word lines WL0 to WL7 respectively.

[0074] Gate transistors DT0 to DT3 are selected to belong to string components SU_0 to SU_3, respectively. Figure 2 In the diagram, DT2 and DT3 are not shown. The gates of the select gate transistors DT0 of each of the multiple NAND strings NS in string assembly SU_0 are connected to the select gate line SGDL0. Similarly, the gates of the select gate transistors DT1, DT2, and DT3 of each of the multiple NAND strings NS in string assemblies SU_1, SU_2, and SU_3 are connected to the select gate lines SGDL1, SGDL2, and SGDL3, respectively.

[0075] The gate of the select gate transistor ST is connected to the select gate line SGSL.

[0076] 1.1.3. Driver

[0077] Figure 3 The components of the drive 15 of the storage device 1 in the first embodiment are shown. For example... Figure 3As shown, driver 15 includes a source line driver SLD. The source line driver SLD includes an n-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) Tr1. Transistor Tr1 is connected at one end to voltage generation circuit 14. Transistor Tr1 is connected at the other end to the source line SL, i.e., a conductor that functions as part of the source line SL. Transistor Tr1 receives a control signal S1 at its gate. Transistor Tr1 receives the control signal S1, for example, from the sequencer 13 or from components of driver 15 other than the source line driver SLD.

[0078] 1.1.4. Sensing Amplifier

[0079] Figure 4 This describes the components of the sensing amplifier in the storage device 1 of the first embodiment and the connections between these components. For example... Figure 4 As shown, the sensing amplifier 17 includes multiple sensing amplifier circuits SAC. The sensing amplifier 17 contains m sensing amplifier circuits SAC, that is, the number of sensing amplifier circuits SAC is the same as the number of bit lines BL. Each sensing amplifier circuit SAC is connected to one bit line BL. That is, one sensing amplifier circuit SAC is connected to each bit line BL.

[0080] The sense amplifier circuit (SAC) outputs a signal based on the voltage across the bit line BL to which it is connected. During data readout, a storage cell transistor MT, to which the data to be read is connected, is positioned on the bit line BL. A voltage is generated on the bit line BL based on the data stored in the storage cell transistor MT. The sense amplifier circuit (SAC) outputs a signal based on this voltage on the bit line BL. The output signal represents the data stored in the storage cell transistor MT to be read.

[0081] 1.1.5. Layout of storage devices

[0082] Figure 5 The layout of the storage device according to the first embodiment is shown. As described below, the storage device 1 includes multiple layers arranged along the z-axis. The layout of these layers is also based on reference... Figure 5 The area described.

[0083] like Figure 5 As shown, storage device 1 extends along the xy plane. Storage device 1 has a quadrilateral shape along the xy plane. Storage device 1 has two sides facing each other along the y-axis and two sides arranged along the x-axis. The lower side of the two sides facing each other along the y-axis is called the lower side DS, and the upper side is called the upper side US.

[0084] Storage device 1 has a pad region PPA along its lower edge DS. The pad region PPA is a region in a layer containing the pad EPD described below, located at a certain coordinate on the z-axis.

[0085] Storage device 1 includes multiple memory surface regions PNA between the pad region PPA and the upper edge US. For example, it includes four memory surface regions PNA. The memory surface regions PNA are arranged along the x-axis. Each memory surface region PNA has substantially the same size. In this specification and claims, "substantially the same" means that although the intent is the same, errors due to unavoidable reasons are permissible.

[0086] Each memory surface region (PNA) contains two sub-memory surface regions (SPNAs). Regarding the SPNAs, within each PNA, the two SPNAs are arranged along the y-axis. The SPNAs located on the upper and lower sides of the y-axis within these two SPNAs are sometimes referred to as SPNAu and SPNAd, respectively.

[0087] The upper region UEA is located between the upper edge US of storage device 1 and the upper edge of the group of memory surface region PNA.

[0088] Each memory plane region PNA contains the constituent elements of one memory plane PLN from PLN_0 to PLN_3, namely, a memory cell array 10, a row decoder 11, and a sense amplifier 17. The memory cell array 10, the row decoder 11, and the sense amplifier 17 formed in a certain memory plane region PNA are sometimes referred to as "the memory cell array 10 corresponding to the memory plane region PNA", "the row decoder 11 corresponding to the memory plane region PNA", and "the sense amplifier 17 corresponding to the memory plane region PNA", respectively.

[0089] Figures 6 to 10 This diagram shows the layout and several constituent elements of a portion of the storage device according to the first embodiment. Figures 6 to 10 This represents one memory plane region (PNA). Four memory plane regions (PNAs) have the same structure. Figures 6 to 10 This represents the region with different coordinates on the z-axis. Figures 6 to 10 Each element is sometimes represented by a dashed line, indicating the region shown in the diagram and the constituent elements of regions with different coordinates on the z-axis. Figure 6 express Figures 6-10 The region shown is the area along the lowest point of the z-axis, and represents the area containing the surface of the semiconductor substrate described below. Figure 7 Indicates and Figure 6 The region shown is higher up on the z-axis. Figure 8 Indicates and Figure 7The region shown is higher up on the z-axis. Figure 9 Indicates and Figure 6 The region shown is higher up compared to along the z-axis and is... Figure 7 The region shown is further down along the z-axis. Figure 10 Indicates and Figure 9 The region shown is higher up compared to along the z-axis and is... Figure 7 The region shown is further down along the z-axis.

[0090] like Figure 6 As shown, the memory plane region PNA includes the row decoder region RDA in both the left and right portions. The left and right row decoder regions RDA are sometimes referred to as row decoder regions RDA1 and RDA1, respectively. The row decoder region RDA is the region in which the row decoder 11 is formed.

[0091] The memory plane region PNA includes a sense amplifier region SAA. The sense amplifier region SAA has the constituent elements of a sense amplifier 17 corresponding to the memory plane region PNA to which the sense amplifier region SAA belongs. The sense amplifier region SAA, for example, faces the boundary of two sub-memory plane regions SPNA in a memory plane region PNA.

[0092] The sub-memory plane region SPNAu contains the source line driver region SDRA. The source line driver region SDRA extends along the upper end of the sub-memory plane region SPNAu and along the x-axis. A source line driver SLD is disposed within the source line driver region SDRA. A contact plug CP5 is disposed within the source line driver region SDRA. The contact plug CP5 is connected to the source line driver SLD via a conductor on its lower surface.

[0093] like Figure 7 As shown, each sub-memory plane region SPNA contains a sub-memory cell array SMCA. The sub-memory cell array SMCA contained in sub-memory plane regions SPNAu and SPNAd are sometimes referred to as sub-memory cell arrays SMCAu and SMCAd, respectively. The sub-memory cell array SMCA in the two sub-memory plane regions SPNA that constitute one memory plane region PNA is provided with the constituent elements of the memory cell array 10 corresponding to that memory plane region PNA.

[0094] The memory surface region PNA includes a word line connection area WHUA in both its left and right portions. The left and right word line connection areas WHUA are sometimes referred to as word line connection areas WHUAl and WHUAr, respectively. The word line connection area WHUA is the area where the contact plug connects to the conductor 44, which functions as a word line WL. The word line connection areas WHUAl and WHUAr extend along the y-axis. For example, the width (dimension along the x-axis) of the word line connection areas WHUAl and WHUAr is smaller than the width (dimension along the x-axis) of the line decoder areas RDAAl and RDAAr.

[0095] like Figure 8 As shown, multiple conductors CD1 and CD2 are disposed in the sub-memory surface regions SPNAu and SPNAd. Conductors CD1 and CD2 extend along the y-axis. Conductors CD1 and CD2 are arranged alternately along the x-axis.

[0096] Conductor CD1 is continuous across sub-memory surface regions SPNAu and SPNAd. Conductor CD1 functions as part of the source line SL. One end of conductor CD1 is located in the upper region UEA. Conductor CD1 is connected to the conductive bonding pad PD2 in the upper region UEA via a conductor.

[0097] One end of conductor CD2 is located in pad region PPA. A portion of conductor CD2 within pad region PPA functions as pad EPD. Pad EPD functions as one of the external connection terminals of storage device 1. Conductor CD2 overlaps with contact plug CP2 in pad region PPA. The other end of conductor CD2 is located in upper region UEA. Conductor CD2 is connected to contact plug CP3 in upper region UEA.

[0098] like Figure 9 As shown, multiple conductors CD3 are disposed in the sub-memory surface region SPNAd. Conductors CD3 extend along the y-axis. One end of conductor CD3 is located in the pad region PPA. Conductors CD3 overlap with contact plug CP2 in the pad region PPA. Conductors CD3 are connected to contact plug CP2 in the pad region PPA via conductors.

[0099] Multiple conductors CD5 and CD6 are disposed in the sub-memory surface region SPNAu. Conductors CD5 and CD6 extend along the y-axis. Conductors CD5 and CD6 are arranged alternately along the x-axis.

[0100] One end of conductor CD5 is located in the upper region UEA. Conductor CD5 is located in the upper region UEA and... Figure 8Conductor CD1 overlaps. Conductor CD5 overlaps with bonding pad PD1 in the upper region UEA. The other end of conductor CD5 is located in the source line driver region SDRA. Conductor CD5 overlaps with contact plug CP6 in the source line driver region SDRA.

[0101] One end of conductor CD6 is located in the upper region UEA. Conductor CD6 is located in the upper region UEA and... Figure 8 Conductor CD2 overlaps. Conductor CD6 overlaps with contact plug CP3 in the upper region UEA.

[0102] Multiple conductors 26a and 26b are disposed in the sub-memory surface regions SPNAu and SPNAd. Conductors 26a and 26b extend along the y-axis, spanning both sub-memory surface regions SPNAu and SPNAd. Conductor 26a is located in the region encompassing the left end of sub-memory surface regions SPNAu and SPNAd. Conductors 26a are arranged along the x-axis. Conductors 26b are located in the region encompassing the right end of sub-memory surface regions SPNAu and SPNAd. Conductors 26b are arranged along the x-axis.

[0103] like Figure 10 As shown, multiple conductors 37 are disposed in each of the sub-memory surface regions SPNAu and SPNAd. The conductors 37 extend along the y-axis and are arranged along the x-axis. None of the conductors 37 in sub-memory surface region SPNAu are connected to any of the conductors 37 in sub-memory surface region SPNAd. For example, a conductor 37 in sub-memory surface region SPNAu may be located on the extension line of a conductor 37 in sub-memory surface region SPNAd.

[0104] Figure 11 An example of a planar layout showing a portion of the storage cell array 10 of the storage device 1 in the first embodiment. Figure 11 This indicates the region containing the ends of the conductors that function as select gate line SGSL, word lines WL0 to WL7, and select gate line SGDL. Figure 11 This represents a region consisting of one block (BLK).

[0105] like Figure 11 As shown, the memory cell array 10 includes a memory region MA and a word line connection region WHUA. The word line connection region WHUA and the memory region MA are arranged along the x-axis. Multiple conductors 44 and multiple components SLT and SHE are disposed in the memory cell array 10. Each conductor 44 functions as a select gate line SGSL, word lines WL0 to WL7, or select gate line SGDL.

[0106] The memory region MA is a region containing multiple NAND strings NS, and is a region forming a sub-memory cell array SMCA. Multiple memory pillars MP are disposed within the memory region MA. As described below, the memory pillar MP is a structure that functions as part of the memory cell transistor MT.

[0107] Multiple component SLTs extend along the x-axis and are arranged along the y-axis. Each component SLT is located at the boundary between adjacent blocks BLK. Each component SLT has, for example, a structure in which an insulator SP and / or a plate-like contact LI are embedded. Figure 11 This illustrates an example where component SLT comprises both an insulator SP and a plate-shaped contact LI. The insulator SP covers the sides of the contact LI. Each component SLT divides the conductor 44.

[0108] Multiple components SHE extend along the x-axis and are arranged along the y-axis. Multiple components SHE are located between each pair of adjacent components SLT. Figure 11 This example illustrates four components SHE. Each component SHE has its two ends located within the word line wiring area WHUA. Each component SHE includes, for example, an insulator. Each component SHE breaks at least one of a plurality of conductors 44. The areas separated by components SLT and SHE form a region containing a string assembly SU.

[0109] The select gate line SGSL, word lines WL0-WL7, and select gate line SGDL have different lengths along the x-axis. Therefore, in the word line wiring area WHUA, the ends of the select gate lines SGSL, WL0-WL7, and SGDL are located at different coordinates on the x-axis. Consequently, each of the select gate lines SGSL, WL0-WL7, and SGDL has a portion that does not overlap with any of the select gate lines SGSL, WL0-WL7, and SGDL. This non-overlapping portion of each of the select gate lines SGSL, WL0-WL7, and SGDL is called a stepped portion. Each of the select gate lines SGSL, WL0-WL7, and SGDL is connected to a contact plug (not shown) at the stepped portion.

[0110] 1.1.6. Cross-sectional structure of the storage device

[0111] Figure 12 This shows a cross-sectional view of a portion of the storage device 1 according to the first embodiment. Specifically, Figure 12 Indicates along Figures 8-10 The cross section of line XII-XII.

[0112] like Figure 12As shown, the storage device 1 includes a first structure 100, a second structure 200, and a third structure 300 arranged along the z-axis. The first structure 100 and the second structure 200 are constructed by being manufactured separately and joined together. Figure 12 The structure shown is as follows. That is, a second structure 200 is formed on a semiconductor substrate (not shown) with its structure reversed relative to the xy plane. The formed structure is then reversed relative to the xy plane and the first structure 100 and the second structure 200 are bonded together. Subsequently, the substrate used for forming the second structure 200 is removed, thereby forming the third structure 300.

[0113] The first structure 100 includes a semiconductor substrate 21 such as silicon, MOSFETs Tr1 and Tr2, conductor groups 22 and 23, conductor CD5, contact plug CP5, insulator 25, and conductive bonding pads PD1 and 27.

[0114] Transistor Tr1 is located in the source line driver region SDRA, on the region including the upper surface of substrate 21 and on the upper surface. Conductor group 22 includes multiple conductors. Adjacent conductors in conductor group 22 along the z-axis are connected to each other. Conductor group 22 is connected to the lower surface of transistor Tr1 and conductor CD5. Conductor group 22 includes contact plug CP6. Conductor CD5 is connected to bonding pad PD1 via contact plug CP5.

[0115] Transistor Tr2 is located in the region and on the upper surface of the substrate 21 within the sense amplifier region SAA. Transistor Tr2 functions as a transistor contained in the sense amplifier 17.

[0116] Conductor group 23 contains multiple conductors. Adjacent conductors in conductor group 23 along the z-axis are connected to each other. Conductor group 23 is connected to a transistor Tr2 and bonding pad 27, electrically connecting transistor Tr2 and bonding pad 27. Bonding pad 27 and bonding pad PD1 are located on the same layer.

[0117] Insulator 25 is located in the layer containing bonding pads PD1 and 27, extending along the xy plane.

[0118] In the first structure 100, the area where the above-described constituent elements are not provided is, for example, provided with an insulator 70.

[0119] The second structure 200 includes an insulator 31, conductive bonding pads PD2 and 32, conductor assemblies 34 and 35, conductor 37, a multilayer structure 39, a memory pillar MP, a semiconductor 40, conductors 41 and 42, a component SLT, conductor 44, and an insulator 45.

[0120] Insulator 31 is located on the upper surface of insulator 25 and extends along the xy plane.

[0121] The bonding pad PD2 is located in the layer of insulator 31. The lower surface of the bonding pad PD2 is in contact with the upper surface of the bonding pad PD1.

[0122] Conductor group 34 contains multiple conductors. Adjacent conductors in conductor group 34 along the z-axis are connected to each other. The lower surface of conductor group 34 is connected to the upper surface of a bonding pad PD2. The upper surface of conductor group 34 is at the height of the lower surface of semiconductor 40.

[0123] The bonding pad 32 is located in the layer of the insulator 31. The lower surface of the bonding pad 32 is in contact with the upper surface of the bonding pad 27.

[0124] Each conductor group 35 contains multiple conductors. Adjacent conductors in conductor group 35 along the z-axis are connected to each other. Conductor group 35 is connected to the upper surface of a bonding pad 32 and the lower surface of a conductor 37.

[0125] Each conductor 37 extends along the y-axis, spanning from near one end of the sub-memory surface region SPNA to near the other end. Two conductors 37 are located... Figure 12 The yz plane is shown. Two conductors 37 are positioned opposite each other at the boundary of the sub-memory plane region SPNA, with a gap between them. Each conductor 37 functions as a bit line BL. Figure 12 Conductors 37 are also disposed on different yz planes as shown. Therefore, as mentioned above... Figure 10 The conductors 37 are arranged at intervals along the x-axis.

[0126] Each stacked structure 39 is located above the conductor 37 in a sub-memory surface region SPNA. The stacked structure 39 includes a plurality of conductors 44 and a plurality of insulators 45. The conductors 44 and insulators 45 are arranged alternately along the z-axis. The conductors 44 and insulators 45 arranged along the z-axis are connected to each other. Each stacked structure 39 extends along the xy plane in a sub-memory surface region SPNA. Two stacked structures 39 are opposite each other at the boundary of the sub-memory surface region SPNA, with a gap between them. That is, the conductors 44 located in the same layer in two stacked structures 39 are opposite each other at the boundary of the sub-memory surface region SPNA, with a gap between them. Similarly, the insulators 45 located in the same layer in two stacked structures 39 are opposite each other at the boundary of the sub-memory surface region SPNA, with a gap between them. The gap between two stacked structures 39 is, for example, wider than the gap between two conductors 37. Each conductor 44 functions as a word line WL, a select gate line SGDL, or a select gate line SGSL.

[0127] Memory pillars MP are located within the stacked structure 39. Each memory pillar MP functions as part of a NAND string NS. The memory pillar MP extends, for example, along the z-axis and has a pillar shape. The memory pillar MP passes through or through the stacked structure 39 and is located within the stacked structure 39. The memory pillar MP comprises a semiconductor, a conductor, and an insulator. The upper end of the memory pillar MP is located within the semiconductor 40. A portion of the surface of the memory pillar MP opens into the semiconductor 40. The semiconductor of the memory pillar MP is connected to the semiconductor 40 through the opening. The structure of the memory pillar MP will be described in more detail below. The lower surface of each memory pillar MP is connected to the conductor 41.

[0128] The component SLT is located in the laminated structure 39. The component SLT extends, for example, along the z-axis and has a plate-like shape extending along the x-axis. The component SLT passes through or through the laminated structure 39. The upper end of the component SLT is located in the semiconductor 40. The contact LI of the component SLT is connected to the semiconductor 40.

[0129] Semiconductor 40 is, for example, silicon, containing impurities, and is conductive. Semiconductor 40 extends along the xy plane and spans two sub-memory plane regions SPNA. A portion of the lower surface of semiconductor 40 is in contact with the respective upper surfaces of the two stacked structures 39. Semiconductor 40 functions as part of the source line SL.

[0130] Conductor 42 has a pillar shape. The lower surface of each conductor 42 is in contact with the upper surface of conductor 41. Conductor 41 has a pillar shape. The lower surface of conductor 41 is in contact with the upper surface of conductor 37.

[0131] In the second structure 200, the area where the above-described constituent elements are not provided is, for example, provided with an insulator 71.

[0132] The third structure 300 includes insulators 51 and 52, conductor CD1, and contact plug CP1.

[0133] Insulator 51 is located on the upper surface of semiconductor 40. Insulator 51 has a partial opening. The opening extends to the upper surface of semiconductor 40.

[0134] Conductor CD1 extends along the y-axis. Conductor CD1 is partially located on the upper surface of insulator 51, and also partially located in an opening in insulator 51. Conductor CD1 is connected to semiconductor 40 in the opening of insulator 51. In the region outside the sub-memory surface region SPNA, conductor CD1 partially penetrates semiconductor 40 and is connected to the upper surface of conductor group 34. The portion of conductor CD1 that penetrates semiconductor 40 and is connected to conductor group 34 functions as contact plug CP1.

[0135] Insulator 52 covers the upper surface of conductor CD1.

[0136] Figure 13 This shows a cross-sectional view of a portion of the storage device 1 according to the first embodiment. Specifically, Figure 13 Indicates along Figures 8-10 The cross section of line XIII-XIII.

[0137] The first configuration 100 further includes a contact plug 24 and a bonding pad 28 for a conductor. The conductor CD4 and the contact plug 24 are located above the substrate 21 in the pad region PPA. The contact plug 24 is located on the upper surface of the conductor CD3. The bonding pad 28 is located on the upper surface of the contact plug 24. The bonding pad 28 is located in the layer containing the insulator 25.

[0138] The second structure 200 also includes a conductive bonding pad 33 and a conductive assembly 36.

[0139] The bonding pad 33 is located in the layer containing the insulator 31. The lower surface of the bonding pad 33 is in contact with the upper surface of the bonding pad 28.

[0140] Each conductor group 36 contains multiple conductors. Adjacent conductors in conductor group 36 along the z-axis are connected to each other. The lower surface of conductor group 36 is in contact with the upper surface of a bonding pad 33.

[0141] The third structure 300 also includes a conductor CD2 and a contact plug CP2. The conductor CD2 extends along the y-axis. The conductor CD2 is partially located on the upper surface of the insulator 51, and also partially located in an opening in the insulator 51. The conductor CD2 penetrates the semiconductor 40 in the pad region PPA and contacts the upper surface of the conductor assembly 36. The portion of the conductor CD2 that penetrates the semiconductor 40 and contacts the conductor assembly 36 functions as the contact plug CP2.

[0142] Insulator 52 has a partial opening in pad region PAA. The opening extends to the upper surface of conductor CD2. The portion of conductor CD2 exposed in the opening of insulator 52 functions as pad EPD.

[0143] Figure 14 This shows a cross-sectional view of a portion of the storage device 1 according to the first embodiment. Specifically, Figure 14 Indicates along Figure 5 The cross section of line XIV-XIV.

[0144] The stacked structures 39 of the sub-memory surface regions SPNA arranged along the x-axis are independent of each other. That is, the conductors 44 and insulators 45 of each sub-memory surface region SPNA are independent of the conductors 44 and insulators 45 of the adjacent sub-memory surface regions SPNA along the x-axis.

[0145] A conductor 44 and an insulator 45 arranged along the z-axis form a pair. Hereinafter, this pair is sometimes referred to as a conductor-insulator pair. In each sub-memory surface region SPNA, the left end of the conductor 44 and insulator 45 has a stepped shape. That is, the left end of each conductor-insulator pair in a certain first layer is located further to the left than the left end of the conductor-insulator pair in the second layer below that first layer. Similarly, in each sub-memory surface region SPNA, the right end of the conductor 44 and insulator 45 has a stepped shape. That is, the right end of each conductor-insulator pair in a certain first layer is located further to the right than the right end of the conductor-insulator pair in the second layer below that first layer. As a result, each conductor 44 has a step at its end that is not covered by the conductor-insulator pair. Each conductor 44 is in contact with the upper surface of a contact plug 55 at the stepped portion. The lower surface of each contact plug 55 is in contact with the upper surface of a conductor 56. The area containing the stepped section and contact plug 55 is the word line wiring area WHUA.

[0146] Conductors 26a and 26b are located in a region that is above transistor Tr2 and below insulator 25. Conductors 26a and 26b are referred to below. Figure 19 A portion of the aforementioned wiring CG performs its function.

[0147] Figure 15 An example showing a detailed cross-sectional view of a portion of the storage device 1 according to the first embodiment. Specifically, Figure 15 This refers to bonding pads PD1 and PD2 and their periphery. Bonding pads 27 and 32 may also have the same features as described below, and the descriptions of bonding pads PD1 and PD2 are also applicable to bonding pads 27 and 32, respectively.

[0148] like Figure 15 As shown, bonding pads PD1 and PD2 have different shapes. Specifically, bonding pad PD1 has an inverted cone shape, and bonding pad PD2 has a cone shape. That is, the radius of the upper surface of bonding pad PD1 and / or the area along the xy plane is greater than the radius of the lower surface of bonding pad PD1 and / or the area along the xy plane. On the other hand, the radius of the upper surface of bonding pad PD2 and / or the area along the xy plane is smaller than the radius of the lower surface of bonding pad PD2 and / or the area along the xy plane.

[0149] The shape difference between bonding pads PD1 and PD2 is due to the different etching directions during their formation. That is, during the formation of the second structure 200 on the substrate, the second structure 200 has a shape relative to the xy plane that... Figure 12The structure shown is an inverted structure. Therefore, the hole used to form the bonding pad PD2 has an inverted conical shape. However, because the second structure 200 and its substrate are reversed relative to the xy plane when they are bonded to the first structure 100, the bonding pad PD2 has a conical shape.

[0150] The bonding pads PD1 and PD2 may shift in position along the xy plane due to misalignment during the assembly of the first structure 100 with the second structure 200 and the substrate that forms the basis of the second structure 200. Therefore, the upper surface of bonding pad PD1 and the lower surface of bonding pad PD2 may have a step difference at the interface.

[0151] The bonding pads PD1 and PD2 can be formed separately or as a single unit. The bonding pad PD1 can also be connected to the conductor CD5 without using the contact plug CP5. Alternatively, the bonding pad PD1 and the conductor CD5 can be connected via multiple contact plugs CP5. The bonding pad PD2 can also be connected to the conductor 341 in the conductor assembly 34 without using the contact plug 342 in the conductor assembly 34. The bonding pad PD2 and the conductor 341 can also be connected via multiple contact plugs 342.

[0152] Figure 16 This shows a cross-sectional structure of the storage cell array 10 of the storage device 1 according to the first embodiment.

[0153] like Figure 16 As shown, insulator 45 and conductor 44 are alternately located on the upper surface of insulator 71. Figure 16 In this example, the conductors 44, starting from the side closest to the semiconductor 40, sequentially function as the select gate line SGSL, word lines WL7, WL6, WL5, WL4, WL3, WL2, WL1, and WL0, and the select gate line SGDL. Two or more conductors 44 can also function as select gate lines SGSL or SGDL.

[0154] The memory column MP includes a core 101, a semiconductor 102, a tunnel insulator 103, a charge storage layer 104, a barrier insulator 105, and a conductor 106.

[0155] Core 101 extends along the z-axis and has a column shape.

[0156] Semiconductor 102 functions as the channel region for the memory cell transistor MT, the select gate transistor DT, and ST. Semiconductor 102 covers the side of core 101.

[0157] Tunnel insulator 103 covers the surface of semiconductor 102. Charge accumulation layer 104 covers the surface of tunnel insulator 103.

[0158] A barrier insulator 105 covers the surface of the charge storage layer 104. The side of the barrier insulator 105 is in contact with the conductor 44 and the insulator 45. The portion of the semiconductor 102, tunnel insulator 103, charge storage layer 104 and barrier insulator 105 facing the conductor 44 functions as a memory cell transistor MT, a select gate transistor DT or a select gate transistor ST.

[0159] The tunnel insulator 103, the charge storage layer 104, and the barrier insulator 105 form an opening in the semiconductor 40B, with a portion of the semiconductor 40B located within the opening. The semiconductor 40B is connected to the semiconductor 102 within the opening.

[0160] Conductor 106 is located on the upper surface of conductor 42. Core 101 and semiconductor 102 are located on the upper surface of conductor 106.

[0161] Semiconductor 40 includes, for example, semiconductors 40A, 40B, and 40C. Semiconductor 40C is located on the upper surface of the uppermost insulator 45. Semiconductor 40B is located on the upper surface of semiconductor 40C. Semiconductor 40A is located on the upper surface of semiconductor 40B.

[0162] 1.1.7. Sub-memory cell array

[0163] Figure 17 This section illustrates the constituent elements of the storage device according to the first embodiment and examples of allocating addresses to these constituent elements. (See reference...) Figure 5 As described, two sub-memory plane regions SPNA in each memory plane region PNA form the constituent elements of one memory plane PLN. Therefore, the two sub-memory cell arrays SMCAU and SMCAD, which form the constituent elements of one memory plane PLN, are assigned the same memory plane address PLNA.

[0164] Figure 18 This section illustrates the constituent elements in the storage cell array of the storage device 1 according to the first embodiment, and an example of assigning addresses to the constituent elements. Figure 18 This is illustrated for a single memory plane PLN. For example... Figure 18 As shown, sub-storage cell arrays SMCAU and SMCAD contain groups of half-blocks HBLK. Half-block HBLK consists of half of block BLK. Half-blocks HBLK in sub-storage cell arrays SMCAU and SMCAD are sometimes referred to as half-blocks HBLKe and HBLKo, respectively.

[0165] Half of the sub-storage cell array SMCAU, block HBLKe, is composed of the first half of each of blocks BLK_0 to BLK_n-1. Half of the sub-storage cell array SMCAU, block HBLKo, is composed of the second half of each of blocks BLK_0 to BLK_n-1.

[0166] Each half-block HBLK contains multiple half-cell components HCU. Each half-cell component HCU contains half the number of memory cell transistors MT that constitute the CU. Therefore, when each memory cell transistor MT stores 1 bit of data, the half-cell component HCU stores half the size of one page, i.e., half a page of data. When each memory cell transistor MT stores p bits of data, the half-cell component HCU stores p half-pages of data.

[0167] A common set of page addresses PGAs is allocated to the group of half-unit components HCU in half-block HBLKe and the group of half-unit components HCU in half-block HBLKo. That is, page addresses PGA0 to PGAt (where t is a positive integer) are allocated to the half-unit components HCU in each half-block HBLKe, and page addresses PGA0 to PGAt are also allocated to the half-unit components HCU in each half-block HBLKo.

[0168] m / 2 bit lines BL are located in each sub-memory cell array SMCA. Bit lines BL extend across all half of the blocks HBLK in each sub-memory cell array SMCA. (See reference...) Figure 2 As described, m is the number of bit lines BL contained in one block BLK, and the number of memory cell transistors MT constituting one unit component CU, for example, 16kB. Therefore, in each half-block HBLK, m / 2, for example, 8kB memory cell transistors MT are arranged along the arrangement direction of the bit lines BL. The memory cell transistors MT of half-block HBLKe are connected to the bit lines BL that are consecutively connected in address, for example, to bit lines BL_0 to BL_m / 2-1 respectively. The memory cell transistors MT of half-block HBLKo are connected to the bit lines BL that are consecutively connected in address, for example, to bit lines BL_m / 2 to BL_m-1 respectively.

[0169] Based on the above composition, such as Figure 19As shown, the sub-memory cell array SMCAU contains half of the blocks HBLKe_0 to HBLKe_n-1, and the sub-memory cell array SMCAD contains half of the blocks HBLKo_0 to HBLKo_n-1. n is an integer greater than or equal to 2. Half of the blocks HBLKe_0 and HBLKo_0 are selected using the block address BA_0 of block BLK_0. Similarly, for all instances where α is greater than 0 and less than n-1, half of the blocks HBLKe_α and HBLKo_α are selected using the block address BA_α of block BLK_α.

[0170] On the other hand, the two sub-memory cell arrays (SMCA) contain groups of bit lines BL with mutually independent bit line addresses. The bit line addresses are specified by column addresses. For example, the sub-memory cell array (SMCA) contains bit lines BL_0 to BL_m / 2. The sub-memory cell array (SMCA) also contains bit lines BL_m / 2+1 to BL_m-1.

[0171] By allocating addresses as described above, the half-cell components (HCUs) of each of the two sub-memory cell arrays (SMCA) can be selected by specifying one memory plane address (PLNA), one block address (BA), and one page address (PGA). Figure 19 This example specifies block address BA_0 and page address PGA_1. By specifying these addresses, half-cell component HCU_1 of half-block HBLKe_0 and half-cell component HCU_1 of half-block HBLKo_0 are selected.

[0172] Therefore, when reading data, it is possible to read half a page of data from each of the two selected half-cell units (HCUs) by specifying one memory plane address (PLNA), one block address (BA), and one page address (PGA), that is, to read a total of one page of data.

[0173] When writing data, it is possible to write a total of one page of data to two half-cell components (HCUs) by specifying one memory plane address (PLNA), one block address (BA), and one page address (PGA).

[0174] In the case of erasing data, it is possible to erase the data of two half-blocks HBLK, i.e., the data of one block BLK, by specifying one memory plane address PLNA and one block address BA.

[0175] 1.1.8. Line Decoder

[0176] Figure 20 The diagram shows the constituent elements of the line decoder of the storage device 1 in the first embodiment and the connections between the constituent elements. Figure 20It also represents the block BLK. For example... Figure 20 As shown, the row decoder 11 includes n block decoders BD_0 to BD_n-1 and n transmission switch groups XSG_0 to XSG_n-1. As mentioned above, n is the number of blocks BLK contained in one memory plane PLN.

[0177] The block decoder (BD) is a circuit that decodes the block address (BA) and outputs the block selection signal (BSS) based on the decoding result. Each block decoder (BD) is associated with one block (BLK). Each block decoder (BD) controls the state to make the associated block (BLK) selected. Block decoder (BD_0) supplies the block selection signal (BSS_0) to the transmission switch group (XSG_0). Similarly, for each instance where α is 1 or more (n-1), block decoder (BD_α) supplies the block selection signal (BSS_α) to the transmission switch circuit (XSG_α). When the block address (BA) specifies its associated block (BLK), the block decoder (BD) outputs the activated block selection signal (BSS).

[0178] A transmission switch group (XSG) is a group of multiple transmission switches (XS). Each transmission switch group (XSG) establishes a correspondence with one block (BLK). Based on the block selection signal (BSS), each transmission switch group (XSG) makes the block (BLK) it corresponds to selected.

[0179] Each transfer switch group XSG includes multiple transfer switches XSD, multiple transfer switches XSW, and one transfer switch XSS. The transfer switches XSD, XSW, and XSS are, for example, n-type MOSFETs. Each transfer switch XSD is connected between the select gate line SGDL and the wiring line SGD. Each transfer switch XSW is connected between a word line WL and a wiring line CG. The transfer switch XSS is connected between the select gate line SGSL and the wiring line SGS. Each transfer switch XSD, XSW, and XSS receives the block selection signal BSS in its own gate.

[0180] Wiring SGD, CG, and SGS receive voltage from driver 15.

[0181] When a block selection signal (BSS) is activated, the transmission switches XSD, XSW, and XSS that receive the BSS are turned on. Consequently, the voltages of wirings SGD, CG, and SGS are transmitted to the select gate line SGDL, word line WL, and select gate line SGSL of the selected block BLK.

[0182] Figure 21 The components of the line decoder of the storage device 1 of the first embodiment and the connections of the components are shown in more detail. Figure 21 This indicates the composition of each block BLK, represented by block BLK0. Other block BLKs also have... Figure 21 The structure shown.

[0183] The block BLK is divided into two halves, HBLK, and each half of the HBLK contains a block decoder (BD) and a transmission switch group (XSG). Details are as follows.

[0184] Block decoder BD_0 includes block decoders BDe_0 and BDo_0. Block decoders BDe_0 and BDo_0 have references... Figure 20 The block decoders BD described herein have the same configuration. When the received block address BA specifies its associated block BLK_0, each block decoder BDe_0 and BDo_0 outputs the effective block selection signals BSSe_0 and BSSo_0, respectively.

[0185] The transmission switch group XSG includes transmission switch groups XSGe_0 and XSGo_0. Transmission switch groups XSGe_0 and XSGo_0 have a reference... Figure 20 The described transmission switch groups XSG have the same configuration.

[0186] The transmission switches XSD, XSW, and XSS of the transmission switch group XSGe_0 are respectively connected to the select gate line SGDL, word line WL, and select gate line SGSL of half-block HBLKe_0. The transmission switches XSD, XSW, and XSS of the transmission switch group XSGe_0 receive the block selection signal BSSe_0 in their own gates.

[0187] The transmission switches XSD, XSW, and XSS of the transmission switch group XSGo_0 are connected to the select gate line SGDL, word line WL, and select gate line SGSL of half-block HBLKo_0, respectively. The transmission switches XSD, XSW, and XSS of the transmission switch group XSGo_0 receive the block selection signal BSSo_0 in their own gates.

[0188] Figure 22 The diagram shows the constituent elements of the line decoder of the storage device 1 in the first embodiment and the connections between the constituent elements. Figure 22 This is shown for two sub-memory plane regions SPNAu and SPNAd, which are constituent elements of a memory plane PLN.

[0189] The portion of the row decoder region RDA1 contained within the sub-memory plane region SPNAu contains n / 2 block decoders BDe. These n / 2 block decoders BDe are used for even-numbered block addresses BA, specifically block decoders BDe_0, BDe_2, BDe_4, ..., BDe_n-2 for block addresses BA_0, BA_2, BA_4, ..., BA_n-2.

[0190] The portion of the row decoder region RDA1 contained within the sub-memory plane region SPNAu contains n / 2 transfer switch groups XSGe. These n / 2 transfer switch groups XSGe are used for even-numbered block addresses BA, specifically the transfer switch groups XSGe_0, XSGe_2, XSGe_4, ..., XSGe_n-2 for block addresses BA_0, BA_2, BA_4, ..., BA_n-2.

[0191] The portion of the row decoder region RDA contained within the sub-memory plane region SPNAu contains n / 2 block decoders BDe. The n / 2 block decoders BDe are used for odd-numbered block addresses BA, namely block decoders BDe_1, BDe_3, BDe_5, ..., BDe_n-1 for block addresses BA_1, BA_3, BA_5, ..., BA_n-1.

[0192] The portion of the line decoder region RDA contained within the sub-memory plane region SPNAu contains n / 2 transfer switch groups XSGe. These n / 2 transfer switch groups XSGe are used for odd-numbered block addresses BA, specifically the transfer switch groups XSGe_1, XSGe_3, XSGe_5, ..., XSGe_n-1 for block addresses BA_1, BA_3, BA_5, ..., BA_n-1.

[0193] The portion of the row decoder region RDA1 contained within the sub-memory plane region SPNAd contains n / 2 block decoders BDo. These n / 2 block decoders BDo are for even-numbered block addresses BA, specifically block decoders BDo_0, BDo_2, BDo_4, ..., BDo_n-2 for block addresses BA_0, BA_2, BA_4, ..., BA_n-2.

[0194] The portion of the line decoder region RDA1 contained within the sub-memory plane region SPNAd contains n / 2 transfer switch groups XSGo. These n / 2 transfer switch groups XSGo are used for even-numbered block addresses BA, specifically the transfer switch groups XSGo_0, XSGo_2, XSGo_4, ..., XSGo_n-2 for block addresses BA_0, BA_2, BA_4, ..., BA_n-2.

[0195] The portion of the row decoder region RDA contained within the sub-memory plane region SPNAd contains n / 2 block decoders BDo. The n / 2 block decoders BDo are used for odd-numbered block addresses BA, namely block decoders BDo_1, BDo_3, BDo_5, ..., BDo_n-1 for block addresses BA_1, BA_3, BA_5, ..., BA_n-1.

[0196] The portion of the line decoder region RDA contained within the sub-memory plane region SPNAd contains n / 2 transfer switch groups XSGo. These n / 2 transfer switch groups XSGo are used for odd-numbered block addresses BA, specifically the transfer switch groups XSGo_1, XSGo_3, XSGo_5, ..., XSGo_n-1 for block addresses BA_1, BA_3, BA_5, ..., BA_n-1.

[0197] 1.2. Actions

[0198] Figure 23 This indicates a state during operation of the storage device in the first embodiment. Figure 23 This is shown for two sub-memory plane regions SPNA that form the constituent elements of a memory plane PLN. Figure 23 This indicates the state of selecting one block (BLK). Figure 23 This represents an example of specifying block address BA_1.

[0199] like Figure 23 As shown, upon receiving block address BA_1, block decoders BDe_1 and BDo_1 are activated. Upon activation, block decoder BDe_1 enables block selection signal BSSe_1, and block decoder BDo_1 enables block selection signal BSSo_1. Other block selection signals, BSS, are negated. As a result, the system selects half of blocks HBLKo_1 and half of blocks HBLKe_1. In other words, it becomes a state where the voltages for wiring CG, SGD, and SGS are transmitted to half of blocks HBLKo_1 and half of blocks HBLKe_1.

[0200] Driver 15 applies voltages to wirings CG, SGD, and SGS based on the operation and address information ADD of the storage device 1. For example, a voltage based on the magnitude of the operation is applied to the word line WL connected to the cell component CU, i.e., the selection cell component CU, which is to be read and written data. Additionally, a selection voltage is applied to the selection gate line SGDL of the string component SU, which includes the selection cell component CU. Furthermore, various voltages are applied to word lines WL other than those connected to the selection cell component CU. Driver 15 applies various patterns of voltages to wirings CG, SGD, and SGS in a manner determined based on the operation and the address of the selected word line WL. The voltages of wirings CG, SGD, and SGS, which are applied with patterns based on the operation and address information ADD, are transmitted via the transfer switch group XSG to the word line WL, selection gate line SGDL, and SGSL of the selected half-block HBLK.

[0201] 1.3. Advantages (Effects)

[0202] According to the first embodiment, as described below, a storage device for high-speed data readout can be provided.

[0203] A memory device capable of reading one page of data (16kB) from a memory cell array in response to receiving an instruction set can have the following configuration: Specifically, the 16kB memory cell transistors storing the one-page-sized data are connected to one word line. Furthermore, each word line is energized via a switch. The length of the word line in the X direction depends on the page size. Therefore, if the page size is large, the word line length is also large, and charging the word line requires a longer time.

[0204] In the memory cell array 10 of the memory device 1 of the first embodiment, in each string assembly SU, a half-page-sized memory cell transistor to be read is connected to one word line. When reading one page of data, two word lines WL are driven. For example, if the page size is 16kB, then the size of half a page is 8kB. Therefore, in each string assembly SU that functions as a unit for reading data, the memory cell transistors MT of the half-page-sized unit assembly HCU to be read, i.e., 8kB of the memory cell transistors MT to be read, are arranged along each word line WL in the arrangement direction of the bit line BL. Compared to the case where 16kB of memory cell transistors to be read, storing one page of data, are connected to one word line, the length of each word line WL in the X direction is shorter. The word lines WL are not electrically connected to each other, nor are they connected to each other. Therefore, the time required for charging based on the word line WL, or even based on the resistor (R) and capacitor (C) (or the charging delay based on the resistor (R) and capacitor (C) (RC (Resistor-Capacitance) delay)) is shorter than the charging time required for the word line when the 16kB memory cell transistors to be read are connected to one word line. This enables the memory device 1 to read data in a short time.

[0205] Two sub-memory cell arrays (SMCAs), each consisting of a memory plane (PLN), are grouped together by the same memory plane address (PLNA), the same block address (BA), and the same page address (PGA). Therefore, the half-cell components (HCUs) of each of the two SMCAs can be selected by specifying the memory plane address (PLNA), the block address (BA), and the page address (PGA). Consequently, it is possible to read a page of data, write data to a page, or erase data from a block (BLK) using the same instructions as before.

[0206] In the two sub-memory plane regions SPNA that form the constituent elements of a single memory plane PLN, the conductor 37 of one sub-memory plane region SPNA is not connected to the other. Therefore, the conductor 37 in one sub-memory plane region SPNA and the conductor 37 in the other sub-memory plane region SPNA can function as different bit lines BL. Utilizing this, even if only the memory cell transistors MT of half-cell components HCU are arranged in the bit line BL direction within the sub-memory plane region SPNA, two different half-cell components HCU will be formed from the two sub-memory plane regions SPNA, and one cell component CU will be formed from the two half-cell components HCU.

[0207] The storage device 1 includes a conductor CD1 that spans two sub-memory plane regions SPNA, which are constituent elements forming a single memory plane PLN. The conductor CD1 functions as part of a source line SL. That is, the source line SL is shared by sub-memory cell arrays SMCA within the sub-memory plane region SPNA, which is a constituent element forming a single memory plane PLN. Therefore, the two sub-memory cell arrays SMCA can share a source line driver SLD. This means that two source line drivers SLD are not required to drive the source line SL of the two sub-memory cell arrays SMCA; one source line driver SLD is sufficient. Thus, the source line driver SLD for the two sub-memory cell arrays SMCA can be located in the upper sub-memory plane region SPNAu, which is a constituent element forming a single memory plane PLN, instead of in the lower sub-memory plane region SPNAd, which contains many constituent elements. This facilitates the configuration of the components of the storage device 1.

[0208] 1.4. Variation Example

[0209] The cross-sectional structure of storage device 1 is not limited to Figure 12 and Figure 14 The cross-sectional structure shown may be other structures.

[0210] 1.4.1. First Variation Example

[0211] Figure 24 The cross-sectional structure of the storage device 1, which represents the first variation of the first embodiment, is shown. Figure 24 and Figure 12 Same, indicating a cross-section along the yz plane. For example... Figure 24 As shown, a slit SLT is disposed between the two stacked structures 39 of the two sub-memory surface regions SPNA. The two stacked structures 39 are electrically separated by the slit SLT. In the first variation, for example, the spacing ratio of the two stacked structures 39 is... Figure 12The spacing between the two stacked structures 39 in the illustrated configuration is narrow. Additionally, for example, in the first variation, it is also similar to... Figure 12 The structure shown is the same, except that the spacing between the two stacked structures 39 separated by the slit SLT is, for example, wider than the spacing between the two conductors 37.

[0212] 1.4.2. Second variation example

[0213] Figure 25 The cross-sectional structure of the storage device 1, which is a second variation of the first embodiment, is shown. Figure 25 and Figure 12 The same refers to a cross-section along the yz plane. The storage device 1 of the second variation does not include the third structure 300. On the other hand, the second structure 200 of the storage device 1 of the second variation also includes a semiconductor substrate 80 such as silicon. (Refer to the above) Figure 12 The substrate 80, for example, functions as the basis for forming structures other than the substrate 80 in the second structure 200. In a second variation, unlike the basic approach of the first embodiment, the substrate 80 is also removed after the second structure 200 is bonded to the first structure 100. The semiconductor 40 is implemented as a well formed in the substrate 80.

[0214] 1.4.3. Third variation example

[0215] Figure 26 and Figure 27 The cross-sectional structure of the storage device 1 in the third variation of the first embodiment is shown. Figure 26 and Figure 12 Same, indicating a cross-section along the yz plane. Figure 27 and Figure 14 Same, indicating a cross-section along the xz plane.

[0216] like Figure 26 As shown, the upper surface of conductor group 23 is connected to the lower surface of conductor 61. Conductor 61 extends along the y-axis, spanning from near one end of the sub-memory plane region SPNA to near the other end. Two conductors 61, similar to conductor 37, are positioned opposite each other at the boundary of the sub-memory plane region SPNA, with a gap between them. Each conductor 61 functions as part of the bit line BL. Figure 26 Conductors 61 are also provided on different yz planes shown, and thus the conductors 61 are arranged at intervals along the x-axis.

[0217] In the region outside the stacked structure 39, the upper surface of the conductor 61 is connected to the lower surface of the contact plug 63.

[0218] A semiconductor 62 is disposed on the upper surface of the insulator 25. The semiconductor 62 is equivalent to... Figure 12Semiconductor 40, identical to semiconductor 40, extends along the xy plane and spans two sub-memory plane regions SPNA. Semiconductor 62 contains impurities and is conductive.

[0219] The assembly of the stacked structure 39, memory column MP, component SLT, conductor 41, and conductor 42 has the function of... Figure 12 The stacked structure 39, memory pillar MP, component SLT, conductor 41, and conductor 42 are arranged in a configuration that is reversed relative to the xy plane. Specifically: The lower end of the memory pillar MP is located in semiconductor 62. A portion of the surface of the memory pillar MP opens into semiconductor 62. The semiconductor of the memory pillar MP is connected to semiconductor 62 through the opening. The lower end of the component SLT is located in semiconductor 62. The conductor of the component SLT is connected to semiconductor 62. The upper surface of conductor 42 is connected to the lower surface of conductor 41. The upper surface of conductor 41 is connected to the lower surface of conductor 64.

[0220] Each conductor 64 extends along the y-axis, spanning from near one end of the sub-memory surface region SPNA to near the other end. Two conductors 64, similar to conductor 61, are positioned opposite each other at the boundary of the sub-memory surface region SPNA, with a gap between them. Each conductor 64 functions as a bit line BL. Figure 26 Conductors 64 are also disposed on different yz planes shown. Thus, the conductors 64 represent the basic configuration of the first embodiment, and are consistent with the reference design. Figure 10 The described conductors 37 are identical and are arranged at intervals along the x-axis.

[0221] Each conductor 64 has its lower surface in contact with the upper surface of conductor 41. The lower surface of conductor 41 is in contact with conductor 42. The lower surface of conductor 42 is in contact with the upper surface of contact plug 63.

[0222] like Figure 27 As shown, in each sub-memory surface region SPNA, the right and left ends of the conductor 44 and the insulator 45 have a stepped shape. However, because the stacked structure 39 has a relative... Figure 12 The layered structure 39 in the middle is a reversed structure, so the shape of the steps is similar to... Figure 14The shapes of the steps differ. Specifically, the left end of each conductor / insulator pair in a certain first layer is located further to the left than the left end of the conductor / insulator pair in the second layer above that first layer. Similarly, the right end of each conductor / insulator pair in a certain first layer is located further to the right than the right end of the conductor / insulator pair in the second layer above that first layer. As a result, each conductor 44 has a stepped portion at its end that is not covered by the conductor / insulator pair. Each conductor 44 is in contact with the lower surface of the contact plug 67 at the stepped portion. The upper surface of each contact plug 67 is in contact with the lower surface of one conductor 68.

[0223] 1.4.4. Fourth Variation Example

[0224] The fourth variation is based on the third variation.

[0225] Figure 28 The layout and several constituent elements of a portion of the storage device 1 in the fourth variation of the first embodiment are shown. Figure 28 Indicates the position on the z-axis relative to Figure 6 The same area as shown. For example... Figure 28 As shown, sub-memory plane regions SPNAu and SPNAd each contain a sensing amplifier region SAA. The sensing amplifier region SAA of sub-memory plane region SPNAu faces the boundary between sub-memory plane regions SPNAu and SPNAd. The sensing amplifier region SAA of sub-memory plane region SPNAd faces the boundary between sub-memory plane regions SPNAu and SPNAd.

[0226] Figure 29 The cross-sectional structure of the storage device 1 in the fourth variation of the first embodiment is shown. Figure 29 and Figure 12 Same, indicating a cross-section along the yz plane. For example... Figure 29 As shown, the groups of conductors 41 and 42, and contact plug 63 are different from the third variation example ( Figure 26 Unlike the sensing amplifier region SAA, the conductors 41 and 42, and the contact plugs 63, are located directly above the conductor group 23 along the z-axis. Based on this, conductor 61 does not extend along the x-axis. Additionally, semiconductors 62 are provided for each sub-memory surface region SPNA. The two semiconductors 62 of the two sub-memory surface regions SPNA are arranged with a gap at the boundary between them. Since both semiconductors 62 of the two sub-memory surface regions SPNA function as part of the source line SL of one memory surface PLN, they have the same potential. Therefore, the two semiconductors 62 in… Figure 29The regions not shown are interconnected via conductors. For example, a conductor is disposed above a conductor 64, which is connected to both semiconductors 62 via a contact plug and / or a group of conductors.

[0227] The contact plug 63 is located in the area between the semiconductors 62.

[0228] 1.4.5. Fifth variation example

[0229] The fifth variation is based on the third variation.

[0230] Figure 30 The layout and several constituent elements of a portion of the storage device 1 in the fifth variation of the first embodiment are shown. Figure 30 Indicates the position on the z-axis relative to Figure 6 The same area as shown. For example... Figure 30 As shown, sub-memory plane regions SPNAu and SPNAd each contain a sense amplifier region SAA. The sense amplifier region SAA of sub-memory plane region SPNAu faces or is connected to the source line driver region SDRA. The sense amplifier region SAA of sub-memory plane region SPNAd is located in the region containing the lower end of sub-memory plane region SPNAd.

[0231] Figure 31 The cross-sectional structure of the storage device 1 in the fifth variation of the first embodiment is shown. Figure 31 and Figure 12 Same, indicating a cross-section along the yz plane. For example... Figure 31 As shown, the sensing amplifier region SAA is located in the area below the group of conductors 41 and 42 and contact plug 63. That is, transistor Tr2 and the third variation ( Figure 26 They are different and located below the group of conductors 41 and 42 and contact plug 63.

[0232] 1.4.6. Sixth Variation Example

[0233] The sixth variation is based on the third variation.

[0234] Figure 32 The layout and several constituent elements of a portion of the storage device 1 in the sixth variation of the first embodiment are shown. Figure 32 Indicates the position on the z-axis relative to Figure 6 The same area as shown. For example... Figure 32As shown, sub-memory surface regions SPNAu and SPNAd each contain a sensing amplifier region SAA. The sensing amplifier region SAA of sub-memory surface region SPNAu is located at the center of the y-axis containing sub-memory surface region SPNAu. The sensing amplifier region SAA of sub-memory surface region SPNAd is located at the center of the z-axis containing sub-memory surface region SPNAd.

[0235] Figure 33 The cross-sectional structure of the storage device 1 in the sixth variation of the first embodiment is shown. Figure 33 and Figure 12 Same, indicating a cross-section along the yz plane. For example... Figure 33 As shown, in each sub-memory plane region SPNA, the stacked structure 39 comprises two parts. The two parts of the stacked structure 39 are not connected and are spaced apart. Similarly, the semiconductor 62 also comprises two parts in each sub-memory plane region SPNA. The two parts of the semiconductor 62 are spaced apart. The two parts of the semiconductor 62 are located below the two parts of the stacked structure 39. Because the two parts of the semiconductor 62 in each sub-memory plane region SPNA both function as part of the source line SL of a memory plane PLN, they have the same potential. Therefore, the two parts of the semiconductor 62 in each sub-memory plane region SPNA are... Figure 33 The regions not shown are interconnected via conductors. For example, a conductor is disposed above conductor 64, which is connected to both portions of semiconductor 62 via contact plugs and / or conductor groups.

[0236] The sensing amplifier region SAA is located in the region between the two portions of the multilayer structure 39 and below the region between the two portions of the semiconductor 62. Additionally, the sets of conductors 41 and 42, and contact plugs 63, are located in the regions between the two portions of the multilayer structure 39 and between the two portions of the semiconductor 62.

[0237] 2. Second Implementation Method

[0238] The second embodiment relates to the detailed operation of the storage device 1 of the first embodiment.

[0239] The storage device 1 of the second embodiment has the same configuration as the storage device 1 of the first embodiment. However, certain components of the storage device 1 of the second embodiment and the memory controller 2 are configured to perform the operations described below.

[0240] Figure 34 This refers to an example of signals transmitted and received between the storage device 1 and the memory controller 2 in the second embodiment. Specifically, Figure 34This indicates the type 1 write instruction set and the standby / busy signal. The type 1 write instruction set is supplied from memory controller 2 to storage device 1.

[0241] Type 1 write instruction set includes Type 1 write address input instruction WWh, address information ADD, and write start instruction AAh. Write data Din is sent between address information ADD and write start instruction AAh. Type 1 write instruction set instructs the writing of data to one cell component CU, which is equivalent to writing one page of data (16kB) to 16kB memory cell transistors MT.

[0242] The Type 1 write address input instruction WWh indicates that 16kB of data should be written, and the address information ADD follows.

[0243] The address information ADD specifies the cell component (CU) to be written data. The address information ADD spans, for example, five loops. In the first loop and immediately following the second loop, column addresses C1 and C2 are transferred. In the remaining third, fourth, and fifth loops, row addresses R1, R2, and R3 are transferred. The row address contains the memory plane address PLNA, the block address BA, and the page address PGA. The page address contains the word line address and the string component address.

[0244] The 16kB write data digit spans dozens of cycles of transmission.

[0245] The write start command AAh instructs the execution of data writing.

[0246] When storage device 1 receives the write start command AAh, it writes 16kB of data to the specified cell component CU. During the data write, storage device 1 outputs a low-level standby / busy signal RB indicating that it is busy. The busy signal is, for example, output during the period TP1.

[0247] Using the received row address, as described in the first embodiment, two half-blocks HBLK with the specified block address BA are selected. Then, within the two specified half-blocks HBLK, the half-cell component HCU specified by the page address PGA is selected. Finally, the write data Din is written across the two specified half-cell components HCU.

[0248] Figure 35 This illustrates an example of signals transmitted and received between the storage device 1 and the memory controller 2 in the second embodiment. Specifically, Figure 35 This indicates the type 2 write instruction set and the standby / busy signal. The type 2 write instruction set is supplied from memory controller 2 to storage device 1.

[0249] The Type 2 write instruction set includes the Type 2 write address input instruction XXh, address information ADD, and write start instruction AAh. Write data Din is sent between the address information ADD and the write start instruction AAh. The Type 2 write instruction set instructs the writing of data to the half-cell component HCU, which is equivalent to writing half-page-sized data (8kB) to the 8kB memory cell transistors MT.

[0250] The Type 2 write address input instruction XXh indicates that 8kB of data should be written, and the address information ADD follows.

[0251] The address information ADD specifies the half-cell component HCU to be written to. The row address contains the memory plane address PLNA, the block address BA, and the page address PGA. The row address also contains the sub-memory plane address SPLNA. The sub-memory plane address SPLNA specifies one of the sub-memory cell arrays SMCAU and SMCAD. The sub-memory plane address SPLNA, for example, has a length of 1 bit. For example, the sub-memory plane address SPLNA specifies the sub-memory cell array SMCAU with a value of "0" and the sub-memory cell array SMCAD with a value of "1".

[0252] As mentioned above Figure 18 The two sub-memory cell arrays (SMCAs), each consisting of a memory plane (PLN), share the same memory plane address (PLNA), the same block address (BA), and the same page address (PGA). Therefore, the memory plane address (PLNA), block address (BA), and page address (PGA) in the address information (ADD) specify each of the two sub-memory cell arrays (SMCAs) with a total of two half-cell components (HCUs). However, the second type of write instruction set includes a sub-memory plane address (SPLNA), which specifies the sub-memory cell array (SMCA). Therefore, the sub-memory plane address (SPLNA) specifies only one half-cell component (HCU) of the sub-memory cell array (SMCA) specified by the sub-memory plane address (SPLNA).

[0253] The 8kB write data digit spans dozens of loop transfers.

[0254] When storage device 1 receives a write start command AAh, it writes 8kB of data to the designated half-cell component HCU, i.e., data smaller than the data size received when a type 1 write command set is received. During the data write, storage device 1 outputs a low-level standby / busy signal RB indicating busy status. The busy signal is, for example, output during period TP2. Period TP2 is shorter than the busy period TP1 when a type 1 write command set is received.

[0255] Figure 36 This illustrates an example of signals transmitted and received between the storage device 1 and the memory controller 2 in the second embodiment. Specifically, Figure 36 This indicates the type 1 read instruction set and the standby / busy signal. The type 1 read instruction set is supplied from memory controller 2 to storage device 1.

[0256] Type 1 read instruction set includes Type 1 read address input instruction YYh, address information ADD, and read start instruction BBh. Type 1 read instruction set indicates reading data from one unit component CU, that is, reading one page of data, i.e., 16kB of data, from 16kB of memory cell transistors MT.

[0257] The Type 1 read address input instruction YYh indicates that 16kB of data should be read and that address information ADD should follow.

[0258] The address information ADD specifies the cell component (CU) from which the data is to be read. The row address includes the memory plane address (PLNA), the block address (BA), and the page address (PGA).

[0259] The read start command BBh indicates that data reading should be performed.

[0260] When storage device 1 receives the read start command BBh, it reads 16kB of data from the specified cell component CU. During the data readout, storage device 1 outputs a low-level standby / busy signal RB indicating busy status. The busy signal is, for example, output during the TR1 period.

[0261] Using the received row address, as described in the first embodiment, two half-blocks HBLK with the specified block address BA are selected. Then, among the two specified half-blocks HBLK, the half-cell component HCU specified by the page address PGA is selected. Finally, data of a total page size is read from the two specified half-cell components HCU.

[0262] When data reading is complete, memory controller 2 repeatedly supplies an activated signal RE to storage device 1. Based on the reception of signal RE, storage device 1 outputs the read 16kB data Dout to memory controller 2.

[0263] Figure 37 This illustrates an example of signals transmitted and received between the storage device 1 and the memory controller 2 in the second embodiment. Specifically, Figure 37 This indicates the type 2 read instruction set and the standby / busy signal. The type 2 read instruction set is supplied from memory controller 2 to storage device 1.

[0264] The Type 2 read instruction set includes the Type 2 read address input instruction ZZh, address information ADD, and read start instruction BBh. The Type 2 read instruction set instructs the reading of data from the half-cell component HCU, that is, reading half a page of data (8kB in size) from the 8kB memory cell transistors MT.

[0265] The Type 2 read address input instruction ZZh instructs the reading of 8kB of data and notifies the address information ADD to follow.

[0266] The address information ADD specifies the half of the memory unit (HCU) from which data is to be read. The row address includes the memory plane address PLNA, the block address BA, and the page address PGA. The row address also includes the sub-memory plane address SPLNA.

[0267] As mentioned above Figure 34 The memory plane address PLNA, block address BA, page address PGA, and sub-memory plane address SPLNA specify only one half-cell component HCU in the sub-memory cell array SMCA specified by the sub-memory plane address SPLNA.

[0268] When storage device 1 receives a read start command BBh, it reads 8kB of data from the specified half-cell component HCU. During the data read, storage device 1 outputs a low-level standby / busy signal RB indicating busy status. The busy signal is, for example, output during period TR2. Period TR2 is shorter than the busy period TR1 when a read command set of type 1 is received.

[0269] Through the received row address, as referred above Figure 34 The process involves selecting one half-cell component (HCU). Then, half-page-sized data, i.e., data smaller than the data size received when the first type of read instruction set is used, is read from the selected half-cell component (HCU).

[0270] When data reading is complete, memory controller 2 repeatedly supplies an activated signal RE to storage device 1. Based on the reception of signal RE, storage device 1 outputs the read 8kB data Dout to memory controller 2.

[0271] Figure 38 This illustrates an example of a signal received between the storage device 1 and the memory controller 2 in the second embodiment. Specifically, Figure 38 This indicates the type 1 erase instruction set and the standby / busy signal. The type 1 erase instruction set is supplied from memory controller 2 to storage device 1.

[0272] The Type 1 erase instruction set includes the Type 1 erase address input instruction UUh, address information ADD, and erase start instruction CCh. The Type 1 erase instruction set indicates the erasure of one block of data (BLK).

[0273] The Type 1 erase address input instruction UUh instructs to erase the data of one block of BLK and notifies the address information ADD to follow.

[0274] Address information ADD, for example, spans three loops. Within these three loops, row addresses R1, R2, and R3 are transferred. The row address contains the memory plane address PLNA and the block address BA.

[0275] The erase start command CCh instructs the execution of data erasure.

[0276] When storage device 1 receives the erase start command CCh, it erases the data in the specified block BLK. During the data erasure, storage device 1 outputs a low-level standby / busy signal RB indicating that it is busy. The busy signal is, for example, output during the TE1 period.

[0277] Figure 39 This illustrates an example of a signal received between the storage device 1 and the memory controller 2 in the second embodiment. Specifically, Figure 39 This indicates the type 2 erase instruction set and the standby / busy signal. The type 2 erase instruction set is supplied from memory controller 2 to storage device 1.

[0278] The Type 2 erase instruction set includes the Type 2 erase address input instruction VVh, address information ADD, and erase start instruction CCh. The Type 2 erase instruction set instructs the erasure of half of the data in block HBLK.

[0279] The type 2 erase address input instruction VVh instructs to erase half of the data in block HBLK and notifies address information ADD to follow.

[0280] The row address of the address information ADD includes the memory plane address PLNA and the block address BA. The row address also includes the sub-memory plane address SPLNA.

[0281] When storage device 1 receives the erase start instruction CCh, it erases the data in the specified half-block HBLK. At this time, storage device 1 does not erase the data in the half-block HBLK not specified by the sub-memory plane address SPLNA within the block BLK specified by memory plane address PLNA and block address BA. During data erasure, storage device 1 outputs a low-level standby / busy signal RB indicating busy status. The busy signal, for example, spans the period TE2 output. Period TE2 is shorter than the busy period TE1 when receiving the first type of erase instruction set.

[0282] Reference Figure 34 , Figure 36 and Figure 38 The state during the described action is shown in Figure 23 As an example, if block address BA specifies block BLK_1, such as... Figure 23 As shown, upon receiving block address BA, block decoders BDe_1 and BDo_1 are activated. Upon activation, block decoder BDe_1 enables block selection signal BSSo_1, and block decoder BDo_1 enables block selection signal BSSe_1. Other block selection signals, BSS, are negated. As a result, half of blocks HBLKo_1 and half of blocks HBLKe_1 are selected. That is, the voltages for wiring SGD, CG, and SGS are transmitted to half of blocks HBLKo_1 and half of blocks HBLKe_1.

[0283] Figure 40 This indicates a state during the operation of a portion of the storage device in the second embodiment. Specifically, Figure 40 This indicates a state of the line decoder 11 in response to receiving an instruction that instructs writing data to the unit component CU, reading data from the unit component CU, or erasing data from the block BLK. In other words, Figure 40 Indicates reference Figure 35 , Figure 37 and Figure 39 A state during the described action. Figure 40 and Figure 23 Similarly, let's illustrate this with an example where block BLK_1 is specified for block address BA. Furthermore, Figure 40 An example is shown where the sub-memory cell array SMCAD is specified for the sub-memory plane address SPLNA.

[0284] like Figure 40 As shown, with Figure 23Similarly, block address BA_1 indicates the activation of block decoders BDe_1 and BDo_1. However, based on the sub-memory plane address SPLNA, which specifies the sub-memory cell array SMCAD, block decoder BDo_1 in block decoders BDe_1 and BDo_1 is activated, while block decoder BDe_1 is not activated. Therefore, only block decoder BDo_1 enables the block selection signal BSSo_1, while the other block selection signals BSS are negated. As a result, half of block HBLKo_1 is selected. That is, the voltages of wiring SGD, CG, and SGS are transmitted to half of block HBLKo_1.

[0285] On the other hand, in the non-selected half-block HBLKe_1, any of the transmission switches XS in the transmission switch group XSGe_1 is open. Therefore, the word line WL and the select gate lines SGDL and SGSL of the non-selected half-block HBLKe_1 are electrically floating.

[0286] In this state, data reading, data writing, or data erasure is performed by applying voltages based on patterns of data reading, data writing, or data erasure to wirings SGD, CG, and SGS. During data reading, for example, a read voltage Vcgr is applied to wiring CG connected to word line WL, which is connected to the half-cell component HCU to be read, and a read on voltage Vread is applied to other wirings CG. The read voltage Vcgr has a variable positive magnitude corresponding to the memory cell transistor MT to be read. The read on voltage Vread is independent of the data stored in the memory cell transistor MT, has a positive magnitude that turns on the memory cell transistor MT, and is higher than the read voltage Vcgr.

[0287] During data writing, for example, a program voltage Vpgm is applied to the wiring CG connected to the word line WL, which is connected to the half-cell component HCU to be written, and a program turn-on voltage Vpass is applied to the other wiring CG. The program voltage Vpgm has a positive magnitude that can inject electrons from the semiconductor 102 into the charge accumulation layer 104 of the memory cell transistor MT to be written. The program turn-on voltage Vpass has a positive magnitude that suppresses the writing of data to the memory cell transistor MT that receives this voltage, and is lower than the program voltage Vpgm.

[0288] During data erasure, for example, Vss (e.g., 0V) is applied to the wiring CG. Simultaneously, an erase voltage Vera is applied to the bit line BL and the source line SL. The erase voltage Vera has a positive magnitude that can pull electrons in the charge accumulation layer 104 of the memory cell transistor MT, which contains the data to be erased, toward the semiconductor 102.

[0289] 2.2. Advantages

[0290] The storage device 1 of the second embodiment supports two types of instruction sets. That is, the storage device 1 can recognize two types of instruction sets and execute the instructions of these instruction sets. The first type of instruction set instructs writing data to the unit component CU, reading data from the unit component CU, or erasing data from one block BLK. The second type of instruction set instructs writing data to half of the unit component HCU, reading data from half of the unit component HCU, or erasing data from half of the block HBLK. In other words, the first type of instruction set targets one block BLK, while the second type of instruction set targets half of the block HBLK. Operations targeting half of the block HBLK consume less current than operations targeting one block BLK. Therefore, the current consumption when operating only on half of the block HBLK is less than the current consumption in a storage device that only supports instruction sets targeting one block when the operation targets only half of the block. The current consumption is, for example, the operating current ICC of the storage device 1.

[0291] Furthermore, according to the second embodiment, since the target of the action can be specified for each half-block HBLK, each half-block HBLK can be managed. If each block BLK is managed individually, then in the event of a local defect in a certain block BLK, the entire block BLK needs to be replaced by a pre-prepared spare block. Thus, even for a local defect, a spare block of one block BLK size is required. This is inefficient because the normal portion of the replaced block containing the defect is not utilized, requiring a large number of spare blocks. According to the second embodiment, as described below, the area that cannot be used and needs to be replaced in the event of a local defect is the half-block HBLK containing the defect. Figure 41 This illustrates an example of a state during operation in the storage device 1 of the second embodiment. Figure 41 This indicates that half-block HBLKo_1 contains a faulty portion, i.e., a broken half-block, and is replaced by a spare redundant half-block HBLKo_R3 by controlling the replacement circuit in the line decoder 11. In this state, it is consistent with the first embodiment. Figure 23Similarly, block BLK_1 is designated. In this case, the block decoder BDe_1, which controls the normal half-block HBLKe_1, is started by the designation of block BLK_1. On the other hand, the block decoder BDo_1, which controls the malfunctioning half-block HBLKo_1, is not started. Instead, the block decoder BDo_R3, which controls the half-block HBLKo_R3, is started by the designation of block BLK_1. As a result, the block selection signal BSSo_R3 is activated, and the transmission switches XSD, XSW, and XSS in the transmission switch group XSGo_R3 are turned on. Thus, the state of selecting half-block HBLKo_R3 is achieved. The units that need to be replaced are limited to half-block HBLK. Thus, replacement can be performed efficiently. That is, areas that cannot be used due to replacement can be suppressed, and many spare areas can be prepared.

[0292] 3. Third Implementation Method

[0293] The difference between the third embodiment and the first embodiment lies in the details of the line decoder.

[0294] Figure 42 The components of the line decoder of the storage device 1 in the third embodiment and the connections of the components are shown. Figure 42 This is shown for two sub-memory plane regions SPNAu and SPNAd, which are constituent elements of a single memory plane PLN.

[0295] like Figure 42 As shown, the difference between the third embodiment and the first embodiment lies in the constituent elements of the sub-memory plane region SPNAd in each of the line decoder regions RDA1 and RDA1.

[0296] The portion of the row decoder region RDA1 contained within the sub-memory plane region SPNAd contains n / 2 block decoders BDo. The n / 2 block decoders BDo are used for odd-numbered block addresses BA, namely block decoders BDo_1, BDo_3, BDo_5, ..., BDo_n-1 for block addresses BA_1, BA_3, BA_5, ..., BA_n-1.

[0297] The portion of the line decoder region RDA1 contained within the sub-memory plane region SPNAd contains n / 2 transfer switch groups XSGo. These n / 2 transfer switch groups XSGo are used for odd-numbered block addresses BA, specifically the transfer switch groups XSGo_1, XSGo_3, XSGo_5, ..., XSGo_n-1 for block addresses BA_1, BA_3, BA_5, ..., BA_n-1.

[0298] The portion of the row decoder region RDA contained within the sub-memory plane region SPNAd contains n / 2 block decoders BDo. These n / 2 block decoders BDo are for even-numbered block addresses BA, specifically block decoders BDo_0, BDo_2, BDo_4, ..., BDo_n-2 for block addresses BA_0, BA_2, BA_4, ..., BA_n-2.

[0299] The portion of the line decoder region RDA contained within the sub-memory plane region SPNAd contains n / 2 transfer switch groups XSGo. These n / 2 transfer switch groups XSGo are used for even-numbered block addresses BA, specifically the transfer switch groups XSGo_0, XSGo_2, XSGo_4, ..., XSGo_n-2 for block addresses BA_0, BA_2, BA_4, ..., BA_n-2.

[0300] With the above configuration, the transmission switch group XSGe and the block decoder BDe, which are used to form one of the two half-blocks HBLKe and HBLKo of each block BLK, are configured in one of the line decoder areas RDA1 and RDA1, and the transmission switch group XSGo and the block decoder BDo, which are used to form the other half-block HBLKe and HBLKo, are configured in the other of the line decoder areas RDA1 and RDA1.

[0301] In other words, for each block BLK, the block decoder BDe and the transport switch group XSGe for that block BLK, and the block decoder BDo and the transport switch group XSGo for that block BLK, are located in different line decoder regions RDA1 and RDA1. On the other hand, in the first embodiment (see...) Figure 22 Regarding each block BLK, the block decoder BDe and the transport switch group XSGe used for that block BLK, as well as the block decoder BDo and the transport switch group XSGo used for that block BLK, are located in the same row decoder region in the row decoder regions RDA1 and RDA1.

[0302] Figure 43 This shows the constituent elements of the driver according to the third embodiment and the connections between the constituent elements. Figure 43 Also shown Figure 42 The components of a line decoder are shown.

[0303] Hereinafter, the wiring CG, SGD, and SGS connected to transmission switch groups XSGo_1, XSGo_3, XSGo_5, ..., XSGo_n-1 are sometimes referred to as wiring CGl, SGDl, and SGSl, respectively. The wiring CG, SGD, and SGS connected to transmission switch groups XSGo_0, XSGo_2, XSGo_4, ..., XSGo_n-2 are sometimes referred to as wiring CGr, SGDr, and SGSr, respectively.

[0304] like Figure 43 As shown, the voltage generation circuit 14 outputs voltages on multiple wiring lines INT respectively. Figure 43 The following diagram illustrates an example of 5 wiring lines INT.

[0305] Driver 15 includes CG line decoding circuits 151l and 151r. CG line decoding circuits 151l and 151r decode address information ADD and output a voltage based on the decoding result from the voltage generation circuit 14. CG line decoding circuits 151l and 151r have the same components and connections. That is, a common pattern of voltage needs to be applied to the group of wirings CGl, SGDl, and SGSl and the group of wirings CGr, SGDr, and SGSr. For this purpose, identical CG line decoding circuits 151l and 151r are provided.

[0306] The CG line decoding circuit 151l is connected to multiple wiring INTs and receives voltage from the voltage generation circuit 14 via the wiring INTs. Based on the decoding result, the CG line decoding circuit 151l applies the voltage from the voltage generation circuit 14 to the group of wirings CG1, SGD1, and SGS1.

[0307] Groups of wiring CGl, SGDl and SGSl, and groups of wiring CGr, SGDr and SGSr, accept voltages of substantially the same (identical) pattern.

[0308] The CG line decoding circuit 151r is connected to multiple wiring INTs and receives voltage from the voltage generation circuit 14 via the wiring INTs. Based on the decoding result, the CG line decoding circuit 151r applies the voltage from the voltage generation circuit 14 to the group of wirings CGr, SGDr, and SGSr.

[0309] Figure 44 This indicates a state during operation of the storage device in the third embodiment. Figure 44 This is shown for two sub-memory plane regions SPNA that form the constituent elements of a memory plane PLN. Figure 44 This indicates the state of selecting one block (BLK). Figure 44 This represents an example of specifying block address BA_1.

[0310] like Figure 44 As shown, upon receiving block address BA_1, block decoders BDe_1 and BDo_1 are started. (Refer to the above text.) Figure 42 The transmission switch group XSGe and block decoder BDe, used to constitute one of the two half-blocks HBLKe and HBLKo of each block BLK, are configured in one of the line decoder regions RDA1 and RDA1, and the transmission switch group XSGo and block decoder BDo, used to constitute the other half of the two half-blocks HBLKe and HBLKo, are configured in the other of the line decoder regions RDA1 and RDA1. Therefore, by selecting one block BLK, the transmission switch group XSG and block decoder BD are activated in each of the line decoder regions RDA1 and RDA1.

[0311] Upon startup, block decoder BDe_1 activates block selection signal BSSe_1, and block decoder BDo_1 activates block selection signal BSSo_1. Other block selection signals BSS are negated. As a result, the system selects half of blocks HBLKe_1 and HBLKo_1. That is, it transmits voltages for wiring CGr, SGDr, and SGSr to half of block HBLKe_1, and voltages for wiring CGl, SGDl, and SGSl to half of block HBLKo_1.

[0312] Transmission switch group XSGe receives voltage from wirings CGr, SGDr, and SGSr, while transmission switch group XSGo receives voltage from wirings CGl, SGDl, and SGSl. Therefore, both CG line decoding circuits 151l and 151r are activated to apply voltage to wirings CGl, SGDl, SGSl, CGr, SGDr, and SGSr.

[0313] Through the above actions, voltages with essentially the same pattern are transmitted to both half-blocks HBLKe_1 and HBLKo_1.

[0314] According to the third embodiment, the transmission switch group XSGe and the block decoder BDe for one of the two half-blocks HBLKe and HBLKo constituting each block BLK are configured in one of the line decoder regions RDA1 and RDA1, and the transmission switch group XSGo and the block decoder BDo for the other half-block HBLKe and HBLKo are configured in the other line decoder region RDA1 and RDA1. Thus, since a certain block BLK is selected, voltage can be transmitted from different groups of wirings CG, SGD, and SGS to the two half-blocks HBLK constituting the selected block BLK. Therefore, the groups of wirings CGl, SGDl, and SGSl, and the groups of wirings CGr, SGDr, and SGSr, only carry the current required to charge the word line WL and the select gate lines SGDL and SGSL of the half-block HBLK. The magnitude of this current is less than the current flowing through wirings CG, SGD, and SGS when the word line WL, select gate line SGDL, and SGSL of a block BLK are charged by the CG line decoding circuit 151l or 151r. Therefore, the voltage drop generated in the group of wirings CGl, SGDl, and SGSl, and the voltage drop generated in wirings CGr, SGDr, and SGSr, are less than the voltage drop generated in wirings CG, SGD, and SGS when the word line WL, select gate line SGDL, and SGSL of a block BLK are charged by the CG line decoding circuit 151l or 151r. Therefore, with the third embodiment, the time required to charge the word line WL, select gate line SGDL, and SGSL of a block BLK via two sets of wirings CG, SGD, and SGS is shorter than the time required to charge the word line WL, select gate line SGDL, and SGSL of a block BLK via only one set of wirings CG, SGD, and SGS.

[0315] 4. Fourth Implementation Method

[0316] The fourth embodiment differs from the third embodiment in the constituent elements of the driver 15.

[0317] Figure 45 This shows the constituent elements of the driver according to the fourth embodiment and the connections between the constituent elements. Figure 45 The third embodiment is also shown. Figure 42 The components of a line decoder are shown.

[0318] The driver 15 includes a CG line decoding circuit 152. The CG line decoding circuit 152 is identical to the CG line decoding circuits 151l and 151r of the third embodiment. The CG line decoding circuit 152 is connected to a plurality of wiring INTs and receives voltage from the voltage generation circuit 14 via the wiring INTs. The CG line decoding circuit 152 is connected to both a group of wirings CGl, SGDl, and SGSl, and a group of wirings CGr, SGDr, and SGSr. Based on the decoding result, the CG line decoding circuit 152 applies the voltage from the voltage generation circuit 14 to both the group of wirings CGl, SGDl, and SGSl, and the group of wirings CGr, SGDr, and SGSr.

[0319] According to the fourth embodiment, similar to the third embodiment, the groups of wirings CGl, SGDl, and SGSl, and the groups of wirings CGr, SGDr, and SGSr, only carry the current required to charge the word line WL and select gate lines SGDL and SGSL of half of the block HBLK. Therefore, the same advantages as the third embodiment are obtained.

[0320] 5. Fifth Implementation Method

[0321] The fifth embodiment differs from the first embodiment in the layout of the constituent elements in each memory surface region (PNA).

[0322] Figure 46 and Figure 47 This diagram shows the layout and several constituent elements of a portion of the storage device according to the fifth embodiment. Figure 46 and Figure 47 This represents one memory plane region (PNA). Four memory plane regions (PNAs) have the same structure. Figure 46 and Figure 47 This represents the regions with different coordinates on the z-axis. Figure 46 Indicates the position on the z-axis relative to the first embodiment. Figure 6 The areas shown are different regions. Figure 47 Indicates the position on the z-axis relative to the first embodiment. Figure 7 The areas shown are different regions.

[0323] like Figure 46 As shown, the row decoder regions RDA1 and RDA2 are located in the center of the memory plane region PNA. The row decoder regions RDA1 and RDA2 are arranged along the x-axis and are adjacent to each other.

[0324] One sense amplifier region SAA in the sub-memory plane region SPNAu is located to the left of the row decoder region RDA1. Another sense amplifier region SAA in the sub-memory plane region SPNAu is located to the right of the row decoder region RDA1.

[0325] One sense amplifier region SAA in the sub-memory plane region SPNAd is located to the left of the row decoder region RDA1. Another sense amplifier region SAA in the sub-memory plane region SPNAd is located to the right of the row decoder region RDA1.

[0326] like Figure 47 As shown, each sub-memory plane region SPNA includes two sub-memory cell arrays SMCA, comprising two sub-memory cell arrays SMCA with shapes corresponding to the sub-memory cell array SMCA of the first embodiment after being divided. More specifically, sub-memory plane region SPNAu includes sub-memory cell arrays SMCAul and SMCAur. Sub-memory cell array SMCAul is located at the left end of sub-memory plane region SPNAu. Sub-memory cell array SMCAur is located at the right end of sub-memory plane region SPNAu. The constituent elements included in the sub-memory cell array SMCAu of the first embodiment are arranged across sub-memory cell arrays SMCAul and SMCAur.

[0327] The sub-memory plane region SPNAd includes sub-memory cell arrays SMCAd1 and SMCAdr. Sub-memory cell array SMCAd1 is located at the left end of the sub-memory plane region SPNAd. Sub-memory cell array SMCAdr is located at the right end of the sub-memory plane region SPNAd. The constituent elements included in the sub-memory cell array SMCAd of the first embodiment are arranged across the sub-memory cell arrays SMCAd1 and SMCAdr.

[0328] The word line connection areas WHUAl and WHUAr span the area between the sub-memory cell arrays SMCAul and SMCAur, and the area between the sub-memory cell arrays SMCAdl and SMCAdr.

[0329] The boundary between a sub-memory cell array SMCAur of a certain sub-memory plane region SPNA and a sub-memory cell array SMCAul of an adjacent memory plane region PNA can be separated by an insulator such as oxide extending along the yz plane. Alternatively, the boundary between a sub-memory cell array SMCAur of a certain memory plane region PNA and a sub-memory cell array SMCAul of an adjacent memory plane region PNA can also be separated by a stacked body extending along the yz plane and having alternating layers of silicon oxide and silicon nitride.

[0330] Similarly, the boundary between a sub-array SMCADr of a memory plane region PNA and a sub-array SMCADl of an adjacent memory plane region PNA can be separated by an insulator such as oxide extending along the yz plane. Alternatively, the boundary between a sub-array SMCADr of a memory plane region PNA and a sub-array SMCADl of an adjacent memory plane region PNA can also be separated by a stacked body extending along the yz plane and alternately arranged with layers of silicon oxide and silicon nitride.

[0331] Figure 48 This shows a cross-sectional view of a portion of the storage device 1 according to the fifth embodiment. Specifically, Figure 48 express Figure 47 The cross-section of the structure shown is along the xz plane.

[0332] Figure 48 and Figure 27 Their structures are similar. For example... Figure 48 As shown, two stacked structures 39 are provided in the sub-memory surface region SPNA. A memory pillar MP is provided in each stacked structure 39. The right end portion of the left-hand stacked structure 39 is included in the word line wiring region WHUA1. Each conductor 44 of the left-hand stacked structure 39 has a stepped portion in the word line wiring region WHUA1, i.e., a portion that does not overlap with another conductor 44. Each conductor 44 is connected to a contact plug 67 at the stepped portion.

[0333] The portion of the left end of the right-side stacked structure 39 is contained within the word line wiring area WHUAr. Each conductor 44 of the right-side stacked structure 39 has a stepped portion within the word line wiring area WHUAr, i.e., a portion that does not overlap with another conductor 44. Each conductor 44 is connected to a contact plug 67 at the stepped portion.

[0334] Figure 49 This illustrates the constituent elements of the storage cell array in the fifth embodiment and an example of assigning addresses to the constituent elements. Figure 49 This is illustrated for a single memory plane PLN. In the fifth embodiment, each half-block HBLK is separated on both sides by two line decoder regions RDA1 and RDA1. That is, as... Figure 49As shown, the sub-array SMCA contains a quarter-block QBLK. More specifically, the sub-array SMCAul contains a quarter-block QBLKel. The sub-array SMCAur contains a quarter-block QBLKer. The sub-array SMCAdl contains a quarter-block QBLKol. The sub-array SMCAdr contains a quarter-block QBLKor. A quarter-block QBLK consists of one-quarter of a block BLK, which is composed of half of a block HBLK.

[0335] Quarter blocks QBLKel and QBLKer constitute half of block HBLKe. Quarter blocks QBLKol and QBLKor constitute half of block HBLKo.

[0336] Each quarter block (QBLK) contains multiple quarter cell components (QCUs). A quarter cell component (QCU) contains one-quarter the number of memory cell transistors (MTs) that make up the cell component (CU). Therefore, a quarter cell component (QCU) stores one-quarter of a page's size (i.e., one-quarter page data) when each memory cell transistor (MT) stores 1 bit of data. Similarly, a quarter cell component (QCU) stores p quarter pages of data when each memory cell transistor (MT) stores p bits of data.

[0337] The quarter-unit components (QCUs) of the four quarter-blocks (QBLK) are assigned a common set of page addresses. That is, page addresses PGA0 to PGA0A are assigned to each quarter-block (QBLK).

[0338] m / 4 bit lines BL are located in each sub-memory cell array SMCA. The bit lines BL extend across the quarter blocks QBLK in each sub-memory cell array SMCA. Taking an example where m is 16kB, then in each quarter block QBLK, m / 4, for example, 4kB, memory cell transistors MT are arranged along the direction of the bit lines BL. The memory cell transistors MT of quarter block QBLKel are connected, for example, to bit lines BL_0 to BL_m / 4-1. The memory cell transistors MT of quarter block QBLKer are connected, for example, to bit lines BL_m / 4 to BL_m / 2-1. The memory cell transistors MT of quarter block QBLKol are connected, for example, to bit lines BL_m / 2 to BL_3m / 4-1. The memory cell transistors MT of quarter block QBLKor are connected, for example, to bit lines BL_3m / 4 to BL_m-1.

[0339] The selection of the quarter-cell component QCU based on a certain address information ADD is the same as in the first embodiment. That is, the difference between the fifth embodiment and the first embodiment is that the half-block HBLK in the first embodiment is configured across two independent regions. This difference is in the configuration and layout of the constituent elements; however, the connections of the constituent elements, i.e., the circuitry, are the same in both the first and fifth embodiments. Therefore, the state of selecting a certain half-cell component HCU in the first embodiment is equivalent to selecting the state of two quarter-cell component QCUs corresponding to that half-cell component HCU in the fifth embodiment. Thus, in the fourth embodiment, the quarter-cell component QCUs of each of the four sub-memory cell arrays SMCA can be selected by specifying one memory plane address PLNA, one block address BA, and one page address PGA.

[0340] Figure 50 This shows the constituent elements of the line decoder in the fifth embodiment and the connections between these constituent elements. Figure 50 This is shown for two sub-memory plane regions SPNAu and SPNAd, which are constituent elements of a memory plane PLN.

[0341] The constituent elements contained in the line decoder regions RDA1 and RDA1 are the same as those in the first embodiment.

[0342] like Figure 50 The diagram shows the pattern of voltage transmissions via wiring CG, SGD, and SGS to each of the two connected quarter-blocks QBLK, with each XSG group XSGe_α transmitting voltage to one quarter-block QBLKel_α and one quarter-block QBLKer_α. Specifically, for all instances where α is 0 or higher than n-1, each XSG group XSGe_α transmits voltage to one quarter-block QBLKel_α and one quarter-block QBLKer_α. For all instances where α is 0 or higher than n-1, each XSG group XSGgo_α transmits voltage to one quarter-block QBLKol_α and one quarter-block QBLKor_α.

[0343] Figure 51 This illustrates an example of signals transmitted and received between the storage device 1 and the memory controller 2 in the fifth embodiment. Specifically, Figure 51 This indicates the type 3 write instruction set and the standby / busy signal. The type 3 write instruction set is supplied from memory controller 2 to storage device 1.

[0344] The third type of write instruction set includes the third type of write address input instruction SSh, address information ADD, and write start instruction AAh. Write data Din is sent between the address information ADD and the write start instruction AAh. The third type of write instruction set instructs the writing of data to the quarter-cell component QCU, which is equivalent to writing a quarter-page size of data (4kB) to the 4kB memory cell transistors MT.

[0345] The Type 3 write address input instruction SSh indicates that 4kB of data should be written, and the address information ADD follows.

[0346] The address information ADD specifies the quarter-cell component (QCU) to be written to. The row address includes the memory plane address PLNA, block address BA, page address PGA, and sub-memory plane address SPLNA. The sub-memory plane address SPLNA specifies one of the sub-memory cell arrays SMCAul, SMCAur, SMCAdl, and SMCAdr. The sub-memory plane address SPLNA, for example, has a length of 2 bits. For example, the sub-memory plane address SPLNA specifies the sub-memory cell array SMCAul with a value of "00", the sub-memory cell array SMCAur with a value of "01", the sub-memory cell array SMCAdl with a value of "10", and the sub-memory cell array SMCAdr with a value of "11".

[0347] As mentioned above Figure 18 The two sub-memory cell arrays (MCAs) forming a single memory plane (PLN) have groups sharing the same memory plane address (PLNA), the same block address (BA), and the same page address (PGA). Therefore, the memory plane address (PLNA), block address (BA), and page address (PGA) in the address information (ADD) specify a total of four quarter-cell components (QCUs) for each of the four sub-memory cell arrays (SMCA). However, the third type of write instruction set includes a sub-memory plane address (SPLNA), which specifies the sub-memory cell array (SMCA). Therefore, the sub-memory plane address (SPLNA) specifies only one quarter-cell component (QCU) from the four quarter-cell components (QCUs) within the sub-memory cell array (SMCA) specified by the sub-memory plane address (SPLNA).

[0348] The 4kB write data digit spans dozens of loop transfers.

[0349] When storage device 1 receives a write start command AAh, it writes 4kB of data to the designated quarter-cell component QCU, which is smaller than the data size when a type 2 write command set is received. During the data write, storage device 1 outputs a low-level standby / busy signal RB indicating busy status. The busy signal, for example, spans period TP3. Period TP3 is shorter than the busy period TP2 when a type 2 write command set is received. The difference between period TP3 and period TP2 is less than the difference between period TP2 and the busy period TP1 when a type 1 write command set is received.

[0350] Figure 52 This illustrates an example of signals transmitted and received between the storage device 1 and the memory controller 2 in the fifth embodiment. Specifically, Figure 52 This indicates the type 3 read instruction set and the standby / busy signal. The type 3 read instruction set is supplied from memory controller 2 to storage device 1.

[0351] The third type of read instruction set includes the third type of read address input instruction TTh, address information ADD, and read start instruction BBh. The third type of read instruction set indicates that data is read from the quarter-cell component QCU, that is, a quarter-page size of data, i.e., 4kB of data, is read from the 4kB memory cell transistors MT.

[0352] The Type 3 read address input instruction TTh instructs the reading of 4kB of data and notifies the address information ADD to follow.

[0353] The address information ADD specifies the quarter-cell unit (QCU) from which data is to be read. The row address includes the memory plane address PLNA, the block address BA, and the page address PGA. The row address also includes the sub-memory plane address SPLNA.

[0354] The memory plane address PLNA, block address BA, page address PGA, and sub-memory plane address SPLNA specify only one quarter cell component QCU in the sub-memory cell array SMCA specified by the sub-memory plane address SPLNA.

[0355] When storage device 1 receives a read start command BBh, it reads 4kB of data from the specified quarter unit component QCU. During the data readout, storage device 1 outputs a low-level standby / busy signal RB indicating busy status. The busy signal is output, for example, across period TR2. Period TR3 is shorter than the busy period TR2 when a second type of read command set is received. The difference between period TR3 and period TR2 is less than the difference between period TR2 and the busy period TR1 when a first type of read command set is received.

[0356] Select a quarter-page unit (QCU) based on the received row address. Then, read data of a quarter page size (i.e., data smaller than the data size received in the case of a type 2 read instruction set) from the selected quarter-page unit (QCU).

[0357] When data reading is complete, memory controller 2 repeatedly supplies an activated signal RE to storage device 1. Based on the reception of signal RE, storage device 1 outputs the read 4kB data Dout to memory controller 2.

[0358] Figure 53 This indicates a state during operation of the storage device in the fifth embodiment. Figure 53 This is shown for two sub-memory plane regions SPNA that form the constituent elements of a memory plane PLN. Figure 53 This indicates the state of selecting one block (BLK). Figure 53 This represents an example of specifying block address BA_1.

[0359] like Figure 53 As shown, upon receiving block address BA_1, block decoder BDe_1 and block decoder BDo_1 are activated. Similar to the third embodiment, the transmission switch group XSGe and block decoder BDe for one of the two halves of each block BLK, HBLKe and HBLKo, are configured in one of the line decoder regions RDA1 and RDA1, and the transmission switch group XSGo and block decoder BDo for the other half of the two halves of HBLKe and HBLKo are configured in the other of the line decoder regions RDA1 and RDA1. Therefore, by selecting one block BLK, the transmission switch group XSG and the block decoder BD are activated in each of the line decoder regions RDA1 and RDA1.

[0360] Upon startup, block decoder BDe_1 activates block selection signal BSSe_1, and block decoder BDo_1 activates block selection signal BSSo_1. Other block selection signals BSS are negated. As a result, the state of selecting quarter-blocks QBLKel_1, QBLKer_1, QBLKol_1, and QBLKor_1 is achieved. That is, the state of transmitting voltages of wiring CGl, SGDl, and SGSl to quarter-blocks QBLKol_1 and QBLKor_1, and transmitting voltages of wiring CGr, SGDr, and SGSr to quarter-blocks QBLKel_1 and QBLKer_1. Thus, voltages of substantially the same pattern are transmitted to all quarter-blocks QBLKel_1, QBLKer_1, QBLKol_1, and QBLKor_1.

[0361] According to the fifth embodiment, since the row decoder regions RDA1 and RDA1 are located in the center of the memory plane region PNA, the sub-memory cell array SMCA includes independent sections located on both sides of the row decoder regions RDA1 and RDA1. However, each transmission switch group XSG is connected to both of the two quarter blocks QBLK, and the voltage pattern of the wiring CG, SGD, and SGS can be transmitted to both of the connected two quarter blocks QBLK. Therefore, by selecting one block BLK, it is possible to transmit a voltage pattern that is substantially the same to all four quarter blocks QBLK. Thus, even when the row decoder regions RDA1 and RDA1 are located in the center of the memory plane region PNA, the same advantages as in the first embodiment are obtained.

[0362] 6. Examples of variations, etc.

[0363] The above description pertains to an example where a memory cell transistor MT stores 1 bit of data, thereby allocating one page address PGA to one cell component. The instance of allocating multiple page addresses to one cell component CU is the same as the instance of allocating one page address PGA to one cell component CU. That is, with... Figure 19 Similarly, the block address BA_0 is specified, and then the page address PGA_1 is specified. Through this specification, the half-unit component HCU, connected to the word line WL with the same word line address WLA, is selected from both half-blocks HBLKe_1 and HBLK_o1. Then, one of the multiple pages provided by the selected half-unit component HCU, based on page address PGA_1, is specified.

[0364] While several embodiments of the present invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are also included in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A storage device comprising: The first conductor extends along the first axis and the second axis; The first memory pillar is disposed inside the first conductor and includes a first semiconductor and a charge accumulation layer surrounding the first semiconductor; The second conductor extends along the second axis and is connected to the first memory column; The third conductor extends along the first axis and the second axis, and is arranged with a gap between it and the first conductor along the second axis; The second memory pillar is disposed inside the third conductor and includes a second semiconductor and a charge accumulation layer surrounding the second semiconductor; A fourth conductor extends along the second axis and is connected to the second memory pillar; and The fifth conductor extends along the second axis and is connected to the first memory pillar and the second memory pillar.

2. The storage device according to claim 1, further comprising a third semiconductor, the third semiconductor being connected to the first semiconductor and the second semiconductor, and connected to the fifth conductor, and containing impurities.

3. The storage device according to claim 1, wherein The second conductor is connected to the first sensing amplifier circuit. The fourth conductor is connected to the second sensing amplifier circuit.

4. The storage device of claim 3, wherein the first sense amplifier circuit and the second sense amplifier circuit are located below the first conductor and the third conductor along a third axis intersecting the first axis and the second axis.

5. The storage device according to claim 1, further comprising: The first pad; and The first transistor is connected to the fifth conductor; and The first pad, the third conductor, the first conductor, and the first transistor are arranged sequentially along the second axis.

6. The storage device according to claim 1, further comprising: Substrate; The second transistor is located on the substrate; The sixth conductor, connected to the second transistor, has an inverted conical shape; and The seventh conductor, disposed on the sixth conductor, has a conical shape.

7. The storage device according to claim 1, further comprising: Substrate; The second transistor is disposed on the substrate, located between the substrate and the first conductor; The eighth conductor is located above the first memory pillar along the third axis and connected to the first memory pillar, the third axis intersecting the first axis and the second axis; and The 9th conductor, connected to the 2nd transistor and the 8th conductor, extends along the 3rd axis.

8. The storage device according to claim 1, further comprising a 10th conductor extending along the 2nd axis and arranged with the 5th conductor along the 1st axis, having an externally exposed portion.

9. The storage device according to claim 1, further comprising: The 11th conductor is arranged along the first axis with the first conductor and extends along both the first and second axes; The third memory pillar is disposed inside the 11th conductor, includes a third semiconductor and a charge accumulation layer around the third semiconductor, and is connected to the fifth conductor; The 12th conductor is located above the 1st conductor along a 3rd axis that intersects the 1st and 2nd axes, connected to the 1st conductor, and extends along the 3rd axis; and The 13th conductor is located above the 11th conductor along the 3rd axis, connected to the 11th conductor, and extends along the 3rd axis.

10. The storage device according to claim 9, further comprising: The first switch has a first terminal connected to the first conductor and a second terminal connected to the first wiring. The first decoder is connected to the control terminal of the first switch via the second wiring; The second switch has a third terminal connected to the third conductor and a fourth terminal connected to the first wiring; and The second decoder is connected to the control terminal of the second switch via the third wiring; and During the period when the signal on the second wiring is denied and the signal on the third wiring is enabled, a first voltage is applied to the third conductor.

11. The storage device according to claim 1, further comprising a first insulator located above the region between the first conductor and the third conductor and opposite to the second conductor and the fourth conductor.

12. The memory device of claim 11, further comprising a fourth semiconductor, the fourth semiconductor being connected to the first memory pillar and the second memory pillar and containing impurities. The first insulator is partially located within the fourth semiconductor.

13. The storage device according to claim 1, further comprising: The first switch has a first terminal connected to the first conductor and a second terminal connected to the first wiring. The first decoder is connected to the control terminal of the first switch via the second wiring; The second switch has a third terminal connected to the third conductor and a fourth terminal connected to the first wiring; and The second decoder is connected to the control terminal of the second switch via the third wiring.

14. The storage device of claim 13, wherein during the period when the signal on the second wiring is active, the signal on the third wiring is active.

15. The storage device according to claim 13, wherein Based on the receipt of the first instruction, during the period when the signal on the second wiring is active, the signal on the third wiring is active. Based on the receipt of the second instruction, during the period when the signal across the second wiring is denied, the signal on the third wiring is activated.

16. The storage device according to claim 13, further comprising: The 13th conductor extends along the first axis and the second axis; The fourth memory pillar is disposed inside the 13th conductor and includes a fourth semiconductor and a charge accumulation layer surrounding the fourth semiconductor; The third switch has a fifth terminal connected to the 13th conductor and a sixth terminal connected to the first wiring; and The third decoder is connected to the control terminal of the third switch via the fourth wiring; and Based on the receipt of a first instruction indicating the activation of signals on the second and third wiring lines, the signals on the second and fourth wiring lines are activated.

17. The storage device according to claim 1, further comprising: The first switch has a first terminal connected to the first conductor and a second terminal connected to the fourth decoder; and The second switch has a third terminal connected to the third conductor and a fourth terminal connected to the fifth decoder.

18. The storage device according to claim 1, further comprising: The first switch has a first terminal connected to the first conductor and a second terminal connected to the sixth decoder; and The second switch has a third terminal connected to the third conductor and a fourth terminal connected to the sixth decoder.

19. The storage device according to claim 1, further comprising a controller configured such that, when the storage device receives a third instruction, it reads data of charge based on the charge accumulation layer of the first memory column, but does not read data of charge based on the charge accumulation layer of the second memory column.

20. The storage device according to claim 1, further comprising a controller configured such that, when the storage device receives a fourth instruction, it erases data based on the charge accumulation layer of the first memory column, but does not erase data based on the charge accumulation layer of the second memory column.

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