Method of manufacturing an mram

Abstract

The application provides a preparation method of MRAM, comprising the following steps: providing a substrate, wherein a via is formed on the substrate; forming a first bottom electrode film above the via; performing a first thinning treatment on the first bottom electrode film; forming a dielectric layer film above the first bottom electrode film after the first thinning treatment; performing photoetching and etching on an alignment mark; removing the dielectric layer film; performing a second thinning treatment on the first bottom electrode film; and forming a second bottom electrode film above the first bottom electrode film after the second thinning treatment. The application can improve the ability of the first bottom electrode film to prevent copper diffusion.

Description

Technical Field

[0001] This invention relates to the field of magnetic random access memory (MRAM) technology, and more particularly to a method for preparing MRAM. Background Technology

[0002] With the rapid development of electronic technology, non-volatile memory has become a key research focus. Non-volatile memory, with its high density, fast read / write speeds, and ultra-long lifespan, has broad market application prospects.

[0003] Magnetic random access memory (MRAM), as a representative of next-generation non-volatile memory, is currently the most promising for mass production. In the MRAM manufacturing process, yield is a key indicator of mass production capability. According to existing metal architectures, the bottom electrode (BE) film of the magnetic tunnel junction is grown above the via. After growing the BE film, alignment marks need to be photolithographically / etched; these alignment marks will be used later when patterning the BE. Because the BE is relatively thick and has poor light transmittance, photolithography cannot penetrate the BE for alignment. Therefore, the actual product process is improved, dividing the bottom electrode fabrication into two steps: after growing the first BE layer, it is thinned, and alignment marks are photolithographically / etched, and then the second BE layer is grown.

[0004] In the fabrication steps of the aforementioned bottom electrode, the copper surface of the vias has depressions after chemical mechanical polishing, and the first BE film is very thin after thinning. Therefore, the first BE film suffers from poor film continuity, and its thickness and flatness are insufficient to prevent copper from diffusing outwards from the vias. This leads to copper diffusion (cubiffuse). Furthermore, the long time required for subsequent photolithography / etching of alignment marks further increases the risk of copper diffusion. Copper diffusion significantly impairs yield; at best, it increases defects, and at worst, it can cause series short circuits. Therefore, it is urgent to solve the copper diffusion problem caused by BE thinning in the bottom electrode fabrication process. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a method for fabricating MRAM that, without altering the existing structural design, optimizes the process flow to enhance the ability of the first bottom electrode film to prevent copper diffusion, effectively solving the copper diffusion problem.

[0006] This invention provides a method for preparing MRAM, comprising:

[0007] A substrate is provided, wherein through-holes are formed on the substrate;

[0008] A first bottom electrode film is formed above the through hole;

[0009] The first bottom electrode film is subjected to a first thinning process;

[0010] A dielectric layer film is formed on top of the first bottom electrode film after the first thinning;

[0011] Perform photolithography and etching of alignment marks;

[0012] Remove the dielectric layer film;

[0013] The first bottom electrode film is subjected to a second thinning process;

[0014] A second bottom electrode film is formed on top of the first bottom electrode film after the second thinning.

[0015] Optionally, the dielectric layer film is a single-layer film structure containing SiN, SiC, or SiCN.

[0016] Optionally, the dielectric layer film is a composite film structure of SiN and SiC.

[0017] Optionally, the thickness of the dielectric layer film is between 10 and 100 nm.

[0018] Optionally, the dielectric layer film can be grown in one of the following ways: atomic layer deposition or chemical vapor deposition.

[0019] Optionally, the time interval between the first thinning treatment of the first bottom electrode film and the formation of the dielectric layer film needs to be controlled.

[0020] Optionally, the method for removing the dielectric layer film includes one of chemical mechanical polishing, wet etching, and dry etching, or a combination of the three methods.

[0021] Optionally, the time interval between the second thinning process of the first bottom electrode film and the formation of the second bottom electrode film needs to be controlled.

[0022] Optionally, the material combination of the first bottom electrode film and the second bottom electrode film includes any one of the following: TaN / TiN, TaN / TaN, TiN / TaN, TiN / TiN.

[0023] Optionally, the method further includes:

[0024] Alignment is performed according to the alignment marks, and the formed bottom electrode is patterned, the bottom electrode comprising a first bottom electrode film and a second bottom electrode film.

[0025] The MRAM fabrication method provided by this invention involves growing a dielectric layer with good light transmittance for protection after the first bottom electrode film is thinned. After the photolithography / etching of the alignment mark is completed, the dielectric layer film is removed, and another bottom electrode film is grown. The dielectric layer film can prevent copper in the via from diffusing outward, greatly reducing the risk of copper diffusion and improving the device yield. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the process flow of an MRAM fabrication method according to an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of the process flow for another embodiment of the MRAM fabrication method of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of this disclosure.

[0029] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0030] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0031] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] This invention provides a method for preparing MRAM, such as... Figure 1As shown, it includes the following steps:

[0033] like Figure 1 As shown in (a), the first step involves providing a substrate 1 with a low-k dielectric layer 2 and vias 3. The vias 3 are typically filled with copper. After chemical mechanical polishing, due to the properties of copper, depressions form on the surface of the vias 3. A first bottom electrode film 4 is formed above the vias 3 by deposition, serving as a copper barrier layer. The thickness of the first bottom electrode film 4 is 200–350 Å, and the surface of the first BE film 4 also has depressions. The material of the first bottom electrode film includes, but is not limited to, materials capable of blocking copper, such as TaN and TiN.

[0034] like Figure 1 As shown in (b), in the second step, the oxide layer on the first bottom electrode film 4 is thinned by CMP treatment, and a dielectric film 5 with good light transmittance is grown as a capping layer. In this embodiment, the dielectric film 5 is an N / C dielectric film, which can be a single-layer film containing SiN, SiC, or SiCN, or a composite film structure of SiN and SiC, etc. The dielectric film 5 is required to have good light transmittance, relatively dense structure, and strong pore-filling ability. The dielectric film 5 is grown by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The deposited Si source precursors include, but are not limited to, K5, TSA, SiH4, etc. The synthesized film material includes, but is not limited to, SiN, SiC, SiCN, and composite film structures of SiN and SiC, etc. The thickness is 10-100 nm, and the deposition temperature is 200-450 °C.

[0035] Additionally, it's important to note that the time interval between the first bottom electrode film thinning (4) and the growth of the dielectric layer film (5) needs to be controlled, i.e., the Q-time needs to be monitored. The dielectric layer film provides better isolation between the electrode substrate (BE) and the external environment.

[0036] like Figure 1 As shown in (c), the third step involves a series of operations such as photolithography / etching of alignment marks. These operations do not require Q-time control. Figure 1 The etching pattern of the alignment mark in (c) is only an example.

[0037] like Figure 1As shown in (d), in the fourth step, the dielectric film 5 above the first bottom electrode film 4 is removed. To ensure sufficient removal, appropriate over-etching / over-polishing is performed, followed by a second thinning of the thickness of the first bottom electrode film 4, with a thinning amount accounting for 20% to 40% of the total thickness. The removal methods for the dielectric film 5 include, but are not limited to, chemical mechanical polishing, wet etching, dry etching, and combinations of these three methods. The removal method can be either time-controlled or endpoint-controlled. Optionally, wet etching of the dielectric film 5 can be used in conjunction with the growth of a relatively loose dielectric film using a low-power method, facilitating the wet etching process to peel off the dielectric film. This step effectively removes the dielectric film, and the resulting structure / performance matches the BSL, enhancing the adaptability and methodological versatility of this technical solution. The etching pattern has no practical impact on this step, therefore, the etching pattern is not shown.

[0038] like Figure 1 As shown in (e), in the fifth step, the bottom electrode film undergoes a second growth, forming a second bottom electrode film 6 on top of the first bottom electrode film 4.

[0039] It is important to note that the time interval between the end of the fourth step (etching / chemical mechanical polishing), the second BE thinning, and the fifth step (forming the second bottom electrode film) needs to be carefully controlled to prevent metal oxidation and copper diffusion. The second bottom electrode film is grown within Q time. The material of the second bottom electrode film includes, but is not limited to, materials that can block metallic copper, such as TaN and TiN. The materials of the first bottom electrode film 4 and the second bottom electrode film 6 can be arbitrarily stacked and combined, including, but not limited to, TaN and TiN, TaN and TaN, TiN and TaN, TiN and TiN, etc.

[0040] The present invention provides an MRAM fabrication method, which is a process integration scheme to reduce copper diffusion in magnetic random access memory. After the first bottom electrode film is thinned, a dielectric layer film with good light transmittance is grown for protection. After the photolithography / etching of the alignment mark is completed, the dielectric layer film is removed, and another bottom electrode film is grown. The dielectric layer film can prevent copper in the via from diffusing outward, greatly reducing the risk of copper diffusion and improving the device yield.

[0041] The underlying principle is as follows: the nitrogen-containing dielectric layer film has a relatively dense lattice, which can isolate the influence of water vapor / air from the external environment on the BE film / underlying copper. Furthermore, the dielectric layer film has strong hole-filling ability, preventing the underlying copper from diffusing along the BE grain boundaries / gaps / holes, and further filling the tiny gaps on the BE surface, thereby improving the yield of MRAM devices. In addition, due to its good light transmittance, the dielectric layer film does not affect the exposure of the AM (Alignment mark), fully meeting the requirements of current process technology.

[0042] Furthermore, based on the above embodiments, in order to meet the requirements of multiple etching operations, and considering the needs of the process integration scheme and the prevention of copper diffusion, the above operation can be repeated n times. The number of repetitions n depends on the process stability control capability and production capacity control. Each operation includes growing a dielectric layer film on the lower bottom electrode film, then performing photolithography / etching operations on alignment marks, then removing the dielectric layer film, and finally growing another bottom electrode film.

[0043] like Figure 2 As shown, the etching process was repeated three times. A dielectric film 5 was grown on the first bottom electrode film 4, and the first alignment mark photolithography / etching operation was performed. Then, the dielectric film 5 was removed. After the removal process reached the first bottom electrode film 4, the removal ended, and the second bottom electrode film 6 was grown. Next, a dielectric film 7 was grown on the second bottom electrode film 6, and the second alignment mark photolithography / etching step was performed. Then, the dielectric film 7 was completely removed, and the process stopped on the second bottom electrode film 6. Then, the third bottom electrode film 8 was grown. Next, a dielectric film 9 was grown on the third bottom electrode film 8, and the third alignment mark photolithography / etching step was performed. Then, the dielectric film 9 was removed, and finally, the fourth bottom electrode film 10 was grown.

[0044] After the above process, the formed bottom electrode can be patterned according to the alignment marks.

[0045] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0046] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for preparing MRAM, characterized in that, include: A substrate is provided, wherein through-holes are formed on the substrate; A first bottom electrode film is formed above the through hole; The first bottom electrode film is subjected to a first thinning process; A dielectric layer film is formed on top of the first bottom electrode film after the first thinning. The dielectric layer film is grown by atomic layer deposition (ALD) or chemical vapor deposition (CVD) at a deposition temperature of 200-450°C and a thickness of 10-100 nm. Perform photolithography and etching of alignment marks; Remove the dielectric layer film; The first bottom electrode film is subjected to a second thinning process; A second bottom electrode film is formed on top of the first bottom electrode film after the second thinning.

2. The method according to claim 1, characterized in that, The dielectric layer film is a single-layer film structure containing SiN, SiC, or SiCN.

3. The method according to claim 1, characterized in that, The dielectric layer film is a composite film structure of SiN and SiC.

4. The method according to claim 1, characterized in that, The time interval between the first thinning treatment of the first bottom electrode film and the formation of the dielectric layer film needs to be controlled.

5. The method according to claim 1, characterized in that, The methods for removing the dielectric layer film include one of chemical mechanical polishing, wet etching, and dry etching, or a combination of the three methods.

6. The method according to claim 1, characterized in that, The time interval between the second thinning process of the first bottom electrode film and the formation of the second bottom electrode film needs to be controlled.

7. The method according to claim 1, characterized in that, The material combination of the first bottom electrode film and the second bottom electrode film includes any one of the following: TaN / TiN, TaN / TaN, TiN / TaN, TiN / TiN.

8. The method according to claim 1, characterized in that, The method further includes: Alignment is performed according to the alignment marks, and the formed bottom electrode is patterned, the bottom electrode comprising a first bottom electrode film and a second bottom electrode film.

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