camera device

Abstract

This invention provides an imaging device with a global shutter function and improved efficiency in terms of semiconductor substrate area. The imaging device includes: a plurality of pixels, each having a plurality of photoelectric conversion units, and outputting a first voltage signal based on the charge of at least one of the plurality of photoelectric conversion units and a second voltage signal based on a combined charge of the charges of the plurality of photoelectric conversion units; and a plurality of holding circuits arranged in a one-to-one relationship with the plurality of pixels, the plurality of holding circuits holding the voltage signals based on the charges generated by the plurality of photoelectric conversion units, and each of the plurality of holding circuits including a plurality of holding portions, the plurality of holding portions including a first holding portion for holding the first voltage signal and a second holding portion for holding the second voltage signal.

Description

Technical Field

[0001] This invention relates to a camera device. Background Technology

[0002] In the field of CMOS solid-state camera devices, a global shutter function that allows all pixels to accumulate charge simultaneously is known as a function to eliminate distortion in the captured image caused when capturing images of moving objects.

[0003] Recent advances in CMOS solid-state imaging technology include back-illuminated technology, which receives light on a surface opposite to the surface where pixel circuitry is formed, and multilayer structure technology, which bonds semiconductor substrates together in a back-illuminated imaging device. In the structure described in Patent Document 1, a memory for maintaining the charge required for global shutter function is provided for each pixel on a substrate different from the substrate where the pixel circuitry is provided.

[0004] Furthermore, a camera device is widely used that enables the simultaneous acquisition of a focus detection signal and an image signal via a phase detection method for detecting defocus amount by receiving light through a split-pupil camera optical system. In the technology described in Patent Document 2, each pixel includes multiple photoelectric conversion units below a microlens to divide the pupil of the optical system, and outputs a signal from at least one photoelectric conversion unit and an image signal that is the sum of all signals from the multiple photoelectric conversion units.

[0005] Citation List

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2010-219339

[0008] Patent Document 2: Japanese Patent Application Publication No. 2013-211832 Summary of the Invention

[0009] The problem the invention aims to solve

[0010] However, in examples such as those described in Patent Document 1, in addition to the memory used to hold the charge of each pixel, the AD conversion circuit is placed on a second semiconductor substrate different from the first semiconductor substrate on which the photoelectric conversion unit is arranged. This increases the area of ​​the second semiconductor substrate and reduces the reduction effect on the unit cost of the chip. Furthermore, in the case where each pixel is provided with multiple photoelectric conversion units and can output focus detection signals and imaging signals via a phase detection method, not only is a memory required for the multiple photoelectric conversion units provided for each pixel, but also the AD conversion circuit. This further increases the area of ​​the second semiconductor substrate.

[0011] The present invention was made in view of the above-mentioned problems and realizes an imaging device with a global shutter function and improved efficiency in terms of semiconductor substrate area.

[0012] Solution for solving the problem

[0013] An imaging device according to the present invention includes: a plurality of pixels, each having a plurality of photoelectric conversion units, and outputting a first voltage signal based on the charge of at least one of the plurality of photoelectric conversion units and a second voltage signal based on a combined charge of the charges of the plurality of photoelectric conversion units; and a plurality of holding circuits configured in a one-to-one relationship with the plurality of pixels, the plurality of holding circuits holding the voltage signals based on the charges generated by the plurality of photoelectric conversion units, characterized in that each of the plurality of holding circuits includes a plurality of holding parts, the plurality of holding parts including a first holding part for holding the first voltage signal and a second holding part for holding the second voltage signal.

[0014] The effects of the invention

[0015] According to the present invention, an imaging device with a global shutter function and improved efficiency in terms of semiconductor substrate area can be provided.

[0016] Other features and advantages of the invention will become clear from the following description taken in conjunction with the accompanying drawings. Note that in the drawings, the same reference numerals denote the same or similar components. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0018] Figure 1 This is a diagram showing the arrangement of the light-receiving surface of the first substrate of the imaging device according to a first embodiment of the present invention.

[0019] Figure 2 This is a diagram showing the arrangement of the surfaces opposite to the light-receiving surface of the first substrate according to the first embodiment.

[0020] Figure 3 This is a diagram showing the configuration of the second substrate according to the first embodiment.

[0021] Figure 4 This is an equivalent circuit diagram showing the configuration of the pixel, pixel circuit, and accumulation circuit according to the first embodiment.

[0022] Figure 5 This is an equivalent circuit diagram showing the configuration of the AD conversion circuit according to the first embodiment.

[0023] Figure 6This is a timing diagram illustrating the driving method of the camera device according to the first embodiment.

[0024] Figure 7 This is a diagram illustrating the pixel configuration of a first variant according to the first embodiment.

[0025] Figure 8 This is a diagram showing the configuration of the second substrate according to a second variation of the first embodiment.

[0026] Figure 9 This is a diagram illustrating the configuration of the accumulation circuit according to the second embodiment.

[0027] Figure 10 This is a timing diagram illustrating the driving method of the camera device according to the second embodiment.

[0028] Figure 11 This is an equivalent circuit diagram showing the configuration of the accumulation circuit according to the third embodiment.

[0029] Figure 12 This is a diagram showing the configuration of the second substrate according to the third embodiment.

[0030] Figure 13 This is an equivalent circuit diagram showing the configuration of the pixel, pixel circuit, and accumulation circuit according to the fourth embodiment.

[0031] Figure 14 This is a diagram illustrating the pixel configuration according to the fifth embodiment.

[0032] Figure 15 This is an equivalent circuit diagram showing the configuration of the pixel, pixel circuit, and accumulation circuit according to the fifth embodiment. Detailed Implementation

[0033] In the following, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. Several features are described in the embodiments, but it is not a limitation requiring all such features, and multiple such features can be suitably combined. Furthermore, in the drawings, the same reference numerals are given to the same or similar configurations, and redundant descriptions thereof are omitted.

[0034] First Embodiment

[0035] Figure 1 This diagram illustrates the arrangement of the light-receiving surface of the first semiconductor substrate 101, which is provided with a photoelectric conversion unit (photodiode, hereinafter referred to as PD), in the imaging apparatus 100 according to the first embodiment of the present invention. The imaging apparatus 100 according to this embodiment has a multilayer structure in which a plurality of semiconductor substrates including the first semiconductor substrate 101 are stacked on top of each other.

[0036] like Figure 1 As shown in the attached figure, reference numeral 10 (pq) denotes the pixel located in the p-th row and q-th column. Figure 1 In this structure, a 6×8 pixel grid is arranged on the light-receiving surface, but in reality, there are tens of millions of pixels arranged in a two-dimensional pattern. Furthermore, since light is received through a segmented pupil area via a camera optical system (not shown), as shown in pixel 10 (00), all pixels 10 (pq) include two photodiodes PDA and PDB that are eccentrically positioned relative to a single microlens.

[0037] Figure 2 This diagram shows the arrangement of the surfaces opposite to the light-receiving surface of the first semiconductor substrate 101 in the imaging apparatus 100 according to this embodiment. On the non-light-receiving surface, pixel circuits 11 (pq) are arranged in a two-dimensional pattern corresponding to the pixels 10 (pq). Voltage signals, which are the outputs of the pixel circuits 11 (pq), are transmitted to another semiconductor substrate (hereinafter referred to as the second semiconductor substrate) 102 forming a multilayer structure (see [reference]) via the electrical contacts (hereinafter referred to as CONT) 18 of each pixel. Figure 3 ).

[0038] Furthermore, CONT 18 is connected to the vertical scanning circuit 20 of the second semiconductor substrate 102, and control signals from the vertical scanning circuit 20 are supplied to photodiodes PDA and PDB on the first semiconductor substrate 101 to achieve global shutter operation, etc. The driving timing of photodiodes PDA and PDB will be described below.

[0039] For example, an N-type silicon substrate is used as the first semiconductor substrate 101. To accumulate electrons in electron / hole pairs generated upon receiving light, photodiodes PDA and PDB are N-type semiconductor regions. Furthermore, photodiodes PDA and PDB are separated by a P-type semiconductor region disposed between them.

[0040] Figure 3 This diagram illustrates the configuration of the second semiconductor substrate 102 of the imaging device 100 according to this embodiment. Corresponding to the pixel circuits 11 (pq) of the first semiconductor substrate 101, the accumulation circuits 12 (pq) are arranged in a two-dimensional pattern. Since the pixel circuits 11 (pq) are connected by CONT 18 as contacts, the output voltage signal can be accumulated in batches by the accumulation circuits 12 (pq) (allowing all pixels to be accumulated in batches). In this way, a global shutter can be achieved.

[0041] The accumulated voltage signal is scanned column-wise by the vertical scanning circuit 20 for scanning the accumulation circuit 12 (pq), and output via the column output line VLq0 to the AD conversion circuit ADq0, which is configured with n signals per column (n is an integer). The AD conversion circuit ADq0 performs AD conversion on the input signal. The digital signal obtained through AD conversion is scanned column-wise by the horizontal scanning circuit 30, and output via the row output line HL to the output section 50.

[0042] The output unit 50 includes a known parallel / serial conversion circuit (hereinafter referred to as a P / S conversion circuit) and sequentially converts the digital camera signal output from the horizontal output line HL into a high-speed serial transmission format such as LVDS. Furthermore, the output unit 50 may include circuitry for performing correction processing on defective pixels, etc.

[0043] In the camera device 100 according to this embodiment, a column output line VLq0 is arranged in each column, and all rows in the same column are shared. Furthermore, an AD conversion circuit ADq0 is provided in each column. The pixel signal output from the column output line VLq0 and the time-varying reference signal RAMP are input to the AD conversion circuit ADq0.

[0044] Note that the configuration of the AD conversion circuit ADq0, the accumulation circuit 12 (pq), the pixel 10 (pq), and the pixel circuit 11 (pq) will be described below using an equivalent circuit diagram. Furthermore, the predetermined drive timing signal sent by the vertical scan circuit 20 to the accumulation circuit 12 (pq) in row-by-row order, the control signal for the AD conversion circuit ADq0, and the horizontal scan timing signal are generated by the timing generation circuit 40. The drive timing will be described below using a timing diagram.

[0045] Next, Figure 4 This is a diagram illustrating an example of the equivalent circuitry of the pixel 10 (pq), pixel circuit 11 (pq), and accumulation circuit 12 (pq) in the camera device 100 according to this embodiment.

[0046] First, pixel 10 (pq) includes photodiodes PDA and PDB. Furthermore, pixel circuit 11 (pq) includes: transfer transistors TXA and TXB, which transfer the charge generated at photodiodes PDA and PDB to a charge / voltage conversion section (floating diffusion section, hereinafter referred to as FD section); a first amplifying transistor (hereinafter referred to as SF1), which forms a source follower circuit via a current source (not shown) and includes a gate connected to the FD section; a reset transistor RES, used to reset the FD section via a predetermined power supply VDD; and a batch transfer transistor GS, which includes a drain connected to the source of SF1.

[0047] In the aforementioned transistors, the gates of the reset transistor RES, transfer transistors TXA and TXB, and batch transfer transistor GS can be controlled by the vertical scan circuit 20. Therefore, for all pixels, control is performed within a batch on the signal corresponding to the charge generated only at photodiode PDA, and on the signal corresponding to the sum of the charges generated at photodiodes PDA and PDB. Note that an overflow drain can be provided to drain unnecessary charges from photodiodes PDA and PDB.

[0048] The source of the batch transfer transistor GS is connected to the accumulation circuit 12 (pq) via CONT 18. The accumulation circuit 12 (pq) is provided with m accumulation capacitors (storage units) (m is an integer greater than or equal to 2) for accumulating the voltage signal of the pixel circuit 11 (pq). In this embodiment, three accumulation capacitors CN, CA and CAB are provided.

[0049] The accumulation capacitor CN accumulates the voltage at FD of pixel circuit 11 (pq) after the reset (hereinafter referred to as the N signal). Furthermore, the accumulation capacitor CA accumulates the voltage at FD that decreases in response to the signal charge of photodiode PDA (hereinafter referred to as the A signal). Additionally, the accumulation capacitor CAB accumulates the voltage at FD that decreases in response to the combined signal charge of photodiodes PDA and PDB (hereinafter referred to as the imaging signal).

[0050] Capacitive elements with increased surface area using trench structures can be utilized in the accumulator capacitor. Furthermore, high-capacitance elements formed between the wiring layers of the second semiconductor substrate 102 using a high-dielectric-constant material can be utilized. Additionally, the transistor gate oxide film of the second semiconductor substrate 102 can be partially utilized. By increasing the accumulator capacitance in this way, thermal noise can be reduced, thereby improving image quality.

[0051] In addition, the accumulation circuit 12 (pq) is provided with memory write transistors MWN, MWA and MWAB for writing voltage signals into the three accumulation capacitors mentioned above.

[0052] Furthermore, the aforementioned accumulation capacitors CN, CA, and CAB are connected to the gates of the second amplifying transistors SF2N, SF2A, and SF2AB, and a source follower circuit is formed using a current source (not shown). Selecting transistors SELN, SELA, and SELAB are provided to selectively transfer the source voltage of the second amplifying transistors to the column output line VLq0. The driving method and sequence for outputting the N-signal, A-signal, and camera signal via these selecting transistors are described below using timing diagrams; however, these selecting transistors are naturally also used for the aforementioned row-direction scanning.

[0053] Next, Figure 5 This is a diagram illustrating an example of the equivalent circuit of the AD conversion circuit ADq0 according to this embodiment.

[0054] The AD conversion circuit ADq0 includes a comparator COMPq0 and a counter COUNTERq0. Comparator COMPq0 takes the pixel signal VLq from the column output line VLq0 and the reference signal RAMP as inputs. Counter COUNTERq0 is stopped and controlled by the output polarity of comparator COMPq0. Comparator COMPq0 compares the voltages of the pixel signal VLq and the reference signal RAMP. When the value of the pixel signal VLq is higher, the output polarity is Hi; when the value of the pixel signal VLq is lower, the output polarity is Lo. When a reset signal (not shown) is released, counter COUNTERq0 continues counting when the output polarity of comparator COMPq0 is Hi and stops when the output polarity is Lo.

[0055] In this way, for example, the counter can be stopped when the voltage of the pixel signal VLq, which decreases in response to the signal charge of the photodiode PDA, is less than the reference signal RAMP, which decreases proportionally with time. This makes it possible to perform A / D conversion on the voltage of the pixel signal VLq. Specifically, since the image signal has a wider voltage range than the A signal, and the A signal has a wider voltage range than the N signal, it is more time-efficient to sequentially perform A / D conversion of various types of signals with different voltage ranges at a single A / D conversion circuit, even if the A / D conversion circuits can be connected in parallel.

[0056] Next, the driving method of the camera device according to this embodiment will be described. Figure 6 This is a timing diagram illustrating the driving method of the camera device according to this embodiment. Figure 6 In the figure, PRES, PTXA, PTXB, PGS, PMWN, PMWA, PMWAB, PSERN, PSELA, and PSELAB represent control signals associated with the gates of RES, TXA, TXB, GS, MWN, MWA, MWAB, SELN, SELA, and SELAB, respectively. Hi indicates the transistor is ON, and Lo indicates the transistor is OFF. Furthermore, RAMP indicates the voltage of the reference signal RAMP supplied to the AD conversion circuit ADq0, COMP indicates the output polarity of comparator COMPq0, and COUNTER indicates the counter value of counter COUNTERq0.

[0057] exist Figure 6In this context, times t600 to t611 represent a so-called global shutter operation, in which voltage signals corresponding to the batch accumulation of charge for all pixels are transmitted in batches to the second semiconductor substrate 102. Furthermore, times t612 to t623 represent the sequential AD conversion operation of the signals from the accumulation circuits 12 (0q) arranged in the 0th row of the second semiconductor substrate 102. Driven from time t612 to time t623 via the vertical scan circuit 20, from the accumulation circuits 12 (0q) arranged in the 0th row, the accumulation circuits 12 (1q) arranged in the 1st row, ..., to the last 5th row, signals from all pixels are output.

[0058] First, from time t600 to time t601, the control signal PRES changes to Hi, and FD is reset to power supply VDD.

[0059] Subsequently, at time t602, the control signal PGS becomes Lo, and at time t603, the control signal PMWN becomes Lo. Thus, the FD reset is released, and the static voltage (i.e., the N signal) is written to the accumulation capacitor CN of the accumulation circuit 12 (pq). When the control signal PMWN becomes Lo after the control signal PGS, the N signal, as a voltage signal, is written to the accumulation capacitor CN, so from time t600, the control signals PGS and PMWA can be Hi.

[0060] Subsequently, from time t604 to time t605, the control signal PTXA changes to Hi, and the signal charge of the photodiode PDA is transferred to FD.

[0061] Subsequently, at time t606, the control signal PGS becomes Lo, and at time t607, the control signal PMWA becomes Lo. Therefore, in response to the signal charge from the photodiode PDA, the reset-released FD is reduced and becomes static. Then, the static voltage (i.e., the A signal) is written to the accumulation capacitor CA of the accumulation circuit 12 (pq). Like the N signal, the control signals PGS and PMWA can be Hi from time t604.

[0062] Subsequently, from time t608 to time t609, control signals PTXA and PTXB change to Hi, and the signal charges of photodiodes PDA and PDB are transferred to FD.

[0063] Subsequently, at time t610, the control signal PGS becomes Lo, and at time t611, the control signal PMWAB becomes Lo. Therefore, in response to the signal charges from photodiodes PDA and PDB, the reset-released FD is reduced and becomes static. Then, the static voltage (i.e., the camera signal) is written to the accumulation capacitor CAB of the accumulation circuit 12 (pq). Like the N signal, the control signals PGS and PMWAB can be Hi from time t608.

[0064] Up to this point, except for the period from time t600 to time t601, FD has not been reset. Through this configuration and driving method of pixel circuit 11 (pq), and the associated double sampling of the camera signal and the N signal described below, noise added to the camera signal can be reduced.

[0065] During the Hi period when the vertical scanning circuit 20 sequentially converts the control signals PSELN, PSELAB, and PSELA to Hi, the voltage signals written to the accumulation capacitors CN, CA, and CAB are subjected to AD conversion through the processing described below.

[0066] In other words, from time t612 to time t615, the control signal PSELN changes to Hi, and the comparator COMPq0 compares the N signal appearing at the column output line VLq0 with the reference signal RAMP, which has been decreasing since time t613. At any time before time t615 (in... Figure 6 (Take time t614). When this size relationship is reversed, the polarity of comparator COMPq0 becomes Lo, and in response, the count value of counter COUNTERq0 stops.

[0067] Here, along with the start of the decrease in the reference signal RAMP at time t613, COUNTERq0 begins counting, and from time t615 to time t616, the count value of the N signal is stored in a latch circuit (not shown). In some cases, down-counting can be used for the N signal. In this case, when performing AD conversion of the captured signal from time t616 to time t619, correlated double sampling can be easily performed by up-counting.

[0068] At time t615, the reference signal RAMP is reset to the same voltage as before time t613.

[0069] From time t616 to time t619, the control signal PSELAB is changed to Hi, and an AD conversion is performed on the camera signal (A+B signal) through an operation similar to that from time t612 to time t615. Furthermore, from time t620 to time t623, the control signal PSELA is changed to Hi, and an AD conversion is performed on the A signal through an operation similar to that from time t612 to time t615.

[0070] After time t623, the AD conversion results of the latched N signal, the AD conversion results of the camera signal, and the AD conversion results of the A signal are sequentially scanned in the column direction by the horizontal scanning circuit 30 and transmitted to the image processor (not shown) via the row output line HL and the output unit 50. Correlated double sampling of the camera signal and N signal, and the A signal and N signal, is performed by subtraction processing at the output unit 50. Furthermore, as described above, down-counting can be used for the N signal.

[0071] Here, the AD conversion period of the image signal has a longer duration than that of the N signal, but has the same reference signal RAMP tilt as the N signal. Similarly, the AD conversion period of the A signal has a shorter duration than that of the image signal, but a longer duration than that of the N signal. Since the A signal corresponds to the signal charge generated when a portion of the light passing through the pupil of the imaging optics is received, its voltage range is smaller than the voltage range of the image signal obtained when the entire pupil of the imaging optics is received; therefore, a short AD conversion period is sufficient. Essentially, the N signal, excluding the received light signal, has an even smaller voltage range than the A signal; therefore, a shorter AD conversion period than that of the A signal is naturally sufficient.

[0072] As described above, by sequentially performing AD conversion on the N signal, the camera signal, and the A signal, such as... Figure 3 As shown, one AD conversion circuit can be shared in each column in the time direction. Therefore, in this embodiment, by providing only one AD conversion circuit in each column, the increase in the area of ​​the second semiconductor substrate can be suppressed. The improvement in time efficiency due to sequential AD conversion will be described in a second variation of this embodiment.

[0073] Note that in the image processor (not shown), the B signal is generated based on the difference between the captured signal and the A signal, and the defocusing amount of the camera optical system is calculated via a known correlation calculation between the A and B signals. In this correlation calculation, it is not necessary to have signals from all rows, and a portion of the A signal can be removed in the row direction. In this case, the A / D conversion period of the A signal from time t619 to time t623 is shortened, and the A / D conversion of the N signal in the next row is performed earlier. Therefore, the frame rate can be increased.

[0074] If frame rate is not critical, from time t619 to time t623, the power supply to the AD conversion circuit ADq0 and the current source to the column output line VLq0 are stopped, thereby reducing power consumption. Furthermore, as a result of performing AD conversion after processing the next row and subsequent rows sequentially in advance, stopping the power supply can reduce power consumption after the last row. Compared to performing AD conversion on all rows of A signals, the frame rate can be increased and power consumption reduced.

[0075] Furthermore, considering that AD conversion is performed while omitting a portion of the A signal in the row direction, AD conversion of the camera signal can begin quickly after AD conversion of the N signal. In this way, the correlation double sampling time interval shared by the N signal and the camera signal using the AD conversion circuit can be reduced. Additionally, the correlation double sampling time interval of the rows where AD conversion is performed while omitting a portion of the A signal in the row direction can be aligned, thereby reducing the noise difference between rows in the camera signal. Furthermore, after repeating AD conversion of the N signal and camera signal from time t612 to time t619 until the last row, and after outputting the N signal and camera signal from all accumulation circuits 12(pq), AD conversion of the A signal for each row required by the A signal can be performed from time t619 to time t623.

[0076] Furthermore, by utilizing the ability to simultaneously accumulate all pixels including the A signal using a global shutter, the imaging device according to this embodiment can make the segmentation direction of the photodiodes PDA and PDB different from that of the PDA. Figure 1 The segmentation direction of pixel 10 (pq) shown. Figure 7 This diagram illustrates pixel 14 (pq) of the imaging device according to a first variation of this embodiment. The segmented photodiodes PDA and PDB are segmented in the row direction of the imaging device, unlike the case of pixel 10 (pq).

[0077] Even in a configuration where all pixels of the imaging device are similar to pixel 14(pq), the A signal of 14(pq) required for the correlation calculation of the q-th column is matched with the imaging signal as synchronization information independent of p. Therefore, vertical correlation calculation can be stably performed even when the subject moves. Furthermore, both pixel 10(pq) and pixel 14(pq) can be arranged. By utilizing both the horizontal correlation calculation using pixel 10(pq) and the vertical correlation calculation using pixel 14(pq), the amount of defocus can be calculated independently of the orientation of the spatial frequency components of the subject.

[0078] In addition, to increase the frame rate, the AD conversions in the row direction from the accumulator circuit 12 (pq) can be connected in parallel. Figure 8 This is a diagram illustrating the configuration of a second semiconductor substrate according to a second variation of this embodiment. This configuration is similar to... Figure 3 The configuration differs in that each column has three column output lines VLq0, VLq1, and VLq2, and each column also has three AD conversion circuits ADq0, ADq1, and ADq2, which are connected in parallel. Furthermore, these components are connected such that column output line VLq0 and AD conversion circuit ADq0 perform AD conversion of the voltage signals from the accumulation circuit 12 (pq) in rows 0 and 3; column output line VLq1 and AD conversion circuit ADq1 perform AD conversion of the voltage signals from the accumulation circuit 12 (pq) in rows 1 and 4; and column output line VLq2 and AD conversion circuit ADq2 perform AD conversion of the voltage signals from the accumulation circuit 12 (pq) in rows 2 and 5.

[0079] In this configuration, the number of A / D conversion circuits and current sources for the column output lines increases, resulting in a larger second semiconductor substrate. However, compared to a configuration where, for example, three column output lines and A / D conversion circuits are connected to all rows and A / D conversions of the N-signal, camera signal, and A-signal are performed in parallel, time efficiency is improved. This is because it is not limited to camera signals with the largest voltage range (i.e., not limited to camera signals with the longest duration of the reference signal RAMP generation period), but rather, A / D conversions of other signals can be performed sequentially while A / D conversion of one of these signals is complete. Furthermore, two other sets of column output lines and A / D conversion circuits can be used in parallel for the transmission and A / D conversion of voltage signals from different rows.

[0080] This further arises from, for example Figure 4 The equivalent circuit shown in the diagram is configured to sequentially perform AD conversion on the voltage signals via a shared column output line when an accumulation circuit 12 (pq) that obtains multiple voltage signals from a pixel is provided. In other words, according to this embodiment, the operating efficiency during the AD conversion period can be improved, and the area efficiency of the second semiconductor substrate can be improved.

[0081] Second Embodiment

[0082] To realize the technical concept of this invention, it is sufficient for the signals from multiple accumulation capacitors in each pixel to share the column output line and the AD conversion circuit. Therefore, other configurations can also be considered.

[0083] In the second embodiment, the second amplifying transistor SF2 of the accumulation circuit 12 (pq) is shared by the signals of multiple accumulation capacitors. Figure 9 This is a diagram illustrating the configuration of the accumulation circuit 12(pq) of the camera device according to this embodiment. This configuration is related to... Figure 5 The difference in the configuration of the accumulation circuit 12(pq) of the camera device according to the first embodiment is that the accumulation capacitors CN, CA and CAB can be input to the gate of a single second amplification transistor SF2 via memory transfer transistors MTN, MTA and MTAB.

[0084] Furthermore, a single selection transistor SEL is arranged for the column output line VLq0. Additionally, there are no dedicated second amplification transistors for each of the accumulators CN, CA, and CAB, and the source follower circuit cannot be configured independently. Therefore, whenever the signal voltage from these accumulators is sequentially transmitted to the AD conversion circuit via the column output line VLq0, the gate of the amplification transistor SF2 needs to be reset, and a second reset transistor RES2 is provided.

[0085] Next, the driving method of the camera device according to this embodiment will be described. Figure 10 This is a timing diagram of the driving method of the camera device according to this embodiment. Due to... Figure 6 The difference in the first embodiment shown is the accumulation circuit 12 (pq), which is used to simultaneously accumulate all pixels during the global shutter's duration (in Figure 6 The interval (from time t600 to time t611) is the same as in the first embodiment and will not be described further. Additionally, the prefix "P" is added... Figure 9 The equivalent circuit diagram shows the names of each transistor, and the gate control signal is indicated as Hi or Lo. When the control signal is Hi, the transistor is ON, and when the control signal is Lo, the transistor is OFF.

[0086] Starting from time t1011, in order to start reading line 0, the control signal PSEL changes to Hi, and the selection transistor SEL of the accumulator circuit 12 (pq) turns ON.

[0087] First, from time t1011 to time t1012, the control signal PRES2 changes to Hi, and the gate of the amplifying transistor SF2 is reset to the power supply voltage VDD.

[0088] Subsequently, at time t1012, an AD conversion is performed on the N signal until the control signal PMTN changes to Hi and the time is t1015. This AD conversion is related to... Figure 6 The AD conversion performed up to time t615 is similar.

[0089] Subsequently, from time t1015 to time t1016, the control signal PRES2 changes to Hi again, and the gate of the amplifying transistor SF2 is reset to the power supply voltage VDD.

[0090] Subsequently, at time t1016, the camera signal (A+B signal) undergoes an AD conversion until the control signal PMTAB changes to Hi and the time is t1019. This AD conversion is related to... Figure 6 The AD conversion performed up to time t619 is similar.

[0091] Subsequently, from time t1019 to time t1020, the control signal PRES2 changes to Hi again, and the gate of the amplifying transistor SF2 is reset to the power supply voltage VDD.

[0092] Subsequently, at time t1020, signal A undergoes an AD conversion until the control signal PMTAB changes to Hi and the time is t1023. This AD conversion is related to... Figure 6 The AD conversion performed up to time t623 is similar.

[0093] Note that this embodiment can also achieve similar effects through variations similar to the first embodiment.

[0094] Third Embodiment

[0095] Using the technical concept of this invention, it is possible to avoid transmitting all the voltage signals of the multiple accumulated capacitors in each pixel to the AD conversion circuit via a shared column output line. Using the configuration according to this embodiment described below, a portion of the multiple accumulated capacitors in each pixel are transmitted to the AD conversion circuit via the shared column output line for AD conversion.

[0096] Figure 11 This is a diagram showing the configuration of the accumulation circuit 12(pq) of the camera device according to this embodiment. Furthermore, Figure 12 This is a diagram showing the configuration of the second semiconductor substrate of the camera device according to this embodiment.

[0097] This configuration and Figure 3 and Figure 5The difference in the configuration shown is that only the A signal and the camera signal (A+B signal) accumulated at the accumulation capacitors CA and CAB are sequentially converted to AD via the shared column output line, and the N signal accumulated at the accumulation capacitor CN is converted to AD in parallel with the camera signal and the A signal via an independent column output line.

[0098] Furthermore, similar effects can be achieved when the N signal and the camera signal are sequentially converted to AD via a shared column output line and the A signal is converted to AD independently, or when the N signal and the A signal are sequentially converted to AD via a shared column output line and the camera signal is converted to AD independently.

[0099] Fourth embodiment

[0100] The technical concept of the present invention can also be applied to situations where the photoelectric conversion unit of a pixel, such as pixel 10 (pq) and pixel 14 (pq), does not necessarily need to be segmented.

[0101] According to this embodiment, pixel 15 (pq) includes a non-segmented photoelectric conversion unit, and accumulation circuit 12 (pq) includes a plurality of accumulation capacitors. Figure 13 This is an equivalent circuit diagram showing the configuration of the pixel 15 (pq), pixel circuit 11 (pq), and accumulation circuit 12 (pq) of the camera device according to this embodiment.

[0102] This configuration and Figure 4 The difference in the configuration shown is that the photoelectric conversion section of pixel 15 (pq) is not divided as in pixels 10 (pq) and 14 (pq), and the accumulation circuit 12 (pq) includes two capacitors CN and CS for accumulating the voltage of the N signal and the camera signal.

[0103] exist Figure 4 In the original text, the transistor for writing the voltage of the image signal (A+B signal), the accumulation capacitor for accumulation, the transistor for amplification, and the transistor for selection are represented by MWAB, CAB, SF2AB, and SELAB, respectively. Conversely, in this embodiment, the transistor for writing the voltage of the image signal, the accumulation capacitor for accumulation, the transistor for amplification, and the transistor for selection are represented by MWS, CS, SF2S, and SELS, respectively.

[0104] Therefore, in Figure 6 Although it is necessary to re-mark the control signal PMWAB as PMWS and the control signal PSELAB as PSELS, the camera device according to this embodiment can be driven in a similar manner from time t600 to time t603 and from time t608 to time t619.

[0105] In this way, by sequentially performing AD conversion on the N signal and the camera signal, which are accumulated at two accumulation capacitors in each pixel and have very different voltage ranges, an effect similar to that of the first embodiment can be obtained.

[0106] Fifth embodiment

[0107] The technical concept of the present invention can be applied to the case of pixels that include photoelectric conversion units that are divided multiple times (more than twice), and is not only applicable to pixels such as pixel 10 (pq) and pixel 14 (pq) that include photoelectric conversion units that are divided into two parts.

[0108] According to this embodiment, pixel 16 (pq) includes a photoelectric conversion unit divided into four parts, and accumulation circuit 12 (pq) includes three accumulation capacitors. Figure 14 This diagram illustrates the configuration of pixels 16 (pq) of the imaging device according to this embodiment. Furthermore, Figure 15 This is an equivalent circuit diagram showing the configuration of the pixel 16 (pq), pixel circuit 11 (pq), and accumulation circuit 12 (pq) of the imaging device according to this embodiment.

[0109] exist Figure 14 In this system, the photoelectric conversion units of the pixels are divided into a cross shape. By outputting an A signal corresponding to the signal charges of the photodiodes PDA and PDB, and an imaging signal corresponding to the signal charges of all photoelectric conversion units, vertical correlation calculations can be performed and a captured image can be generated. Furthermore, by outputting the imaging signal and the A signal corresponding to the signal charges of the photodiodes PDA and PDC, horizontal correlation calculations can be performed and a captured image can be generated.

[0110] Furthermore, the signal charge accumulation duration of photodiodes PDA and PDD can be set to be longer, while the signal charge accumulation duration of photodiodes PDB and PDC can be set to be shorter. Therefore, by outputting a long-duration signal corresponding to the signal charge of the former and a short-duration signal corresponding to the signal charge of the latter, image synthesis can be performed at an image processor (not shown), and an image signal with expanded dynamic range can be generated.

[0111] In any case, the accumulation circuit 12 (pq) may include three accumulation capacitors having accumulation capacitors for the N signal, as in the foregoing embodiments. Figure 15 Configuration and Figure 4 The difference in the configuration is that pixel 16 (pq) includes four photodiodes PDA, PDB, PDC and PDD, and is provided with transfer transistors TXA, TXB, TXC and TXD for transferring signal charge to FD.

[0112] Next, we will refer to the first embodiment. Figure 6 Describe the driving method of the camera device. First, when performing AD conversion sequentially on the horizontal correlation calculation and the signals to be used in the camera, in conjunction with... Figure 6 The control signal PTXC is controlled at the same timing as the control signal PTXA, and the control signal PTXD is controlled at the same timing as the control signal PTXB.

[0113] In order to sequentially perform AD conversion on the signals used in vertical correlation calculations and imaging, control signals PTXA and PTXB are controlled at the same timing, and control signals PTXC and PTXD are controlled at the same timing.

[0114] Furthermore, when sequentially performing AD conversion on short-duration accumulated signals (the voltage of the A signal corresponding to the signal charges of photodiodes PDA and PDD) and long-duration accumulated signals (the voltage of the imaging signal corresponding to the signal charges of photodiodes PDB and PDC), from Figure 6 From time t604 to time t605, the control signal PTXD is controlled at the same timing as the control signal PTXA. Furthermore, from... Figure 6 During the time interval from t608 to t609, control signals PTXC and PTXB are controlled at the same timing. From time t608 to t609, control signal PTXA changes to Lo, and the interval from time t606 to t608 can be extended.

[0115] In any case, by sequentially performing AD conversion on the N signal, the camera signal (A+B signal), and the A signal, which are accumulated at three accumulation capacitors in each pixel and have very different voltage ranges, an effect similar to that of the first embodiment can be obtained.

[0116] Other embodiments

[0117] This invention can be implemented by providing a program for implementing one or more functions of the above embodiments to a system or device via a network or storage medium, and by having the program read and executed by one or more processors of the computer of the system or device. Alternatively, this invention can be implemented by a circuit (e.g., an ASIC) for implementing one or more functions.

[0118] This invention is not limited to the embodiments described above, and various changes and modifications can be made within the spirit and scope of this invention. Therefore, the appended claims have been made to inform the public of the scope of this invention.

[0119] This application claims priority to Japanese Patent Application 2021-022046, filed on February 15, 2021, which is incorporated herein by reference.

Claims

1. A camera device, comprising: Multiple pixels, each having multiple photoelectric conversion units, output a first voltage signal based on the charge of at least one of the multiple photoelectric conversion units and a second voltage signal based on the combined charge of the charges of the multiple photoelectric conversion units; as well as Multiple holding circuits are configured in a one-to-one relationship with the multiple pixels, and the multiple holding circuits hold voltage signals based on the charges generated by the multiple photoelectric conversion units. Each of the plurality of holding circuits includes a plurality of holding sections, an amplifying transistor, and a plurality of transmitting transistors. The plurality of holding sections include a first holding section for holding the first voltage signal and a second holding section for holding the second voltage signal. The plurality of transmitting transistors include a first transmitting transistor disposed between the first holding section and the amplifying transistor, and a second transmitting transistor disposed between the second holding section and the amplifying transistor. The number of amplifying transistors included in each of the plurality of holding circuits is less than the number of the plurality of holding portions included in each of the plurality of holding circuits, and the plurality of transmitting transistors sequentially transmit the voltage signals of the plurality of holding portions to the amplifying transistors.

2. The camera device according to claim 1, wherein, Each of the plurality of holding circuits further includes a third holding section for holding a third voltage signal obtained after the reset operation of each of the plurality of pixels has been released.

3. The camera device according to claim 2, wherein, Each of the plurality of holding circuits includes three holding portions, namely the first holding portion, the second holding portion, and the third holding portion.

4. The camera device according to claim 2, wherein, The first voltage signal, the second voltage signal, and the third voltage signal have different voltage ranges.

5. The camera device according to claim 1, wherein, Each of the plurality of holding circuits outputs the second voltage signal before the first voltage signal.

6. The camera device according to claim 1, wherein, Each of the plurality of pixels includes a microlens, and the plurality of photoelectric conversion parts divide the pupil area of ​​the imaging optical system and receive light.

7. The camera device according to claim 1, wherein, The camera device includes a plurality of semiconductor substrates stacked on top of each other, the plurality of pixels being arranged on a first semiconductor substrate among the plurality of semiconductor substrates, and the plurality of holding circuits being arranged on a second semiconductor substrate among the plurality of semiconductor substrates.

8. The camera device according to claim 1, wherein, The number of holding parts in each of the plurality of holding circuits is greater than the number of photoelectric conversion parts in each of the plurality of pixels.

9. The camera device according to claim 1, further comprising: An AD conversion circuit is arranged in each column of the plurality of pixels in a number smaller than the number of the plurality of holding portions provided in each of the plurality of holding circuits. The AD conversion circuit is used to sequentially perform AD conversion on the voltage signals of the plurality of holding portions.

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