Common mode current detection circuit

Abstract

The application discloses a common-mode current detection circuit, comprising: a sampling unit comprising a detection unit, an operational amplifier and a switch tube, a first input end and a second input end of the operational amplifier being connected with a first end and a second end of the detection unit, an output end of the operational amplifier being connected with a control end of the switch tube, a first end of the switch tube being connected with the second end of the detection unit; a first output unit being connected with a second end of the switch tube to generate a first output signal; a current injection unit being connected with the first end of the switch tube to generate a compensation current; and a second output unit being connected with the current injection unit to generate a second output signal. According to the common-mode current detection circuit, the interference brought by a power supply voltage or a ground voltage through other circuits is eliminated through a differential structure, and the step response of the circuit is optimized; the injection of adjustable compensation current is realized through the current injection unit, and the output common-mode is adjustable and the offset calibration is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a common-mode current detection circuit. Background Technology

[0002] Current detection circuits are mainly used for fault monitoring and overcurrent protection in circuits. The basic principle is to use a detection resistor in series with the current path to be detected, and then collect and amplify the voltage drop across the detection resistor to output a voltage signal that is proportional to the magnitude of the current to be measured. The resistance of the detection resistor is very small, so its power consumption and impedance can be ignored.

[0003] like Figure 1 As shown, a traditional current detection circuit includes operational amplifier A1, proportional resistors R1 and R2, MOSFET M0, and buffer A2. The operational amplifier A1 clamps the current sensing resistor R... SNS The voltage is transferred to both ends of the proportional resistor R1, and then amplified by a factor of R2 / R1. Buffer A2 provides driving capability for the subsequent stage. This structure is relatively simple but has some problems. On the one hand, its power supply rejection performance to ground is poor, and the jitter caused by crosstalk on the ground line will be directly transmitted to the output voltage. On the other hand, the output voltage is only determined by the input, lacking voltage regulation means, and the overall imbalance in the circuit will affect the detection accuracy. In addition, the circuit also has the problem of slow input step response.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a common-mode current detection circuit that can eliminate interference from ground voltage or power supply voltage, make the common-mode voltage controllable, and improve the step response in the circuit.

[0006] To achieve the above objectives, embodiments of the present invention provide a common-mode current detection circuit, comprising:

[0007] A sampling unit is used to sample the current to be measured to obtain a sampled current. The sampling unit includes a detection unit, an operational amplifier, and a switching transistor. The first input terminal of the operational amplifier is connected to the first terminal of the detection unit, the second input terminal of the operational amplifier is connected to the second terminal of the detection unit, the output terminal of the operational amplifier is connected to the control terminal of the switching transistor, and the first terminal of the switching transistor is connected to the second terminal of the detection unit.

[0008] The first output unit is connected to the second terminal of the switching transistor and is used to generate a first output signal based on the sampled current.

[0009] A current injection unit, connected to the first terminal of the switching transistor, is used to generate a compensation current; and

[0010] The second output unit, connected to the current injection unit, is used to generate a second output signal based on the compensation current.

[0011] In one or more embodiments of the present invention, the current injection unit includes a first current injection unit and a second current injection unit, wherein the first current injection unit is connected to a first terminal of the switching transistor to output a first compensation current, and the second current injection unit is connected to a second output unit to output a second compensation current.

[0012] In one or more embodiments of the present invention, the first current injection unit includes one or more first current branches, wherein multiple first current branches are connected in parallel, and each first current branch includes a first current source and a first control switch connected in series; and / or

[0013] The second current injection unit includes one or more second current branches, and the multiple second current branches are connected in parallel. Each second current branch includes a second current source and a second control switch connected in series.

[0014] In one or more embodiments of the present invention, the current injection unit includes a common-mode feedback control unit and a current generation unit. The common-mode feedback control unit is used to generate a control signal based on a first output signal and a second output signal. The current generation unit generates a compensation current based on the control signal. The current generation unit is connected to the second terminal of the switching transistor and the second output unit.

[0015] In one or more embodiments of the present invention, the common-mode feedback control unit includes a first MOSFET, a second MOSFET, a first bias current source, a second bias current source, a first bias resistor, a second bias resistor, and a comparator;

[0016] The control terminal of the first MOSFET is connected to the first output signal, and the control terminal of the second MOSFET is connected to the second output signal. The second terminal of the first MOSFET is connected to the first terminal of the first bias current source, and the second terminal of the second MOSFET is connected to the first terminal of the second bias current source. The second terminals of the first and second bias current sources are connected to ground voltage. The first terminal of the first MOSFET is connected to the first terminal of the first bias resistor, and the first terminal of the second MOSFET is connected to the first terminal of the second bias resistor. The second terminals of the first and second bias resistors are connected to the first input terminal of the comparator. The second input terminal of the comparator is connected to the reference voltage, and the output terminal of the comparator is connected to the current generation unit.

[0017] In one or more embodiments of the present invention, the current generating unit includes a third MOSFET and a fourth MOSFET. The first terminal of the third MOSFET is connected to the power supply voltage, the second terminal of the third MOSFET is connected to the first terminal of the switching transistor, the first terminal of the fourth MOSFET is connected to the power supply voltage, the second terminal of the fourth MOSFET is connected to the second output unit, and the control terminals of the third MOSFET and the fourth MOSFET are connected to the common-mode feedback control unit.

[0018] In one or more embodiments of the present invention, the current generating unit further includes a fifth MOS transistor, the first end of the fifth MOS transistor is connected to the second end of the fourth MOS transistor, the second end of the fifth MOS transistor is connected to the second output unit, and the control terminal of the fifth MOS transistor is connected to the control terminal of the switching transistor.

[0019] In one or more embodiments of the present invention, the first output unit includes a first resistor unit and one or more first amplification units. The first end of the first resistor unit is connected to the second end of the switching transistor and the input end of the first amplification unit. The first amplification unit is used to output a first output signal that is proportional to the voltage on the first end of the first resistor unit. The multiple first amplification units are connected in series.

[0020] In one or more embodiments of the present invention, the second output unit includes a second resistor unit and one or more stages of a second amplification unit. The first end of the first resistor unit is connected to the second end of the switching transistor and the input end of the second amplification unit. The second amplification unit is used to output a second output signal that is proportional to the voltage on the first end of the second resistor unit. The multiple stages of the second amplification unit are connected in series.

[0021] In one or more embodiments of the present invention, the first amplification unit is a buffer or a proportional amplifier.

[0022] In one or more embodiments of the present invention, the second amplification unit is a buffer or a proportional amplifier.

[0023] In one or more embodiments of the present invention, the sampling unit further includes a first resistor, a first end of which is connected to a first input terminal of an operational amplifier, and a second end of which is connected to a first terminal of a detection unit.

[0024] Compared with the prior art, the common-mode current detection circuit according to the embodiments of the present invention forms a differential structure by using a first output unit and a second output unit in conjunction with a current injection unit. This eliminates interference from other circuits caused by power supply voltage or ground voltage, improves detection accuracy, and optimizes the step response of the circuit. By injecting adjustable compensation current through the current injection unit, the output common-mode can be adjusted and offset calibration can be achieved, which is beneficial for subsequent circuits to process the signal. The addition of a differential calibration mechanism achieves better performance at a relatively low cost. Attached Figure Description

[0025] Figure 1 This is a circuit diagram of a common-mode current detection circuit in existing technology.

[0026] Figure 2 This is a circuit diagram of a common-mode current detection circuit according to Embodiment 1 of the present invention.

[0027] Figure 3 This is a circuit diagram of a common-mode current detection circuit according to Embodiment 2 of the present invention.

[0028] Figure 4 This is a circuit diagram of a common-mode current detection circuit according to Embodiment 3 of the present invention. Detailed Implementation

[0029] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0030] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0031] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0033] Example 1

[0034] like Figure 2As shown, a common-mode current detection circuit includes: a sampling unit 10, a first output unit 20, a current injection unit, and a second output unit 40.

[0035] The sampling unit 10 is used to sample the current to be measured to obtain a sampled current. The sampling unit 10 includes a detection unit, an operational amplifier A, a first resistor R1, and a switching transistor M0. The detection unit includes a detection resistor R... SNS .

[0036] The first end of the first resistor R1 is connected to the first input terminal of the operational amplifier A, the second end of the first resistor R1 is connected to the first terminal of the detection unit, the second input terminal of the operational amplifier A is connected to the second terminal of the detection unit, the output terminal of the operational amplifier A is connected to the control terminal of the switching transistor M0, the first end of the switching transistor M0 is connected to the second terminal of the detection unit, and the second end of the switching transistor M0 is connected to the first output unit 20.

[0037] In one embodiment, the first terminal of the detection unit is the detection resistor R. SNS The first terminal of the detection unit is the second terminal of the detection resistor; the first input terminal of operational amplifier A is the negative input terminal, and the second input terminal of operational amplifier A is the positive input terminal; the switching transistor M0 is a P-channel MOS transistor, that is, the first terminal of switching transistor M0 is the source, the second terminal of switching transistor M0 is the drain, and the control terminal of switching transistor M0 is the gate. In other embodiments, the detection unit may be composed of multiple resistors connected in series and / or in parallel; the first input terminal of operational amplifier A may be the positive input terminal, and the second input terminal of operational amplifier A may be the negative input terminal; the switching transistor M0 may be an N-channel MOS transistor.

[0038] like Figure 2 As shown, the first output unit 20 is connected to the second terminal of the switching transistor M0, and the first output unit 20 is used to generate a first output signal VOUTP based on the sampled current.

[0039] The first output unit 20 includes a first resistor unit and a first amplifier unit. The first terminal of the first resistor unit is connected to the second terminal of the switching transistor M0 and the input terminal of the first amplifier unit. The first amplifier unit is used to output a first output signal VOUTP that is proportional to the voltage on the first terminal of the first resistor unit.

[0040] In one embodiment, the first amplification unit is a buffer, specifically, the first amplification unit includes a first operational amplifier A1. The first input terminal of the first operational amplifier A1 is connected to the first terminal of the first resistor unit and the second terminal of the switching transistor M0. The second input terminal of the first operational amplifier A1 is connected to its output terminal. The first input terminal of the first operational amplifier A1 is a positive input terminal, and the second input terminal is a negative input terminal. In other embodiments, the first input terminal of the first operational amplifier A1 is a negative input terminal, and the second input terminal is a positive input terminal.

[0041] In one embodiment, the first resistor unit includes a second resistor R2, the first end of which is connected to the second end of the switching transistor M0 and the first input terminal of the first operational amplifier A1. In other embodiments, the first resistor unit may consist of multiple resistors connected in series and / or in parallel, or it may consist of resistors with adjustable resistance values.

[0042] The current injection unit is connected to the first terminal of the switching transistor M0 and is used to generate a compensation current; the second output unit 40 is connected to the current injection unit and is used to generate a second output signal VOUTN based on the compensation current.

[0043] like Figure 2 As shown, the current injection unit includes a first current injection unit 31 and a second current injection unit 32. The first current injection unit 31 is connected to the first terminal of the switching transistor M0 to output a first compensation current, and the second current injection unit 32 is connected to the second output unit 40 to output a second compensation current.

[0044] The second output unit 40 includes a second resistor unit and a second amplification unit. The first end of the second resistor unit is connected to the second current injection unit 32 and the input end of the second amplification unit. The second amplification unit is used to output a second output signal VOUTN that is proportional to the voltage on the first end of the second resistor unit. Multiple second amplification units are connected in series.

[0045] In one embodiment, the second amplification unit is a buffer, specifically, the second amplification unit includes a second operational amplifier A2. The first input terminal of the second operational amplifier A2 is connected to the first terminal of the second resistor unit and the second current injection unit 32, and the second input terminal of the second operational amplifier A2 is connected to its output terminal. The first input terminal of the second operational amplifier A2 is a positive input terminal, and the second input terminal of the second operational amplifier A2 is a negative input terminal. In other embodiments, the first input terminal of the second operational amplifier A2 is a negative input terminal, and the second input terminal of the second operational amplifier A2 is a positive input terminal.

[0046] In one embodiment, the second resistor unit includes a third resistor R3, the first end of which is connected to the first input terminal of the second operational amplifier A2 and the second current injection unit 32. In other embodiments, the second resistor unit may consist of multiple resistors connected in series and / or in parallel, or it may consist of resistors with adjustable resistance values.

[0047] By adjusting the resistance values ​​of the first and second resistor units, gain error calibration can be achieved, further improving current detection accuracy. In addition to using resistors with adjustable resistance values, the first and second resistor units can also be composed of multiple fuses and multiple corresponding resistors connected in parallel, and then connected in series and / or parallel to each other. The resistance value of the entire resistor unit is controlled by controlling the number of fuses that open.

[0048] like Figure 2 As shown, the first current injection unit 31 includes multiple first current branches connected in parallel. Each first current branch includes a first current source and a first control switch connected in series. In one embodiment, n first current sources are provided, namely first current sources I1, I2~I... n-1 I n There are also n first control switches, namely the first control switches S1, S2 to S3. n-1 S n By controlling the number of times the first control switch is closed, the magnitude of the first compensation current output by the first current injection unit 31 can be changed.

[0049] like Figure 2 As shown, the second current injection unit 32 includes multiple second current branches connected in parallel. Each second current branch includes a second current source and a second control switch connected in series. In one embodiment, the second current injection unit 32 and the first current injection unit 31 have the same structure.

[0050] In this embodiment, as Figure 2 As shown, the voltage V at the first input terminal of operational amplifier A is used. X Equal to the voltage V at the second input terminal of operational amplifier A Y That is, the current to be measured is within the sensing resistor R SNS The sum of the voltage generated on the first resistor R1 and the voltage on the first resistor R1 is equal to zero. The current generated by the voltage on the first resistor R1 flows through the second resistor R2, thereby realizing the voltage gain of R2 / R1.

[0051] To address the issue of slow input step response caused by the complete turn-off of switch M0 in the existing structure at zero input, this design adds an additional first compensation current by adding a first current injection unit 31 to the source of switch M0, ensuring that switch M0 can be turned on even at zero input, thus optimizing the input step response.

[0052] Furthermore, a second compensation current is injected into the second output unit 40 using a second current injection unit 32 that is mirrored in the first current injection unit 31. The second output unit 40 and the first output unit 20 form a pseudo-differential structure. Since the interference of the ground voltage on the second output unit 40 and the first output unit 20 is basically the same, the interference on the ground voltage can be eliminated (by subtracting the second output signal VOUTN from the first output signal VOUTP).

[0053] Simultaneously, the common-mode voltage of the final output can be easily adjusted by regulating the magnitude of the compensation current injected by the first current injection unit 31 and the second current injection unit 32. At the same time, differentially adjusting the magnitude of the compensation current injected by the first current injection unit 31 and the second current injection unit 32 can also achieve the system (mainly operational amplifier A) offset calibration function. In high-precision applications, this includes, but is not limited to, replacing the first operational amplifier A1 and the second operational amplifier A2 with a zero-drift operational amplifier circuit with chopping function. This structure can also attenuate the ripple of the output signal by differential operation.

[0054] Example 2

[0055] like Figure 3 As shown, this embodiment modifies the structure of the current injection unit based on embodiment 1.

[0056] Specifically, the current injection unit includes a common-mode feedback control unit 51 and a current generation unit 52. The common-mode feedback control unit 51 is used to generate a control signal based on the first output signal VOUTP and the second output signal VOUTN. The current generation unit 52 generates a compensation current based on the control signal. The current generation unit 52 is connected to the second terminal of the switching transistor M0 and the second output unit 40.

[0057] The common-mode feedback control unit 51 includes a first MOSFET M1, a second MOSFET M2, a first bias current source 511, a second bias current source 512, a first bias resistor Rp, a second bias resistor Rn, and a comparator CMP.

[0058] The control terminal of the first MOSFET M1 is connected to the first output signal VOUTP, and the control terminal of the second MOSFET M2 is connected to the second output signal VOUTN. The second terminal of the first MOSFET M1 is connected to the first terminal of the first bias current source 511, and the second terminal of the second MOSFET M2 is connected to the first terminal of the second bias current source 512. The second terminals of the first bias current source 511 and the second terminals of the second bias current source 512 are connected to ground. The first terminal of the first MOSFET M1 is connected to the first terminal of the first bias resistor Rp and the power supply voltage, and the first terminal of the second MOSFET M2 is connected to the first terminal of the second bias resistor Rn and the power supply voltage. The second terminals of the first bias resistor Rp and the second terminals of the second bias resistor Rn are connected to the first input terminal of the comparator CMP. The second input terminal of the comparator CMP is connected to the reference voltage VCM_REF, and the output terminal of the comparator CMP is connected to the current generation unit 52.

[0059] In one embodiment, the first MOSFET M1 and the second MOSFET M2 are P-channel MOSFETs, meaning that the first terminal of the first MOSFET M1 and the first terminal of the second MOSFET M2 are the sources, the second terminals of the first MOSFET M1 and the second MOSFET M2 are the drains, and the control terminals of the first MOSFET M1 and the second MOSFET M2 are the gates. In other embodiments, the first MOSFET M1 and the second MOSFET M2 can also be N-channel MOSFETs.

[0060] In one embodiment, the first input of comparator CMP is a positive input, and the second input of comparator CMP is a negative input. In other embodiments, the first input of comparator CMP can be a negative input, and the second input of comparator CMP can be a positive input.

[0061] The current generating unit 52 includes a third MOSFET M3 and a fourth MOSFET M4. The first terminal of the third MOSFET M3 is connected to the power supply voltage, and the second terminal of the third MOSFET M3 is connected to the first terminal of the switching transistor M0. The first terminal of the fourth MOSFET M4 is connected to the power supply voltage, and the second terminal of the fourth MOSFET M4 is connected to the second output unit 40. The control terminals of the third MOSFET M3 and the fourth MOSFET M4 are connected to the output terminal of the comparator CMP of the common-mode feedback control unit 51.

[0062] In one embodiment, the third MOSFET M3 and the fourth MOSFET M4 are P-channel MOSFETs, meaning that the first terminals of the third MOSFET M3 and the fourth MOSFET M4 are the sources, the second terminals of the third MOSFET M3 and the fourth MOSFET M4 are the drains, and the control terminals of the third MOSFET M3 and the fourth MOSFET M4 are the gates. In other embodiments, the third MOSFET M3 and the fourth MOSFET M4 can also be N-channel MOSFETs.

[0063] In addition, the current generation unit 52 also includes a fifth MOS transistor ( Figure 3 (Not shown in the diagram), the first terminal of the fifth MOSFET is connected to the second terminal of the fourth MOSFET. The second terminal of the fifth MOSFET is connected to the first input terminal of the second operational amplifier A2 of the second output unit 40 and the first terminal of the third resistor R3. The control terminal of the fifth MOSFET is connected to the control terminal of the switching transistor. In one embodiment, the fifth MOSFET is a P-channel MOSFET, that is, the first terminal of the fifth MOSFET is the source, the second terminal of the fifth MOSFET is the drain, and the control terminal of the fifth MOSFET is the gate. In other embodiments, the fifth MOSFET is an N-channel MOSFET, or a fifth MOSFET may not be provided. By forming a symmetrical structure with the fifth MOSFET and the switching transistor M0, the current compensation accuracy is improved.

[0064] In this embodiment, the voltages at the control terminals of the third MOSFET M3 and the fourth MOSFET M4 are clamped by the control signal output by the comparator CMP. The comparator CMP outputs a control signal based on the reference voltage VCM_REF and the node voltage at the connection of the first bias resistor Rp and the second bias resistor Rn. The reference voltage VCM_REF is set equal to the node voltage at the connection of the first bias resistor Rp and the second bias resistor Rn. This node voltage = 0.5(VOUTP+VOUTN)+VGS, where VGS is the voltage between the gate and source of the first MOSFET M1 or the second MOSFET M2. Adjusting the magnitude of the reference voltage VCM_REF adjusts the output common-mode signal. When the input signal changes, the common-mode signal is stabilized by the common-mode feedback control unit 51 and the current generation unit 52, facilitating signal processing in subsequent circuits. By employing a source follower structure to acquire the first output signal VOUTP and the second output signal VOUTN, the gain of the corresponding operational amplifier is avoided. The output common-mode voltage is extracted using a structure where the first bias resistor Rp and the second bias resistor Rn are connected in series.

[0065] Example 3

[0066] This embodiment modifies the structure of the first output unit 20 and the second output unit 40 based on embodiment 1 or embodiment 2. The following description takes the modification of the structure of the first output unit 20 and the second output unit 40 based on embodiment 1 as an example.

[0067] like Figure 4 As shown, in one embodiment, the first amplification unit of the first output unit 20 and the second amplification unit of the second output unit 40 are both proportional amplifiers, and the first amplification unit and the second amplification unit can be configured with one stage or multiple stages; the multiple stages of the first amplification units are connected in sequence, and the multiple stages of the second amplification units are connected in sequence.

[0068] Taking the first stage amplification unit and the second stage amplification unit as examples, the first amplification unit includes operational amplifier A11, resistor R4 and resistor R5, and resistor R4 and resistor R5 constitute the amplification ratio; the second amplification unit includes operational amplifier A21, resistor R8 and resistor R9, and resistor R8 and resistor R9 constitute the amplification ratio.

[0069] The first input terminal of operational amplifier A11 is connected to the first terminal of the second resistor R2. The second input terminal of operational amplifier A11 is connected to the first terminals of resistors R5 and R4. The second terminal of resistor R5 is connected to ground voltage. The second terminal of resistor R4 is connected to the output terminal of operational amplifier A11.

[0070] The first input terminal of operational amplifier A21 is connected to the first terminal of the third resistor R3. The second input terminal of operational amplifier A21 is connected to the first terminals of resistors R9 and R8. The second terminal of resistor R9 is connected to ground voltage. The second terminal of resistor R8 is connected to the output terminal of operational amplifier A21.

[0071] In one embodiment, the first input terminal of operational amplifier A11 is a positive input terminal, and the second input terminal of operational amplifier A11 is a negative input terminal; the first input terminal of operational amplifier A21 is a positive input terminal, and the second input terminal of operational amplifier A21 is a negative input terminal. In other embodiments, the first input terminal of operational amplifier A11 can be a negative input terminal, and the second input terminal of operational amplifier A11 can be a positive input terminal; the first input terminal of operational amplifier A21 can be a negative input terminal, and the second input terminal of operational amplifier A21 can be a positive input terminal.

[0072] If there is only one first-stage amplification unit, the output of operational amplifier A11 outputs the first output signal VOUTP; if there are multiple first-stage amplification units, the output of operational amplifier A11 is connected to the first input of the next stage operational amplifier. Similarly, if there is only one second-stage amplification unit, the output of operational amplifier A21 outputs the second output signal VOUTN; if there are multiple second-stage amplification units, the output of operational amplifier A21 is connected to the first input of the next stage operational amplifier.

[0073] The overall gain can be increased by increasing the number of cascaded proportional amplifiers, thus meeting the application scenarios that require high-gain amplification of detection current.

[0074] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A common-mode current detection circuit, characterized in that, include: A sampling unit is used to sample the current to be measured to obtain a sampled current. The sampling unit includes a detection unit, an operational amplifier, and a switching transistor. The first input terminal of the operational amplifier is connected to the first terminal of the detection unit, the second input terminal of the operational amplifier is connected to the second terminal of the detection unit, the output terminal of the operational amplifier is connected to the control terminal of the switching transistor, and the first terminal of the switching transistor is connected to the second terminal of the detection unit. The first output unit is connected to the second terminal of the switching transistor and is used to generate a first output signal based on the sampled current. The current injection unit is connected to the first terminal of the switching transistor and is used to generate compensation current; as well as The second output unit, connected to the current injection unit, is used to generate a second output signal based on the compensation current. The current injection unit includes a first current injection unit and a second current injection unit. The first current injection unit is connected to the first terminal of the switching transistor to output a first compensation current, and the second current injection unit is connected to the second output unit to output a second compensation current.

2. The common-mode current detection circuit as described in claim 1, characterized in that, The first current injection unit includes one or more first current branches, with multiple first current branches connected in parallel. Each first current branch includes a first current source and a first control switch connected in series; and / or The second current injection unit includes one or more second current branches, and the multiple second current branches are connected in parallel. Each second current branch includes a second current source and a second control switch connected in series.

3. The common-mode current detection circuit as described in claim 1, characterized in that, The current injection unit includes a common-mode feedback control unit and a current generation unit. The common-mode feedback control unit is used to generate a control signal based on a first output signal and a second output signal. The current generation unit generates a compensation current based on the control signal. The current generation unit is connected to the second terminal of the switching transistor and the second output unit.

4. The common-mode current detection circuit as described in claim 3, characterized in that, The common-mode feedback control unit includes a first MOSFET, a second MOSFET, a first bias current source, a second bias current source, a first bias resistor, a second bias resistor, and a comparator; The control terminal of the first MOSFET is connected to the first output signal, and the control terminal of the second MOSFET is connected to the second output signal. The second terminal of the first MOSFET is connected to the first terminal of the first bias current source, and the second terminal of the second MOSFET is connected to the first terminal of the second bias current source. The second terminals of the first and second bias current sources are connected to ground voltage. The first terminal of the first MOSFET is connected to the first terminal of the first bias resistor, and the first terminal of the second MOSFET is connected to the first terminal of the second bias resistor. The second terminals of the first and second bias resistors are connected to the first input terminal of the comparator. The second input terminal of the comparator is connected to the reference voltage, and the output terminal of the comparator is connected to the current generation unit.

5. The common-mode current detection circuit as described in claim 3, characterized in that, The current generating unit includes a third MOSFET and a fourth MOSFET. The first terminal of the third MOSFET is connected to the power supply voltage, the second terminal of the third MOSFET is connected to the first terminal of the switching transistor, the first terminal of the fourth MOSFET is connected to the power supply voltage, the second terminal of the fourth MOSFET is connected to the second output unit, and the control terminals of the third MOSFET and the fourth MOSFET are connected to the common-mode feedback control unit.

6. The common-mode current detection circuit as described in claim 5, characterized in that, The current generating unit also includes a fifth MOS transistor, the first end of which is connected to the second end of the fourth MOS transistor, the second end of which is connected to the second output unit, and the control terminal of the fifth MOS transistor is connected to the control terminal of the switching transistor.

7. The common-mode current detection circuit as described in claim 1, characterized in that, The first output unit includes a first resistor unit and one or more first amplification units. The first end of the first resistor unit is connected to the second end of the switching transistor and the input end of the first amplification unit. The first amplification unit is used to output a first output signal that is proportional to the voltage on the first end of the first resistor unit. The multiple first amplification units are connected in series.

8. The common-mode current detection circuit as described in claim 1, characterized in that, The second output unit includes a second resistor unit and one or more stages of second amplification units. The first end of the second resistor unit is connected to the second end of the switching transistor and the input end of the second amplification unit. The second amplification unit is used to output a second output signal that is proportional to the voltage on the first end of the second resistor unit. The multiple stages of the second amplification units are connected in series.

9. The common-mode current detection circuit as described in claim 7, characterized in that, The first amplification unit is a buffer or a proportional amplifier.

10. The common-mode current detection circuit as described in claim 8, characterized in that, The second amplification unit is a buffer or a proportional amplifier.

11. The common-mode current detection circuit as described in claim 1, characterized in that, The sampling unit further includes a first resistor, the first end of which is connected to the first input terminal of the operational amplifier, and the second end of which is connected to the first terminal of the detection unit.

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