Anti-latch circuit and control method thereof

Abstract

The application relates to the technical field of circuits, in particular to a latch prevention circuit and a control method thereof, which comprises a main processor, a coprocessor, a first power supply end, a second power supply end and a delay circuit; the transmitting end of the main processor is connected with the receiving end of the coprocessor, and the receiving end of the main processor is connected with the transmitting end of the coprocessor; the first power supply end is connected with the second power supply end through the delay circuit; the delay circuit is used for triggering the second power supply end to supply power to the coprocessor after the first power supply end supplies power to the main processor; the power supply sequence of the main processor and the coprocessor is coordinated and controlled, and the latch phenomenon is effectively prevented.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more specifically to an anti-latch-up circuit and its control method. Background Technology

[0002] With the rapid development of integrated circuit manufacturing processes, coprocessors are being used more and more widely, and the performance requirements for coprocessors are becoming more and more stringent, especially in circuit environments where multiple coprocessors work together.

[0003] In related technologies, the circuit structure for multiple coprocessors to work together mainly includes a main processor, a coprocessor, and a power module. However, since the coprocessor's I / O ports are already energized when connected to the main processor, powering on the coprocessor again can easily cause some pins of the coprocessor to enter a latch-up effect and fail to communicate normally. Summary of the Invention

[0004] To address the aforementioned problems, the present invention provides an anti-latch-up circuit and its control method to solve one or more technical problems existing in the prior art, and at least provide a beneficial option or create conditions.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] An anti-latch-up circuit includes: a main processor, a coprocessor, a first power supply terminal, a second power supply terminal, and a delay circuit;

[0007] The main processor's transmitter is connected to the coprocessor's receiver, and the main processor's receiver is connected to the coprocessor's transmitter; the first power supply is connected to the second power supply via a delay circuit.

[0008] The delay circuit is used to delay triggering the second power supply terminal to supply power to the coprocessor after the first power supply terminal supplies power to the main processor.

[0009] Furthermore, the anti-latch-up circuit also includes a first resistor and a second resistor, with the two ends of the first resistor connected to the first power supply terminal and the receiving terminal of the main processor, respectively, and the two ends of the second resistor connected to the first power supply terminal and the transmitting terminal of the main processor, respectively.

[0010] Furthermore, the anti-latch-up circuit also includes a first control circuit and a second control circuit. The first control circuit is used to delay-trigger power supply to the transmitter of the coprocessor after the second power supply terminal is powered on. The second control circuit is used to delay-trigger power supply to the receiver of the coprocessor after the second power supply terminal is powered on.

[0011] Furthermore, the first control circuit includes a first voltage divider circuit, a third resistor, and a first transistor. The input terminal of the first voltage divider circuit and one end of the third resistor are connected to the second power supply terminal. The voltage divider terminal of the first voltage divider circuit is connected to the base of the first transistor. The output terminal of the first voltage divider circuit is grounded. The emitter of the first transistor and the other end of the third resistor are connected to the transmitter terminal of the coprocessor. The collector of the first transistor is connected to the receiver terminal of the main processor.

[0012] Furthermore, the first voltage divider circuit includes a fifth resistor and a sixth resistor. One end of the fifth resistor is connected to the second power supply terminal, and the other end is connected to the base of the first transistor and one end of the sixth resistor, respectively. The other end of the sixth resistor is grounded.

[0013] Furthermore, the second control circuit includes a second voltage divider circuit, a fourth resistor, and a second transistor. The input terminal of the second voltage divider circuit and one end of the fourth resistor are connected to the second power supply terminal. The voltage divider terminal of the second voltage divider circuit is connected to the base of the second transistor. The output terminal of the second voltage divider circuit is grounded. The collector of the second transistor and the other end of the fourth resistor are connected to the receiver terminal of the coprocessor. The emitter of the second transistor is connected to the transmitter terminal of the main processor.

[0014] Furthermore, the second voltage divider circuit includes a seventh resistor and an eighth resistor. One end of the seventh resistor is connected to the second power supply terminal, and the other end is connected to the base of the second transistor and one end of the eighth resistor, respectively. The other end of the eighth resistor is grounded.

[0015] Furthermore, the delay circuit includes an RC circuit and a voltage regulator. The input terminal of the voltage regulator is connected to the power input terminal, the enable terminal is connected to the first power supply terminal through the RC circuit, and the output terminal is connected to the second power supply terminal.

[0016] Furthermore, the RC circuit includes a first capacitor and a ninth resistor. One end of the first capacitor and one end of the ninth resistor are connected to the enable terminal of the voltage regulator. The other end of the first capacitor is grounded, and the other end of the ninth resistor is connected to the first power supply terminal.

[0017] A control method for an anti-latch-up circuit, applied to any of the anti-latch-up circuits described above, the method comprising the following steps:

[0018] Step S100: In response to the power supply request of the anti-latch-up circuit, the first power supply terminal is triggered to supply power to the main processor;

[0019] Step S200: After the main processor is powered by the first power supply terminal, the delay circuit delays and triggers the second power supply terminal to power the coprocessor.

[0020] The beneficial effects of the present invention are as follows: The present invention provides an anti-latch-up circuit and its control method. By controlling the power supply order of the main processor and the coprocessor, the present invention starts the main processor first and then starts the coprocessor, thereby achieving the beneficial effect of effectively preventing latch-up. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a circuit block diagram of an anti-latch-up circuit according to an embodiment of the present invention;

[0023] Figure 2 This is a circuit diagram of an anti-latch-up circuit according to an embodiment of the present invention;

[0024] Figure 3 This is another circuit diagram of an anti-latch-up circuit in an embodiment of the present invention. Detailed Implementation

[0025] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but they should not be construed as limiting the scope of protection of the present invention.

[0026] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0027] In the description of this invention, if there are words such as "several", they mean one or more, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0028] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0029] First, let's analyze some of the terms used in the invention:

[0030] Latch-up occurs when a low-impedance path is created between a device's power supply pin and ground. This condition is triggered by a event (current injection or overvoltage), but once triggered, the low-impedance path persists even if the triggering condition is no longer present. This low-impedance path can lead to system turbulence or catastrophic damage due to excessive current levels. When designing circuit applications, it is essential to ensure that the voltage and current levels applied to the device meet the absolute maximum ratings.

[0031] In related technologies, the circuit structure in which multiple processors work together mainly includes a main processor U1, a coprocessor U2, and a power module. The main processor U1 and coprocessor U2 communicate via I / O ports (such as UART, GPIO, and SPI interfaces). The enable pin of the main processor U1 is connected to the power pin of the coprocessor U2 through the power module, thereby controlling the power module to power on the coprocessor U2. However, since the I / O ports of the coprocessor U2 already have voltage when connected to the main processor U1, powering on the coprocessor U2 again can easily cause some pins of the coprocessor U2 to enter a latch-up state, preventing normal communication.

[0032] This invention provides an anti-latch-up circuit and its control method for the power receiving end under DC power supply. This invention effectively prevents latch-up by coordinating the power supply order of the main processor U1 and the coprocessor U2, starting the main processor U1 first and then starting the coprocessor U2.

[0033] refer to Figure 1 This invention provides an anti-latch-up circuit, comprising: a main processor U1, a coprocessor U2, a first power supply terminal VCC1, a second power supply terminal VCC2, and an RC circuit 310;

[0034] The transmitter HOST_TX of the main processor U1 is connected to the receiver SLAVE_RX of the coprocessor U2, and the receiver HOST_RX of the main processor U1 is connected to the transmitter SLAVE_TX of the coprocessor U2; the first power supply VCC1 is connected to the second power supply VCC2 through the RC circuit 310;

[0035] The RC circuit 310 is used to delay and trigger the second power supply terminal VCC2 to supply power to the coprocessor U2 after the first power supply terminal VCC1 supplies power to the main processor U1.

[0036] It should be noted that in the embodiments provided by this invention, the main processor U1 is first powered by the first power supply terminal VCC1. The main processor U1 starts first, so no voltage flows back to the I / O ports of the main processor U1 during startup, i.e., the receiver terminal HOST_RX and the transmitter terminal HOST_TX of the main processor U1. Then, the coprocessor U2 is powered by the second power supply terminal VCC2 slowly through the RC circuit 310. After the power supply to the second power supply terminal VCC2 is activated, the coprocessor U2 starts. When the second power supply terminal VCC2 is not powered, no voltage flows back to the I / O ports of the coprocessor U2, i.e., the receiver terminal SLAVE_RX and the transmitter terminal HOST_TX of the main processor U1. By controlling the order of power supply to the main processor U1 and the coprocessor U2, this invention starts the main processor U1 first and then the coprocessor U2, achieving the beneficial effect of effectively preventing latch-up.

[0037] refer to Figure 2 As a preferred embodiment of the above embodiment, the anti-latch-up circuit further includes a first resistor R1 and a second resistor R2. The two ends of the first resistor R1 are respectively connected to the first power supply terminal VCC1 and the receiving terminal HOST_RX of the main processor U1, and the two ends of the second resistor R2 are respectively connected to the first power supply terminal VCC1 and the transmitting terminal HOST_TX of the main processor U1.

[0038] It should be noted that in the embodiments provided by the present invention, the first resistor R1 and the second resistor R2 serve as pull-up resistors. The first resistor R1 is used to pull up the voltage of the receiving terminal SLAVE_RX of the coprocessor U2 to the voltage of the first power supply terminal VCC1, and the second resistor R2 is used to pull up the voltage of the transmitting terminal SLAVE_TX of the coprocessor U2 to the voltage of the first power supply terminal VCC1.

[0039] As a preferred embodiment of the above, the anti-latch-up circuit further includes a first control circuit 100, which is used to delay triggering the supply of power to the transmitter SLAVE_TX of the coprocessor U2 after the second power supply terminal VCC2 is powered on.

[0040] As a preferred embodiment of the above, the first control circuit 100 includes a first voltage divider circuit 110, a third resistor R3, and a first transistor Q1. The input terminal of the first voltage divider circuit 110 and one end of the third resistor R3 are connected to the second power supply terminal VCC2. The voltage divider terminal of the first voltage divider circuit 110 is connected to the base of the first transistor Q1. The output terminal of the first voltage divider circuit 110 is grounded. The emitter of the first transistor Q1 and the other end of the third resistor R3 are connected to the transmitter terminal SLAVE_TX of the coprocessor U2. The collector of the first transistor Q1 is connected to the receiver terminal HOST_RX of the main processor U1.

[0041] It should be noted that in the embodiments provided by the present invention, the third resistor R3 acts as a pull-up resistor. After the second power supply terminal VCC2 is powered on, the voltage of the transmitter terminal SLAVE_TX of the coprocessor U2 is pulled up to the voltage of the second power supply terminal VCC2 through the third resistor R3, thereby triggering the transmitter terminal SLAVE_TX of the coprocessor U2 to be powered on.

[0042] As a preferred embodiment of the above embodiment, the first voltage divider circuit 110 includes a fifth resistor R5 and a sixth resistor R6. One end of the fifth resistor R5 is connected to the second power supply terminal VCC2, and the other end is connected to the base of the first transistor Q1 and one end of the sixth resistor R6, respectively. The other end of the sixth resistor R6 is grounded.

[0043] As a preferred embodiment of the above, the anti-latch-up circuit further includes a second control circuit 200, which is used to delay triggering the supply of power to the receiver SLAVE_RX of the coprocessor U2 after the second power supply terminal VCC2 is powered on.

[0044] In a preferred embodiment of the above, the second control circuit 200 includes a second voltage divider circuit 210, a fourth resistor R4, and a second transistor Q2. The input terminal of the second voltage divider circuit 210 and one end of the fourth resistor R4 are connected to the second power supply terminal VCC2. The voltage divider terminal of the second voltage divider circuit 210 is connected to the base of the second transistor Q2. The output terminal of the second voltage divider circuit 210 is grounded. The collector of the second transistor Q2 and the other end of the fourth resistor R4 are connected to the receiver terminal SLAVE_RX of the coprocessor U2. The emitter of the second transistor Q2 is connected to the transmitter terminal HOST_TX of the main processor U1.

[0045] It should be noted that in the embodiments provided by the present invention, the fourth resistor R4 acts as a pull-up resistor. After the second power supply terminal VCC2 is powered on, the fourth resistor R4 is used to pull up the voltage of the receiver terminal SLAVE_RX of the coprocessor U2 to the voltage of the second power supply terminal VCC2, thereby triggering the receiver terminal SLAVE_RX of the coprocessor U2 to be powered on.

[0046] As a preferred embodiment of the above, the second voltage divider circuit 210 includes a seventh resistor R7 and an eighth resistor R8. One end of the seventh resistor R7 is connected to the second power supply terminal VCC2, and the other end is connected to the base of the second transistor Q2 and one end of the eighth resistor R8, respectively. The other end of the eighth resistor R8 is grounded.

[0047] refer to Figure 3 As a preferred embodiment of the above, the delay circuit 300 includes an RC circuit 310 and a voltage regulator U3. The input terminal of the voltage regulator U3 is connected to the power input terminal VCC_IN, the enable terminal is connected to the first power supply terminal VCC1 through the RC circuit 310, and the output terminal is connected to the second power supply terminal VCC2.

[0048] As a preferred embodiment of the above, the RC circuit 310 includes a first capacitor C1 and a ninth resistor R9. One end of the first capacitor C1 and one end of the ninth resistor R9 are connected to the enable terminal of the voltage regulator U3. The other end of the first capacitor C1 is grounded, and the other end of the ninth resistor R9 is connected to the first power supply terminal VCC1.

[0049] In some embodiments, the voltage regulator U3 is a linear voltage regulator U3 of model SGM2019. The voltage at the first power supply terminal VCC1 is 1.8V, and the voltage at the second power supply terminal VCC2 is 3.3V.

[0050] The working principle of this invention is as follows:

[0051] 1) Upon power-up, the main processor U1 starts first. The transmitter HOST_TX and receiver HOST_RX of the main processor U1 are pulled up to the voltage of the first power supply terminal VCC1 through the first resistor R1 and the second resistor R2. Since the main processor U1 starts first, no voltage flows back to the I / O ports of the main processor U1, i.e., the receiver HOST_RX and the transmitter HOST_TX of the main processor U1, during startup.

[0052] 2) After the main processor U1 is powered on, the voltage regulator U3 is slowly started through the RCRC circuit 310, thereby providing voltage to the second power supply terminal VCC2.

[0053] 3) After the VCC_3V3 power supply is powered on, the voltage at the receiver terminal SLAVE_RX and the transmitter terminal SLAVE_TX of coprocessor U2 is pulled up to the voltage at the second power supply terminal VCC2 through pull-up resistors. The voltage at the base of the first transistor Q1 is obtained by voltage division of the voltage at the second power supply terminal VCC2 by the first control circuit 100, and the voltage at the base of the second transistor Q2 is obtained by voltage division of the voltage at the second power supply terminal VCC2 by the second control circuit 200. When the second power supply terminal VCC2 is not powered on, the voltage at the second power supply terminal VCC2 is 0, and the receiver terminal SLAVE_RX and the transmitter terminal SLAVE_TX of coprocessor U2 are floating. There is no backflow of voltage to the receiver terminal SLAVE_RX and the transmitter terminal SLAVE_TX of coprocessor U2, thus avoiding latch-up. This is the beneficial effect of the present invention. It should be noted that the first transistor Q1 and the second transistor Q2 can play a role in starting level conversion during the communication between the main processor U1 and the coprocessor.

[0054] Before incorporating the anti-latch-up circuit of this invention, the main processor U1 and the coprocessor were powered on together, and the I / O ports of the main processor U1 and the coprocessor were powered on sequentially. Therefore, there was a certain probability that latch-up would occur in the GPIO ports of the main processor U1 and / or the coprocessor, leading to failure. This invention controls the power supply of the coprocessor U2 through the main processor U1. The bases of the first transistor Q1 and the second transistor Q2 are controlled by the coprocessor U2. The main processor U1 is powered on first, followed by the coprocessor U2. The I / O ports of the coprocessor U2 are controlled by the voltage regulator U3 of the coprocessor, effectively preventing latch-up.

[0055] Furthermore, embodiments of the present invention provide a control method for an anti-latch-up circuit, applied to the anti-latch-up circuit described in any of the above embodiments, the method comprising the following steps:

[0056] Step S100: In response to the power supply request of the anti-latch-up circuit, the first power supply terminal VCC1 is triggered to supply power to the main processor U1;

[0057] In step S200, after the first power supply terminal VCC1 supplies power to the main processor U1, the RC circuit 310 delays and triggers the second power supply terminal VCC2 to supply power to the coprocessor U2.

[0058] Corresponding to the circuit embodiment described above, in this embodiment, the main processor U1 is first powered through the first power supply terminal VCC1. Since the main processor U1 starts up first, no voltage flows back to the I / O ports of the main processor U1 during startup, i.e., the receiver terminal HOST_RX and the transmitter terminal HOST_TX of the main processor U1. Next, the coprocessor U2 is slowly powered up through the second power supply terminal VCC2 via the RC circuit 310. After the second power supply terminal VCC2 is powered on, the coprocessor U2 starts up. When the second power supply terminal VCC2 is not powered, no voltage flows back to the I / O ports of the coprocessor U2, i.e., the receiver terminal SLAVE_RX and the transmitter terminal HOST_TX of the main processor U1. This invention, by controlling the order of power supply to the main processor U1 and the coprocessor U2, starts the main processor U1 first and then the coprocessor U2, effectively preventing latch-up.

[0059] The embodiments described in this invention are for the purpose of more clearly illustrating the technical solutions of the embodiments of this invention, and do not constitute a limitation on the technical solutions provided by the embodiments of this invention. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this invention are also applicable to similar technical problems.

[0060] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present invention, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0061] The device embodiments described above are merely illustrative. The circuits described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network circuits. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0062] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / circuits in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0063] The terms "first," "second," "third," "fourth," etc. (if present) in the specification and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or circuits is not necessarily limited to those steps or circuits explicitly listed, but may include other steps or circuits not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0064] It should be understood that in this invention, "at least one (item)" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0065] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the circuit division described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple circuits or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, apparatus, or circuits, and may be electrical, mechanical, or other forms.

[0066] The circuits described above as separate components may or may not be physically separate. The components shown as circuits may or may not be physical circuits; that is, they may be located in one place or distributed across multiple network circuits. Some or all of the circuits can be selected to achieve the purpose of this embodiment according to actual needs.

[0067] Furthermore, the functional circuits in the various embodiments of the present invention can be integrated into a single processing circuit, or each circuit can exist physically separately, or two or more circuits can be integrated into a single circuit. The integrated circuits described above can be implemented in hardware or as software functional circuits.

[0068] The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of the present invention should be within the scope of the claims of the present invention. Although the description of the present invention has been quite detailed and particularly of several described embodiments, it is not intended to limit itself to any of these details or embodiments or any particular embodiment, but should be regarded as effectively covering the intended scope of the present invention by referring to the appended claims and considering the prior art to provide a broad possible interpretation of these claims. Furthermore, the present invention has been described above with respect to embodiments foreseeable by the inventors in order to provide a useful description, and non-substantial modifications to the present invention that have not yet been foreseen may still represent equivalent modifications to this disclosure.

Claims

1. An anti-latch-up circuit, characterized in that, It includes a main processor and a coprocessor, wherein the transmitter of the main processor is connected to the receiver of the coprocessor, and the receiver of the main processor is connected to the transmitter of the coprocessor; a first power supply is connected to a second power supply via a delay circuit; The anti-latch-up circuit is characterized in that it further includes: A first resistor, the two ends of which are respectively connected to the first power supply terminal and the receiving terminal of the main processor; The second resistor has its two ends connected to the first power supply terminal and the transmitter terminal of the main processor, respectively. A first control circuit is used to delay and trigger power supply to the transmitter of the coprocessor after the second power supply terminal is powered on. The second control circuit is used to delay triggering the supply of power to the receiver of the coprocessor after the second power supply terminal is powered on. The first control circuit includes a first voltage divider circuit, a third resistor, and a first transistor. The input terminal of the first voltage divider circuit and one end of the third resistor are connected to the second power supply terminal. The voltage divider terminal of the first voltage divider circuit is connected to the base of the first transistor. The output terminal of the first voltage divider circuit is grounded. The emitter of the first transistor and the other end of the third resistor are connected to the transmitter terminal of the coprocessor. The collector of the first transistor is connected to the receiver terminal of the main processor. The first voltage divider circuit includes a fifth resistor and a sixth resistor. One end of the fifth resistor is connected to the second power supply terminal, and the other end is connected to the base of the first transistor and one end of the sixth resistor, respectively. The other end of the sixth resistor is grounded. The second control circuit includes a second voltage divider circuit, a fourth resistor, and a second transistor. The input terminal of the second voltage divider circuit and one end of the fourth resistor are connected to the second power supply terminal. The voltage divider terminal of the second voltage divider circuit is connected to the base of the second transistor. The output terminal of the second voltage divider circuit is grounded. The collector of the second transistor and the other end of the fourth resistor are connected to the receiver terminal of the coprocessor. The emitter of the second transistor is connected to the transmitter terminal of the main processor. The second voltage divider circuit includes a seventh resistor and an eighth resistor. One end of the seventh resistor is connected to the second power supply terminal, and the other end is connected to the base of the second transistor and one end of the eighth resistor, respectively. The other end of the eighth resistor is grounded.

2. The anti-latch-up circuit according to claim 1, characterized in that, The delay circuit includes an RC circuit and a voltage regulator. The input terminal of the voltage regulator is connected to the power input terminal, the enable terminal is connected to the first power supply terminal through the RC circuit, and the output terminal is connected to the second power supply terminal.

3. The anti-latch-up circuit according to claim 2, characterized in that, The RC circuit includes a first capacitor and a ninth resistor. One end of the first capacitor and one end of the ninth resistor are connected to the enable terminal of the voltage regulator. The other end of the first capacitor is grounded, and the other end of the ninth resistor is connected to the first power supply terminal.

4. A control method for an anti-latch-up circuit, characterized in that, Applied to the anti-latch-up circuit according to any one of claims 1 to 3, the method includes the following steps: Step S100: In response to the power supply request of the anti-latch-up circuit, the first power supply terminal is triggered to supply power to the main processor; Step S200: After the main processor is powered by the first power supply terminal, the delay circuit delays and triggers the second power supply terminal to power the coprocessor.

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