Chip quality detection model construction method and terminal
By constructing a chip quality inspection model and establishing a mapping relationship between attribute features and semantic features using convolutional neural networks and generative models, the problems of insufficient generalization and robustness of existing models are solved, enabling the identification and classification of new chip defects and improving the detection accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOUTHERN UNIVERSITY OF SCIENCE AND TECHNOLOGY
- Filing Date
- 2023-06-06
- Publication Date
- 2026-06-12
Smart Images
Figure CN116883316B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip quality testing technology, and in particular to a method and terminal for constructing a chip quality testing model. Background Technology
[0002] With the high-quality development of the manufacturing industry, the market needs to vigorously develop the chip industry to improve the application adaptability of chips. Among them, chip quality testing is a very important part of the chip manufacturing process, which determines whether the entire chip can meet the customer's usage requirements.
[0003] Chip quality inspection methods are mainly divided into manual inspection and automatic inspection. Manual inspection relies on human eyesight and experience to inspect the chip, which is inefficient and lacks accuracy. Automatic inspection, on the other hand, uses machines and technology to identify quality problems in the chip, greatly improving efficiency and accuracy. Image recognition is a commonly used method in automatic inspection, detecting and identifying quality problems such as short circuits, broken lines, scratches, and defects by analyzing images of the chip's exterior.
[0004] Currently, there are many research results on chip quality inspection methods based on image recognition. Patent (Patent Publication No. CN115359022A) discloses a power chip quality inspection method and system. This method performs quality inspection on the pins of the power chip based on appearance images and feature information. No image grayscale processing is performed before image segmentation, which preserves more detailed information than grayscale processing, effectively improving the accuracy of pin inspection of power management chips using image recognition technology. Patent (Patent Publication No. CN115601351A) discloses a bonding defect identification method, system, device, and medium that integrates multi-mode information. By inputting defect parameters such as defect morphology and stain edges in the chip into a defect identification model for discrimination, the accuracy of chip defect identification can be effectively improved. The patent (patent publication number CN115239712A) discloses a method, device, electronic device and storage medium for detecting defects on the surface of a circuit board. By inputting the acquired circuit board image into a pre-trained CNN-Transformer fusion model for defect recognition, the model can achieve good results in both accuracy and detection efficiency while taking into account performance and inference speed.
[0005] However, the models used in the above detection methods have insufficient generalization and robustness, and cannot effectively identify new types of chip defects or unseen similar chip defects, resulting in low overall recognition accuracy of the models. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to provide a method and terminal for constructing a chip quality inspection model, which enhances the generalization and robustness of the inspection model, effectively identifies new types of chip defects, and improves the accuracy of chip quality inspection.
[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:
[0008] A method for constructing a chip quality inspection model, comprising the following steps:
[0009] Obtain a sample dataset, and obtain the corresponding semantic feature vector based on the sample dataset;
[0010] The chip quality inspection model is obtained by extracting the attribute feature vectors of the sample dataset through convolutional neural networks and generative models, and mapping the attribute feature vectors to the semantic feature vectors through deep neural networks.
[0011] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows:
[0012] A chip quality inspection model construction terminal includes a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it performs the following steps:
[0013] Obtain a sample dataset, and obtain the corresponding semantic feature vector based on the sample dataset;
[0014] The chip quality inspection model is obtained by extracting the attribute feature vectors of the sample dataset through convolutional neural networks and generative models, and mapping the attribute feature vectors to the semantic feature vectors through deep neural networks.
[0015] The beneficial effects of this invention are as follows: By constructing semantic feature vectors through sample datasets, the recognition and classification of sample datasets can be achieved. At the same time, by establishing a mapping relationship between the attribute feature vectors of images and semantic feature vectors, it is possible to identify and classify chip defects that have not been learned before, achieving zero-learning. This enables the chip quality inspection model to identify chip defect problems that have never appeared before, thereby improving the accuracy of the chip quality inspection model. Finally, by expanding the attribute feature vectors of images through convolutional neural networks and generative models, the sample dataset is expanded. This eliminates the need to extract the attribute feature vectors of images multiple times through convolutional neural networks, effectively enhancing the generalization and robustness of the model while reducing the computational load of convolutional neural networks. Attached Figure Description
[0016] Figure 1 This is a flowchart illustrating the steps of constructing a chip quality inspection model as disclosed in this invention.
[0017] Figure 2 A flowchart illustrating the modeling process of the chip quality inspection model provided in this embodiment of the invention;
[0018] Figure 3 This is a schematic diagram of the structure of a convolutional neural network provided in an embodiment of the present invention;
[0019] Figure 4 This is a schematic diagram of the structure of the VAE model provided in an embodiment of the present invention;
[0020] Figure 5 A schematic diagram of a chip quality detection model based on zero-learning provided in an embodiment of the present invention;
[0021] Figure 6 This is a schematic diagram of the structure of a terminal for constructing a chip quality inspection model disclosed in this invention;
[0022] Label Explanation:
[0023] 201. Memory; 202. Processor. Detailed Implementation
[0024] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0025] Please refer to Figure 1 This invention provides a method for constructing a chip quality inspection model, characterized by the following steps:
[0026] Obtain a sample dataset, and obtain the corresponding semantic feature vector based on the sample dataset;
[0027] The chip quality inspection model is obtained by extracting the attribute feature vectors of the sample dataset through convolutional neural networks and generative models, and mapping the attribute feature vectors to the semantic feature vectors through deep neural networks.
[0028] As can be seen from the above description, the beneficial effects of the present invention are as follows: by constructing semantic feature vectors through sample datasets, the recognition and classification of sample datasets can be achieved. At the same time, by establishing a mapping relationship between the attribute feature vectors of images and semantic feature vectors, it is possible to identify and classify chip defects that have not been learned before, achieving zero-learning. This enables the chip quality inspection model to identify chip defect problems that have never appeared before, thereby improving the accuracy of the chip quality inspection model. Finally, by expanding the attribute feature vectors of images through convolutional neural networks and generative models, the sample dataset is expanded. This eliminates the need to extract the attribute feature vectors of images multiple times through convolutional neural networks, effectively enhancing the generalization and robustness of the model while reducing the computational load of convolutional neural networks.
[0029] Furthermore, the sample dataset includes a training sample set and a test sample set; the defect types contained in the test sample set are not exactly the same as those in the training sample set.
[0030] The specific steps of obtaining the sample dataset and obtaining the corresponding semantic feature vector based on the sample dataset are as follows:
[0031] Sample images of the chip are acquired as training and testing sample sets, and the defect types in the training and testing sample sets are labeled respectively to obtain training labels and testing labels.
[0032] Based on the training labels and test labels, corresponding semantic feature texts are constructed respectively. Based on the corresponding semantic feature texts, the corresponding semantic feature vectors are obtained by mapping through a word vector model.
[0033] As described above, by training the model using the training sample set, the model can classify defects in the test sample set. However, the defect types in the training sample set and the test sample set are not entirely the same; that is, some defect types in the training sample set and the test sample set do not overlap. Therefore, by labeling the images with training labels and test labels respectively to classify defect types, and constructing corresponding semantic feature text, a connection is established between the training sample set and the test sample set, making the model's classification and recognition effective.
[0034] Furthermore, the convolutional neural network includes a first convolutional layer, a second convolutional layer, a first sampling layer, and a second sampling layer;
[0035] The extraction of attribute feature vectors from the sample dataset using convolutional neural networks and generative models specifically involves:
[0036] The first feature vector of the sample dataset is extracted by the first convolutional layer, and the first feature vector is sampled by the first sampling layer to obtain the second feature vector;
[0037] The third feature vector of the second feature vector is extracted by the second convolutional layer, and the third feature vector is reduced in dimensionality by the second sampling layer to obtain the initial feature vector.
[0038] The initial attribute feature vector is input into the generative model for optimization training to obtain similar feature vectors;
[0039] The initial feature vector and the set of similar feature vectors are used as the attribute feature vector.
[0040] As described above, by extracting initial feature vectors from images through convolutional neural networks and optimizing each type of initial feature vector using a generative model to generate more similar feature vectors, the attribute feature vectors are expanded, the distribution of model training data is broadened, and the generalization and robustness of the model are effectively enhanced.
[0041] Furthermore, the step of mapping the attribute feature vector to the semantic feature vector using a deep neural network to obtain the chip quality inspection model specifically involves:
[0042] The attribute feature vector is mapped to the semantic feature vector through the mapping function and loss function of the deep neural network to obtain the chip quality inspection model;
[0043] The mapping function is:
[0044] S=σ(W s A g +b s );
[0045] The loss function is:
[0046] Loss = min||W s A g -S|| 2 +β||W s ||2;
[0047] Where σ is the activation function of the deep neural network; W s For convolution kernel; A g b is the attribute feature vector; s S is the bias parameter matrix; S is the semantic feature vector; β is the hyperparameter; ||W s ||2 is a 2-norm constraint. k is the number of semantic feature vectors.
[0048] As described above, by mapping attribute feature vectors to semantic feature vectors, image features can be matched with defect types. This enables knowledge transfer between datasets of different defect types through attribute feature vectors, achieving zero-step learning. This allows the chip quality inspection model to identify chip defect problems that have never appeared before, thus improving the accuracy of the chip quality inspection model.
[0049] Furthermore, the generative model is a VAE model;
[0050] The step of inputting the initial attribute feature vector into the generative model for optimization training to obtain similar feature vectors specifically involves:
[0051] The initial attribute feature vector is input into the encoder of the VAE model to obtain the Gaussian distribution function;
[0052] The Gaussian distribution function is sampled to obtain sampled data;
[0053] The sampled data is input into the decoder of the VAE model, and optimized and trained using an objective function to generate similar feature vectors;
[0054] The objective function is:
[0055]
[0056] Where E represents expectation; a represents attribute feature vector; z represents latent variable; and p and q represent probability density distribution functions.
[0057] As described above, after model training is completed, more similar attribute features can be generated by the encoder of the generative model, thereby obtaining optimized and expanded attribute feature vectors. This expands the distribution of model training data, thus effectively enhancing the generalization and robustness of the model while reducing computational load.
[0058] Please refer to Figure 6 Another embodiment of the present invention provides a chip quality inspection model construction terminal, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it performs the following steps:
[0059] Obtain a sample dataset, and obtain the corresponding semantic feature vector based on the sample dataset;
[0060] The chip quality inspection model is obtained by extracting the attribute feature vectors of the sample dataset through convolutional neural networks and generative models, and mapping the attribute feature vectors to the semantic feature vectors through deep neural networks.
[0061] As can be seen from the above description, the beneficial effects of the present invention are as follows: by constructing semantic feature vectors through sample datasets, the recognition and classification of sample datasets can be achieved. At the same time, by establishing a mapping relationship between the attribute feature vectors of images and semantic feature vectors, it is possible to identify and classify chip defects that have not been learned before, achieving zero-learning. This enables the chip quality inspection model to identify chip defect problems that have never appeared before, thereby improving the accuracy of the chip quality inspection model. Finally, by expanding the attribute feature vectors of images through convolutional neural networks and generative models, the sample dataset is expanded. This eliminates the need to extract the attribute feature vectors of images multiple times through convolutional neural networks, effectively enhancing the generalization and robustness of the model while reducing the computational load of convolutional neural networks.
[0062] Furthermore, the sample dataset includes a training sample set and a test sample set; the defect types contained in the test sample set are not exactly the same as those in the training sample set.
[0063] The specific steps of obtaining the sample dataset and obtaining the corresponding semantic feature vector based on the sample dataset are as follows:
[0064] Sample images of the chip are acquired as training and testing sample sets, and the defect types in the training and testing sample sets are labeled respectively to obtain training labels and testing labels.
[0065] Based on the training labels and test labels, corresponding semantic feature texts are constructed respectively. Based on the corresponding semantic feature texts, the corresponding semantic feature vectors are obtained by mapping through a word vector model.
[0066] As described above, by training the model using the training sample set, the model can classify defects in the test sample set. However, the defect types in the training sample set and the test sample set are not entirely the same; that is, some defect types in the training sample set and the test sample set do not overlap. Therefore, by labeling the images with training labels and test labels respectively to classify defect types, and constructing corresponding semantic feature text, a connection is established between the training sample set and the test sample set, making the model's classification and recognition effective.
[0067] Furthermore, the convolutional neural network includes a first convolutional layer, a second convolutional layer, a first sampling layer, and a second sampling layer;
[0068] The extraction of attribute feature vectors from the sample dataset using convolutional neural networks and generative models specifically involves:
[0069] The first feature vector of the sample dataset is extracted by the first convolutional layer, and the first feature vector is sampled by the first sampling layer to obtain the second feature vector;
[0070] The third feature vector of the second feature vector is extracted by the second convolutional layer, and the third feature vector is reduced in dimensionality by the second sampling layer to obtain the initial feature vector.
[0071] The initial attribute feature vector is input into the generative model for optimization training to obtain similar feature vectors;
[0072] The initial feature vector and the set of similar feature vectors are used as the attribute feature vector.
[0073] As described above, by extracting initial feature vectors from images through convolutional neural networks and optimizing each type of initial feature vector using a generative model to generate more similar feature vectors, the attribute feature vectors are expanded, the distribution of model training data is broadened, and the generalization and robustness of the model are effectively enhanced.
[0074] Furthermore, the step of mapping the attribute feature vector to the semantic feature vector using a deep neural network to obtain the chip quality inspection model specifically involves:
[0075] The attribute feature vector is mapped to the semantic feature vector through the mapping function and loss function of the deep neural network to obtain the chip quality inspection model;
[0076] The mapping function is:
[0077] S=σ(W s A g +b s );
[0078] The loss function is:
[0079] Loss = min||W s A g -S|| 2 +β||W s ||2;
[0080] Where σ is the activation function of the deep neural network; W s For convolution kernel; A g b is the attribute feature vector; s S is the bias parameter matrix; S is the semantic feature vector; β is the hyperparameter; ||W s ||2 is a 2-norm constraint. k is the number of semantic feature vectors.
[0081] As described above, by mapping attribute feature vectors to semantic feature vectors, image features can be matched with defect types. This enables knowledge transfer between datasets of different defect types through attribute feature vectors, achieving zero-step learning. This allows the chip quality inspection model to identify chip defect problems that have never appeared before, thus improving the accuracy of the chip quality inspection model.
[0082] Furthermore, the generative model is a VAE model;
[0083] The step of inputting the initial attribute feature vector into the generative model for optimization training to obtain similar feature vectors specifically involves:
[0084] The initial attribute feature vector is input into the encoder of the VAE model to obtain the Gaussian distribution function;
[0085] The Gaussian distribution function is sampled to obtain sampled data;
[0086] The sampled data is input into the decoder of the VAE model, and optimized and trained using an objective function to generate similar feature vectors;
[0087] The objective function is:
[0088]
[0089] Where E represents expectation; a represents attribute feature vector; z represents latent variable; and p and q represent probability density distribution functions.
[0090] As described above, after model training is completed, more similar attribute features can be generated by the encoder of the generative model, thereby obtaining optimized and expanded attribute feature vectors. This expands the distribution of model training data, thus effectively enhancing the generalization and robustness of the model while reducing computational load.
[0091] This invention provides a method and terminal for constructing a chip quality inspection model, which can be applied to the chip manufacturing process to achieve chip quality inspection and improve inspection efficiency and accuracy. The following specific embodiments illustrate this:
[0092] Please refer to Figures 1 to 5 Embodiment 1 of the present invention is as follows:
[0093] A method for constructing a chip quality inspection model, comprising the following steps:
[0094] S1. Obtain the sample dataset and obtain the corresponding semantic feature vector based on the sample dataset.
[0095] The sample dataset includes a training sample set and a test sample set; the test sample set contains different defect types than the training sample set.
[0096] It should be noted that the test sample set includes some other image data that are not within the scope of the training sample set.
[0097] Specifically, S1 is:
[0098] S11. Obtain sample images of the chip as training sample set and test sample set, and label the defect types in the training sample set and test sample set respectively to obtain training label and test label.
[0099] It should be noted that the sample image of the chip is a chip image with defects; the defects include scratches, broken wires, short circuits, damage, stains, etc.
[0100] S12. Construct corresponding semantic feature texts based on the training labels and test labels respectively, and obtain corresponding semantic feature vectors by mapping the corresponding semantic feature texts through a word vector model.
[0101] In some embodiments, the training sample set X and the test sample set X are obtained. t The training sample set X and the test sample set X are labeled respectively. t The defect type is used to obtain the training label Y and the test label Y. t At the same time, construct each training label Y and test label Y. t (i.e., the semantic feature text corresponding to each defect type); for example, if the test label Y t If the (defect type) is "broken line", then the test label Y t The corresponding semantic feature text includes wire, break, crack width, etc. Simultaneously, each training label Y and test label Y... t The semantic feature text corresponding to each defect type is used to obtain the corresponding semantic feature vector S = [s1, s2, ..., s] through a word vector model in the field of natural language processing. n ] and S t =[s t1 ,s t2 ,…,s tn ].
[0102] S2. Extract the attribute feature vectors of the sample dataset through a convolutional neural network and a generative model, and map the attribute feature vectors to the semantic feature vectors through a deep neural network to obtain the chip quality inspection model.
[0103] The convolutional neural network includes a first convolutional layer, a second convolutional layer, a first sampling layer, and a second sampling layer.
[0104] In some embodiments, the convolutional neural network is a CNN algorithm model.
[0105] Specifically, S2 is:
[0106] S21. Extract the first feature vector of the sample dataset through the first convolutional layer, and sample the first feature vector through the first sampling layer to obtain the second feature vector.
[0107] S22. Extract the third feature vector of the second feature vector through the second convolutional layer, and perform data dimensionality reduction on the third feature vector through the second sampling layer to obtain the initial feature vector.
[0108] In some embodiments, such as Figure 3As shown, after inputting the training sample set into the model, the first convolutional layer extracts a coarse first feature vector A1 using 5 convolutional kernels, specifically expressed as: A1 = σ(W1 + b1). After the first convolutional layer, the first sampling layer reduces the amount of data to be processed using maximum downsampling, i.e., compressing the images in the training sample set, specifically expressed as: A2 = MaxPool(A1). Then, the second convolutional layer extracts a more detailed third feature vector A3 from the second feature vector A2 using 11 convolutional kernels, specifically expressed as: A3 = σ(W2A2 + b2). Finally, the second sampling layer performs dimensionality reduction on the third feature vector A3 to obtain the initial feature vector A. Here, σ represents the activation function in the convolutional neural network, specifically the RelU function; W1 and W2 represent the convolutional kernels; and b1 and b2 represent the bias parameter matrices.
[0109] S23. Input the initial attribute feature vector into the generation model for optimization training to obtain similar feature vectors.
[0110] In one optional implementation, the generative model is a VAE model, then step S23 specifically involves:
[0111] S231. Input the initial attribute feature vector into the encoder of the VAE model to obtain the Gaussian distribution function;
[0112] S232. Sample the Gaussian distribution function to obtain sampled data;
[0113] S233. Input the sampled data into the decoder of the VAE model, perform optimization training through the objective function, and generate similar feature vectors;
[0114] The objective function is:
[0115]
[0116] Where E represents expectation; a represents attribute feature vector; z represents latent variable; and p and q represent probability density distribution functions.
[0117] S24. The set of the initial feature vector and similar feature vectors is taken as the attribute feature vector.
[0118] In some embodiments, after obtaining the initial feature vector, in order to identify as many similar defect problems as possible in a limited sample dataset, the initial feature vector A of each class is further expanded and improved by a generative model to generate more similar attribute feature vectors.
[0119] In some embodiments, such as Figure 4As shown, the initial feature vector A is input into the encoder of the VAE model. The encoder maps the initial feature vector A to a Gaussian distribution function in the latent space Z, samples data z from the Gaussian distribution function, and then inputs the sampled data z into the decoder for optimization training to generate a similar feature vector A'. The set of the initial feature vector A and the similar feature vector A' is used as the attribute feature vector A'. g .
[0120] S25. The attribute feature vector is mapped to the semantic feature vector through the mapping function and loss function of the deep neural network to obtain the chip quality inspection model;
[0121] The mapping function is:
[0122] S=σ(W s A g +b s );
[0123] The loss function is:
[0124] Loss = min||W s A g -S|| 2 +β||W s ||2;
[0125] Where σ is the activation function of the deep neural network; W s For convolution kernel; A g b is the attribute feature vector; s S is the bias parameter matrix; S is the semantic feature vector; β is the hyperparameter; ||W s ||2 is a 2-norm constraint.
[0126] It should be noted that, as Figure 2 As shown, after completing the modeling process of the chip quality inspection model through steps S1-S2, the model is continuously trained iteratively using the training sample set, while the model is verified and optimized using the test sample set until a chip quality inspection model that meets the expected requirements is obtained.
[0127] In some embodiments, the model is trained using a training sample set X containing chip defect problems and corresponding training template labels Y, enabling the model to complete the testing of the test sample set X. t The identification and classification, due to the difference between the training sample set X and the test sample set X t The types of defects involved differ, therefore the model needs to achieve knowledge transfer and learning recognition between the two through semantic feature text. For example, refer to... Figure 5During the training of the model on the training sample set X, the model learns the semantic feature text corresponding to the training label Y1 "damage" including "fracture," meaning the model can identify "fracture" from the image and classify it as a "damage" problem. Simultaneously, the model learns the semantic feature text corresponding to the training label Y2 "short circuit" including "wire," meaning the model can identify "wire" from the image and classify it as a "short circuit." On the test sample set X... t During the testing of the model, for test labels Y that have not been seen before... T The model can identify two features in an image: "broken wire" and "wire". Therefore, it only needs to assign the test label Y... T By matching the semantic feature text corresponding to "broken line" with the aforementioned features "break" and "wire", the model can effectively identify the defect of "broken line".
[0128] In the chip quality inspection process, it is only necessary to acquire an image of the chip under test and input the image into the chip quality inspection model to complete the quality inspection of the chip under test.
[0129] This invention primarily employs a zero-learning method to enable the detection model to effectively identify unseen chip defects, while simultaneously utilizing a generative model to improve the efficiency of sample feature learning during the zero-learning process. First, a training sample set of chip quality inspection images is constructed, along with their corresponding training labels, semantic feature text, and semantic feature vectors. Then, a convolutional neural network is used to calculate and extract the attribute vectors of the images. A generative model is then used to simulate and generate similar data for each type of attribute vector. The expanded and optimized attribute vectors are mapped onto the pre-constructed semantic feature vectors corresponding to the defect problems, enabling the classification and identification of chip defects. This significantly enhances the model's generalization and robustness, effectively improving the accuracy of quality detection.
[0130] Please refer to Figure 6 Embodiment two of the present invention is as follows:
[0131] A chip quality inspection model construction terminal includes a memory 201, a processor 202, and a computer program stored in the memory 201 and running on the processor 202. When the processor 202 executes the computer program, it implements each step of the chip quality inspection model construction method described in Embodiment 1.
[0132] In summary, the chip quality inspection model construction method and terminal provided by this invention trains the model using a training sample set, enabling the model to classify defects in the test sample set. Simultaneously, a test sample set with defect types not entirely identical to the training sample set is acquired. Training and test labels are constructed between the training and test sample sets, generating corresponding semantic feature text and semantic feature vectors. A mapping relationship is established between the image attribute feature vectors and semantic feature vectors, allowing the model trained on the training sample set to achieve knowledge transfer. This effectively identifies chip defects never seen in the training sample set and achieves automatic classification, achieving zero-learning and improving the accuracy of the detection model. Furthermore, after extracting the initial feature vector of the image using a convolutional neural network, this invention further optimizes and expands the initial feature vector using a generative model, extracting similar feature vectors from the initial feature vector, expanding the distribution of the sample dataset, and improving the learning efficiency of sample features during zero-learning. This effectively enhances the generalization and robustness of the model while reducing the computational load of the convolutional neural network.
[0133] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A method for constructing a chip quality inspection model, characterized in that, Including the following steps: Obtain a sample dataset, and obtain the corresponding semantic feature vector based on the sample dataset; The chip quality inspection model is obtained by extracting the attribute feature vectors of the sample dataset through convolutional neural networks and generative models, and mapping the attribute feature vectors to the semantic feature vectors through deep neural networks. The sample dataset includes a training sample set and a test sample set; the test sample set does not contain the same defect types as the training sample set. The specific steps of obtaining the sample dataset and obtaining the corresponding semantic feature vector based on the sample dataset are as follows: Sample images of the chip are acquired as training and testing sample sets, and the defect types in the training and testing sample sets are labeled respectively to obtain training labels and testing labels. Based on the training labels and test labels, construct corresponding semantic feature texts respectively, and based on the corresponding semantic feature texts, obtain the corresponding semantic feature vectors through word vector model mapping; The convolutional neural network includes a first convolutional layer, a second convolutional layer, a first sampling layer, and a second sampling layer; The extraction of attribute feature vectors from the sample dataset using convolutional neural networks and generative models specifically involves: The first feature vector of the sample dataset is extracted by the first convolutional layer, and the first feature vector is sampled by the first sampling layer to obtain the second feature vector; The third feature vector of the second feature vector is extracted by the second convolutional layer, and the third feature vector is reduced in dimensionality by the second sampling layer to obtain the initial feature vector. The initial feature vector is input into the generative model for optimization training to obtain similar feature vectors; The set of the initial feature vector and similar feature vectors is used as the attribute feature vector; The generative model is a VAE model; The step of inputting the initial feature vector into the generative model for optimization training to obtain similar feature vectors specifically involves: The initial feature vector is input into the encoder of the VAE model to obtain the Gaussian distribution function; The Gaussian distribution function is sampled to obtain sampled data; The sampled data is input into the decoder of the VAE model, and optimized and trained using an objective function to generate similar feature vectors; The objective function is: ； Where E represents expectation; a represents attribute feature vector; z represents latent variable; and p and q represent probability density distribution functions.
2. The method for constructing a chip quality inspection model according to claim 1, characterized in that, The specific steps of mapping the attribute feature vector to the semantic feature vector using a deep neural network to obtain the chip quality inspection model are as follows: The attribute feature vector is mapped to the semantic feature vector through the mapping function and loss function of the deep neural network to obtain the chip quality inspection model; The mapping function is: ； The loss function is: ； Where σ is the activation function of the deep neural network; W s For convolution kernel; A g b is the attribute feature vector; s S is the bias parameter matrix; S is the semantic feature vector; β is the hyperparameter. For 2-norm constraints, , where k is the number of semantic feature vectors.
3. A terminal for constructing a chip quality inspection model, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it performs the following steps: Obtain a sample dataset, and obtain the corresponding semantic feature vector based on the sample dataset; The chip quality inspection model is obtained by extracting the attribute feature vectors of the sample dataset through convolutional neural networks and generative models, and mapping the attribute feature vectors to the semantic feature vectors through deep neural networks. The sample dataset includes a training sample set and a test sample set; the test sample set does not contain the same defect types as the training sample set. The specific steps of obtaining the sample dataset and obtaining the corresponding semantic feature vector based on the sample dataset are as follows: Sample images of the chip are acquired as training and testing sample sets, and the defect types in the training and testing sample sets are labeled respectively to obtain training labels and testing labels. Based on the training labels and test labels, construct corresponding semantic feature texts respectively, and based on the corresponding semantic feature texts, obtain the corresponding semantic feature vectors through word vector model mapping; The convolutional neural network includes a first convolutional layer, a second convolutional layer, a first sampling layer, and a second sampling layer; The extraction of attribute feature vectors from the sample dataset using convolutional neural networks and generative models specifically involves: The first feature vector of the sample dataset is extracted by the first convolutional layer, and the first feature vector is sampled by the first sampling layer to obtain the second feature vector; The third feature vector of the second feature vector is extracted by the second convolutional layer, and the third feature vector is reduced in dimensionality by the second sampling layer to obtain the initial feature vector. The initial feature vector is input into the generative model for optimization training to obtain similar feature vectors; The set of the initial feature vector and similar feature vectors is used as the attribute feature vector; The generative model is a VAE model; The step of inputting the initial feature vector into the generative model for optimization training to obtain similar feature vectors specifically involves: The initial feature vector is input into the encoder of the VAE model to obtain the Gaussian distribution function; The Gaussian distribution function is sampled to obtain sampled data; The sampled data is input into the decoder of the VAE model, and optimized and trained using an objective function to generate similar feature vectors; The objective function is: ； Where E represents expectation; a represents attribute feature vector; z represents latent variable; and p and q represent probability density distribution functions.
4. The terminal for constructing a chip quality inspection model according to claim 3, characterized in that, The specific steps of mapping the attribute feature vector to the semantic feature vector using a deep neural network to obtain the chip quality inspection model are as follows: The attribute feature vector is mapped to the semantic feature vector through the mapping function and loss function of the deep neural network to obtain the chip quality inspection model; The mapping function is: ； The loss function is: ； Where σ is the activation function of the deep neural network; W s For convolution kernel; A g b is the attribute feature vector; s S is the bias parameter matrix; S is the semantic feature vector; β is the hyperparameter. It is subject to 2-norm constraints.