Memory circuit and method of operation thereof

Abstract

Embodiments of the present invention provide a memory circuit comprising: a first bit line and a second bit line coupled to a set of memory cells; a local input-output circuit comprising a first data line and a second data line; a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal; a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal; a switch circuit configured to pass a first input signal and a second input signal to the corresponding first data line and second data line during a write operation, and electrically isolate the first data line and the second data line from the first input signal and the second input signal during a read operation; and a first latch configured to be a sense amplifier during a read operation, and configured to be a write latch during a write operation. Embodiments of the present invention also provide a method of operating a memory circuit.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to memory circuits and methods of operating thereof. Background Technology

[0002] The semiconductor integrated circuit (IC) industry manufactures a wide variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured to store data. As ICs become smaller and more complex, the resistance of the wires in these digital devices changes, thus affecting the operating voltage of these digital devices and the overall IC performance. Summary of the Invention

[0003] An embodiment of the present invention provides a memory circuit, comprising: a set of memory cells; a first bit line and a second bit line coupled to the set of memory cells; a local input / output (LIO) circuit coupled to the set of memory cells via the first bit line and the second bit line, the LIO circuit comprising: a first data line and a second data line; a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal inversely phase to the first sense amplifier signal; a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal; and a switching circuit coupled to the first data line, the second data line, and the second control circuit, and configured to receive the third control signal, configured to... During a write operation of the memory cell set, a first input signal and a second input signal are transmitted to the corresponding first data line and second data line, and during a read operation of the memory cell set, the first data line and the second data line are electrically isolated from the first input signal and the second input signal; and a first latch circuit is coupled to the first data line, the second data line, the first control circuit, and the second control circuit, wherein during the read operation, in response to the third control signal and the second sense amplifier signal, the first latch circuit is configured as a sense amplifier, and during the write operation, in response to the third control signal and the first control signal, the first latch circuit is configured as a write latch.

[0004] Another embodiment of the present invention provides a memory circuit, comprising: a set of memory cells; a first bit line and a second bit line coupled to the set of memory cells; a first data line and a second data line; a first control circuit configured to receive a global sense amplifier signal and generate a first sense amplifier signal and a second sense amplifier signal inversely to the first sense amplifier signal; a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal; a third control circuit coupled between the first control circuit and the second control circuit and configured to generate the second control signal in response to the global sense amplifier signal and a fourth control signal; and a switching circuit coupled to the first data line, the second data line and the second control circuit, and configured to... The device is configured to receive the third control signal, transmit a first input signal and a second input signal to corresponding first data lines and second data lines during a write operation of the memory cell set, and electrically isolate the first data lines and second data lines from the first input signal and the second input signal during a read operation of the memory cell set; and a first latch circuit coupled to the first data line, the second data line, the first control circuit, and the second control circuit, wherein during the read operation, in response to the third control signal and the second sense amplifier signal, the first latch circuit is configured as a sense amplifier, and during the write operation, in response to the third control signal and the first control signal, the first latch circuit is configured as a write latch.

[0005] Another embodiment of the present invention provides a method for operating a memory circuit, the method comprising: generating an inverting sense amplifier signal and a sense amplifier signal inverted by the inverting sense amplifier signal via a first control circuit; generating a first control signal via a second control circuit in response to at least a second control signal or a third control signal; and reading a first memory cell via a local input / output (LIO) circuit in response to at least the sense amplifier signal, the second control signal, or a first clock signal, the first memory cell being coupled to the LIO circuit, wherein reading the first memory cell comprises: disabling a switching circuit in response to the third control signal; precharging a first data line and a second data line to a precharge voltage via a precharge / equalization circuit in response to a precharge control signal, and equalizing the voltages of the first data line and the second data line, the switching circuit being coupled to the first data line and the second data line; and in response to at least the third control signal, generating a first control signal via a second control circuit in response to the third control signal; and reading a first memory cell via a second control circuit in response to the third control signal, the method comprising: disabling a switching ... The control signal and the sense amplifier signal enable a first latch circuit configured as a sense amplifier, the first latch circuit being coupled to the first data line and the second data line; in response to at least the third control signal and the sense amplifier signal, the first data line signal and the second data line signal are sensed by the first latch circuit; in response to the sense amplifier signal and the inverting sense amplifier signal, the first data line signal is transmitted to the output node of the second latch circuit via a second latch circuit, the second latch circuit being coupled to the first data line and the first latch circuit; in response to the sense amplifier signal and the inverting sense amplifier signal, the first data line signal is latched by the second latch circuit; and a first value of data stored in the first memory cell is output via the LIO circuit, wherein the first data line signal corresponds to the first value of data stored in the first memory cell. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1 This is a block diagram of a memory circuit according to some embodiments.

[0008] Figure 2 This is a circuit diagram of a memory circuit according to some embodiments.

[0009] Figure 3 According to some embodiments Figure 1 and Figure 2 Circuit diagram of the memory cells that can be used in the system.

[0010] Figure 4 This is a circuit diagram of a memory circuit according to some embodiments.

[0011] Figure 5 This is a circuit diagram of a memory circuit according to some embodiments.

[0012] Figure 6 According to some embodiments, such as Figure 2 The memory circuit in Figure 4 The memory circuit in Figure 5 Memory circuits or Figure 7 Timing diagram of the waveform of the memory circuit in the image.

[0013] Figure 7 This is a circuit diagram of a memory circuit according to some embodiments.

[0014] Figure 8 This is a circuit diagram of a memory circuit according to some embodiments.

[0015] Figure 9 According to some embodiments, such as Figure 8 Timing diagram of the waveform of the memory circuit in the image.

[0016] Figures 10A-10B This is a flowchart of a method for operating circuits according to some embodiments. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples of various features for carrying out the subject matter of this invention. Specific examples of components, materials, values, steps, arrangements, etc., are described below to simplify this disclosure. Of course, these are examples and not intended to be limiting. Other components, materials, values, steps, arrangements, etc., are contemplated. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various embodiments of the invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0019] According to some embodiments, the memory circuit includes a set of memory cells, a first bit line, and a second bit line coupled to the set of memory cells. In some embodiments, the memory circuit also includes local input / output (LIO) circuitry coupled to the set of memory cells via the first bit line and the second bit line.

[0020] In some embodiments, the LIO circuit includes a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal inverted from the first sense amplifier signal.

[0021] In some embodiments, the LIO circuit further includes a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal.

[0022] In some embodiments, the LIO circuit further includes a switching circuit coupled to the first data line, the second data line, and the second control circuit. In some embodiments, the switching circuit is configured to receive a third control signal.

[0023] In some embodiments, the switching circuit is configured to transmit a first input signal and a second input signal to corresponding first data lines and second data lines during a write operation of the group of memory cells. In some embodiments, the switching circuit is configured to electrically isolate the first data lines and second data lines from the first input signal and second input signal during a read operation of the group of memory cells.

[0024] In some embodiments, the LIO circuit further includes a first latch circuit coupled to the first data line, the second data line, the first control circuit, and the second control circuit.

[0025] In some embodiments, the first latch circuit is configured as a sense amplifier that responds to a third control signal and a second sense amplifier signal during a read operation.

[0026] In some embodiments, the first latch circuit is configured as a write latch responsive to a third control signal and a first control signal during a write operation.

[0027] In some embodiments, the functions of both the sense amplifier and the write latch are demonstrated by a first latch circuit, and the memory circuit includes fewer transistors or logic devices compared to other methods in which the sense amplifier circuit and the write latch circuit are independent circuits.

[0028] In some embodiments, memory circuits that include fewer transistors or logic devices than other methods occupy less area and consume less power than other methods.

[0029] Figure 1 This is a block diagram of a memory circuit 100 according to some embodiments.

[0030] For the purpose of explanation, simplification is required. Figure 1 In some embodiments, the memory circuitry 100 includes, in addition to Figure 1 Various elements other than those described herein, or arranged in other ways to perform the operations discussed below.

[0031] The memory circuit 100 is an IC that includes memory partitions 102A-102D, a global control circuit 100GC, and a global input / output (GIO) circuit 100BL.

[0032] Each memory partition 102A-102D includes memory groups 110U and 110L adjacent to word line (WL) drive circuitry 110AC and local control circuitry 110LC. Each memory group 110U and 110L includes memory cell array 110AR and local input / output (LIO) circuitry 110BS.

[0033] Memory partitions (e.g., memory partitions 102A-102D) are part of memory circuitry 100, which includes memory devices ( Figure 1 (Not shown in the diagram) A subset of adjacent circuits and a subset of which are configured to selectively access the memory device during programming and read operations. Figure 1 In the illustrated embodiment, the memory circuit 100 comprises a total of four partitions. In some embodiments, the memory circuit 100 comprises a total of more or less than four partitions.

[0034] The GIO circuit 100BL is a circuit configured to control access to one or more electrical paths (e.g., bit lines) to each memory device in the corresponding memory group 110U or 110L of each memory partition 102A-102D, for example, by generating one or more bit line signals. In some embodiments, the GIO circuit 100BL includes global bit line driver circuitry. In some embodiments, the GIO circuit 100BL is coupled to each memory group 110U and 110L via corresponding global bit lines (not shown).

[0035] The global control circuit 100GC is a circuit configured to control some or all programming and reading operations on each memory partition 102A-102D, for example, by generating and / or outputting one or more control and / or enable signals.

[0036] In some embodiments, the global control circuit 100GC includes one or more analog circuits configured to connect to memory partitions 102A-102D, enabling data to be programmed in one or more memory devices, and / or using data received from one or more memory devices in the operation of one or more circuits. In some embodiments, the global control circuit 100GC includes one or more global address decoder or pre-decoder circuits configured to output one or more address signals to the WL driver circuit 110AC of each memory partition 102A-102D.

[0037] Each WL driver circuit 110AC is configured to generate a word line signal on the corresponding word line WL. In some embodiments, each WL driver circuit 110AC is configured to output the word line signal on the corresponding word line WL to adjacent memory groups 110U and 110L of the corresponding memory partitions 102A-102D.

[0038] Each local control circuit 110LC is an electronic circuit configured to receive one or more address signals. Each local control circuit 110LC is configured to generate a signal corresponding to a neighboring subset of a memory device identified by one or more address signals. In some embodiments, the neighboring subset of the memory device corresponds to a column of the memory device. In some embodiments, each local control circuit 110LC is configured to generate each signal as a complementary signal pair. In some embodiments, each local control circuit 110LC is configured to output a signal to a corresponding word line driver circuit within the adjacent WL driver circuit 110AC of the corresponding memory partition 102A-102D. In some embodiments, the local control circuit 110DC includes a group decoder circuit.

[0039] Each LIO circuit 110BS is configured to selectively access one or more bit lines (e.g., based on one or more BL control signals) of an adjacent subset of memory devices coupled to the corresponding memory cell array 110AR in response to the GIO circuit 100BL. Figure 2 (As shown). In some embodiments, adjacent subsets of the memory device correspond to rows of the memory device. In some embodiments, the LIO circuit 110BS includes a bit line selection circuit.

[0040] Each LIO circuit 110BS includes one or more circuits 114. In some embodiments, each circuit 114 includes circuitry configured as a sense amplifier circuit and a write latch circuit. For example, according to some embodiments, during a write operation, circuit 114 is a write latch circuit configured to write data to at least one memory cell 112 in a corresponding memory cell column in the corresponding memory cell array 110AR. For example, according to some embodiments, during a read operation, circuit 114 is a sense amplifier circuit configured to read data from at least one memory cell 112 in a corresponding memory cell column in the corresponding memory cell array 110AR. In some embodiments, each circuit 114 in the LIO circuit 110BS is coupled to a memory device 112 in a corresponding column in the memory cell array 110AR. In some embodiments, the GIO circuit 100BL includes one or more circuits 114 (not shown).

[0041] Each memory group 110U and 110L includes a corresponding memory cell array 110AR, including memory cells or memory devices 112, which are configured to be accessed by adjacent LIO circuits 110BS and adjacent WL driver circuits 110AC during programming and read operations.

[0042] Each memory cell array 110AR includes an array of memory devices 112 having N rows and M columns, where M and N are positive integers. Rows of cells in the memory cell array 102 are arranged along a first direction X. Columns of cells in the memory cell array 102 are arranged along a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is divided into an upper region and a lower region (not shown). In some embodiments, each column of memory devices 112 in the memory cell array 110AR is coupled to a corresponding circuit 114 in the LIO circuit 110BS.

[0043] Storage device 112 is shown in memory groups 110U and 110L of memory partition 102A. For ease of illustration, storage device 112 is not shown in memory groups 110U and 110L of memory partitions 102B, 102C and 102D.

[0044] Storage device 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logical states. At least one logical state of storage device 112 can be programmed in a write operation and detected in a read operation. In some embodiments, the logical state corresponds to the voltage level of a charge stored in a given storage device 112. In some embodiments, the logical state corresponds to a physical characteristic of a component of a given storage device 112, such as voltage, current, resistance, or magnetic orientation.

[0045] In some embodiments, memory device 112 includes one or more single-port (SP) static random access memory (SRAM) cells. In some embodiments, memory device 112 includes one or more dual-port (DP) SRAM cells. In some embodiments, memory device 112 includes one or more multi-port SRAM cells. Different types of memory cells in memory device 112 are within the scope of this disclosure. In some embodiments, memory device 112 includes one or more dynamic random access memory (DRAM) cells. In some embodiments, memory device 112 includes one or more once-programmable (OTP) memory devices, such as electronic fuse or antifuse devices, flash memory devices, random access memory (RAM) devices, resistive RAM devices, ferroelectric RAM devices, magnetoresistive RAM devices, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, etc. In some embodiments, memory device 112 is an OTP memory device including one or more OTP memory cells.

[0046] Other configurations of the memory circuit 100 are within the scope of this disclosure.

[0047] Figure 2 This is a circuit diagram of a memory circuit 200 according to some embodiments.

[0048] Memory circuit 200 is Figure 1 The embodiments are of a column of memory cells in the memory cell array 110AR or circuit 114, and therefore similar detailed descriptions are omitted. For example, a non-limiting example is described for memory circuit 200, wherein the memory cell array 202 of memory circuit 200 is... Figure 1 An embodiment of a column of memory cells in the memory cell array 110AR, and the sense amplifier circuit / write circuit 204 of the memory circuit 200 corresponds to Figure 1 The circuit 114 is described in detail below, therefore a similar detailed description is omitted. In some embodiments, the sense amplifier circuit / write circuit 204 of the memory circuit 200 can be used in a manner similar to that of circuit 114 of the LIO circuit 110BS. Figure 1 The GIO circuit 100BL is used in the example, so a similar detailed description is omitted.

[0049] The memory circuit 200 includes a memory cell array 202 coupled to the sense amplifier circuit / write circuit 204 via bit line BL and anti-phase line BLB.

[0050] Memory cell array 202 includes a memory cell array MCB having N rows and one column, where N is a positive integer. The column is shown as a non-limiting example. Other numbers of columns in the memory cell array 202 are within the scope of this disclosure. In some embodiments, Figure 1 Each column of memory cells 112 in the memory cell array 102 is coupled to the corresponding sense amplifier circuit / write circuit 204.

[0051] The sense amplifier circuit / write circuit 204 is a circuit configured as both a sense amplifier circuit and a write latch circuit. For example, according to some embodiments, during a write operation, the sense amplifier circuit / write circuit 204 is a write latch circuit configured to receive input data (e.g., Din and DinB) on a data input line and to write the data (e.g., Din or DinB) to at least one memory cell MCB in column 0 of the memory cell array 202.

[0052] For example, according to some embodiments, during a read operation, the sense amplifier circuit / write circuit 204 is a sense amplifier circuit configured to sense or read data from at least one memory cell MCB in column 0 of the memory cell array 202, and configured to output a data signal Q. In some embodiments, the data signal Q corresponds to data read from at least one memory cell MCB in column 0 of the memory cell array 202. In some embodiments, the data signal Q corresponds to data stored in at least one memory cell MCB in column 0 of the memory cell array 202.

[0053] In some embodiments, the sense amplifier circuit / write circuit 204 is configured to demonstrate the functionality of both the sense amplifier circuit and the write latch circuit, and the sense amplifier circuit / write circuit 204 includes fewer transistors or logic devices compared to other methods in which the sense amplifier circuit and the write latch circuit are independent circuits.

[0054] In some embodiments, the sense amplifier circuit / write circuit 204 includes fewer transistors or logic devices than other methods, and occupies less area than other methods.

[0055] In some embodiments, by including fewer transistors or logic devices than other methods, the sense amplifier circuit / write circuit 204 consumes less active power than other methods because fewer transistors or logic devices in the sense amplifier circuit / write circuit 204 switch between logic high and logic low states and vice versa.

[0056] In some embodiments, by including fewer transistors or logic devices than other methods, the sense amplifier circuit / write circuit 204 has less static leakage than other methods because fewer transistors or logic devices in the sense amplifier circuit / write circuit 204 results in a lower total gate number than other methods.

[0057] Other configurations of the memory circuitry 200 are within the scope of this disclosure.

[0058] memory unit

[0059] Figure 3 According to some embodiments Figure 1 and Figure 2 The circuit diagram of the memory unit 300 that can be used in the memory.

[0060] Memory unit 300 can be used as Figure 1 At least one or more memory cells MCB in the memory cell array 110AR Figure 1 Storage device 112, Figure 2 memory cell MCB or Figure 2 The memory cell array 202.

[0061] Memory cell 300 is a six-transistor (6T) single-port (SP) SRAM memory cell for illustration. In some embodiments, memory cell 300 employs multiple transistors instead of six transistors. Other types of memory are within the scope of various embodiments.

[0062] Memory cell 300 includes two P-type metal-oxide-semiconductor (PMOS) transistors P1 and P2, and four N-type metal-oxide-semiconductor (NMOS) transistors N1, N2, N3, and N4. Transistors P1, P2, N1, and N2 form a cross-latch or a pair of cross-coupled inverters. For example, PMOS transistor P1 and NMOS transistor N1 form a first inverter, while PMOS transistor P2 and NMOS transistor N2 form a second inverter.

[0063] The source terminal of each of PMOS transistors P1 and P2 is configured as voltage supply node NODE_1. Each voltage supply node NODE_1 is coupled to a first voltage source VDDI. The drain terminal of PMOS transistor P1 is coupled to the drain terminal of NMOS transistor N1, the gate terminal of PMOS transistor P2, the gate terminal of NMOS transistor N2, and the source terminal of NMOS transistor N3, and is configured as storage node ND.

[0064] The drain terminal of PMOS transistor P2 is coupled to the drain terminal of NMOS transistor N2, the gate terminal of PMOS transistor P1, the gate terminal of NMOS transistor N1, and the source terminal of NMOS transistor N4, and is configured as a storage node NDB. The source terminals of each NMOS transistor N1 and N2 are configured as a reference supply voltage node (not shown) with a reference supply voltage VSS. The source terminal of each of NMOS transistors N1 and N2 is also coupled to the reference voltage source VSS.

[0065] Word line WL is coupled to the gate terminal of each of NMOS transistors N3 and N4. Word line WL is also called the write control line because NMOS transistors N3 and N4 are configured to be controlled by signals on word line WL to transfer data between bit lines BL, BLB and corresponding nodes ND, NDB.

[0066] The drain terminal of NMOS transistor N3 is coupled to bit line BL. The drain terminal of NMOS transistor N4 is coupled to bit line BLB. Bit lines BL and BLB are configured as data inputs and outputs of memory cell 300. In some embodiments, during a write operation, a logic value is applied to bit line BL and an opposite logic value is applied to the other bit line BLB, enabling the logic value on the bit line to be written to memory cell 300. Each of bit lines BL and BLB is referred to as a data line because the data carried on bit lines BL and BLB is written to and read from the corresponding nodes ND and NDB.

[0067] The word line WL corresponds to Figure 1 One or more word lines WL. Bit line BL corresponds to Figure 2 One or more bit lines BL in the middle. The anti-phase line BLB corresponds to Figure 2 One or more anti-phase lines in the BLB.

[0068] Other configurations of the memory unit 300 are within the scope of this disclosure.

[0069] Memory circuit:

[0070] Figure 4 This is a circuit diagram of a memory circuit 400 according to some embodiments.

[0071] Memory circuit 400 is Figure 2 An embodiment of the sense amplifier circuit / write circuit 204 is provided, therefore a similar detailed description is omitted. Figure 7 The memory circuit 700 (described below) and Figure 8 The memory circuit 800 described below is Figure 2 An embodiment of the sense amplifier circuit / write circuit 204 is provided, therefore a similar detailed description is omitted.

[0072] The memory circuit 400 includes a control signal generation circuit 402 coupled to latch circuits 410 and 440. For ease of illustration, the control signal generation circuit 402 is not shown as coupled to latch circuits 410 and 440.

[0073] Control signal generation circuit 402 is configured to control latch circuit 410 via sense amplifier enable signal SAE. Control signal generation circuit 402 is configured to control latch circuit 440 via sense amplifier enable signal SAE and inverted sense amplifier enable signal SAEB. Control signal generation circuit 402 is configured to generate inverted sense amplifier enable signal SAEB in response to global sense amplifier enable signal GLB_SAE. Control signal generation circuit 402 is also configured to generate sense amplifier enable signal SAE in response to inverted sense amplifier enable signal SAEB. In some embodiments, sense amplifier enable signal SAE is inverted from inverted sense amplifier enable signal SAEB. In some embodiments, control signal generation circuit 402 is coupled to... Figure 1 The GIO circuit 100BL in the middle is configured to be from Figure 1 The GIO circuit 100BL in the middle receives the global sense amplifier enable signal GLB_SAE.

[0074] The control signal generation circuit 402 includes inverter I1 and inverter I2.

[0075] Inverter I1 is configured to generate an inverted sense amplifier enable signal SAEB in response to a global sense amplifier enable signal GLB_SAE. In some embodiments, the global sense amplifier enable signal GLB_SAE is inverted from the inverted sense amplifier enable signal SAEB. The input terminal of inverter I1 is configured to receive the global sense amplifier enable signal GLB_SAE. In some embodiments, the input terminal of inverter I1 is coupled to... Figure 1 The GIO circuit 100BL is used in this circuit. The output terminal of inverter I1 is coupled to the input terminal of inverter I2 and is configured to output the inverting sense amplifier enable signal SAEB. The output terminal of inverter I1 is further coupled to latch circuit 440.

[0076] Inverter I2 is configured to generate a sense amplifier enable signal SAE in response to an inverting sense amplifier enable signal SAEB. The input terminal of inverter I2 is coupled to the output terminal of inverter I1 and is configured to receive the inverting sense amplifier enable signal SAEB. The output terminal of inverter I2 is coupled to latch circuit 410 and latch circuit 440. The output terminal of inverter I2 is configured to output the sense amplifier enable signal SAE.

[0077] Other configurations, types, or quantities of circuit elements in the control signal generation circuit 402 are within the scope of this disclosure.

[0078] The memory circuit 400 also includes a control signal generation circuit 404 coupled to the switching circuit 406 and the latch circuit 410. For ease of illustration, the control signal generation circuit 404 is not shown as being coupled to the switching circuit 406 and the latch circuit 410.

[0079] Control signal generation circuit 404 is configured to control switching circuit 406 via control signal DCKB. Control signal generation circuit 404 is configured to control latch circuit 410 via control signal DCK and control signal DCKB. Control signal generation circuit 404 is configured to generate control signal DCKB in response to global control signal GLB_DCK. In some embodiments, control signal GLB_DCK is a clock signal. Control signal generation circuit 404 is also configured to generate control signal DCK based on control signal DCKB and control signal IWEB. In some embodiments, control signal IWEB is an inverted write enable signal configured to logic 1 during a read operation of one or more memory cells coupled to memory circuit 400. In some embodiments, control signal IWEB is an inverted write enable signal configured to logic 0 during a write operation of one or more memory cells coupled to memory circuit 400. In some embodiments, control signal IWEB is generated by external circuitry (not shown). In some embodiments, control signal generation circuit 404 is coupled to... Figure 1 The GIO circuit 100BL in the middle is configured to be from Figure 1 The GIO circuit 100BL in the middle receives the global control signal GLB_DCK.

[0080] The control signal generation circuit 404 includes an inverter I3 and a NOR logic gate NOR1.

[0081] Inverter I3 is configured to generate a control signal DCKB in response to a global control signal GLB_DCK. In some embodiments, the control signal DCKB is inverted compared to the global control signal GLB_DCK. The input terminal of inverter I3 is configured to receive the global control signal GLB_DCK. In some embodiments, the input terminal of inverter I3 is coupled to... Figure 1 The GIO circuit 100BL is used in this circuit. The output terminal of inverter I3 is coupled to the first input terminal of NOR logic gate NOR1 and is configured to output control signal DCKB. The output terminal of inverter I3 is further coupled to switching circuit 406 and latch circuit 410.

[0082] The first input terminal of the NOR logic gate NOR1 is configured to receive the control signal DCKB. The second input terminal of the NOR logic gate NOR1 is configured to receive the control signal IWEB. In some embodiments, the second input terminal of the NOR logic gate NOR1 is directly coupled to the source (not shown) of the control signal IWEB. The output terminal of the NOR logic gate NOR1 is configured to output the control signal DCK. The NOR logic gate NOR1 is configured to generate the control signal DCK based on the control signal DCKB and the control signal IWEB. The output terminal of the NOR logic gate NOR1 is coupled to the latch circuit 410.

[0083] Other configurations, types, or quantities of circuit elements in the control signal generation circuit 404 are within the scope of this disclosure.

[0084] The memory circuit 400 also includes a switching circuit 406. The switching circuit 406 is configured to receive input signals Din and DinB. The switching circuit 406 is configured to transmit the input signals Din and DinB to the latch circuit 410 via the data line DL and the inverted data line DLB, respectively.

[0085] Switching circuit 406 is enabled or disabled in response to control signal DCKB. For example, according to some embodiments, in one or more memory cells coupled to memory circuit 400 (e.g., Figure 2 During a write operation of the memory cell MCB in the memory, the switching circuit 406 is enabled by the control signal DCKB, and the switching circuit 406 is configured to couple the data line DL and the inverting data line DLB to the input circuit (e.g., Figure 5 The input circuit 504 in the memory circuit. For example, according to some embodiments, in one or more memory cells coupled to the memory circuit 400 (e.g., Figure 2 During a read operation of the memory cell MCB in the memory, the switching circuit 406 is disabled by the control signal DCKB, and the switching circuit 406 is configured to connect the data line DL and the inverting data line DLB to the input circuit (e.g., Figure 5The input circuit 504 in the middle is decoupled.

[0086] In some embodiments, the switching circuit 406 is configured to transmit input signals Din and DinB to the corresponding data lines DL and DLB during a write operation of one or more memory cells. In some embodiments, the switching circuit is configured to electrically isolate the data lines DL and DLB from the corresponding input signals Din and DinB during a read operation of one or more memory cells.

[0087] In some embodiments, the latch circuit 410 can be configured as a sense amplifier during a read operation by electrically isolating the data lines DL and DLB from the corresponding input signals Din and DinB during a read operation of one or more memory cells. In some embodiments, the latch circuit 410 is configured as a write latch during a write operation by configuring the switching circuit 406 to transmit the input signals Din and DinB to the corresponding data lines DL and DLB during a write operation of one or more memory cells.

[0088] The switching circuit 406 includes NMOS transistors MN5 and MN6.

[0089] The source of NMOS transistor MN5 is configured to receive the data signal Din. The source of NMOS transistor MN5 is coupled to the source of the data signal Din (e.g., Figure 5 The input circuit 504 in the circuit is used. The gate of NMOS transistor MN5 is configured to receive the control signal DCKB and is coupled to the output terminal of inverter I3 and the gate of NMOS transistor MN6. The drain of NMOS transistor MN5 is coupled to at least the inverting data line DLB and node n1.

[0090] The source of NMOS transistor MN6 is configured to receive the data signal DinB. The source of NMOS transistor MN6 is coupled to the source of the data signal DinB (e.g., Figure 5 The input circuit 504 in the circuit is used. The gate of NMOS transistor MN6 is configured to receive the control signal DCKB and is coupled to the output terminal of inverter I3 and the gate of NMOS transistor MN5. The drain of NMOS transistor MN6 is coupled to at least the data line DL and node n2.

[0091] Other configurations, the number of transistors, or the type of transistors in the switching circuit 406 are within the scope of this disclosure. For example, in some embodiments, the source and drain of NMOS transistor MN5 are switched, and the source and drain of NMOS transistor MN6 are switched. For example, in some embodiments, NMOS transistors MN5 and MN6 may be replaced with corresponding transmission gates.

[0092] The memory circuit 400 also includes a latch circuit 410. The latch circuit 410 is coupled to a control signal generation circuit 402, a control signal generation circuit 404, a switching circuit 406, a precharge and equalization circuit 420, an output circuit 430, a latch circuit 440, a PMOS transistor MP11, and an NMOS transistor MN11. The latch circuit 410 is configured to receive at least one of a sense amplifier enable signal SAE, a control signal DCK, or a control signal DCKB. The latch circuit 410 is enabled or disabled in response to at least one of the sense amplifier enable signal SAE, the control signal DCK, or the control signal DCKB.

[0093] The latch circuit 410 is coupled to the inverting data line DLB at least at node n1 and to the data line DL at node n2. The latch circuit 410 is configured to latch the inverted data line signal on the inverted data line DLB at node n1 and to latch the data line signal on the data line DL at node n2.

[0094] At least latch circuit 410 is configured as a sense amplifier circuit and a write latch circuit. For example, in some embodiments, during a read operation, latch circuit 410 and latch circuit 440 are configured to act as a sense amplifier, which is configured to sense or read one or more memory cells (e.g., ...) stored in memory circuit 400 via a bit line split between bit line BL and anti-phase line BLB. Figure 2 The data in the memory cell (MCB) in the system. In some embodiments, during a read operation, at least latch circuit 410 is configured to act as part of the sense amplifier in response to the sense amplifier enable signal SAE and the control signal DCKB.

[0095] For example, in some embodiments, during a write operation, latch circuit 410, switching circuit 406, and output circuit 430 are write latch circuits configured to receive input data (e.g., Din and DinB) on data input lines, latch the input data (e.g., Din and DinB) on data line DL and inverting data line DLB, and be configured to write data (e.g., Din or DinB) to one or more memory cells coupled to memory circuit 400 (e.g., ...). Figure 2 (Memory cell MCB in the memory). In some embodiments, during a read operation, at least latch circuit 410 is configured to function as part of a write latch circuit in response to control signals DCK and DCKB.

[0096] The latch circuit 410 includes PMOS transistors MP1, MP2, and MP3, and NMOS transistors MN1, MN2, MN3, and MN4. Transistors MP1, MP2, MN1, and MN2 form a cross-latch or a pair of cross-coupled inverters. For example, PMOS transistor MP1 and NMOS transistor MN1 form a first inverter (not shown), while PMOS transistor MP2 and NMOS transistor MN2 form a second inverter (not shown).

[0097] The drains of PMOS transistor MP1, NMOS transistor MN1, PMOS transistor MP2, and NMOS transistor MN2 are coupled together at node n1. Node n1 is coupled to the inverting data line DLB. In some embodiments, node n1 is configured as a storage node. The drains of PMOS transistor MP1 and NMOS transistor MN1, and the gates of PMOS transistor MP2 and NMOS transistor MN2 are connected to the inverting data line DLB.

[0098] The sources of PMOS transistors MP1, MP2, and MP3 are coupled together at node n3. The source of PMOS transistor MP3 is configured as a power supply voltage node (not shown) and coupled to the power supply voltage VDDM. The sources of PMOS transistor MP3, MP5, and MP6 are coupled together and further coupled to the power supply voltage VDDM. The gate of PMOS transistor MP3 is configured to receive the control signal DCKB. The gate of PMOS transistor MP3 is coupled to the output terminal of inverter I3. In some embodiments, PMOS transistor MP3 is referred to as a "head switch".

[0099] The drains of PMOS transistor MP2 and NMOS transistor MN2, and the gates of PMOS transistor MP1 and NMOS transistor MN1 are coupled together at node n2. Node n2 is coupled to the data line DL. In some embodiments, node n2 is configured as a storage node. The drains of each of PMOS transistor MP2 and NMOS transistor MN2, and the gates of each of PMOS transistor MP1 and NMOS transistor MN1, are coupled to the data line DL.

[0100] The drains of NMOS transistors MN3 and MN4, the source of NMOS transistor MN1, and the source of NMOS transistor MN2 are coupled together at node n4. The source of NMOS transistor MN3 is configured as a reference power supply voltage node (not shown) with a reference power supply voltage VSS. The source of NMOS transistor MN4 is configured as a reference power supply voltage node (not shown) with a reference power supply voltage VSS. In some embodiments, the sources of NMOS transistors MN3 and MN4 are coupled together.

[0101] The gate of NMOS transistor MN3 is configured to receive the sense amplifier enable signal SAE. The gate of NMOS transistor MN3 is coupled to the output terminal of inverter I2. The gate of NMOS transistor MN4 is configured to receive the control signal DCK. The gate of NMOS transistor MN4 is coupled to the output terminal of NOR logic gate NOR1. In some embodiments, NMOS transistor MN3 is referred to as the "first pin switch" and NMOS transistor MN4 is referred to as the "second pin switch".

[0102] In some embodiments, when the control signal DCKB is a low logic value and the sense amplifier enable signal SAE is a high logic value, the latch circuit 410 is enabled and configured to function as a sense amplifier. For example, when the control signal DCKB is applied to the PMOS transistor MP3 at a low logic value, the PMOS transistor MP3 is turned on, pulling node n3 to the voltage level of the power supply voltage VDDM. Similarly, for example, when the sense amplifier enable signal SAE is applied to the NMOS transistor MN3 at a high logic value, the NMOS transistor MN3 is turned on, pulling node n4 to the voltage level of the reference power supply voltage VSS. As a result, the latch circuit 410 is enabled and configured to amplify the voltage levels of the data line DL and the inverting data line DLB, and is configured to output read data from the memory cell to the latch circuit 440.

[0103] In some embodiments, when the control signal DCKB is a low logic value and the control signal DCK is a high logic value, the latch circuit 410 is enabled and configured to function as a write latch circuit. For example, when the control signal DCKB is applied to the PMOS transistor MP3 at a low logic value, the PMOS transistor MP3 is turned on, pulling node n3 to the voltage level of the supply voltage VDDM. Similarly, for example, when the control signal DCK is applied to the NMOS transistor MN4 at a high logic value, the NMOS transistor MN4 is turned on, pulling node n4 to the voltage level of the reference supply voltage VSS. As a result, the latch circuit 410 is enabled and configured to output write data (e.g., Din or DinB) to the output circuit 430.

[0104] Other configurations, number of transistors, or types of transistors in latch circuit 410 are within the scope of this disclosure.

[0105] The memory circuit 400 also includes a pre-charge and equalization circuit 420.

[0106] The pre-charge and equalization circuit 420 is coupled to the data line DL, the inverting data line DLB, the switching circuit 406, the latch circuit 410, the output circuit 430, the latch circuit 440, the PMOS transistor MP11, and the NMOS transistor MN11.

[0107] The precharge and equalization circuit 420 is configured to precharge and equalize the data line DL and the inverting data line DLB to voltage VDL in response to the signal DLEQB. In some embodiments, the precharge and equalization circuit 420 is configured to precharge and equalize the data line DL and the inverting data line DLB to voltage VDL in one or more memory cells coupled to the memory circuit 400 (e.g., Figure 2 Before a read operation of a memory cell (MCB) in a non-NAP design, the data line DL and the inverting data line DLB are precharged and equalized to voltage VDL. In some embodiments, the precharge and equalization circuit 420 is configured to precharge and equalize the data line DL and the inverting data line DLB (or the bit line BL and the inverting line BLB) to voltage VDL before the word line WL provides access or before the memory nodes ND and NDB are coupled to the corresponding bit lines and bit lines BLB in the NAP design. In some embodiments, the precharge and equalization circuit 420 is configured to precharge and equalize the data line DL and the inverting data line DLB (or the bit line BL and the inverting line BLB) to voltage VDL after the word line WL provides access or after the memory nodes ND and NDB are coupled to the corresponding bit lines and bit lines BLB in the non-NAP design. In some embodiments, voltage VDL is equal to the power supply voltage VDDM. In some embodiments, voltage VDL is equal to the reference power supply voltage VSS. In some embodiments, voltage VDL is equal to power supply voltage VDDM / 2.

[0108] The pre-charge and equalization circuit 420 includes PMOS transistors MP5, MP6, and MP4. PMOS transistors MP5 and MP6 are pre-charge circuits. PMOS transistors MP5 and MP6 are configured to pre-charge the data line DL and the inverting data line DLB to voltage VDL in response to the signal DLEQB. PMOS transistor MP4 is an equalization circuit. PMOS transistor MP4 is configured to make the voltage of the data line DL and the inverting data line DLB equal to voltage VDL in response to the signal DLEQB. The gates of PMOS transistors MP5, MP6, and MP4 are coupled together and configured to receive the signal DLEQB. In some embodiments, the signal DLEQB is at least a pre-charge signal or an equalization signal.

[0109] The sources of PMOS transistors MP6 and MP5 are coupled to the data line DL and the inverted data line DLB, respectively. The drains of PMOS transistors MP5 and MP6 are coupled together and configured to receive the power supply voltage VDDM. For example, when a low logic value is applied to the signal EQB, transistors MP5 and MP6 turn on, pulling the corresponding data line DL and the inverted data line DLB to the power supply voltage VDDM. As a result, the data line DL and the inverted data line DLB are pre-charged to the power supply voltage VDDM.

[0110] PMOS transistor MP4 is connected between the data line DL and the inverting data line DLB. The source of PMOS transistor MP4 is coupled to the inverting data line DLB. The drain of PMOS transistor MP4 is coupled to the data line DL. For example, when a low logic value is applied to the signal EQB, transistor MP4 turns on and couples the inverting data line DLB to the data line DL. As a result, the voltage on the data line DL and the inverting data line DLB is equal to the supply voltage VDDM. In some embodiments, the drain and source of each of PMOS transistors MP5, MP6, and MP4 can be interchanged.

[0111] Other configurations, the number of transistors, or the type of transistors in the pre-charge and equalization circuit 420 are within the scope of this disclosure. For example, other circuitry and / or other types of transistors, such as NMOS transistors, or other numbers of transistors, for pre-charging and / or equalizing the data line DL and the inverting data line DLB are all within the scope of various embodiments. Other values ​​for the voltage VDL are within the scope of various embodiments.

[0112] The memory circuit 400 also includes an output circuit 430. The output circuit 430 is coupled to a data line DL, an inverting data line DLB, a precharge and equalization circuit 420, a switching circuit 406, a latch circuit 410, a latch circuit 440, a PMOS transistor MP11, and an NMOS transistor MN11. The output circuit 430 is further coupled to one or more memory cells (not shown) and is configured to control write operations to one or more memory cells.

[0113] The output circuit 430 includes NOR logic gates NOR2 and NOR logic gates NOR3 and NMOS transistors MN12 and MN13.

[0114] NOR gate NOR2 is configured to generate a signal WC. Signal WC controls NMOS transistor MN12. NOR gate NOR2 has a first input terminal coupled to at least the data line DL, and a second input terminal configured to receive a control signal WCLK. In some embodiments, the control signal WCLK is a clock signal. In some embodiments, for a write operation, the control signal WCLK is logic low. In some embodiments, for a read operation, the control signal WCLK is logic high. The output terminal of NOR gate NOR2 is coupled to the gate of NMOS transistor MN12. The output terminal of NOR gate NOR2 is configured to output the signal WC to NMOS transistor MN12.

[0115] NOR gate NOR3 is configured to generate signal WT. Signal WT controls NMOS transistor MN13. The first input terminal of NOR gate NOR3 is coupled to at least the inverting data line DLB, and the second input terminal is configured to receive the control signal WCLK. The output terminal of NOR gate NOR3 is coupled to the gate of NMOS transistor MN13. The output terminal of NOR gate NOR3 is configured to output signal WT to NMOS transistor MN13.

[0116] The NMOS transistor MN12 is coupled to the NOR logic gate NOR12 and the bit line BL.

[0117] The gate of NMOS transistor MN12 is configured to receive signal WC. The gate of NMOS transistor MN12 is coupled to the output terminal of NOR logic gate NOR2. The source of NMOS transistor MN12 is coupled to a reference voltage source VSS. The drain of NMOS transistor MN12 is coupled to bit line BL. In some embodiments, bit line BL and anti-phase line BLB are coupled to one or more memory cells (not shown).

[0118] The NMOS transistor MN13 is coupled to the NOR logic gate NOR3 and the anti-phase line BLB.

[0119] The gate of NMOS transistor MN13 is configured to receive signal WT. The gate of NMOS transistor MN13 is coupled to the output terminal of NOR logic gate NOR3. The source of NMOS transistor MN13 is coupled to the reference voltage source VSS. The drain of NMOS transistor MN13 is coupled to the anti-phase line BLB.

[0120] Other configurations, quantities, or types of transistors in the output circuit 430 are within the scope of this disclosure.

[0121] The memory circuit 400 also includes a latch circuit 440.

[0122] The latch circuit 440 is coupled to the data line DL, the control signal generation circuit 402, the switching circuit 406, the pre-charge and equalization circuit 420, and the output circuit 430.

[0123] The latch circuit 440 is configured to receive at least one of a sense amplifier enable signal SAE, an inverting sense amplifier enable signal SAEB, and a data line signal of the data line DL. The latch circuit 440 is enabled or disabled in response to at least one of the sense amplifier enable signal SAE or the inverting sense amplifier enable signal SAEB.

[0124] In some embodiments, during a read operation, latch circuit 440 is configured to latch a data line signal on data line DL at node n2 in response to at least one of a sense amplifier enable signal SAE or an inverting sense amplifier enable signal SAEB. Latch circuit 440 includes an output node (e.g., node NO) configured to output signal Q.

[0125] The latch circuit 440 includes PMOS transistors MP7, MP8, MP9 and MP10, NMOS transistors MN7, MN8, MN9 and MN10, inverter I4 and inverter I5.

[0126] The source terminal of PMOS transistor MP7 is coupled to the voltage source VDDM. The gate of PMOS transistor MP7, the gate of NMOS transistor MN8, and the data line DL are coupled together. The gates of both PMOS transistor MP7 and NMOS transistor MN8 are configured to receive the data line signal on data line DL. The drain of PMOS transistor MP7 is coupled to the source of PMOS transistor MP8.

[0127] The gate of PMOS transistor MP8 is coupled to the output terminal of inverter I1. The gate of PMOS transistor MP8 is configured to receive the inverting sense amplifier enable signal SAEB.

[0128] The drains of PMOS transistor MP8, NMOS transistor MN7, PMOS transistor MP10, and NMOS transistor MN9, as well as the input terminals of inverter I4 and inverter I5, are coupled together. In some embodiments, the drain of PMOS transistor MP8 or NMOS transistor MN7 is configured to output an inverted output signal QB. In some embodiments, the drain of PMOS transistor MP10 or NMOS transistor MN9 is configured to output an inverted output signal QB.

[0129] The gate of NMOS transistor MN7 is coupled to the output terminal of inverter I2. The gate of NMOS transistor MN7 is configured to receive the sense amplifier enable signal SAE.

[0130] The source of NMOS transistor MN7 is coupled to the drain of NMOS transistor MN8. The source of NMOS transistor MN8 is coupled to the reference voltage source VSS.

[0131] In some embodiments, when PMOS transistor MP8 and NMOS transistor MN7 are enabled or turned on, PMOS transistor MP7 and NMOS transistor MN8 form an inverter (not shown).

[0132] The source of PMOS transistor MP9 is coupled to voltage source VDDM. The gates of PMOS transistor MP9, NMOS transistor MN10, and the output terminal of inverter I5 are coupled together. Each of the gates of PMOS transistor MP9 and NMOS transistor MN10 is configured to receive an output signal Q1 from the output terminal of inverter I5. In some embodiments, the output signal Q1 corresponds to a feedback signal fed back to the gates of PMOS transistor MP9 and NMOS transistor MN10. In some embodiments, signal Q1 is inverted with and vice versa of the inverted output signal QB. The drain of PMOS transistor MP9 is coupled to the source of PMOS transistor MP10.

[0133] The gate of PMOS transistor MP10 is coupled to the output terminal of inverter I2 and the gate of NMOS transistor MN7. The gate of PMOS transistor MP10 is configured to receive the sense amplifier enable signal SAE.

[0134] The gate of NMOS transistor MN9 is coupled to the output terminal of inverter I1 and the gate of PMOS transistor MP8. The gate of NMOS transistor MN9 is configured to receive the inverting sense amplifier enable signal SAEB.

[0135] The source of NMOS transistor MN9 is coupled to the drain of NMOS transistor MN10. The source of NMOS transistor MN10 is coupled to the reference voltage source VSS.

[0136] In some embodiments, when PMOS transistor MP10 and NMOS transistor MN9 are enabled or turned on, PMOS transistor MP9 and NMOS transistor MN10 form an inverter (not shown).

[0137] Inverter I4 is configured to generate an output signal Q in response to an inverted output signal QB. The input terminals of inverter I4 are configured to receive the inverted output signal QB. The output terminals of inverter I4 are configured to output the output signal Q. In some embodiments, the inverted output signal QB is inverted compared to signal Q, and vice versa.

[0138] Inverter I5 is configured to generate output signal Q1 in response to inverted output signal QB. The input terminals of inverter I5 are configured to receive the inverted output signal QB. The output terminals of inverter I5 are configured to output output signal Q1.

[0139] Other configurations, number of transistors, or types of transistors in latch circuit 440 are within the scope of this disclosure.

[0140] The memory circuit 400 also includes an NMOS transistor MN11 and a PMOS transistor MP11. The source of the PMOS transistor MP11 is coupled to a voltage source VDDM. The drain of the PMOS transistor MP11 is floating. The source of the NMOS transistor MN11 is coupled to a reference voltage source VSS. The drain of the NMOS transistor MN11 is floating.

[0141] The gate of PMOS transistor MP11, the gate of NMOS transistor MN11, the source of PMOS transistor MP4, the drain of PMOS transistor MP5, the inverting data line DLB, node n1, the drain of NMOS transistor MN5, the drain of PMOS transistor MP1, the drain of NMOS transistor MN1, the gate of PMOS transistor MP2, the gate of NMOS transistor MN2, and the first input terminal of NOR logic gate NOR3 are coupled together.

[0142] The gate of PMOS transistor MP7, the gate of NMOS transistor MN8, the drain of PMOS transistor MP4, the drain of PMOS transistor MP6, the data line DL, node n2, the drain of NMOS transistor MN6, the drain of PMOS transistor MP2, the drain of NMOS transistor MN2, the gate of PMOS transistor MP1, the gate of NMOS transistor MN1, and the second input terminal of NOR logic gate NOR2 are coupled together.

[0143] Other configurations, number of transistors, or types of transistors in the PMOS transistor MP11 or NMOS transistor MN11 are within the scope of this disclosure.

[0144] In some embodiments, memory circuitry 400 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 100 or 200.

[0145] Other configurations of the memory circuit 400 are within the scope of this disclosure.

[0146] Figure 5 This is a circuit diagram of a memory circuit 500 according to some embodiments. The memory circuit 500 is coupled to, for example,... Figure 4The following is a non-limiting example of the input circuit of the memory circuit 400 (e.g., input circuit 504), and therefore a similar detailed description is omitted.

[0147] The memory circuit 500 includes a memory circuit 502 coupled to the input circuit 504.

[0148] In some embodiments, memory circuit 502 is Figure 2 Sensing amplifier circuit / writing circuit 204 Figure 4 Memory circuit 400, Figure 7 7007 memory circuit or Figure 8 At least one of the memory circuits 800, therefore a similar detailed description is omitted.

[0149] Input circuit 504 is configured to receive input signal Din. Input circuit 504 is configured to generate input signal DinB in response to input signal Din. In some embodiments, input signal DinB is inverted compared to input signal Din. In some embodiments, input circuit 504 is coupled to... Figure 4 , Figure 7 and Figure 8 The switching circuit 406 is included. The input circuit 504 includes an inverter I6.

[0150] Inverter I6 is configured to generate an input signal DinB in response to an input signal Din. The input terminal of inverter I6 is configured to receive the input signal Din. In some embodiments, the input terminal of inverter I6 is coupled to a source (not shown) of the input signal Din. The input terminal of inverter I6 is further coupled to memory circuit 502. The output terminal of inverter I6 is coupled to memory circuit 502. The output terminal of inverter I6 is configured to output the input signal DinB to memory circuit 502. In some embodiments, inverter I6 is coupled to... Figure 4 , Figure 7 and Figure 8 The switching circuit 406 is included. The inverter I6 is also coupled to the power supply voltage VDDI. In some embodiments, the input signals Din and DinB are part of a voltage domain (e.g., VDDI) different from the voltage domain (e.g., VDDM) of the memory circuits 400, 700, and 800. In some embodiments, the power supply voltage VDDI has a different voltage swing than the power supply voltage VDDM. In some embodiments, the input signals Din and DinB are part of the same voltage domain (e.g., VDDI) as the voltage domain (e.g., VDDM) of the memory circuits 400, 700, and 800. In some embodiments, the power supply voltage VDDI has the same voltage swing as the power supply voltage VDDM.

[0151] Other configurations, types, or numbers of circuit elements in the input circuit 504, inverter I6, or memory circuit 500 are within the scope of this disclosure.

[0152] In some embodiments, memory circuitry 500 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 100 or 200.

[0153] Other configurations of the memory circuit 500 are within the scope of this disclosure.

[0154] Waveform diagram

[0155] Figure 6 According to some embodiments, such as Figure 2 The memory circuit 200 in Figure 4 The memory circuit 400 in Figure 5 The memory circuit 500 in the middle Figure 7 Timing diagram 600 of the waveforms of the memory circuit 700 in the memory circuit. In some embodiments, according to some examples, Figure 6 It is at least memory circuit 100-200, memory circuit 400, memory circuit 500 or Figure 7 Timing diagram 600 for memory circuit 700.

[0156] In some embodiments, at least in Figure 1 One or more read and write operations of the memory bank in the memory circuit 100 are applied to at least one of the memory partitions 102A, 102B, 102C or 102D, and the timing diagram 600 corresponds to the waveforms during the read and write operations of at least one of the memory partitions 102A, 102B, 102C or 102D.

[0157] In some embodiments, one or more read operations and write operations are applied to at least Figure 2 At least one memory cell in column 0 of the memory cell array 202 in the memory circuit 200, and the timing diagram 600 corresponds to Figure 2 The waveform during read and write operations of at least one memory cell in column 0 of the memory cell array 202 in at least the memory circuit 200.

[0158] Timing diagram 600 includes the waveforms of control signal IWEB, clock signal CLK, control signal DCKB, control signal DCK, signal DLEQB, and sense amplifier enable signal SAE.

[0159] At time T0, the control signal IWEB is logic low, the clock signal CLK is logic low, the control signal DCKB is logic high, the control signal DCK is logic low, the signal DLEQB is logic high, and the sense amplifier enable signal SAE is logic low.

[0160] At time T0, in response to the control signal DCKB being logic high, the switching circuit 406 is turned on, and the latch circuit 410 is transparent. Figure 6 and Figure 9 This is marked as "Din Transparent". For example, at time T0, in response to the control signal DCKB being logic high, NMOS transistors MN5 and MN6 are turned on, thereby coupling the data signals Din and DinB to the corresponding data lines DL and DLB.

[0161] Between time T1 and time T7, a read operation is performed on the memory cell.

[0162] At time Tl, the clock signal CLK and the control signal IWEB transition from logic low to logic high. At least in response to the transition of the clock signal CLK from logic low to logic high, a memory cell read operation is triggered.

[0163] At time T2, the control signal DCKB and the signal DLEQB change from logic high to logic low.

[0164] Between time T2 and T3, the control signal IWEB is logic high.

[0165] At time T3, the control signal DCKB is logic low, thereby turning on the PMOS transistor MP3, turning off the switching circuit 406, and disabling the latch circuit 410. Figure 6 and Figure 9 This is marked as "Din Latch Disabled". For example, at time T3, in response to the control signal DCKB being logic low, NMOS transistors MN5 and MN6 are turned off, thereby decoupling the data signals Din and DinB from the corresponding data lines DL and DLB.

[0166] At time T3, signal DLEQB is logic low, thereby enabling the precharge and equalization circuit 420. For example, at time T3, in response to signal DLEQB being logic low, PMOS transistor MP4 is turned on, thereby coupling the data line DL and the inverted data line DLB together, and PMOS transistors MP5 and MP6 are turned on, thereby connecting the data line DL and the inverted data line DLB to the power supply voltage VDDM and precharging the data line DL and the inverted data line DLB to the precharge voltage (e.g., voltage VDL).

[0167] At time T4, the signal DLEQB transitions from logic low to logic high. In some embodiments, the signal DLEQB transitions from logic low to logic high at time T4 because the data line DL and the inverting data line DLB have been fully charged to the pre-charge voltage (e.g., voltage VDL).

[0168] At time T5, signal DLEQB is logic high, thereby disabling the precharge and equalization circuit 420. For example, at time T5, in response to signal DLEQB being logic high, PMOS transistor MP4 is turned off, thereby decoupling the data line DL and the inverting data line DLB from each other, and PMOS transistors MP5 and MP6 are turned off, thereby disconnecting the data line DL and the inverting data line DLB from the power supply voltage VDDM.

[0169] At time T6, the sense amplifier enable signal SAE transitions from logic low to logic high. In some embodiments, the sense amplifier enable signal SAE transitions from logic low to logic high at time T6 because sufficient time has elapsed to allow sufficient splitting between the data line signal on data line DL or the inverted data line signal on inverted data line DLB.

[0170] At time T7, the sense amplifier enable signal SAE is logic high, thereby enabling the latch circuit 410. In some embodiments, when the sense amplifier enable signal SAE is logic high, the inverting sense amplifier enable signal SAEB is logic low. For example, at time T7, in response to the sense amplifier enable signal SAE being logic high, the NMOS transistor MN3 is turned on, thereby pulling the data line signal on the data line DL (e.g., node n2) or the inverting data line signal on the inverting data line DLB (e.g., node n1) towards the reference supply voltage VSS. In some embodiments, the node n1 or node n2 that is pulled low is a node with a lower voltage level.

[0171] At time T7, the sense amplifier enable signal SAE is logic high, thereby disabling the latches (e.g., inverter I5, PMOS transistors MP9-MP10, and NMOS transistors MN9-MN10) within the latch circuit 440, and transmitting the data line signal from the data line DL to the output node NO. For example, at time T7, in response to the sense amplifier enable signal SAE being logic high, NMOS transistor MN7 is turned on and PMOS transistor MP10 is turned off; in response to the inverting sense amplifier enable signal SAE being logic low, PMOS transistor MP8 is turned on and NMOS transistor MN9 is turned off, thereby setting the output signal QB by PMOS transistors MP7 and NMOS transistor MN8. In some embodiments, the output signal QB is inverted compared to the data line signal on the data line DL. Subsequently, inverter I4 is configured to invert the output signal QB when setting the output signal Q, the output signal Q corresponding to the data value read from the memory cell in a read operation.

[0172] At time T7, the clock signal CLK transitions from logic high to logic low. The transition of the clock signal CLK to logic low causes the read operation of the memory cell to terminate.

[0173] At time T8, the sense amplifier enable signal SAE transitions from logic high to logic low. In some embodiments, the sense amplifier enable signal SAE transitions from logic high to logic low at time T8 because sufficient time has elapsed to transmit or deliver the data line signal from data line DL to output node NO.

[0174] At time T9, the control signal IWEB changes from logic high to logic low, and the control signal DCKB changes from logic low to logic high.

[0175] At time T10, the sense amplifier enable signal SAE is logic low, thereby disabling the latch circuit 410. In some embodiments, when the sense amplifier enable signal SAE is logic low, the inverting sense amplifier enable signal SAEB is logic high. For example, at time T10, in response to the sense amplifier enable signal SAE being logic low, the NMOS transistor MN3 is turned off, and node n4 is disconnected from the reference voltage source VSS.

[0176] At time T10, the sense amplifier enable signal SAE is logic low, thereby enabling the latches within latch circuit 440 (e.g., inverter I5, PMOS transistors MP9-MP10, and NMOS transistors MN9-MN10), and the data line signal is no longer transmitted from data line DL to output node NO. For example, at time T10, in response to the sense amplifier enable signal SAE being logic low, NMOS transistor MN7 is turned off and PMOS transistor MP10 is turned on; in response to the inverting sense amplifier enable signal SAE being logic high, PMOS transistor MP8 is turned off and NMOS transistor MN9 is turned on, thereby latching at least inverter I5, PMOS transistor MP9, and NMOS transistor MN10 to latch the output signal QB. After time T10, the output signal QB is latched by latch circuit 440 during subsequent write operations to the memory cell. After time T10, inverter I4 is configured to invert output signal QB when setting output signal Q, which corresponds to the data value read from the memory cell in the read operation.

[0177] At time T11, the control signal IWEB is logic low. At time T11, the control signal DCKB is logic high, thereby turning on the switching circuit 406 and making the latch circuit 410 transparent. For example, at time T11, in response to the control signal DCKB being logic high, NMOS transistors MN5 and MN6 are turned on, thereby coupling the data signals Din and DinB to the corresponding data lines DL and DLB.

[0178] Between time T12 and time T15, a write operation is performed on the memory cell.

[0179] At time T12, the clock signal CLK changes from logic low to logic high, thereby triggering a write operation to the memory cell.

[0180] At time T13, the control signal DCKB transitions from logic high to logic low. In response to the transition of control signal DCKB from logic high to logic low, and the control signal IWEB being logic low, the control signal DCK transitions from logic low to logic high through the NOR logic gate NOR1.

[0181] At time T14, the control signal DCKB is logic low, thus turning on the PMOS transistor MP3 and turning off the switching circuit 406. Conversely, the control signal DCK is logic high, thus turning on the NMOS transistor MN4 and enabling the latch circuit 410. Figure 6 and Figure 9This is marked as "Din Latched". For example, at time T14, in response to the control signal DCKB being logic low, NMOS transistors MN5 and MN6 are turned off, thereby decoupling the data signals Din and DinB from the corresponding data lines DL and DLB. However, since latch circuit 410 is enabled, even if the data lines DL and DLB are disconnected from the source of the data signals Din and DinB, latch circuit 410 still latches the input data (e.g., the input data signals Din and DinB).

[0182] At time T14, the control signal WCLK is logic low, and either the data line DL or the inverted data line DLB is logic low, causing the corresponding NOR logic gate NOR2 or NOR3 to output the corresponding signal WC or WT as logic high. In response to the signal WC or WT being logic high, the corresponding NMOS transistor MN12 or MN13 is turned on, causing the corresponding NMOS transistor MN12 or MN13 to discharge the corresponding bit line BL or the inverted data line BLB to logic low (this is the state of DL or DLB during a write operation).

[0183] At time T15, the clock signal CLK changes from logic high to logic low, thus ending the write operation to the memory cell. At time T15, the control signal DCKB changes from logic low to logic high, thereby causing the control signal DCK to change from logic high to logic low through the NOR logic gate NOR1.

[0184] At time T16, control signal DCKB is logic high and control signal DCK is logic low. At time T16, control signal DCK is logic low, thus turning off NMOS transistor MN4. The time period from time T16 onwards is similar to time T0, therefore a detailed description is omitted.

[0185] In some embodiments, timing diagram 600 enables memory circuitry 400 or 700 to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 100 or 200. In some embodiments, timing diagram 600 matches a NAP design.

[0186] In some embodiments, although timing diagram 600 is described with respect to memory circuit 400, timing diagram 600 is also applicable to memory circuit 700 in a similar manner, and is not described for the sake of brevity.

[0187] Other configurations of timing diagram 600 are within the scope of this disclosure.

[0188] Memory circuit:

[0189] Figure 7 This is a circuit diagram of a memory circuit 700 according to some embodiments.

[0190] Memory circuit 700 is Figure 4 Variations of the memory circuit 400 are shown, therefore similar detailed descriptions are omitted. For example, a non-limiting example of the memory circuit 700 is shown, wherein... Figure 4 Compared to the corresponding data line DL and the corresponding inverting data line DLB in the memory circuit 400, Figure 7 The data lines DL and DLB are flipped, so a similar detailed description is omitted.

[0191] The memory circuit 700 includes a control signal generation circuit 402, a control signal generation circuit 404, a latch circuit 410, a precharge and equalization circuit 420, an output circuit 430, and a latch circuit 740.

[0192] and Figure 4 Compared to the memory circuit 400, Figure 7 The latch circuit 740 replaces the latch circuit 440, therefore a similar detailed description is omitted. Figure 4 Compared to the latch circuit 440, Figure 7 The latch circuit 740 does not include inverter I4, therefore Figure 7 The output signal QB in Figure 7 The output signal Q is the same, so a similar detailed description is omitted.

[0193] exist Figure 7 In this circuit, the data line DL, node nl, the gate of PMOS transistor MP11, the gate of NMOS transistor MN11, the source of PMOS transistor MP4, the drain of PMOS transistor MP5, the drain of NMOS transistor MN5, the drain of PMOS transistor MP1, the drain of NMOS transistor MN1, the gate of PMOS transistor MP2, the gate of NMOS transistor MN2, and the first input terminal of NOR logic gate NOR3 are coupled together.

[0194] exist Figure 7 In the diagram, the data line DLB, node n2, the gate of PMOS transistor MP7, the gate of NMOS transistor MN8, the drain of PMOS transistor MP4, the drain of PMOS transistor MP6, the drain of PMOS transistor MP6, the drain of NMOS transistor MN6, the drain of PMOS transistor MP2, the drain of NMOS transistor MN2, the gate of PMOS transistor MP1, the gate of NMOS transistor MN1, and the second input terminal of NOR logic gate NOR2 are coupled together.

[0195] In some embodiments, memory circuitry 700 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 100, 200, or 400.

[0196] Other configurations of the memory circuit 700 are within the scope of this disclosure. In some embodiments, the operation of the memory circuit 700 is the same as the operation of the memory circuit 400, therefore Figure 6 The timing diagram 600 is also applicable to the memory circuit 700, and will not be described in detail for the sake of simplicity.

[0197] Figure 8 This is a circuit diagram of a memory circuit 800 according to some embodiments. The memory circuit 800 is... Figure 4 Variations of the memory circuit 400 are shown, therefore a similar detailed description is omitted. For example, a non-limiting example of the memory circuit 800 is shown, in which an NMOS transistor MN14 is used instead of... Figure 4 The NMOS transistors MN3 and MN4 in the memory circuit 400 are omitted from the detailed description.

[0198] The memory circuit 800 includes a control signal generation circuit 802, a latch circuit 810, a precharge and equalization circuit 420, an output circuit 430, and a latch circuit 440.

[0199] and Figure 4 Compared to the memory circuit 400, Figure 8 The latch circuit 810 replaces the latch circuit 410, therefore a similar detailed description is omitted. Figure 4 Compared to the latch circuit 410, Figure 8 The latch circuit 810 uses NMOS transistor MN14 instead. Figure 4 The NMOS transistors MN3 and MN4 in the latch circuit 410 are omitted from the detailed description.

[0200] The drain of NMOS transistor MN14, the source of NMOS transistor MN1, and the source of NMOS transistor MN2 are coupled together at node n4. The source of NMOS transistor MN14 is configured to a reference supply voltage node (not shown) with a reference supply voltage VSS. The gate of NMOS transistor MN14 is configured to receive a control signal SAE_DCK. In some embodiments, the control signal SAE_DCK is a combination of a sense amplifier enable signal SAE and a control signal DCKB. The gate of NMOS transistor MN14 is coupled to the output terminal of the NOR logic gate NOR1 of the control signal generation circuit 802. In some embodiments, NMOS transistor MN14 is referred to as a "foot switch".

[0201] and Figure 4Compared to the memory circuit 400, Figure 8 The control signal generation circuit 802 includes components coupled together. Figure 4 The control signal generation circuits 402 and 404 are used, therefore a similar detailed description is omitted. For example, by coupling control circuits 402 and 404 together, control circuit 802 generates the control signal SAE_DCK instead of the control signal DCK, therefore a similar detailed description is omitted.

[0202] The control signal generation circuit 802 includes a control signal generation circuit 402, a control signal generation circuit 404, and a NOR logic gate NOR4.

[0203] and Figure 4 Compared to the control signal generation circuit 402, Figure 8 The input terminal of the inverter I1 of the control signal generation circuit 402 is also coupled to the first input terminal of the NOR logic gate NOR4, so a similar detailed description is omitted.

[0204] The first input terminal of the NOR logic gate NOR4 is configured to receive the global sense amplifier enable signal GLB_SAE. The second input terminal of the NOR logic gate NOR4 is configured to receive the control signal IWE. In some embodiments, the control signal IWE is a write enable signal that is configured to logic 0 during a read operation of one or more memory cells coupled to the memory circuit 800. In some embodiments, the control signal IWE is a write enable signal that is configured to logic 1 during a write operation of one or more memory cells coupled to the memory circuit 800. In some embodiments, the control signal IWE is generated by external circuitry (not shown). In some embodiments, the control signal generation circuit 802 is coupled to... Figure 1 The GIO circuit 100BL in the middle is configured to be from Figure 1 The GIO circuit 100BL receives the global sense amplifier enable signal GLB_SAE. In some embodiments, the second input terminal of the NOR logic gate NOR4 is directly coupled to the source of the control signal IWE (not shown). The output terminal of the NOR logic gate NOR4 is configured to output the control signal SAEB_IWEB. The NOR logic gate NOR4 is configured to generate the control signal SAEB_IWEB based on the global sense amplifier enable signal GLB_SAE and the control signal IWE. The output terminal of the NOR logic gate NOR4 is coupled to... Figure 8 The control signal generation circuit 404.

[0205] and Figure 4 Compared to the control signal generation circuit 404, Figure 8The second input terminal of the NOR logic gate NOR1 of the control signal generation circuit 404 is coupled to the output terminal of the NOR logic gate NOR4, so a similar detailed description is omitted.

[0206] Figure 8 The NOR logic gate NOR1 is configured to generate the control signal SAE_DCK based on the control signal DCKB and the control signal SAEB_IWEB. Figure 8 The output terminal of the NOR logic gate NOR1 is configured to output the control signal SAE_DCK. Figure 8 The output terminal of the NOR logic gate NOR1 is coupled to the gate of the NMOS transistor MN14 of the latch circuit 810. In some embodiments, the control signal SAE_DCK is a combination of the sense amplifier enable signal SAE and the control signal DCKB.

[0207] In some embodiments, memory circuit 800 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuits 100, 200, or 400. In some embodiments, the operation of memory circuit 800 is similar to the operation of memory 400, and the same descriptions are omitted for brevity. For example, according to some embodiments, for a read operation, the data signal Q for memory circuit 800 is the same as the data signal Q for memory circuit 400 or 700. For example, according to some embodiments, for a read operation, the signals WC and WT for memory circuit 800 are the same as the corresponding signals WC and WT for memory circuit 400 or 700. In some embodiments, the operation of memory circuit 800 is... Figure 9 As described below.

[0208] Other configurations of the memory circuit 800 are within the scope of this disclosure.

[0209] Waveform diagram

[0210] Figure 9 According to some embodiments, such as Figure 8 Timing diagram 900 shows the waveforms of the memory circuit in the storage circuit 800. In some embodiments, according to certain examples, Figure 9 It is a timing diagram 900 for at least memory circuit 100-200 or memory circuit 500.

[0211] In some embodiments, at least in Figure 1One or more read and write operations of the memory bank in the memory circuit 100 are applied to at least one of the memory partitions 102A, 102B, 102C or 102D, and the timing diagram 900 corresponds to the waveforms during the read and write operations of at least one of the memory partitions 102A, 102B, 102C or 102D.

[0212] In some embodiments, one or more read operations and write operations are applied to at least Figure 2 At least one memory cell in column 0 of the memory cell array 202 in the memory circuit 200, and timing diagram 900 corresponds to Figure 2 The waveform during read and write operations of at least one memory cell in column 0 of the memory cell array 202 in at least the memory circuit 200.

[0213] Timing diagram 900 includes the waveforms of control signal IWE, clock signal CLK, control signal DCKB, control signal SAE_DCK, signal DLEQB, and sense amplifier enable signal SAE.

[0214] At time T0, the control signal IWE is logic high, the clock signal CLK is logic low, the control signal DCKB is logic high, the control signal DCK is logic low, the signal DLEQB is logic high, the sense amplifier enable signal SAE is logic low, and the control signal SAEB_IWEB is logic low.

[0215] At time T0, in response to the control signal DCKB being logic high, the switching circuit 406 is turned on, and the latch circuit 810 is transparent and is marked "Din Transparent". Figure 9 Time T0 in the middle is similar to Figure 6 The time T0 in the equation is used, so a similar detailed description is omitted.

[0216] Between time T1 and time T7, a read operation is performed on the memory cell. At time T1, the clock signal CLK changes from logic low to logic high, thereby triggering the read operation on the memory cell.

[0217] At time T1, the control signal IWE changes from logic high to logic low, thereby causing the control signal SAEB_IWEB to change from logic low to logic high.

[0218] At time T2, the control signal DCKB and the signal DLEQB change from logic high to logic low.

[0219] Between time T2 and T3, the control signal IWE transitions to logic low, and the control signal SAEB_IWEB transitions to logic high.

[0220] At time T3, the control signal DCKB goes low, turning on the PMOS transistor MP3 and turning off the switching circuit 406, while disabling the latch circuit 810. Figure 6 and Figure 9 It is marked as "Din Latch Disabled".

[0221] At time T3, signal DLEQB is logic low, thereby enabling the precharge and equalization circuit 420. Figure 9 Time T3 in the middle is similar to Figure 6 The time T3 in the text is omitted, so a similar detailed description is omitted.

[0222] At time T4, the signal DLEQB changes from logic low to logic high. Figure 9 Time T4 in the middle is similar to Figure 6 The time T4 in the text is omitted, so a similar detailed description is omitted.

[0223] At time T5, signal DLEQB is logic high, thereby disabling the precharge and equalization circuit 420. Figure 9 The time T5 in the middle is similar to Figure 6 The time T5 in the text is omitted, so a similar detailed description is omitted.

[0224] At time T6, the sense amplifier enable signal SAE changes from logic low to logic high, thereby causing the control signal SAEB_IWEB to change from logic high to logic low through the NOR logic gate NOR4, and thus causing the control signal SAE_DCK to change from logic low to logic high through the NOR logic gate NOR1.

[0225] At time T7, the control signal SAE_DCK is logic high, thereby enabling the latch circuit 810. For example, at time T7, in response to the control signal SAE_DCK being logic high, the NMOS transistor MN14 is turned on, thereby pulling the data line signal on the data line DL (e.g., node n2) or the inverted data line signal on the inverted data line DLB (e.g., node n1) towards the reference supply voltage VSS. In some embodiments, the node n1 or node n2 that is pulled low is a node with a lower voltage level.

[0226] At time T7, the sense amplifier enable signal SAE goes high, thereby disabling the latches within latch circuit 440 (e.g., inverter I5, PMOS transistors MP9-MP10, and NMOS transistors MN9-MN10) and transferring the data line signal from data line DL to output node NO, similar to... Figure 6 The time T7 is used, so a similar detailed description is omitted.

[0227] At time T7, the clock signal CLK transitions from logic high to logic low. The transition of the clock signal CLK to logic low causes the read operation of the memory cell to terminate.

[0228] At time T7, the control signal SAEB_IWEB is logic low.

[0229] At time T8, the sense amplifier enable signal SAE changes from logic high to logic low, thereby causing the control signal SAEB_IWEB to change from logic low to logic high through the NOR logic gate NOR4, and thus causing the control signal SAE_DCK to change from logic high to logic low through the NOR logic gate NOR1.

[0230] At time T8, the sense amplifier enable signal SAE changes from logic high to logic low, similar to... Figure 6 The time T in the equation is omitted, hence similar detailed descriptions are omitted.

[0231] At time T9, the control signal SAE_DCK is logic low, thereby disabling the latch circuit 810. For example, at time T9, in response to the control signal SAE_DCK being logic low, the NMOS transistor MN14 is turned off, and node n4 is disconnected from the reference voltage source VSS.

[0232] At time T9, the sense amplifier enable signal SAE goes low, thereby enabling the latches within latch circuit 440 (e.g., inverter I5, PMOS transistors MP9-MP10, and NMOS transistors MN9-MN10), and the data line signal is no longer transmitted from data line DL to output node NO. Figure 6 The time T10 is similar, so a similar detailed description is omitted.

[0233] At time T9, the control signal SAE_DCK is logic low and the control signal SAEB_IWEB is logic high.

[0234] At time T9, the control signal DCKB changes from logic low to logic high.

[0235] At time T10a, the control signal DCKB is logic high, thus turning on the switching circuit 406 and making the latch circuit 810 transparent. Figure 6 The time T11 is similar, so a similar detailed description is omitted.

[0236] At time T10b, the control signal IWE changes from logic low to logic high, thereby causing the control signal SAEB_IWEB to change from logic high to logic low.

[0237] At time T10c, the control signal IWE is logic high and the control signal SAEB_IWEB is logic low.

[0238] Between time T11 and time T14, a write operation is performed on the memory cell. At time T11, the clock signal CLK changes from logic low to logic high, thereby triggering the write operation on the memory cell.

[0239] At time T12, the control signal DCKB transitions from logic high to logic low. In response to the transition of the control signal DCKB from logic high to logic low, and with the control signal IWE being logic low, the control signal SAE_DCK transitions from logic low to logic high through the NOR logic gate NOR1, thereby enabling the latch circuit 810.

[0240] At time T13, the control signal SAE_DCK is logic high, thereby enabling the latch circuit 810. For example, at time T12, in response to the control signal SAE_DCK being logic high, the NMOS transistor MN14 is turned on, thereby pulling the data line signal on the data line DL (e.g., node n2) or the inverted data line signal on the inverted data line DLB (e.g., node n1) to the reference supply voltage VSS.

[0241] At time T13, the control signal DCKB is logic low, thus turning on the PMOS transistor MP3, turning off the switching circuit 406, and enabling the latch circuit 810. Figure 6 The time T14 is similar, so a similar detailed description is omitted.

[0242] At time T13, the control signal WCLK is logic low, and similar to Figure 6 The time T14 is used, so a similar detailed description is omitted.

[0243] At time T14, the control signal DCKB transitions from logic low to logic high. In response to the transition of the control signal DCKB from logic low to logic high, and with the control signal IWE being logic high, the control signal SAE_DCK transitions from logic high to logic low through the NOR logic gate NOR1.

[0244] At time T14, the clock signal CLK changes from logic high to logic low, thus ending the write operation to the memory cell.

[0245] At time T15, the control signal DCKB is logic high and the control signal SAE_DCK is logic low.

[0246] At time T15, the control signal SAE_DCK is logic low, thus turning off the NMOS transistor MN14. The events from time T15 onwards are similar to those at time T0, therefore a detailed description is omitted.

[0247] In some embodiments, timing diagram 900 enables memory circuitry 500 or 800 to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 100 or 200.

[0248] Other configurations of timing diagram 900 are within the scope of this disclosure.

[0249] method:

[0250] Figures 10A-10B This is a flowchart of a method 1000 for operating circuits according to some embodiments.

[0251] In some embodiments, Figures 10A-10B It is an operation Figure 1 Memory circuit 100 Figure 2 Memory circuit 200, Figure 4 Memory circuit 400, Figure 5 Memory circuit 500, Figure 7 Memory circuit 700 or Figure 8 Memory circuit 800 or Figure 3 A flowchart of a method 1000 for at least one of the memory units 300.

[0252] In some embodiments, Figures 10A-10B This is a flowchart of a method 1000 for operating a memory circuit, and method 1000 includes... Figure 6 Timing diagram 600 and Figure 9 The characteristics of timing diagram 900 are described, and similar detailed descriptions are omitted for brevity.

[0253] It should be understood that it is possible Figures 10A-10B Additional operations are performed before, during, and / or after method 1000 shown herein; therefore, only a few other operations are briefly described herein. It should be understood that method 1000 utilizes… Figure 1 Memory circuit 100 Figure 2 Memory circuit 200, Figure 4 Memory circuit 400, Figure 5 Memory circuit 500, Figure 7 Memory circuit 700 or Figure 8 Memory circuit 800 or Figure 3 For the sake of brevity, a detailed description of one or more features of at least one of the memory cells 300 is omitted.

[0254] In some embodiments, the order of other operations of method 1000 is within the scope of this disclosure. Method 1000 includes exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be appropriately added, replaced, rearranged, and / or removed in accordance with the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of method 1000 are not performed.

[0255] In operation 1002 of method 1000, an inverting sense amplifier signal SAEB and a sense amplifier signal SAE are generated.

[0256] In some embodiments, operation 1002 is performed by a first control circuit. In some embodiments, the first control circuit includes a control signal generation circuit 402.

[0257] In operation 1004 of method 1000, at least a first control signal is generated. In some embodiments, the first control signal is generated in response to at least a second control signal or a third control signal.

[0258] In some embodiments, the first control signal includes at least one of control signal DCK or control signal SAE_DCK. In some embodiments, the second control signal includes at least one of control signal IWEB, control signal IWE, or control signal SAEB_IWEB. In some embodiments, the third control signal includes control signal DCKB.

[0259] In some embodiments, operation 1004 is performed by a second control circuit. In some embodiments, the second control circuit includes at least one of a control signal generation circuit 404 or a NOR logic gate NOR4. In some embodiments, the second control circuit includes a control signal generation circuit 802.

[0260] In operation 1006 of method 1000, a first memory cell is read in response to at least a sense amplifier signal, a second control signal, or a first clock signal. In some embodiments, the first memory cell is read by an LIO circuit. In some embodiments, the LIO circuit includes memory circuit 200, memory circuit 400, memory circuit 500, memory circuit 800, or memory circuit 200. In some embodiments, the LIO circuit includes LIO circuit 110BS. In some embodiments, the first memory cell is coupled to the LIO circuit.

[0261] In some embodiments, the first memory cell includes at least one of the memory cells 112, or at least one or more memory cells in the memory cell array 202 or memory cell 300. In some embodiments, the first clock signal includes a clock signal CLK.

[0262] In some embodiments, operation 1006 includes at least one of operations 1008, 1010, 1012, 1014, 1016, 1018, or 1020.

[0263] In operation 1008 of method 1000, the switching circuit 406 is disabled in response to the third control signal.

[0264] In operation 1010 of method 1000, in response to a precharge control signal (e.g., signal DLEQB), the first data line and the second data line are precharged to a precharge voltage (e.g., voltage VDL), and the voltages of the first data line and the second data line are equalized. In some embodiments, a switching circuit is coupled to the first data line and the second data line.

[0265] In some embodiments, operation 1010 is performed by a pre-charge / equalization circuit. In some embodiments, the pre-charge / equalization circuit includes a pre-charge and equalization circuit 420. In some embodiments, the first data line includes one of a data line DL or an inverted data line DLB, and the second data line includes the other of a data line DL or an inverted data line DLB. In some embodiments, the pre-charge / equalization circuit includes a pre-charge and equalization circuit 420.

[0266] In operation 1012 of method 1000, in response to at least a third control signal and a sense amplifier signal, a first latch circuit is enabled and configured as a sense amplifier. In some embodiments, the first latch circuit is coupled to a first data line and a second data line.

[0267] In some embodiments, the first latch circuit includes at least one of latch circuit 410 or latch circuit 810.

[0268] In operation 1014 of method 1000, the first latch circuit senses the first data line signal and the second data line signal in response to at least the third control signal and the sense amplifier signal.

[0269] In some embodiments, the first data line signal is a signal of a first data line. In some embodiments, the second data line signal is a signal of a second data line.

[0270] In operation 1016 of method 1000, a first data line signal is transmitted to the output node (e.g., node NO) of the second circuit in response to a sense amplifier signal and an inverting sense amplifier signal. In some embodiments, the first data line signal is transmitted to the output node of the second circuit by a second latch circuit.

[0271] In some embodiments, the second latch circuit is coupled to the first data line and the first latch. In some embodiments, the second latch circuit includes at least one of latch circuit 440 or latch circuit 740.

[0272] In operation 1018 of method 1000, a first data line signal is latched in response to a sense amplifier signal and an inverting sense amplifier signal. In some embodiments, the first data line signal is latched by a second latch circuit.

[0273] In operation 1020 of method 1000, a first value of the data stored in the first memory cell is output by the LIO circuit. In some embodiments, a first data line signal corresponds to the first value of the data stored in the first memory cell. In some embodiments, the first value of the data includes logic 0 or logic 1.

[0274] In operation 1022 of method 1000, in response to at least a third control signal, a first control signal, or a first clock signal, a second value of the data is written to a first memory cell. In some embodiments, the second value of the data includes logic 0 or logic 1.

[0275] In some embodiments, the second value of the data is equal to the first value of the data. In some embodiments, the second value of the data is different from the first value of the data.

[0276] In some embodiments, operation 1022 is performed by LIO circuitry. In some embodiments, operation 1022 is performed on the same memory cell as operation 1006. In some embodiments, operation 1022 is performed on a different memory cell than operation 1006.

[0277] In some embodiments, operation 1022 includes at least one of operations 1024, 1026, 1028, 1030, 1032, or 1034.

[0278] In operation 1024 of method 1000, the switching circuit 406 is enabled or turned on in response to the third control signal, and the first input signal (e.g., data signal Din) and the second input signal (e.g., data signal DinB) are transmitted to the corresponding first data line and second data line.

[0279] In operation 1026 of method 1000, the first latch circuit is configured as a write latch circuit that is set to a transparent state in response to at least a third control signal.

[0280] In operation 1028 of method 1000, the switching circuit 406 is disabled or turned off in response to the third control signal.

[0281] In operation 1030 of method 1000, in response to at least a third control signal and a first control signal, a first latch circuit configured to write to a latch (406) is set to a latched state.

[0282] In operation 1032 of method 1000, a first signal (e.g., signal WC or signal WT) is set in response to a second clock signal (e.g., clock signal WCLK) and at least a first data line signal or a second data line signal.

[0283] In some embodiments, the first signal (e.g., WC / WT) is set by a first NOR logic gate. In some embodiments, the first NOR logic gate includes at least one of NOR logic gate NOR2 or NOR logic gate NOR3. In some embodiments, the first signal (e.g., WC / WT) is set by output circuit 430.

[0284] In operation 1034 of method 1000, the first transistor is turned on in response to the first signal, thereby setting the voltage of the first bit line or the second bit line. In some embodiments, the voltage of the first bit line or the second bit line corresponds to a second value of data stored in the first memory cell.

[0285] In some embodiments, the first transistor includes at least one of NMOS transistor MN12 or NMOS transistor MN13. In some embodiments, the first bit line includes one of bit line BL or anti-phase line BLB, and the second bit line includes the other of bit line BL or anti-phase line BLB.

[0286] By operating method 1000, the circuit operation achieves the above-mentioned... Figure 1 Memory circuit 100 Figure 2 Memory circuit 200, Figure 4 Memory circuit 400, Figure 5 Memory circuit 500, Figure 7 Memory circuit 700 or Figure 8 Memory circuit 800 or Figure 3 memory cell 300 or Figure 6 Timing diagram 600 and Figure 9 At least one of the benefits discussed in the timing diagram 900.

[0287] In some embodiments, one or more operations of method 1000 are not performed. Furthermore, Figures 3-4 and Figures 6-8 The various PMOS or NMOS transistors shown have specific dopant types (e.g., N-type or P-type) for illustrative purposes. The embodiments of this disclosure are not limited to specific transistor types, and... Figures 3-5 and Figures 7-8One or more of the PMOS or NMOS transistors shown can be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are also for illustrative purposes. Embodiments of this disclosure are not limited to specific logic values ​​when a signal is activated and / or deactivated. Different logic values ​​are chosen within the scope of the various embodiments. Figures 3-5 and Figures 7-8 Different numbers of inverters are selected within a range of various embodiments. Figures 3-5 and Figures 7-8 Different numbers of transistors are selected within a range of various embodiments. Figure 4 and Figures 7-8 Different numbers of NOR logic gates are selected within the range of various embodiments.

[0288] It will be apparent to those skilled in the art that the disclosed one or more embodiments achieve one or more of the advantages set forth above. After reading the foregoing specification, those skilled in the art will be able to conceive of various variations, equivalent substitutions, and numerous other embodiments as broadly disclosed herein. Therefore, the scope of protection claimed herein is intended to be limited only by the limitations contained in the appended claims and their equivalents.

[0289] One aspect of the present invention relates to a memory circuit. The memory circuit includes a set of memory cells, a first bit line and a second bit line coupled to the set of memory cells, and a local input / output (LIO) circuit coupled to the set of memory cells via the first bit line and the second bit line. In some embodiments, the LIO circuit includes a first data line and a second data line, a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal inversely phase to the first sense amplifier signal, and a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal. In some embodiments, the LIO circuit further includes a switching circuit coupled to the first data line, the second data line, and the second control circuit, configured to receive the third control signal, configured to transmit a first input signal and a second input signal to the corresponding first data line and second data line during a write operation of the set of memory cells, and electrically isolate the first data line and the second data line from the first input signal and the second input signal during a read operation of the set of memory cells. In some embodiments, the LIO circuit further includes a first latch circuit coupled to a first data line, a second data line, a first control circuit, and a second control circuit. During a read operation, the first latch circuit is configured as a sense amplifier in response to a third control signal and a second sense amplifier signal. During a write operation, the first latch circuit is configured as a write latch in response to the third control signal and the first control signal.

[0290] In some embodiments, the LIO circuit further includes: a second latch circuit coupled to the first data line and the first latch circuit, and configured to transmit a first data line signal to the output node of the second latch circuit in response to the second sense amplifier signal and the first sense amplifier signal during the read operation.

[0291] In some embodiments, the LIO circuit further includes a precharge / equalization circuit configured to precharge the first data line and the second data line to a precharge voltage in response to a precharge control signal, and to equalize the voltages of the first data line and the second data line, the precharge / equalization circuit being coupled to the first data line and the second data line.

[0292] In some embodiments, the LIO circuit further includes: a first N-type transistor having a first gate configured to receive the third control signal, a first source configured to receive the first input signal, and a first drain coupled to the first data line and coupled to the first latch circuit through a first node; and a second N-type transistor having a second gate configured to receive the third control signal, a second source configured to receive the second input signal, and a second drain coupled to the second data line and coupled to the first latch circuit through a second node.

[0293] In some embodiments, the first latch circuit includes: a first inverter coupled to the first data line and a first node; a second inverter coupled to the second data line and the first node, the first inverter and the second inverter being cross-coupled to each other; a head switch configured to receive the third control signal and coupled to a first voltage source and the first inverter and the second inverter via the first node; a first foot switch configured to receive the second sense amplifier signal and coupled between a second node and a second voltage source different from the first voltage source; and a second foot switch configured to receive the first control signal and coupled between the second node and the second voltage source. Another aspect of the invention relates to a memory circuit. The memory circuit includes a set of memory cells, a first bit line and a second bit line coupled to the set of memory cells, a first data line and a second data line, and a first control circuit configured to receive a global sense amplifier signal and generate a first sense amplifier signal and a second sense amplifier signal inversely phase to the first sense amplifier signal. In some embodiments, the memory circuit further includes a second control circuit configured to generate the first control signal in response to at least a second control signal or a third control signal. The memory circuitry also includes a third control circuit coupled between the first and second control circuits and configured to generate a second control signal in response to a global sense amplifier signal and a fourth control signal. The memory circuitry also includes a switching circuit coupled to the first data line, the second data line, and the second control circuitry and configured to receive the third control signal, and configured to transmit a first input signal and a second input signal to the corresponding first and second data lines during a write operation of the group of memory cells, and to electrically isolate the first and second data lines from the first and second input signals during a read operation of the group of memory cells. The memory circuitry also includes a first latch circuit coupled to the first data line, the second data line, the first control circuit, and the second control circuitry. During a read operation, in response to the third control signal and the second sense amplifier signal, the first latch circuitry is configured as a sense amplifier; and during a write operation, in response to the third control signal and the first control signal, the first latch circuitry is configured as a write latch. In some embodiments, the first control circuit includes: a first inverter configured to generate a first sense amplifier signal in response to the global sense amplifier signal, the first inverter including a first input terminal coupled to a global input / output (GIO) circuit and a first output terminal; and a second inverter configured to generate a second sense amplifier signal in response to the first sense amplifier signal, the second inverter including a second input terminal coupled to the first output terminal and a first output terminal coupled to the first latch circuit.

[0294] In some embodiments, the second control circuit includes: a third inverter configured to generate the third control signal in response to a fifth control signal, the third inverter including a third input terminal coupled to the GIO circuit and a third output terminal; and a first NOR logic gate having a first NOR input terminal coupled to the third output terminal and configured to receive the third control signal, a second NOR input terminal configured to receive the second control signal, and a first NOR output terminal configured to output the first control signal.

[0295] In some embodiments, the third control circuit includes: a second NOR logic gate having a third NOR input terminal coupled to the first input terminal and configured to receive the global sense amplifier signal, a fourth NOR input terminal configured to receive the fourth control signal, and a second NOR output terminal coupled to the second NOR input terminal and configured to output the second control signal.

[0296] In some embodiments, the first latch circuit includes: a first inverter coupled to the first data line and a first node; a second inverter coupled to the second data line and the first node, the first inverter and the second inverter being cross-coupled to each other; a head switch configured to receive the third control signal and coupled to a first voltage source and the first inverter and the second inverter via the first node; and a foot switch configured to receive the first control signal and coupled to the second control circuit, the second node, and a second voltage source different from the first voltage source.

[0297] In some embodiments, the memory circuitry further includes an output circuit coupled between the first data line and the second data line and the first bit line and the second data line, the output circuitry being configured to write data to the group of memory cells during the write operation.

[0298] In some embodiments, the memory circuit further includes: a second latch circuit coupled to the first data line and the first latch circuit, and configured to transmit a first data line signal to the output node of the second latch circuit in response to the second sense amplifier signal and the first sense amplifier signal during the read operation.

[0299] In some embodiments, the memory circuitry further includes a precharge / equalization circuit configured to precharge the first data line and the second data line to a precharge voltage in response to a precharge control signal, and to equalize the voltages of the first data line and the second data line, the precharge / equalization circuit being coupled to the first data line and the second data line.

[0300] In some embodiments, the precharge / equalization circuit includes: a first P-type transistor, comprising: a first terminal of the first P-type transistor configured to receive the precharge control signal; a second terminal of the first P-type transistor coupled to the first data line; and a third terminal of the first P-type transistor coupled to at least a first voltage source; a second P-type transistor, comprising: a first terminal of the second P-type transistor configured to receive the precharge control signal; a second terminal of the second P-type transistor coupled to the second data line; and a third terminal of the second P-type transistor coupled to the first voltage source and the third terminal of the first P-type transistor; and a third P-type transistor, comprising: a first terminal of the third P-type transistor configured to receive the precharge control signal; a second terminal of the third P-type transistor coupled to the first data line; and a third terminal of the third P-type transistor coupled to the second data line.

[0301] Another aspect of the present invention relates to a method of operating a memory circuit. The method includes generating an inverting sense amplifier signal and a sense amplifier signal inverted by a first control circuit. In some embodiments, the method further includes generating a first control signal by a second control circuit in response to at least a second control signal or a third control signal. In some embodiments, the method further includes reading a first memory cell via a local input / output (LIO) circuit coupled to the LIO circuit in response to at least the sense amplifier signal, the second control signal, or a first clock signal. In some embodiments, reading the first memory cell includes disabling a switching circuit in response to a third control signal, and precharging a first data line and a second data line to a precharge voltage and equalizing the voltages of the first data line and the second data line via a precharge / equalization circuit in response to a precharge control signal, the switching circuit being coupled to the first data line and the second data line. In some embodiments, reading the first memory cell further includes enabling a first latch circuit configured as a sense amplifier in response to at least a third control signal and the sense amplifier signal, the first latch circuit being coupled to the first data line and the second data line. In some embodiments, reading the first memory unit further includes sensing a first data line signal and a second data line signal via a first latch circuit in response to at least a third control signal and a sense amplifier signal. In some embodiments, reading the first memory unit further includes transmitting the first data line signal to the output node of a second latch circuit via a second latch circuit in response to the sense amplifier signal and an inverting sense amplifier signal, the second latch circuit being coupled to the first data line and the first latch circuit. In some embodiments, reading the first memory unit further includes latching the first data line signal via a second latch circuit in response to the sense amplifier signal and the inverting sense amplifier signal. In some embodiments, reading the first memory unit further includes outputting a first value of data stored in the first memory unit via an LIO circuit, wherein the first data line signal corresponds to the first value of data stored in the first memory unit.

[0302] In some embodiments, the method further includes: writing a second value of data into the first memory cell via the LIO circuit in response to at least the third control signal, the first control signal, or the first clock signal, wherein writing the second value of data into the first memory cell includes: enabling the switching circuit in response to the third control signal and transmitting a first input signal and a second input signal to corresponding first data lines and second data lines; setting / enabling the first latch circuit to configure it as a write latch and in a transparent state in response to at least the third control signal; disabling the switching circuit in response to the third control signal; setting / enabling the first latch circuit configured as the write latch to a latched state in response to at least the third control signal and the first control signal; setting a first signal via a first NOR logic gate in response to a second clock signal and at least the first data line signal or the second data line signal; and turning on a first transistor in response to the first signal to set the voltage of a first bit line or a second bit line, wherein the voltage of the first bit line or the second bit line corresponds to the second value of data stored in the first memory cell.

[0303] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A memory circuit, comprising: A set of memory units; The first bit line and the second bit line are coupled to the group of memory cells; A local input / output circuit is coupled to the group of memory cells via the first bit line and the second bit line. The local input / output circuit includes: First data line and second data line; A first control circuit is configured to generate a first sense amplifier signal and a second sense amplifier signal that is inversely phase to the first sense amplifier signal. The second control circuit is configured to generate a first control signal in response to at least a second control signal or a third control signal; A switching circuit, coupled to the first data line, the second data line, and the second control circuit, and configured to receive the third control signal, configured to transmit a first input signal and a second input signal to the corresponding first data line and second data line during a write operation of the group of memory cells, and electrically isolate the first data line and the second data line from the first input signal and the second input signal during a read operation of the group of memory cells; and A first latch circuit, coupled to the first data line, the second data line, the first control circuit, and the second control circuit, is configured as a sense amplifier in response to the third control signal and the second sense amplifier signal during the read operation, and is configured as a write latch in response to the third control signal and the first control signal during the write operation.

2. The memory circuit according to claim 1, wherein, The local input / output circuit also includes: A second latch circuit, coupled to the first data line and the first latch circuit, is configured to transmit a first data line signal to the output node of the second latch circuit during the read operation in response to the second sense amplifier signal and the first sense amplifier signal.

3. The memory circuit according to claim 1, wherein, The local input / output circuit also includes: A precharge / equalization circuit is configured to precharge the first data line and the second data line to a precharge voltage in response to a precharge control signal, and to equalize the voltages of the first data line and the second data line, the precharge / equalization circuit being coupled to the first data line and the second data line.

4. The memory circuit according to claim 1, wherein, The local input / output circuit also includes: A first N-type transistor has a first gate configured to receive the third control signal, a first source configured to receive the first input signal, and a first drain coupled to the first data line and coupled to the first latch circuit through a first node; and The second N-type transistor has a second gate configured to receive the third control signal, a second source configured to receive the second input signal, and a second drain coupled to the second data line and coupled to the first latch circuit through a second node.

5. The memory circuit according to claim 1, wherein, The first latch circuit includes: The first inverter is coupled to the first data line and the first node; The second inverter is coupled to the second data line and the first node, and the first inverter and the second inverter are cross-coupled to each other; A head switch is configured to receive the third control signal and is coupled to a first voltage source and the first inverter and the second inverter via a first node; A first-pin switch is configured to receive a signal from the second sensing amplifier and is coupled between a second node and a second voltage source different from the first voltage source; and The second foot switch is configured to receive the first control signal and is coupled between the second node and the second voltage source.

6. The memory circuit according to claim 1, wherein, The first control circuit includes: A first inverter, configured to generate the first sense amplifier signal in response to a global sense amplifier signal, includes a first input terminal coupled to a global input / output circuit and a first output terminal; and A second inverter is configured to generate a second sense amplifier signal in response to a first sense amplifier signal. The second inverter includes a second input terminal coupled to the first output terminal and a first output terminal coupled to the first latch circuit.

7. The memory circuit according to claim 1, wherein, The second control circuit includes: A first inverter, configured to generate the third control signal in response to a fourth control signal, includes a first input terminal coupled to a global input / output circuit and a first output terminal; and A first NOR logic gate has a first NOR input terminal coupled to the first output terminal and configured to receive the third control signal, a second NOR input terminal configured to receive the second control signal, and a first NOR output terminal configured to output the first control signal.

8. The memory circuit according to claim 1, wherein, The local input / output circuit also includes: An output circuit, coupled between the first data line and the second data line and the first bit line and the second data line, is configured to write data to the group of memory cells during the write operation.

9. The memory circuit according to claim 8, wherein, The output circuit includes: The first NOR logic gate is configured to generate a first signal in response to a second clock signal and a first data line signal; The second NOR logic gate is configured to generate a second signal in response to the second clock signal and the second data line signal; A first N-type transistor has a first gate coupled to the output of the first NOR logic gate and configured to receive the first signal, a first source coupled to a reference voltage source, and a first drain coupled to the first bit line; and The second N-type transistor has a second gate coupled to the output of the second NOR logic gate and configured to receive the second signal, a second source coupled to the reference voltage source, and a second drain coupled to the second bit line.

10. A memory circuit, comprising: A set of memory units; The first bit line and the second bit line are coupled to the group of memory cells; First data line and second data line; A first control circuit is configured to receive a global sense amplifier signal and generate a first sense amplifier signal and a second sense amplifier signal that is inversely related to the first sense amplifier signal. The second control circuit is configured to generate a first control signal in response to at least a second control signal or a third control signal; A third control circuit is coupled between the first control circuit and the second control circuit, and is configured to generate the second control signal in response to the global sense amplifier signal and the fourth control signal; A switching circuit, coupled to the first data line, the second data line and the second control circuit, and configured to receive the third control signal, configured to transmit the first input signal and the second input signal to the corresponding first data line and the second data line during a write operation of the group of memory cells, and electrically isolate the first data line and the second data line from the first input signal and the second input signal during a read operation of the group of memory cells; as well as A first latch circuit, coupled to the first data line, the second data line, the first control circuit, and the second control circuit, is configured as a sense amplifier in response to the third control signal and the second sense amplifier signal during the read operation, and is configured as a write latch in response to the third control signal and the first control signal during the write operation.

11. The memory circuit according to claim 10, wherein, The first control circuit includes: A first inverter, configured to generate the first sense amplifier signal in response to the global sense amplifier signal, includes a first input terminal coupled to a global input / output circuit and a first output terminal; and A second inverter is configured to generate a second sense amplifier signal in response to a first sense amplifier signal. The second inverter includes a second input terminal coupled to the first output terminal and a first output terminal coupled to the first latch circuit.

12. The memory circuit according to claim 11, wherein, The second control circuit includes: A third inverter, configured to generate the third control signal in response to the fifth control signal, includes a third input terminal coupled to the global input / output circuitry and a third output terminal; and A first NOR logic gate has a first NOR input terminal coupled to the third output terminal and configured to receive the third control signal, a second NOR input terminal configured to receive the second control signal, and a first NOR output terminal configured to output the first control signal.

13. The memory circuit according to claim 12, wherein, The third control circuit includes: The second NOR logic gate has a third NOR input terminal coupled to the first input terminal and configured to receive the global sense amplifier signal, a fourth NOR input terminal configured to receive the fourth control signal, and a second NOR output terminal coupled to the second NOR input terminal and configured to output the second control signal.

14. The memory circuit according to claim 10, wherein, The first latch circuit includes: The first inverter is coupled to the first data line and the first node; The second inverter is coupled to the second data line and the first node, and the first inverter and the second inverter are cross-coupled to each other; A head switch is configured to receive the third control signal and is coupled to a first voltage source and the first and second inverters via a first node; and A foot switch is configured to receive the first control signal and coupled to the second control circuit, the second node, and a second voltage source different from the first voltage source.

15. The memory circuit according to claim 10, further comprising: An output circuit, coupled between the first data line and the second data line and the first bit line and the second data line, is configured to write data to the group of memory cells during the write operation.

16. The memory circuit according to claim 10, further comprising: A second latch circuit, coupled to the first data line and the first latch circuit, is configured to transmit a first data line signal to the output node of the second latch circuit during the read operation in response to the second sense amplifier signal and the first sense amplifier signal.

17. The memory circuit according to claim 10, further comprising: A precharge / equalization circuit is configured to precharge the first data line and the second data line to a precharge voltage in response to a precharge control signal, and to equalize the voltages of the first data line and the second data line, the precharge / equalization circuit being coupled to the first data line and the second data line.

18. The memory circuit according to claim 17, wherein, The pre-charge / equalization circuit includes: The first P-type transistor includes: The first terminal of the first P-type transistor is configured to receive the precharge control signal; The second terminal of the first P-type transistor is coupled to the first data line; and The third terminal of the first P-type transistor is coupled to at least a first voltage source; The second P-type transistor includes: The first terminal of the second P-type transistor is configured to receive the precharge control signal; The second terminal of the second P-type transistor is coupled to the second data line; and The third terminal of the second P-type transistor is coupled to the first voltage source and the third terminal of the first P-type transistor; and The third P-type transistor includes: The first terminal of the third P-type transistor is configured to receive the precharge control signal; The second terminal of the third P-type transistor is coupled to the first data line; and The third terminal of the third P-type transistor is coupled to the second data line.

19. A method of operating a memory circuit, the method comprising: The first control circuit generates an inverting sense amplifier signal and a sense amplifier signal that is inverted by the inverting sense amplifier signal. In response to at least a second control signal or a third control signal, a first control signal is generated by a second control circuit; as well as In response to at least the sense amplifier signal, the second control signal, or the first clock signal, a first memory cell is read via a local input / output circuit, the first memory cell being coupled to the local input / output circuit, wherein reading the first memory cell includes: The switching circuit is disabled in response to the third control signal; In response to a precharge control signal, the first data line and the second data line are precharged to a precharge voltage via a precharge / equalization circuit, and the voltages of the first data line and the second data line are equalized. The switching circuit is coupled to the first data line and the second data line. A first latch circuit configured as a sense amplifier is enabled in response to at least the third control signal and the sense amplifier signal, the first latch circuit being coupled to the first data line and the second data line; In response to at least the third control signal and the sensing amplifier signal, the first data line signal and the second data line signal are sensed through the first latch circuit; In response to the sensing amplifier signal and the inverting sensing amplifier signal, the first data line signal is transmitted to the output node of the second latch circuit through the second latch circuit, and the second latch circuit is coupled to the first data line and the first latch circuit. In response to the sensing amplifier signal and the inverting sensing amplifier signal, the first data line signal is latched by the second latch circuit; and The first value of the data stored in the first memory cell is output through the local input / output circuit, wherein the first data line signal corresponds to the first value of the data stored in the first memory cell.

20. The method of claim 19, further comprising: In response to at least the third control signal, the first control signal, or the first clock signal, a second value of the data is written to the first memory unit via the local input / output circuit, wherein writing the second value of the data to the first memory unit includes: The switching circuit is enabled in response to the third control signal, and the first input signal and the second input signal are transmitted to the corresponding first data line and second data line. In response to at least the third control signal, the first latch circuit is set / enabled to be configured for writing to the latch and is in a transparent state; The switching circuit is disabled in response to the third control signal; In response to at least the third control signal and the first control signal, the first latch circuit configured as the write latch is set / enabled to be in a latched state; In response to a second clock signal and at least the first data line signal or the second data line signal, a first signal is set through a first NOR logic gate; and In response to the first signal, the first transistor is turned on, thereby setting the voltage of the first bit line or the second bit line, wherein the voltage of the first bit line or the second bit line corresponds to the second value of the data stored in the first memory cell.

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