Screening method for flash memory testing

Abstract

The application discloses a screening method for flash memory test, which comprises the following steps: step one, writing according to a first data pattern, wherein the data of each storage bit in the same row is the same, and the data of adjacent two rows is opposite; the data of adjacent two columns of storage chips in the same row is opposite; step two, short-circuit defect test, which comprises the following steps: step 21, selecting two bit lines and storage chips to be tested; step 22, selecting a row with storage data of 0 in the first selected storage chip as a selected row; step 23, selecting a selected storage bit for reading in the first selected storage chip, and the selected storage bit is close to the side of the second bit line; step 24, reading the selected storage bit, and setting the read amplification time between the pull-up time when there is a short-circuit defect and the pull-up time when there is no short-circuit defect, so as to screen the short-circuit defect. The application can screen the short-circuit defect of two adjacent bit lines located on both sides of the field oxide.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a screening method for flash memory testing. Background Technology

[0002] like Figure 1 The diagram shown is a schematic diagram of the circuit structure of a conventional flash memory storage cell 101; as shown... Figure 2 The diagram shown is a cross-sectional view of a storage cell 101 in a conventional flash memory. The conventional flash memory includes multiple storage cells 101, which are arranged to form an array structure of a memory.

[0003] Each of the aforementioned storage cells 101 employs a discrete-gate floating-gate device.

[0004] like Figure 2 As shown, the split-gate floating gate device includes: a symmetrical first source / drain region 205a and a second source / drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source / drain region 205a and the second source / drain region 205b, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0005] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0006] The separated gate floating gate device is an N-type device, and both the first source / drain region 205a and the second source / drain region 205b are composed of N+ regions.

[0007] The P-type doped channel region is located between the first source / drain region 205a and the second source / drain region 205b and is covered by each of the first gate structure and the second gate structure 103. The first source / drain region 205a and the second source / drain region 205b are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205a and the second source / drain region 205b or by further doping on the P-type semiconductor substrate 201.

[0008] The second source / drain region 205b of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BL1.

[0009] The first source-drain region 205a of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BL0.

[0010] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0011] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0012] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WL. Figure 1 In the above, the memory cell 101 includes two first gate structures, so the control gate line also includes two lines, denoted by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0013] Operations on the storage unit 101 include: erasing, programming, and reading. Figure 1 Taking the memory bit 'a' corresponding to the floating gate 104 in the first gate structure 102a as an example, please refer to Table 1 for the three operating voltages:

[0014] Table 1

[0015] Erase -7V 8V -7V 0V 0V Prog 8V 1.5V 5V 5V Idp Read 0V 3.5V 5V 0V Isense

[0016] In Table 1, Erase indicates erasure, Prog indicates programming (writing), Read indicates reading, Idp indicates bit line programming current, and Isense indicates sensing current (reading current). CG0 indicates the voltage of the control gate 105 of the first gate structure 102a, WL indicates the voltage of the word line gate 106 of the second gate structure 103, CG1 indicates the voltage of the control gate 105 of the first gate structure 102b, BL0 indicates the voltage of bit line BL0, and BL1 indicates the signal of bit line BL1.

[0017] As can be seen, during the erasure process, CG0 and CG1 are both -7V, WL is 8V, and BL0 and BL1 are both 0V. Thus, the large voltage difference between CG0 and WL enables the erasure of memory bit 'a'. Typically, the voltage difference between CG1 and WL also erases the memory bit corresponding to the floating gate 104 in the first gate structure 102b.

[0018] During programming (writing), WL is 1.5V and CG1 is 5V, which enables the channels controlled by the second gate structure 103 and the first gate structure 102b to conduct, respectively. CG0 is 8V, BL0 is 5V, and BL1 is supplied with programming current Idp. In this way, programming current Idp flows to BL0 through the channels controlled by the first gate structure 102b and the second gate structure 103. Under the action of the 5V voltage of BL0, hot carriers are formed. Under the high voltage of 8V of CG0, the hot carriers are injected into the floating gate 104 corresponding to the storage bit 'a'.

[0019] During reading, CG0 is 0V. Thus, the channel of the first gate structure 102a corresponding to CG0 is entirely determined by the state of the storage bit 'a'. The 3.5V voltage of WL and the 5V voltage of CG1 enable the channel controlled by the second gate structure 103 and the first gate structure 102b to conduct. BL0 is 0V (grounded), and BL1 can then read the read current, i.e., Isense. In the sensitive amplifier, the read current Isense is used as the storage cell current. The sensitive amplifier compares Isense with the reference current to read the data.

[0020] like Figure 3 The diagram shown is an array structure diagram of an existing flash memory; the array structure includes:

[0021] Multiple storage blocks 301, each of which is isolated by a corresponding field oxygen (not shown).

[0022] Each of the storage blocks 301 includes multiple rows of storage chips 302, and each of the storage chips 302 is isolated from the corresponding field oxygen.

[0023] Each of the aforementioned storage blocks 301 is an input / output block. Figure 3 The image shows three storage blocks 301, denoted as IO0 and IO1 respectively.

[0024] Each of the aforementioned storage blocks 301 includes two columns of the aforementioned storage slices 302; Figure 3 In the text, the two columns of storage chips 302 are also represented by Slice0 and Slice1, respectively.

[0025] Each of the aforementioned memory chips 302 includes two memory columns and three bit lines. For example, Figure 3 In the diagram, the three bit lines corresponding to Slice0 in IO0 are represented by BL0, BL1, and BL2, respectively, and the three bit lines corresponding to Slice1 in IO0 are represented by BL3, BL4, and BL5, respectively. Similarly, IO1 also displays six bit lines, represented by BL6, BL7, BL8, BL9, BL10, and BL11, respectively.

[0026] In each of the memory chips 302, the first source-drain region 205a of each memory cell 101 in the first memory column is connected to one of the first bit line and the second bit line, and the second source-drain region 205b is connected to the other of the first bit line and the second bit line. Similarly, the first source-drain region 205a of each memory cell 101 in the second memory column is connected to one of the third bit line and the second bit line, and the second source-drain region 205b is connected to the other of the third bit line and the second bit line. Figure 3 As shown, the second bit line in each of the memory chips 302 corresponds to the bit line in the middle position, such as bit line BL1 in Slice1, which is the second bit line.

[0027] Typically, in the array structure, each of the memory cells 101 in the same row is provided with multiple control gate lines (not shown) and corresponding word lines (not shown).

[0028] The number of control gate lines is the same as the number of the first gate structure, and the positions of each of the memory cells 101 in the same row are the same. The control gates 105 at the top of the memory bits are all connected to the same control gate line.

[0029] The number of word lines is the same as the number of the second gate structure 103, and the positions of each memory cell 101 in the same row are the same. The second gate structure 103 is connected to the same word line.

[0030] In the flash memory test, a checkerboard data pattern was used, such as... Figure 4 The image shows a checkerboard data graph in an existing flash memory testing method. In the checkerboard data graph, the data of two adjacent storage bits in the same row are opposite, and the data of two adjacent storage bits in the same column are also opposite. In the existing flash memory testing method, when Slice0 is selected, Slice1 is floating, and the existing checkerboard cannot filter out short circuit defects between BL2 and BL3, and between BL5 and BL6. Summary of the Invention

[0031] This invention provides a screening method for flash memory testing, which can screen for short-circuit defects on two adjacent bit lines located on both sides of the field oxygen.

[0032] In the flash memory testing screening method provided by the present invention, the flash memory includes multiple storage cells; each of the storage cells adopts a split-gate floating-gate device, and the multiple storage cells are arranged to form an array structure of flash memory.

[0033] The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged; a plurality of separate first gate structures with floating gates located between the first source-drain region and the second source-drain region; and a second gate structure located between the first gate structures; each of the first gate structures has a control gate located on top of the floating gate; each of the floating gates serves as a storage bit.

[0034] The array structure includes:

[0035] Multiple storage blocks, each isolated by a corresponding field oxygen.

[0036] Each of the storage blocks includes multiple rows of storage chips, and each storage chip is isolated from the corresponding field oxygen.

[0037] Each of the aforementioned memory chips includes two memory columns and three bit lines.

[0038] In each of the aforementioned memory chips, the first source-drain region of each memory cell in the first memory column is connected to one of the first bit line and the second bit line, and the second source-drain region is connected to the other of the first bit line and the second bit line. The first source-drain region of each memory cell in the second memory column is connected to one of the third bit line and the second bit line, and the second source-drain region is connected to the other of the third bit line and the second bit line.

[0039] The screening method includes identifying short-circuit defects on two adjacent bit lines located on both sides of each of the said oxygen fields; the screening method includes the following steps:

[0040] Step 1: Write the data according to the first data pattern, which includes:

[0041] In each of the aforementioned storage slices, the data stored in each of the storage bits in two storage cells in the same row is the same, and the data stored in each of the storage bits in the current row of the storage cell is opposite to the data stored in each of the storage bits in the adjacent row of the storage cell; the data stored in each storage bit is 0 or 1.

[0042] In the same row, the data stored in each storage bit of the storage cell of the current storage chip is opposite to the data stored in each storage bit of the storage cell of the adjacent storage chip.

[0043] Step 2: Conduct short-circuit defect testing, including:

[0044] Step 21: Select two bit lines located on both sides of the field oxygen and two adjacent columns of memory chips for the short-circuit defect test. Let the two selected bit lines be the first selected bit line and the second selected bit line, and the two selected memory chips be the first selected memory chip and the second selected memory chip. The first selected bit line is one of the first bit line and the third bit line of the first selected memory chip, and the second selected bit line is one of the first bit line and the third bit line of the second selected memory chip.

[0045] Step 22: Select a row in the first selected storage segment where the stored data is 0 as the selected row; in the second selected storage segment, the data of each storage bit located on the selected row is 1.

[0046] Step 23: Select a selected memory bit for reading in the first selected memory chip. The selected memory bit is the memory bit that is close to the second bit line in the first selected memory chip and the memory bit that is far away from the first selected bit line.

[0047] Step 24: Read the selected storage bit and determine whether the short-circuit defect exists based on the reading result.

[0048] During the reading process, the data of each storage bit in the selected row of the second selected storage chip is 1, so that the three bit lines of the second selected storage chip are connected together; the first selected bit line is connected to the bit line read node.

[0049] When the first and second selection lines are short-circuited, the bit line reading node has a first parasitic capacitance, which is determined by the first selection line.

[0050] When the short-circuit defect is present, the first and second selection lines are short-circuited, and the bit line read node has a second parasitic capacitance. The second parasitic capacitance is determined by the first selection line and the three bit lines of the second selected memory chip, and the second parasitic capacitance is greater than the first parasitic capacitance.

[0051] The pull-up time of the bit line read node from the initial voltage at the start of read amplification to the first voltage that causes the read voltage to flip is determined by the parasitic capacitance of the bit line read node. The first parasitic capacitance corresponds to the pull-up time as the first time, and the second parasitic capacitance corresponds to the pull-up time as the second time. The second time is greater than the first time. The read amplification time is set between the first time and the second time to achieve the screening of the short circuit defect.

[0052] A further improvement is that, in step 24, a pre-charging step is included before the read amplification, wherein the pre-charging causes the voltage of the bit line read node to reach the initial voltage; under the same pre-charging time and current conditions, the initial voltage corresponding to the second parasitic capacitance is less than the initial voltage corresponding to the first parasitic capacitance, thereby increasing the difference between the first time and the second time.

[0053] A further improvement is to set the pre-charge time in step 24 to less than 80% of the pre-charge time of the flash memory in normal operating mode, in order to reduce the initial voltage of the bit line read node.

[0054] A further improvement is that, in the array structure, each of the memory cells in the same row is provided with multiple control gate lines and corresponding word lines.

[0055] The number of control gate lines is the same as the number of the first gate structure, and the positions of each memory cell in the same row are the same. The control gates at the top of each memory bit are all connected to the same control gate line.

[0056] The number of word lines is the same as the number of the second gate structures, and the positions of each memory cell in the same row are the same. The second gate structures are all connected to the same word line.

[0057] A further improvement is that, in step 24, in the selected row, the control gate line corresponding to the selected memory bit is connected to a 0V voltage, the voltage connected to the control gate line corresponding to each non-selected memory bit causes the region segment of the channel controlled by the first gate structure corresponding to each non-selected memory bit to be turned on, and the voltage connected to each word line causes the region segment of the channel controlled by each second gate structure to be turned on.

[0058] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0059] A further improvement is that the separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions.

[0060] The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

[0061] A further improvement is that each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate.

[0062] The second gate structure is formed by stacking a word line gate dielectric layer and a word line gate.

[0063] A further improvement is that the floating gate is a polysilicon floating gate; the control gate is a polysilicon gate; and the word line gate is a polysilicon gate.

[0064] The tunneling dielectric layer is made of an oxide layer, the control gate dielectric layer is made of an oxide layer, and the word line gate dielectric layer is made of an oxide layer.

[0065] A further improvement is that each of the storage blocks includes two columns of the storage chips.

[0066] A further improvement is that each of the aforementioned storage blocks is an input / output block.

[0067] A further improvement is that the flash memory also includes a sensitive amplifier, and the bit line read node is connected to the sensitive amplifier.

[0068] A further improvement is that the sensitive amplifier has a reference current path, through which the reference current provided by the reference current path is used to pull up the voltage of the bit line read node.

[0069] A further improvement is that the sensitive amplifier also includes a pre-charge path; in the pre-charge step, the pre-charge path is turned on to pre-charge the bit line read node.

[0070] A further improvement is that the control terminal of the pre-charge path is connected to a pre-charge enable signal, and the pre-charge time is adjusted by setting the effective level time of the pre-charge enable signal.

[0071] To address short-circuit defects on two adjacent bit lines located on both sides of each field oxygen, this invention first specially sets the first data pattern written into the flash memory for testing; secondly, in the short-circuit defect test, the storage bit used to screen for short-circuit defects is selected according to the first data pattern, and the read amplification time is set during the reading of the selected storage bit, thereby enabling the detection of short-circuit defects. In other words, this invention can screen for short-circuit defects on two adjacent bit lines located on both sides of the field oxygen. Attached Figure Description

[0072] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0073] Figure 1 This is a schematic diagram of the circuit structure of an existing flash memory storage cell;

[0074] Figure 2 This is a cross-sectional structural diagram of an existing flash memory storage cell;

[0075] Figure 3This is a diagram of the existing flash memory array structure;

[0076] Figure 4 It is a checkerboard data graph in existing flash memory testing methods;

[0077] Figure 5 This is a flowchart of the screening method for flash memory testing according to an embodiment of the present invention;

[0078] Figure 6 This is the first data graph in the screening method for flash memory testing according to an embodiment of the present invention;

[0079] Figure 7 This is a timing curve during the reading process in the screening method for flash memory testing according to an embodiment of the present invention. Detailed Implementation

[0080] like Figure 4 The image shown is a checkerboard data graph from an existing flash memory testing screening method; please also refer to the structural diagram of the flash memory storage unit 101 in this embodiment of the invention. Figure 1 and Figure 2 Please refer to the array structure diagram shown below. Figure 3 As shown, in the screening method for flash memory testing in this embodiment of the invention, the flash memory includes multiple storage cells 101; each of the storage cells 101 adopts a split-gate floating-gate device, and the multiple storage cells 101 are arranged to form an array structure of flash memory.

[0081] like Figure 2 As shown, the split-gate floating gate device includes: a symmetrical first source / drain region 205a and a second source / drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source / drain region 205a and the second source / drain region 205b, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0082] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0083] The separated gate floating gate device is an N-type device, and both the first source / drain region 205a and the second source / drain region 205b are composed of N+ regions.

[0084] The P-type doped channel region is located between the first source / drain region 205a and the second source / drain region 205b and is covered by each of the first gate structure and the second gate structure 103. The first source / drain region 205a and the second source / drain region 205b are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205a and the second source / drain region 205b or by further doping on the P-type semiconductor substrate 201.

[0085] The second source / drain region 205b of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BL1.

[0086] The first source-drain region 205a of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BL0.

[0087] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0088] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0089] The floating gate 104 is a polysilicon floating gate 104; the control gate 105 is a polysilicon gate, and the word line gate is a polysilicon gate.

[0090] The material of the tunneling dielectric layer is an oxide layer, the material of the control gate 105 dielectric layer is an oxide layer, and the material of the word line gate dielectric layer is an oxide layer.

[0091] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WL. Figure 1 In the above, the memory cell 101 includes two first gate structures, so the control gate line also includes two lines, denoted by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0092] The array structure includes:

[0093] Multiple storage blocks 301, each of which is isolated by a corresponding field oxygen (not shown).

[0094] Each of the storage blocks 301 includes multiple rows of storage chips 302, and each of the storage chips 302 is isolated from the corresponding field oxygen.

[0095] In some embodiments, each of the storage blocks 301 is an input / output block. Figure 3 The image shows three storage blocks 301, denoted as IO0 and IO1 respectively.

[0096] Each of the aforementioned storage blocks 301 includes two columns of the aforementioned storage slices 302; Figure 3 In the text, the two columns of storage chips 302 are also represented by Slice0 and Slice1, respectively.

[0097] Each of the aforementioned memory chips 302 includes two memory columns and three bit lines. For example, Figure 3 In the diagram, the three bit lines corresponding to Slice0 in IO0 are represented by BL0, BL1, and BL2, respectively, and the three bit lines corresponding to Slice1 in IO0 are represented by BL3, BL4, and BL5, respectively. Similarly, IO1 also displays six bit lines, represented by BL6, BL7, BL8, BL9, BL10, and BL11, respectively.

[0098] In each of the memory chips 302, the first source-drain region 205a of each memory cell 101 in the first memory column is connected to one of the first bit line and the second bit line, and the second source-drain region 205b is connected to the other of the first bit line and the second bit line. Similarly, the first source-drain region 205a of each memory cell 101 in the second memory column is connected to one of the third bit line and the second bit line, and the second source-drain region 205b is connected to the other of the third bit line and the second bit line. Figure 3 As shown, the second bit line in each of the memory chips 302 corresponds to the bit line in the middle position, such as bit line BL1 in Slice1, which is the second bit line.

[0099] In this embodiment of the invention, in the array structure, each of the storage cells 101 in the same row is provided with multiple control gate lines (not shown) and corresponding word lines (not shown).

[0100] The number of control gate lines is the same as the number of the first gate structure, and the positions of each of the memory cells 101 in the same row are the same. The control gates 105 at the top of the memory bits are all connected to the same control gate line.

[0101] The number of word lines is the same as the number of the second gate structure 103, and the positions of each memory cell 101 in the same row are the same. The second gate structure 103 is connected to the same word line.

[0102] The screening method includes identifying short-circuit defects on two adjacent bit lines located on both sides of each of the said oxygen fields; the screening method includes the following steps:

[0103] Step 1, such as Figure 6As shown, data is written according to the first data pattern, which includes:

[0104] In each of the storage chips 302, the data stored in each storage bit of two storage cells 101 in the same row is the same, and the data stored in each storage bit of the storage cell 101 in the current row is opposite to the data stored in each storage bit of the storage cell 101 in the adjacent row; the data stored in each storage bit is 0 or 1.

[0105] In the same row, the data stored in each storage bit of the current storage cell 101 of the storage chip 302 is opposite to the data stored in each storage bit of the adjacent storage cell 101 of the storage chip 302.

[0106] Figure 6 Is Figure 3 Based on the array structure, data is added. With the row corresponding to each storage bit as the X coordinate and the corresponding column as the Y coordinate, the first data graph is shown in Table 2:

[0107] Table 2

[0108]

[0109] like Figure 6 As shown, 00 in the X coordinate represents the coordinate of the storage bit in the first row, and 01 represents the coordinate of the storage bit in the second row; 00 in the Y coordinate represents the coordinate of the storage bit in the first column, 01 in the Y coordinate represents the coordinate of the storage bit in the second column, 10 in the Y coordinate represents the coordinate of the storage bit in the third column, and 11 in the Y coordinate represents the coordinate of the storage bit in the fourth column.

[0110] Figure 6 The table shows the values ​​corresponding to Table 1 in IO0 in detail, while IO1 only shows the four data points corresponding to the X coordinate of 00, and the others are omitted.

[0111] Step 2: Conduct short-circuit defect testing, including:

[0112] Step 21: Select the two bit lines located on both sides of the field oxygen and the two adjacent columns of memory chips 302 that need to be tested for the short circuit defect. Let the two selected bit lines be the first selected bit line and the second selected bit line, and the two selected memory chips 302 be the first selected memory chip 302 and the second selected memory chip 302, respectively. The first selected bit line is one of the first bit line and the third bit line of the first selected memory chip 302, and the second selected bit line is one of the first bit line and the third bit line of the second selected memory chip 302.

[0113] In the method of the embodiments of the present invention, such as Figure 6As shown, to test whether the two adjacent bit lines between Slice0 and Slice1 are short-circuited, the two selected bit lines are bit lines BL2 and BL3, and the two columns of the selected memory chips 302 are Slice0 and Slice1, respectively. The first selected bit line is bit line BL2, and the second selected bit line is bit line BL3.

[0114] Step 22: Select a row in the first selected storage chip 302 where the stored data is 0 as the selected row; in the second selected storage chip 302, the data of each storage bit located on the selected row is 1.

[0115] In embodiments of the present invention, such as Figure 6 As shown, based on step 21, the row corresponding to the storage unit in the first row is further selected as the selected row.

[0116] Step 23: Select a selected storage bit for reading in the first selected storage chip 302. The selected storage bit is the storage bit that is close to the second bit line in the first selected storage chip 302 and the storage bit that is far away from the first selected bit line.

[0117] In embodiments of the present invention, such as Figure 6 As shown, based on step 23, since the selected rows include two rows corresponding to the storage bits, further selection of the storage bits is required. Figure 6 In the above, the storage bits corresponding to X coordinate 01 and Y coordinate 01 are the selected storage bits.

[0118] Step 24: Read the selected storage bit and determine whether the short-circuit defect exists based on the reading result.

[0119] During the reading process, the data of each storage bit in the selected row of the second selected storage chip 302 is 1, so that the three bit lines of the second selected storage chip 302 are connected together; the first selected bit line is connected to the bit line read node.

[0120] In this embodiment of the invention, in the selected row, the control gate line corresponding to the selected memory bit is connected to a 0V voltage, the voltage connected to the control gate line corresponding to each non-selected memory bit causes the region segment of the channel region controlled by the first gate structure corresponding to each non-selected memory bit to be turned on, and the voltage connected to each word line causes the region segment of the channel region controlled by each second gate structure 103 to be turned on. Figure 6Since the first row of memory cells is a selected row, the word lines and control gate lines on the selected row are shared. For the two memory cells in the selected row with Y coordinates of 10 and 11, the channel region controlled by the word line is turned on, and each memory bit is 1. Therefore, it is not necessary to apply voltage to the control gate line corresponding to each memory bit. The channel region corresponding to the bottom of the two memory bits is also turned on. In this way, the three bit lines of the second selected memory chip 302, namely bit lines BL3, BL4 and BL5, will be connected together.

[0121] When the first and second selection lines are short-circuited, the bit line reading node has a first parasitic capacitance, which is determined by the first selection line, i.e., bit line BL2.

[0122] When the short-circuit defect is present, the first and second selection lines are short-circuited, and the bit line read node has a second parasitic capacitance. The second parasitic capacitance is determined by the first selection line and the three bit lines of the second selected memory chip 302, i.e., by bit lines BL2 to BL5 together. The second parasitic capacitance is greater than the first parasitic capacitance.

[0123] The pull-up time of the bit line read node from the initial voltage at the start of read amplification to the first voltage that causes the read voltage to flip is determined by the parasitic capacitance of the bit line read node. The first parasitic capacitance corresponds to the pull-up time as the first time, and the second parasitic capacitance corresponds to the pull-up time as the second time. The second time is greater than the first time. The read amplification time is set between the first time and the second time to achieve the screening of the short circuit defect.

[0124] In this embodiment of the invention, a pre-charging step is further included before the read amplification. The pre-charging causes the voltage of the bit line read node to reach the initial voltage. Under the same pre-charging time and current conditions, the initial voltage corresponding to the second parasitic capacitance is less than the initial voltage corresponding to the first parasitic capacitance, thereby increasing the difference between the first time and the second time.

[0125] The precharge time in step 24 is set to less than 80% of the precharge time of the flash memory in normal operating mode to reduce the initial voltage of the bit line read node.

[0126] The flash memory also includes a sensitive amplifier, and the bit line read node is connected to the sensitive amplifier.

[0127] The sensitive amplifier has a reference current path, and the voltage of the bit line read node is pulled up by the reference current provided by the reference current path.

[0128] The sensitive amplifier further includes a pre-charge path; in the pre-charge step, the pre-charge path is turned on to pre-charge the bit line read node.

[0129] The control terminal of the pre-charge path is connected to a pre-charge enable signal, and the pre-charge time is adjusted by setting the effective level time of the pre-charge enable signal. For example... Figure 7 The figure shows the timing curves during the read process in the flash memory testing screening method of this embodiment of the invention. The curve Pre_ch represents the precharge enable signal, which is active high. That is, precharging will occur when the precharge enable signal is high and will stop when it is low. The precharge time is the high-level time width Tpre in the curve Pre_ch. Figure 7 The diagram also shows the curve Sense, which is the control signal curve for controlling read amplification. It can be seen that after the curve Pre_ch ends at a high level, the curve Sense is at a high level, and these sensitive amplifiers enter the read amplification stage to perform read amplification.

[0130] In the method of this invention embodiment, the short-circuit defect can be screened by directly setting Tpre to 80% of the pre-charge time in the existing normal read operation. Subsequently, the high-level time of the Sense signal, i.e., the read amplification time, can remain unchanged (i.e., the same as the read amplification time in the existing normal read operation), or it can be changed. In summary, in this embodiment of the invention, by setting the first data pattern and tightening the specific timing during the read process, the short-circuit failure defect can be screened.

[0131] For short-circuit defects on two adjacent bit lines located on both sides of each field oxygen, the embodiments of the present invention first specially set the first data pattern written into the flash memory for testing; secondly, in the short-circuit defect test, the storage bit used to screen for short-circuit defects is selected according to the first data pattern, and the read amplification time is set during the reading of the selected storage bit, so as to realize the detection of short-circuit defects. That is, the embodiments of the present invention can realize the screening of short-circuit defects on two adjacent bit lines located on both sides of the field oxygen.

[0132] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A screening method for flash memory testing, characterized in that: Flash memory includes multiple storage cells; each storage cell employs a discrete-gate floating-gate device, and the multiple storage cells are arranged to form an array structure of flash memory; The split-gate floating-gate device includes: a first source-drain region and a second source-drain region symmetrically arranged; a plurality of separate first gate structures with floating gates located between the first source-drain region and the second source-drain region; and a second gate structure located between the first gate structures; each of the first gate structures has a control gate located on top of the floating gate; each floating gate serves as a storage bit. The array structure includes: Multiple storage blocks, each of which is isolated by a corresponding field oxygen; Each of the aforementioned storage blocks includes multiple rows of storage chips, and each of the aforementioned storage chips is isolated from the corresponding field oxygen. Each of the aforementioned memory chips includes two memory columns and three bit lines; In each of the aforementioned memory chips, the first source-drain region of each memory cell in the first memory column is connected to one of the first bit line and the second bit line, and the second source-drain region is connected to the other of the first bit line and the second bit line; the first source-drain region of each memory cell in the second memory column is connected to one of the third bit line and the second bit line, and the second source-drain region is connected to the other of the third bit line and the second bit line. The screening method includes identifying short-circuit defects on two adjacent bit lines located on both sides of each of the said oxygen fields; the screening method includes the following steps: Step 1: Write the data according to the first data pattern, which includes: In each of the aforementioned storage slices, the data stored in each storage bit of two storage cells in the same row is the same, and the data stored in each storage bit of the storage cell in the current row is opposite to the data stored in each storage bit of the storage cell in the adjacent row; the data stored in each storage bit is 0 or 1; In the same row, the data stored in each storage bit of the current storage cell is opposite to the data stored in each storage bit of the adjacent storage cell; Step 2: Conduct short-circuit defect testing, including: Step 21: Select the two bit lines located on both sides of the field oxygen and the two adjacent columns of memory chips that need to be tested for the short circuit defect. Let the two selected bit lines be the first selected bit line and the second selected bit line, and the two selected memory chips be the first selected memory chip and the second selected memory chip, respectively. The first selected bit line is one of the first bit line and the third bit line of the first selected memory chip, and the second selected bit line is one of the first bit line and the third bit line of the second selected memory chip. Step 22: Select a row in the first selected storage segment where the stored data is 0 as the selected row; in the second selected storage segment, the data of each storage bit located on the selected row is 1; Step 23: Select a selected memory bit for reading in the first selected memory chip. The selected memory bit is the memory bit that is close to the second bit line in the first selected memory chip and the memory bit that is far away from the first selected bit line. Step 24: Read the selected storage bit and determine whether the short-circuit defect exists based on the reading result; During the reading process, the data of each storage bit in the selected row of the second selected memory chip is 1, so that the three bit lines of the second selected memory chip are connected together; the first selected bit line is connected to the bit line read node; When the first and second selection lines are short-circuited and disconnected, the bit line reading node has a first parasitic capacitance, which is determined by the first selection line. When the short-circuit defect is present, the first and second selection lines are short-circuited, and the bit line read node has a second parasitic capacitance. The second parasitic capacitance is determined by the first selection line and the three bit lines of the second selected memory chip, and the second parasitic capacitance is greater than the first parasitic capacitance. The pull-up time of the bit line read node from the initial voltage at the start of read amplification to the first voltage that causes the read voltage to flip is determined by the parasitic capacitance of the bit line read node. The first parasitic capacitance corresponds to the pull-up time as the first time, and the second parasitic capacitance corresponds to the pull-up time as the second time. The second time is greater than the first time. The read amplification time is set between the first time and the second time to achieve the screening of the short circuit defect.

2. The screening method for flash memory testing as described in claim 1, characterized in that: In step 24, a pre-charging step is included before the read amplification. The pre-charging causes the voltage of the bit line read node to reach the initial voltage. Under the same pre-charging time and current conditions, the initial voltage corresponding to the second parasitic capacitance is less than the initial voltage corresponding to the first parasitic capacitance, thereby increasing the difference between the first time and the second time.

3. The screening method for flash memory testing as described in claim 2, characterized in that: The precharge time in step 24 is set to less than 80% of the precharge time of the flash memory in normal operating mode to reduce the initial voltage of the bit line read node.

4. The screening method for flash memory testing as described in claim 1, characterized in that: In the array structure, each of the memory cells in the same row is provided with multiple control gate lines and corresponding word lines; The number of control gate lines is the same as the number of the first gate structure, and the positions of each memory cell in the same row are the same. The control gates at the top of the memory bits are all connected to the same control gate line. The number of word lines is the same as the number of the second gate structures, and the positions of each memory cell in the same row are the same. The second gate structures are all connected to the same word line.

5. The screening method for flash memory testing as described in claim 4, characterized in that: In step 24, in the selected row, the control gate line corresponding to the selected memory bit is connected to a 0V voltage, the voltage connected to the control gate line corresponding to each non-selected memory bit causes the region segment of the channel controlled by the first gate structure corresponding to each non-selected memory bit to be turned on, and the voltage connected to each word line causes the region segment of the channel controlled by each second gate structure to be turned on.

6. The screening method for flash memory testing as described in claim 1, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

7. The screening method for flash memory testing as described in claim 1, characterized in that: The separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions; The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

8. The screening method for flash memory testing as described in claim 1, characterized in that: Each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate; The second gate structure is formed by stacking a word line gate dielectric layer and a word line gate.

9. The screening method for flash memory testing as described in claim 8, characterized in that: The floating gate is a polysilicon floating gate; the control gate is a polysilicon gate; and the word line gate is a polysilicon gate. The tunneling dielectric layer is made of an oxide layer, the control gate dielectric layer is made of an oxide layer, and the word line gate dielectric layer is made of an oxide layer.

10. The screening method for flash memory testing as described in claim 1, characterized in that: Each of the aforementioned storage blocks includes two columns of the aforementioned storage slices.

11. The screening method for flash memory testing as described in claim 1, characterized in that: Each of the aforementioned storage blocks is an input / output block.

12. The screening method for flash memory testing as described in claim 2, characterized in that: The flash memory also includes a sensitive amplifier, and the bit line read node is connected to the sensitive amplifier.

13. The screening method for flash memory testing as described in claim 12, characterized in that: The sensitive amplifier has a reference current path, and the voltage of the bit line read node is pulled up by the reference current provided by the reference current path.

14. The screening method for flash memory testing as described in claim 12, characterized in that: The sensitive amplifier further includes a pre-charge path; in the pre-charge step, the pre-charge path is turned on to pre-charge the bit line read node.

15. The screening method for flash memory testing as described in claim 14, characterized in that: The control terminal of the pre-charge path is connected to a pre-charge enable signal, and the pre-charge time is adjusted by setting the effective level time of the pre-charge enable signal.

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