Wafer edge recognition method, wafer positioning method and device

Abstract

The application discloses a round edge recognition method, a wafer positioning method, a probe station, a wafer edge recognition device, an electronic device and a storage medium, and belongs to the technical field of wafer positioning, wherein an edge image of a wafer in a preset orientation is acquired; a shadow area formed by the wafer on a support is extracted from the edge image; an edge point of the shadow area is extracted; and an edge of the wafer in the preset orientation is obtained by fitting the edge point. The method replaces direct extraction of a wafer edge by extracting a shadow of the wafer on the support, and can utilize stability of optical imaging characteristics of the shadow area to improve stability of wafer edge extraction.

Description

Technical Field

[0001] This application belongs to the field of wafer positioning technology, specifically relating to a circular edge recognition method, a wafer positioning method, a probe station, a wafer edge recognition device, an electronic device, and a storage medium. Background Technology

[0002] Probe stations are primarily used in wafer testing. They place or insert electrical, optical, or RF probes onto specific test areas of the wafer, and transmit signals to test chip parameters via a testing machine. The most crucial indicator in probe station testing is testing accuracy, which directly impacts wafer testing efficiency and quality. Deviations in positioning accuracy can damage the wafer; therefore, ensuring accurate positioning is essential. Probe positioning mainly involves probe positioning and wafer positioning. A key step in wafer positioning is wafer centering. A common method for wafer centering is to determine the center point using three points. A camera captures the wafer edge, converts the edge pixel coordinates into physical coordinates, and fits a circular function to calculate the center position, which is the wafer center. A robotic arm then corrects and adjusts the wafer center position to ensure accuracy. Therefore, the accuracy of wafer edge extraction directly affects the positioning accuracy of the wafer center.

[0003] Conventional vision-based wafer edge detection methods directly identify wafer edges in images. However, their versatility is poor. The characteristics of wafer edges vary depending on the wafer's material and quality, and changes in lighting also affect edge extraction. Traditional image processing methods require frequent parameter adjustments to adapt to different wafers, while deep learning methods require large amounts of data and suffer from poor stability and maintainability. Currently, there is no publicly available wafer edge detection method that possesses both universality and stability. Therefore, a universal and stable wafer edge detection method is needed for wafer edge extraction. Summary of the Invention

[0004] The purpose of this application is to provide a circular edge recognition method, a wafer positioning method, a probe station, a wafer edge recognition device, an electronic device, and a storage medium to solve the problem of the difficulty in wafer edge recognition.

[0005] According to a first aspect of the embodiments of this application, a wafer edge recognition method is provided, the method comprising:

[0006] Acquire the edge image of the wafer at a preset orientation;

[0007] Extract the shadow region formed by the wafer on the support from the edge image;

[0008] Extract the edge points of the shaded area;

[0009] The edge points are fitted to obtain the edge of the wafer at the preset orientation.

[0010] In some alternative embodiments of this application, extracting the shadow region formed by the wafer on the support from the edge image includes:

[0011] Obtain the binary image of the edge image;

[0012] Determine whether there is an initial connected component in the binary image with a pixel size larger than a preset size. If so, select the shadow region from the initial connected component. If not, obtain the connected component with the largest pixel size from the binary image as the shadow region.

[0013] In some optional embodiments of this application, filtering the shaded region from the initial connected component includes:

[0014] Obtain the positioning point corresponding to the preset orientation from the edge image;

[0015] Obtain the first distance between the initial connected component and the positioning point;

[0016] The initial connected component with the smallest first distance is designated as the shaded region.

[0017] In some optional embodiments of this application, obtaining the first distance between the initial connected component and the positioning point includes:

[0018] Obtain the minimum enclosing moment of the initial connected component;

[0019] The distance between the center of the minimum enclosing moment and the positioning point is obtained as the first distance.

[0020] In some optional embodiments of this application, obtaining the positioning point corresponding to the preset orientation from the edge image includes:

[0021] When the preset orientation is upward, the upper left corner or the upper right corner is obtained as the positioning point;

[0022] When the preset orientation is down, the lower left or lower right corner is obtained as the positioning point;

[0023] When the preset orientation is left, the upper left corner or the lower left corner is obtained as the positioning point;

[0024] When the preset orientation is right, the upper right corner or the lower right corner is obtained as the positioning point.

[0025] In some optional embodiments of this application, extracting the edge points of the shaded region includes:

[0026] Extract the edge point from the edge of the shaded area near the edge of the support.

[0027] In some alternative embodiments of this application, extracting the edge points from the shadowed area near the edge of the support includes:

[0028] The pixel values ​​of the shadow region in the edge image are adjusted to a first preset pixel value, and the pixel values ​​of the remaining regions are adjusted to a second pixel value to obtain a shadow binary image;

[0029] When the preset orientation is up, the shadow binary image is traversed from top to bottom to obtain the first pixel value of the first preset pixel value in each column as the edge point;

[0030] When the preset orientation is down, the shadow binary image is traversed from bottom to top to obtain the first pixel value of the first preset pixel value in each column as the edge point;

[0031] When the preset orientation is left, the shadow binary image is traversed from left to right to obtain the first pixel value of the first preset pixel value in each row as the edge point;

[0032] When the preset orientation is right, the shadow binary image is traversed from right to left to obtain the first pixel value of each row as the edge point.

[0033] In some optional embodiments of this application, fitting the edge points to obtain the edge of the wafer at a preset orientation includes:

[0034] An initial straight line is obtained by fitting an initial straight line to the edge points;

[0035] Obtain the second distance between each edge point and the initial line;

[0036] The edge points whose second distance is less than or equal to a preset distance are selected as target edge points;

[0037] The edge of the wafer at a preset orientation is obtained by fitting a target straight line to the target edge point.

[0038] According to a second aspect of the embodiments of this application, a wafer positioning method is provided, comprising:

[0039] A wafer edge recognition method as described in any embodiment of the first aspect is used to obtain the edges of the wafer at at least three different preset orientations;

[0040] The wafer center position is obtained based on the edge to complete wafer positioning.

[0041] According to a third aspect of the embodiments of this application, a probe station is provided, which uses a wafer edge recognition method as described in any embodiment of the first aspect to identify wafer edges.

[0042] According to a fourth aspect of the embodiments of this application, a wafer edge recognition device is provided, comprising:

[0043] The first acquisition module is used to acquire the edge image of the wafer at a preset orientation;

[0044] The second acquisition module is used to extract the shadow area formed by the wafer on the support from the edge image;

[0045] The third acquisition module is used to extract the edge points of the shadowed area;

[0046] The fitting module is used to fit the edge points to obtain the edge of the wafer in a preset orientation.

[0047] According to a fifth aspect of the embodiments of this application, an electronic device is provided, which may include:

[0048] processor;

[0049] Memory used to store processor-executable instructions;

[0050] The processor is configured to execute instructions to implement the wafer edge recognition method as shown in any embodiment of the first aspect.

[0051] The above-mentioned technical solution of this application has the following beneficial technical effects:

[0052] The wafer edge recognition method provided in this application extracts the shadow of the wafer on the support instead of directly extracting the wafer edge. It can improve the stability of wafer edge extraction by utilizing the stability of the optical imaging features of the shadow area. Attached Figure Description

[0053] Figure 1 This is a schematic flowchart of a wafer edge recognition method according to an exemplary embodiment of this application;

[0054] Figure 2 This is an edge image with a preset orientation of "up" in an exemplary embodiment of this application;

[0055] Figure 3 This is an edge image with a preset orientation of right in an exemplary embodiment of this application;

[0056] Figure 4 This is an edge image with a preset orientation in an exemplary embodiment of this application;

[0057] Figure 5This is a flowchart illustrating step S102 in an exemplary embodiment of this application;

[0058] Figure 6 This is a binary graph in an exemplary embodiment of this application;

[0059] Figure 7 This is a flowchart illustrating step S1023 in an exemplary embodiment of this application;

[0060] Figure 8 This is a flowchart illustrating step S10232 in an exemplary embodiment of this application;

[0061] Figure 9 This is a flowchart illustrating step S10231 in an exemplary embodiment of this application;

[0062] Figure 10 This is a flowchart illustrating step S103 in an exemplary embodiment of this application;

[0063] Figure 11 This is a shaded binary image in an exemplary embodiment of this application;

[0064] Figure 12 This is a schematic diagram of edge point extraction when the preset orientation is upward, as shown in an exemplary embodiment of this application;

[0065] Figure 13 This is a schematic diagram of edge point extraction when the preset orientation is downward in an exemplary embodiment of this application;

[0066] Figure 14 This is a schematic diagram of edge point extraction when the preset orientation is left, in an exemplary embodiment of this application;

[0067] Figure 15 This is a schematic diagram of edge point extraction when the preset orientation is right in an exemplary embodiment of this application;

[0068] Figure 16 This is a flowchart illustrating step S104 in an exemplary embodiment of this application;

[0069] Figure 17 This is a schematic flowchart of a wafer positioning method according to an exemplary embodiment of this application;

[0070] Figure 18 This is a schematic diagram of a wafer edge recognition device structure according to an exemplary embodiment of this application;

[0071] Figure 19 This is a schematic diagram of the electronic device structure in an exemplary embodiment of this application;

[0072] Figure 20 This is a schematic diagram of the hardware structure of an electronic device in an exemplary embodiment of this application. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0074] The accompanying drawings illustrate layer structure diagrams according to embodiments of this application. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0075] Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0076] In the description of this application, it should be noted that the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0077] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0078] Research has revealed that due to differences in wafer material and quality, wafer edges exhibit significant variations in image features. Directly extracting wafer edge contours leads to considerable interference and instability. Existing image processing algorithms suffer from poor versatility, while deep learning models require vast amounts of sample data and are difficult to maintain, failing to achieve ideal results. Therefore, a redesigned algorithm is necessary to improve compatibility and stability. Wafer edges are highly susceptible to light source influences. Current segmentation methods, relying solely on thresholding, fail to provide stable results and require frequent parameter adjustments due to variations in light intensity and / or uneven lighting, making maintenance challenging. Thus, a redesigned segmentation method is needed to enhance adaptability to different light sources. Current techniques extract wafer edges by fitting a linear function to describe the edge after obtaining edge points. However, wafer edges may contain defects or burrs, causing the fitted line to be suboptimal. Therefore, outlier removal is required to improve the accuracy of edge calculations.

[0079] The wafer edge recognition method, wafer edge recognition device, electronic device, and storage medium provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0080] like Figure 1 As shown, in a first aspect of this application embodiment, a wafer edge recognition method is provided, which may include:

[0081] Step S101: Obtain the edge image of the wafer at a preset orientation;

[0082] Step S102: Extract the shadow area formed by the wafer on the support from the edge image;

[0083] Step S103: Extract the edge points of the shaded area;

[0084] Step S104: Fit the edge points to obtain the edge of the wafer in the preset orientation.

[0085] In this embodiment, the preset orientation can be any of the following: up, down, left, or right. The support can be a tray with a uniform color and smooth surface; the tray can be white. After the wafer is placed on the top surface of the tray, an image of the wafer's upper, lower, left, or right edge position under a preset light source is captured by a camera as the edge image. The preset light source can be located directly above the wafer. The projection of the wafer onto the top surface of the tray forms a shadow area. Figure 2 , 3As shown in Figure 4, in the edge image, the shadow area is displayed as a black border between the tray and the wafer. The shadow area surrounding the wafer edge has a uniform width. Finding the shadow area is more stable than directly finding the wafer edge. This embodiment helps to reduce the influence of the light source and the interference of abnormal points on the wafer and tray surfaces by finding the shadow area instead of directly extracting the wafer edge. It can utilize the stability of the optical imaging features of the shadow area to improve the stability of wafer edge extraction.

[0086] like Figure 5 As shown, in some embodiments, step S102 may include:

[0087] Step S1021: Obtain the binary image of the edge image;

[0088] Step S1022: Determine whether there exists an initial connected component in the binary image whose pixel size is larger than a preset size;

[0089] Step S1023: If the judgment result of step S1022 is yes, then the shaded region is selected from the initial connected component;

[0090] Step S1024: If the judgment result of step S1022 is negative, then obtain the connected component with the largest pixel size from the binary image as the shadow region.

[0091] In this embodiment, the edge image is first converted to grayscale to obtain a grayscale image. The operation of converting a color image to a grayscale image is called image grayscale conversion. Then, local adaptive thresholding is performed on the grayscale image to obtain a binary image. The principle of local adaptive segmentation is to calculate the mean, median, and Gaussian weighted average of the grayscale image to determine the threshold, achieving adaptability to changes in brightness. The binary image consists of a first pixel value and a second pixel value. The first pixel value is greater than the second pixel value. The first pixel value can be 255, which is displayed as a white area in the binary image, and the second pixel value can be 0, which is displayed as a black area in the binary image. Figure 6As shown, in the binary image, the first pixel value represents the low-brightness region (shadow region) in the edge image, and the second pixel value represents the high-brightness region. Connected white pixels in the binary image form a connected component. The pixel size represents the number of pixels. The preset size represents the number of pixels in the shadow region. Selecting initial connected components with pixel sizes larger than the preset size from the binary image enables area filtering, which filters out smaller dark interferences on the wafer or tray. When multiple initial connected components are selected, further orientation filtering can be performed based on a preset orientation to select the shadow region. Unstable light sources may cause initial connected component filtering to fail. Since theoretically, the connected component pixel area corresponding to the shadow region is the largest, when no initial connected component with the correct size is found, the connected component with the largest pixel area can be directly used as the shadow region. This embodiment effectively improves the adaptability of wafer edge recognition to illumination by extracting shadow regions using binary images, and through size and orientation filtering, it effectively ensures the accuracy of shadow region extraction.

[0092] like Figure 7 As shown, in some embodiments, step S1023 may include:

[0093] Step S10231: Obtain the positioning point corresponding to the preset orientation from the edge image;

[0094] Step S10232: Obtain the first distance between the initial connected component and the positioning point;

[0095] Step S10233: Select the initial connected component with the smallest first distance as the shaded region.

[0096] In this embodiment, the positional relationship between the wafer and the shadow region is determined based on a preset orientation. The initial connected components are then filtered by orientation, and the positioning point can be a point on the edge of the edge image located at the preset orientation. Since the support component has a uniform and smooth color, noise is typically located within the wafer. Compared to the initial connected components within other wafers, the shadow region is closest to the positioning point. Therefore, the shadow region can be found by comparing the first distances between multiple initial connected components and the positioning point.

[0097] like Figure 8 As shown, in some embodiments, step S10232 may include:

[0098] Step S102321: Obtain the minimum enclosing moment of the initial connected components;

[0099] Step S102322: Obtain the distance between the center of the minimum enclosing moment and the positioning point as the first distance.

[0100] In this embodiment, the minimum bounding moment is the minimum bounding rectangle of the initial connected domain. The center of the minimum bounding rectangle can represent the center of the initial connected domain. Therefore, the first distance can be obtained by obtaining the distance between the center of the minimum bounding moment and the positioning point.

[0101] like Figure 9 As shown, in some embodiments, step S10231 may include:

[0102] When the preset orientation is up, the top left or top right corner is used as the positioning point;

[0103] When the preset orientation is down, the bottom left or bottom right corner is used as the positioning point;

[0104] When the preset orientation is left, the top left corner or bottom left corner is used as the positioning point;

[0105] When the preset orientation is right, the upper right corner or lower right corner is used as the positioning point.

[0106] In this embodiment, since the tray is relatively flat and glossy, there is little interference from dark materials. Interfering materials are typically located on the wafer surface; therefore, the shadowed area is usually the initial connected region closest to the image corner closest to the tray. Based on the input preset orientation data, the orientation of the wafer in the edge image is determined, thereby determining the positional relationship between the wafer, the tray, and the shadowed area. When the preset orientation is "up," the wafer is below the shadowed area, and the upper left or upper right corner can be used as the positioning point. When the preset orientation is "down," the wafer is above the shadowed area, and the lower left or lower right corner can be used as the positioning point. When the preset orientation is "left," the wafer is to the right of the shadowed area, and the upper left or lower left corner can be used as the positioning point. When the preset orientation is "right," the wafer is to the left of the shadowed area, and the upper right or lower right corner can be used as the positioning point. This embodiment can determine the positional distribution of the wafer and the shadowed area through the preset orientation, thereby finding positioning points whose distance from the shadowed area is less than the distance from the wafer.

[0107] Because the tray has a uniform and smooth color, the boundary between the shaded area and the tray is clearer. Therefore, in some embodiments, extracting edge points from the edge of the shaded area near the support helps to improve the accuracy of edge point extraction.

[0108] like Figure 10 As shown, in some embodiments, step S103 may include:

[0109] Step S1031: Adjust the pixel values ​​of the shadow areas in the edge image to the first preset pixel values, and adjust the pixel values ​​of the remaining areas to the second pixel values ​​to obtain a shadow binary image;

[0110] Step S1032: When the preset orientation is up, perform column traversal on the shadow binary image from top to bottom to obtain the first pixel value of each column as the first preset pixel value as the edge point;

[0111] When the preset orientation is down, the shadow binary image is traversed from bottom to top to obtain the first pixel value of the first preset pixel value in each column as the edge point;

[0112] When the preset orientation is left, the shadow binary image is traversed from left to right to obtain the first pixel value of the first preset pixel value in each row as the edge point.

[0113] When the preset orientation is right, the shadow binary image is traversed from right to left to obtain the first pixel value of each row as the edge point.

[0114] In this embodiment, as Figure 11 As shown, the first preset pixel value can be 255, and the shadow area will be displayed in white. First, an edge point collection container is set, and then the edge points of the shadow area at a preset location are collected using the edge point collection container. For example... Figure 12 As shown, when the preset orientation is upward, the upper edge of the shadow area is the boundary of the wafer projection onto the tray. Using a column traversal method, each column of the shadow binary image is traversed from top to bottom. If a pixel with a value of 255 is encountered, its pixel coordinates are recorded and stored in the first edge point collection container. After the traversal is complete, the points in the first edge point collection container are the edge points of the shadow area near the support. Figure 13 As shown, when the preset orientation is downward, the lower edge of the shadow area is the boundary of the wafer projection onto the tray. Using a column traversal method, each column of the shadow binary image is traversed from bottom to top. If a pixel with a value of 255 is encountered, its pixel coordinates are recorded and stored in the second edge point collection container. After the traversal is complete, the points in the second edge point collection container are the edge points of the shadow area near the support. Figure 14 As shown, when the preset orientation is left, the left edge of the shadow area is the boundary of the wafer projection onto the tray. A row traversal is used, iterating through each row of the shadow binary image from left to right. If a pixel with a value of 255 is encountered, its pixel coordinates are recorded and stored in the third edge point collection container. After the traversal is complete, the points in this third edge point collection container represent the edge points of the shadow area near the support. Figure 15As shown, when the preset orientation is right, the right edge of the shadow area is the boundary of the wafer projection on the tray. The row traversal method is used to traverse each row of the shadow binary image from right to left. If a pixel with a pixel value of 255 is traversed, the pixel coordinates of that position are recorded and stored in the fourth edge point collection container. After the traversal is completed, the points in the fourth edge point collection container are the edge points of the shadow area near the support.

[0115] like Figure 16 As shown, in some embodiments, step S104 may include:

[0116] Step S1041: Perform initial line fitting on the edge points to obtain the initial line;

[0117] Step S1042: Obtain the second distance between each edge point and the initial line;

[0118] Step S1043: Obtain edge points whose second distance is less than or equal to a preset distance as target edge points;

[0119] Step S1044: Perform target line fitting on the target edge points to obtain the edge of the wafer in the preset orientation.

[0120] In this embodiment, edge points may contain abnormal points due to edge burrs, edge defects, and lighting. An initial straight line is obtained through preliminary fitting. Then, based on the distance between the edge points and the initial straight line, abnormal points that are far from the initial straight line can be eliminated. Refitting the target edge points after removing abnormal points helps to improve the accuracy of wafer edge positioning.

[0121] like Figure 17 As shown, in a second aspect of the embodiments of this application, a wafer positioning method is provided, comprising:

[0122] Step S201: Use a wafer edge recognition method according to any embodiment of the first aspect to obtain the edges of the wafer at at least three different preset orientations;

[0123] Step S202: Obtain the position of the wafer center based on the edge to complete wafer positioning.

[0124] In this embodiment, edge images are acquired from any three of the wafer's top, bottom, left, and right edges using a camera, and preset orientations of top, bottom, left, and right are recorded. The edge positions in the three edge images are acquired respectively, and then a circle is fitted based on the three edge positions to obtain the center of the circle, which is the position of the wafer center. The position of the wafer center is then used as the wafer position.

[0125] In a third aspect of the embodiments of this application, a probe station is provided, which identifies wafer edges using a wafer edge recognition method according to any embodiment of the first aspect or positions wafers using a wafer positioning method according to any embodiment of the second aspect.

[0126] like Figure 18 As shown, in a fourth aspect of the embodiments of this application, a wafer edge recognition device is provided, comprising:

[0127] The first acquisition module 11 is used to acquire the edge image of the wafer at a preset orientation;

[0128] The second acquisition module 12 is used to extract the shadow area formed by the wafer on the support from the edge image;

[0129] The third acquisition module 13 is used to extract the edge points of the shadow area;

[0130] Fitting module 14 is used to fit edge points to obtain the edge of the wafer in a preset orientation.

[0131] The wafer edge recognition device in this application embodiment can also be a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, mobile electronic devices can be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc., while non-mobile electronic devices can be servers, network-attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This application embodiment does not impose specific limitations.

[0132] The wafer edge recognition device provided in this application embodiment can implement all the processes of the wafer edge recognition method provided in any of the above embodiments. To avoid repetition, it will not be described again here.

[0133] Optionally, such as Figure 19 As shown, this application embodiment also provides an electronic device 1100, including a processor 1101, a memory 1102, and a program or instructions stored in the memory 1102 and executable on the processor 1101. When the program or instructions are executed by the processor 1101, they implement the various processes of the above-described wafer edge recognition method embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0134] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0135] Figure 20 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0136] The electronic device 1200 includes, but is not limited to, components such as: radio frequency unit 1201, network module 1202, audio output unit 1203, input unit 1204, sensor 1205, display unit 1206, user input unit 1207, interface unit 1208, memory 1209, and processor 1210.

[0137] Those skilled in the art will understand that the electronic device 1200 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1210 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 16 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0138] It should be understood that, in this embodiment, the input unit 1204 may include a graphics processing unit (GPU) 12041 and a microphone 12042. The GPU 12041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1206 may include a display panel 12061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, etc. The user input unit 1207 includes a touch panel 12071 and other input devices 12072. The touch panel 12071 is also called a touch screen. The touch panel 12071 may include a touch detection device and a touch controller. Other input devices 12072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, joysticks, etc., which will not be described in detail here. The memory 1209 can be used to store software programs and various data, including but not limited to applications and operating systems. Processor 1210 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into processor 1210.

[0139] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described wafer edge recognition method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0140] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0141] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described wafer edge recognition method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0142] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0143] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0144] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0145] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A wafer edge recognition method, characterized by, include: Acquire the edge image of the wafer at a preset orientation; Extract the shadow region formed by the wafer on the support from the edge image; Extract the edge points of the shaded area; Fit the edge points to obtain the edge of the wafer at the preset orientation; Extracting the edge points of the shaded area includes: Extract the edge point from the edge of the shadowed area near the edge of the support; Extracting the edge point from the edge of the shaded area near the edge of the support includes: The pixel values ​​of the shadow region in the edge image are adjusted to a first preset pixel value, and the pixel values ​​of the remaining regions are adjusted to a second pixel value to obtain a shadow binary image; When the preset orientation is up, the shadow binary image is traversed from top to bottom to obtain the first pixel value of the first preset pixel value in each column as the edge point; When the preset orientation is down, the shadow binary image is traversed from bottom to top to obtain the first pixel value of the first preset pixel value in each column as the edge point; When the preset orientation is left, the shadow binary image is traversed from left to right to obtain the first pixel value of the first preset pixel value in each row as the edge point; When the preset orientation is right, the shadow binary image is traversed from right to left to obtain the first pixel value of each row as the edge point. Fitting the edge points to obtain the edge of the wafer at a preset orientation includes: An initial straight line is obtained by fitting an initial straight line to the edge points; Obtain the second distance between each edge point and the initial line; The edge points whose second distance is less than or equal to a preset distance are selected as target edge points; The edge of the wafer at a preset orientation is obtained by fitting a target straight line to the target edge point.

2. The wafer edge recognition method of claim 1, wherein Extracting the shadow region formed by the wafer on the support from the edge image includes: Obtain the binary image of the edge image; Determine whether there is an initial connected component in the binary image with a pixel size larger than a preset size. If so, select the shadow region from the initial connected component. If not, obtain the connected component with the largest pixel size from the binary image as the shadow region.

3. The wafer edge recognition method of claim 2, wherein Filtering the shaded region from the initial connected component includes: Obtain the positioning point corresponding to the preset orientation from the edge image; Obtain the first distance between the initial connected component and the positioning point; The initial connected component with the smallest first distance is taken as the shaded region.

4. The wafer edge recognition method of claim 3, wherein Obtaining the first distance between the initial connected component and the positioning point includes: Obtain the minimum enclosing moment of the initial connected component; The distance between the center of the minimum enclosing moment and the positioning point is obtained as the first distance.

5. The wafer edge recognition method of claim 3, wherein Obtaining the positioning point corresponding to the preset orientation from the edge image includes: When the preset orientation is upward, the upper left corner or the upper right corner is obtained as the positioning point; When the preset orientation is down, the lower left or lower right corner is obtained as the positioning point; When the preset orientation is left, the upper left corner or the lower left corner is obtained as the positioning point; When the preset orientation is right, the upper right corner or the lower right corner is obtained as the positioning point.

6. A wafer positioning method, comprising: A wafer edge recognition method according to any one of claims 1-5 is used to obtain the edge of the wafer in at least three different preset orientations; The wafer center position is obtained based on the edge to complete wafer positioning.

7. A probe station characterized by The wafer edge is identified using a wafer edge identification method according to any one of claims 1-5.

8. A wafer edge recognition apparatus, characterized by comprising: include: The first acquisition module is used to acquire the edge image of the wafer at a preset orientation; The second acquisition module is used to extract the shadow area formed by the wafer on the support from the edge image; The third acquisition module is used to extract the edge points of the shadowed area; A fitting module is used to fit the edge points to obtain the edge of the wafer in a preset orientation; Extracting the edge points of the shaded area includes: Extract the edge point from the edge of the shadowed area near the edge of the support; Extracting the edge point from the edge of the shaded area near the edge of the support includes: The pixel values ​​of the shadow region in the edge image are adjusted to a first preset pixel value, and the pixel values ​​of the remaining regions are adjusted to a second pixel value to obtain a shadow binary image; When the preset orientation is up, the shadow binary image is traversed from top to bottom to obtain the first pixel value of the first preset pixel value in each column as the edge point; When the preset orientation is down, the shadow binary image is traversed from bottom to top to obtain the first pixel value of the first preset pixel value in each column as the edge point; When the preset orientation is left, the shadow binary image is traversed from left to right to obtain the first pixel value of the first preset pixel value in each row as the edge point; When the preset orientation is right, the shadow binary image is traversed from right to left to obtain the first pixel value of each row as the edge point. Fitting the edge points to obtain the edge of the wafer at a preset orientation includes: An initial straight line is obtained by fitting an initial straight line to the edge points; Obtain the second distance between each edge point and the initial line; The edge points whose second distance is less than or equal to a preset distance are selected as target edge points; The edge of the wafer at a preset orientation is obtained by fitting a target straight line to the target edge point.

9. An electronic device, comprising: include: A processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement a wafer edge identification method as described in any one of claims 1-5 or a wafer positioning method as described in claim 6.

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