Structure and preparation method of compound semiconductor and carbon nanotube monolithic integrated device

Abstract

This invention relates to the structure and fabrication method of a monolithic integrated device combining a compound semiconductor and carbon nanotubes. The structure includes: a substrate layer, a nucleation layer, a buffer layer, a channel layer, a barrier layer, an electrical isolation layer, a carbon nanotube device disposed on the barrier layer, a first source and a first drain spaced apart on the barrier layer, a passivation layer disposed on the first source, the first drain, and the barrier layer on the other side of the electrical isolation layer, and a first gate disposed within a gate trench in the passivation layer and partially on the passivation layer. This invention fabricates N-channel and P-channel devices with high switching speeds and significantly saves CMOS circuit chip area compared to traditional discrete packaging structures on a PCB board, while simultaneously improving the performance of the circuit in processing digital signals.

Description

Technical Field

[0001] This invention relates to the field of radio frequency application technology, specifically to the structure and fabrication method of a monolithic integrated device of compound semiconductor and carbon nanotube. Background Technology

[0002] III-V compound semiconductors, such as GaN, GaAs, and InP, are second- and third-generation semiconductors with advantages including high electron mobility, large band gaps with a wide continuously modulated range, good uniformity in large-size crystals, good lattice matching, low power consumption, and relatively simple fabrication processes. However, in the post-Moore's Law era, the semiconductor industry faces enormous technical and engineering challenges, while the demand for data computing and storage capabilities in the information society is increasing daily. Therefore, while reaching the bottlenecks of silicon-based technology, the semiconductor field is increasingly focusing on new materials and device systems to extend Moore's Law. Among many new material structures, carbon nanotubes (CNTs) have also attracted widespread attention due to their unique quasi-one-dimensional structure and excellent electrical properties.

[0003] Existing methods for realizing carbon nanotube CMOS integrated circuits primarily involve a doped approach on the same Si substrate, using Pd contacts to implement P-type transistors and Sc contacts to implement N-type transistors, with symmetrical performance matching between the P-type and N-type transistors, thus enabling lateral realization of CMOS integrated circuits on the substrate. Currently, the method for integrating high electron mobility transistors and carbon nanotubes is discrete packaging technology, which involves fabricating two separate devices, soldering them onto a PCB (Printed Circuit Board), and then interconnecting them via external leads for integration.

[0004] Based on existing integration technologies, the integration method using external interconnect leads significantly increases the manufacturing complexity. It also introduces numerous parasitic parameters, reducing efficiency and not only increasing the chip's size but also severely impacting the performance of the RF front-end module. Furthermore, the incompatibility between carbon nanotubes and high electron mobility transistors in discrete packaging reduces the feasibility of this integrated device structure. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a structure and fabrication method for a monolithic integrated device combining a compound semiconductor and carbon nanotubes. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] A device structure integrating a compound semiconductor and a carbon nanotube monolith, comprising:

[0007] Substrate layer;

[0008] A nucleation layer is disposed on the substrate layer;

[0009] A buffer layer is disposed on the nucleation layer, and a groove is provided in the middle region of the buffer layer;

[0010] A channel layer is disposed on the upper surface of the buffer layer, excluding the portion of the groove;

[0011] A barrier layer is disposed on the upper surface of the channel layer, excluding the portion of the groove.

[0012] An electrical isolation layer is disposed in the groove, and the upper surface of the electrical isolation layer is located above the barrier layer;

[0013] A carbon nanotube device is disposed on the barrier layer and located on one side of the electrical isolation layer;

[0014] A first source and a first drain are disposed at intervals on the barrier layer and located on the other side of the electrical isolation layer, and the sidewall of the first drain is in contact with the sidewall of the electrical isolation layer.

[0015] A passivation layer is disposed on the first source, the first drain, and the barrier layer located on the other side of the electrical isolation layer;

[0016] A first gate is disposed within the gate trench of the passivation layer and on a portion of the passivation layer.

[0017] In one embodiment of the present invention, the carbon nanotube device includes:

[0018] Carbon nanotube array;

[0019] The second source and the second drain are disposed at intervals on the carbon nanotube array, and the sidewall of the second drain is in contact with the sidewall of the electrical isolation layer.

[0020] A dielectric layer is disposed on the carbon nanotube array, a portion of the second source electrode, and a portion of the second drain electrode;

[0021] A second gate is disposed on the dielectric layer.

[0022] In one embodiment of the present invention, the first drain and the second drain are connected by a first interconnect metal, the first gate and the second gate are connected by a second interconnect metal, the first source is connected to the ground terminal through a through-hole on the back, and the second source is connected to the power supply terminal.

[0023] In one embodiment of the present invention, the first source, the first drain, the second source, and the second drain are all extended to the channel layer by annealing, so that the first source, the first drain, the second source, and the second drain are in ohmic contact with the heterojunction channel, wherein the channel layer and the barrier layer form a heterojunction channel.

[0024] In one embodiment of the invention, the materials of the buffer layer and the channel layer comprise group III-V compounds.

[0025] In one embodiment of the present invention, the buffer layer and the channel layer are made of the same material, and the material of the buffer layer and the channel layer includes any one of GaN, GaAs, and InP.

[0026] In one embodiment of the present invention, the device structure further includes electrical isolation of the active region, which is formed by ion implantation into the end barrier layer, the channel layer and a buffer layer to a certain depth.

[0027] An embodiment of the present invention also provides a method for fabricating a device structure that integrates a compound semiconductor and a carbon nanotube monolith, used to fabricate the device structure described in any of the above embodiments, the fabrication method comprising:

[0028] An epitaxial substrate is prepared, wherein the epitaxial substrate comprises, from bottom to top, a substrate layer, a nucleation layer, a buffer layer, a channel layer and a barrier layer;

[0029] ICP etching is performed in the middle region of the epitaxial substrate to etch into the buffer layer, forming a groove;

[0030] A first source and a first drain are fabricated on the barrier layer;

[0031] Electrical isolation of the active region is formed by ion implantation into the barrier layer, channel layer and buffer layer at a certain depth at the end.

[0032] A passivation layer is grown on the barrier layer of the first source, the first drain, and the active region;

[0033] The gate trench region is photolithographically etched, and the gate trench region is etched to form the gate trench.

[0034] The first gate region is photolithographically etched, and the first gate is fabricated in the first gate region and the gate trench using an electron beam evaporation process.

[0035] An electrical isolation layer is grown within the groove, and the upper surface of the electrical isolation layer is located above the barrier layer;

[0036] A carbon nanotube film is fabricated on the barrier layer, and the carbon nanotube film is then fabricated into a carbon nanotube array using electrophoresis.

[0037] A second source and a second drain are fabricated on the carbon nanotube array;

[0038] A dielectric layer is grown on the carbon nanotube array, a portion of the second source electrode, and a portion of the second drain electrode;

[0039] A second gate region is photolithographically etched on the dielectric layer, and a second gate is fabricated in the second gate region using an electron beam evaporation process.

[0040] Photolithographically etch the metal interconnect layer opening region on the passivation layer of the first drain electrode, and then etch away the passivation layer of the metal interconnect layer opening region using ICP process.

[0041] The epitaxial substrate under the back of the first source electrode is etched, and the back of the first source electrode is connected to the ground terminal through a via, and the second source electrode is connected to the power supply terminal.

[0042] The first drain and the second drain are connected by a first interconnect metal, and the first gate and the second gate are connected by a second interconnect metal.

[0043] In one embodiment of the invention, the materials of the buffer layer and the channel layer comprise group III-V compounds.

[0044] In one embodiment of the present invention, the buffer layer and the channel layer are made of the same material, and the material of the buffer layer and the channel layer includes any one of GaN, GaAs, and InP.

[0045] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0046] This invention proposes a method for integrating carbon nanotube devices and high electron mobility transistors (HMTs) on the same horizontal epitaxial material, leveraging the higher electron mobility of GaN HEMTs and the higher hole mobility of carbon nanotubes. Therefore, using HMTs to realize NMOS transistors and carbon nanotubes to realize PMOS transistors allows for the full utilization of their respective advantages. By simultaneously achieving high electron and hole mobility on a single substrate, N-channel and P-channel devices with high switching speeds are fabricated. Furthermore, compared to traditional discrete packaging on PCBs, this significantly reduces the area of ​​the CMOS circuit chip while improving the performance of the circuit in processing digital signals.

[0047] This invention utilizes monolithic integrated circuits, fabricating high electron mobility transistors and carbon-based carbon nanotubes on the same single-crystal epitaxial material, to improve circuit performance. Furthermore, by integrating N-channel and P-channel CMOS devices, digital logic is realized, enabling the effective realization of high-speed, radiation-resistant digital circuits.

[0048] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of a device structure that integrates a compound semiconductor and a carbon nanotube monolith, according to an embodiment of the present invention.

[0050] Figure 2 This is a circuit logic diagram provided in an embodiment of the present invention;

[0051] Figures 3a-3l This is a schematic diagram illustrating the process of a device structure integrating a compound semiconductor and a carbon nanotube monolith, as provided in an embodiment of the present invention.

[0052] Figure 4 This is a schematic diagram illustrating the specific process of fabricating a device structure that integrates a compound semiconductor and a carbon nanotube monolith, as provided in an embodiment of the present invention. Detailed Implementation

[0053] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0054] Example 1

[0055] Please see Figure 1 , Figure 1 This is a schematic diagram of a device structure integrating a compound semiconductor and a carbon nanotube monolithically, provided by an embodiment of the present invention. The device structure includes:

[0056] Substrate 1;

[0057] Nucleation layer 2 is disposed on substrate layer 1;

[0058] A buffer layer 3 is disposed on the nucleation layer 2, and a groove is provided in the middle region of the buffer layer 3;

[0059] The channel layer 4 is disposed on the upper surface of the buffer layer 3, excluding the portion with grooves.

[0060] Barrier layer 5 is disposed on the upper surface of the channel layer 4, excluding the portion with grooves.

[0061] An electrical isolation layer 6 is disposed in the groove, and the upper surface of the electrical isolation layer 6 is located above the barrier layer 5, for isolating the two-dimensional electron gas of the barrier layer 5.

[0062] A carbon nanotube device is disposed on the barrier layer 5 and located on one side of the electrical isolation layer 6;

[0063] The first source electrode 7 and the first drain electrode 8 are disposed at intervals on the barrier layer 5 and are located on the other side of the electrical isolation layer 6, and the sidewall of the first drain electrode 8 is in contact with the sidewall of the electrical isolation layer 6.

[0064] A passivation layer 9 is disposed on the first source 7, the first drain 8 and the barrier layer 5 located on the other side of the electrical isolation layer 6;

[0065] The first gate 10 is disposed in the gate trench of the passivation layer 9 and on a portion of the passivation layer 9.

[0066] Existing single semiconductor materials struggle to simultaneously achieve high electron and hole mobility in a single device, thus reducing the device's saturation drain current level and impacting its switching speed. This invention proposes a method for integrating carbon nanotube devices and high electron mobility transistors (HEMTs) on the same horizontal epitaxial substrate. This reduces the complexity of the integration process while leveraging the higher electron mobility of GaN HEMTs and the higher hole mobility of carbon nanotubes. Therefore, using HEMTs to implement NMOS transistors and carbon nanotube devices to implement PMOS transistors allows for the full utilization of their respective advantages.

[0067] In one specific embodiment, the carbon nanotube device includes:

[0068] Carbon nanotube array 11;

[0069] The second source electrode 12 and the second drain electrode 13 are disposed at intervals on the carbon nanotube array 11, and the sidewall of the second drain electrode 13 is in contact with the sidewall of the electrical isolation layer 6.

[0070] A dielectric layer 14 is disposed on the carbon nanotube array 11, a portion of the second source 12 and a portion of the second drain 13;

[0071] The second gate 15 is disposed on the dielectric layer 14.

[0072] In one specific embodiment, please also refer to Figure 1 and Figure 2 The first drain 8 and the second drain 13 are connected through the first interconnect metal 16, the first gate 10 and the second gate 15 are connected through the second interconnect metal 17, the first source 7 is connected to the ground terminal through the through hole 18 on the back, and the second source 12 is connected to the power supply terminal.

[0073] In one specific embodiment, the first source 7, the first drain 8, the second source 12, and the second drain 13 are all extended down to the channel layer 4 through annealing, so that the first source 7, the first drain 8, the second source 12, and the second drain 13 are in ohmic contact with the heterojunction channel, wherein the channel layer 4 and the barrier layer 5 form a heterojunction channel.

[0074] This invention utilizes high electron mobility transistors (HEMTs) and carbon nanotube devices (CNTs) fabricated in the left and right regions of the same epitaxial substrate. Then, interconnecting metals connect the isolated HEMTs and CNTs according to digital logic. The gate and drain of the HEMT are connected to the corresponding terminals of the CNTs, with the source of the HEMT grounded and the source of the CNT connected to VDD. Thus, the gate serves as the input and the drain as the output, enabling digital logic through this horizontal integration method. This heterogeneous integration structure achieves high electron and hole mobility simultaneously on a single substrate, fabricating N-channel and P-channel devices with high switching speeds. Compared to traditional discrete packaging on a PCB, it significantly saves CMOS chip area. Furthermore, the device structure utilizes complementary MOSFETs, namely pMOS (for PMOS with CNTs) and nMOS (for NMOS with HEMTs), to form a complementary circuit. It features low power consumption: In CMOS circuits, MOSFETs only consume energy when the input signal changes. Therefore, CMOS circuits can achieve low-power operation and consume almost no energy when at rest. High integration: CMOS circuits have advantages such as small size, high reliability, and high integration, allowing a large number of circuit functions to be integrated on a single chip. High noise immunity: CMOS circuits have very high noise immunity and can operate normally in high-noise environments.

[0075] In one specific embodiment, the materials of the buffer layer and the channel layer include group III-V compounds.

[0076] This invention proposes a method for integrating carbon nanotube devices and III-V compound semiconductor transistors on the same horizontal epitaxial substrate, leveraging the higher electron mobility of GaN HEMT devices and the higher hole mobility of carbon nanotube devices. Therefore, NMOS transistors can be realized on III-V compound semiconductors, and PMOS transistors on carbon nanotube devices, fully utilizing their respective advantages.

[0077] Optionally, the buffer layer 3 and the channel layer 4 are made of the same material, which may include any one of GaN, GaAs, and InP.

[0078] In one specific embodiment, the device structure of this embodiment further includes electrical isolation of the active region, which is formed by ion implantation into the end barrier layer 5, the channel layer 4, and the buffer layer 3 to a certain depth.

[0079] Optionally, the substrate layer 1 is made of any one of Si, SiC, and Al2O3; the nucleation layer 2 is made of AlN; the barrier layer 5 is made of AlN; the electrical isolation layer 6 is made of SiO2 or Al2O3; the passivation layer 10 is made of SiN; and the dielectric layer 14 is made of H. f O2.

[0080] The present invention proposes a method for integrating carbon nanotube devices and high electron mobility transistors on the same epitaxial substrate in the horizontal direction. It utilizes the higher electron mobility of GaN HEMT devices and the higher hole mobility of carbon nanotubes. By employing III-V semiconductors and carbon-based materials fusion and heterogeneous integration technology, it is possible to simultaneously realize N-channel and P-channel devices with high switching speeds. The integration saves chip area, and the process compatibility is improved by processing on the same epitaxial substrate. It is an excellent choice for realizing small-size, high-speed, radiation-resistant digital logic circuits.

[0081] Example 2

[0082] Please see Figures 3a-3l , Figures 3a-3l This is a schematic diagram illustrating the process of a device structure integrating a compound semiconductor and a carbon nanotube monolithically, provided in an embodiment of the present invention. Based on Embodiment 1, the present invention also provides a method for fabricating a device structure integrating a compound semiconductor and a carbon nanotube monolithically, used to fabricate the device structure described in Embodiment 1. The method for fabricating this device structure includes:

[0083] Step 1, please refer to Figure 3a An epitaxial substrate is prepared, which includes, from bottom to top, a substrate layer 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5.

[0084] In one specific embodiment, the materials of the buffer layer and the channel layer include group III-V compounds.

[0085] Optionally, the buffer layer 3 and the channel layer 4 are made of the same material, which may include any one of GaN, GaAs, and InP.

[0086] Optionally, the substrate layer 1 is made of any one of Si, SiC, and Al2O3, the nucleation layer 2 is made of AlN, and the barrier layer 5 is made of AlN.

[0087] Step 2, please continue reading Figure 3a ICP (Inductive Coupled Plasma) etching is performed in the middle region of the epitaxial substrate, etching into the buffer layer 3 to form a groove.

[0088] Step 3, please refer to Figure 3bA first source electrode 7 and a first drain electrode 8 are fabricated on the barrier layer 5, with the first source electrode 7 and the first drain electrode 8 located on one side of the groove.

[0089] In one specific embodiment, the first source 7 and the first drain 8 are both extended down to the channel layer 4 through annealing, so that the first source 7, the first drain 8 and the heterojunction channel are in ohmic contact, wherein the channel layer 4 and the barrier layer 5 form a heterojunction channel.

[0090] Step 4, please refer to Figure 3c Electrical isolation of the active region is formed by ion implantation into the end barrier layer 5, the channel layer 6, and the buffer layer 3 at a certain depth.

[0091] Specifically, an electrically isolated region of the active region is photolithographically formed at the end of the epitaxial substrate, and the electrically isolated region of the device active region is fabricated by ion implantation.

[0092] Step 5, please refer to Figure 3d A passivation layer 9 is grown on the first source electrode 7, the first drain electrode 8, and the barrier layer 5 of the active region.

[0093] Specifically, a passivation layer 9 is deposited on the barrier layer 5, the first source electrode 7, and the first drain electrode 8 using plasma-enhanced chemical vapor deposition (PECVD).

[0094] Optionally, the material of the passivation layer 9 includes SiN.

[0095] Step 6, please refer to Figure 3e The gate trench area is photolithographically etched and etched to form the gate trench.

[0096] Specifically, a gate trench region is photolithographically etched on the passivation layer 9, and the passivation layer in the gate trench region is etched using an ICP process.

[0097] Step 7, please refer to Figure 3f The first gate region is photolithographically etched, and the first gate 10 is fabricated in the first gate region and gate trench using an electron beam evaporation process.

[0098] Specifically, a first gate region is photolithographically etched on the barrier layer 5 using a double-layer photoresist technique, and a T-shaped first gate 10 is formed by depositing gate metal using an electron beam evaporation process.

[0099] Step 8, please refer to Figure 3g An electrical isolation layer 6 is grown in the groove, and the upper surface of the electrical isolation layer 6 is located above the barrier layer 5.

[0100] Specifically, a layer of SiO2 is grown in the groove between the two devices using PECVD, or Al2O3 is grown using plasma atomic layer deposition (PEALD) to form electrical isolation.

[0101] Step 9, please refer to Figure 3h A carbon nanotube film was fabricated on the barrier layer 5, and the carbon nanotube film was then used to fabricate a carbon nanotube array 11 by electrophoresis.

[0102] Specifically, 99% pure carbon nanotubes were catalytically centrifuged twice, and 90% of the supernatant was collected to obtain impurity-free carbon nanotubes. Then, Cr / Au was deposited on a barrier layer on the other side of an epitaxial substrate using magnetron sputtering, followed by photolithography to create an array pattern. The electrodes were then connected to a function generator, and electrophoresis was performed at 100 kHz and 10 V to fabricate a carbon nanotube array on the barrier layer. The grown carbon nanotube array was then immersed in BOE solution to etch away the Cr / Au metal electrodes.

[0103] Step 10, please continue reading Figure 3h A second source electrode 12 and a second drain electrode 13 are fabricated on the carbon nanotube array 11.

[0104] In one specific embodiment, the second source 12 and the second drain 13 are both extended to the channel layer 4 by annealing, so that the second source 12, the second drain 13 and the heterojunction channel are in ohmic contact.

[0105] Step 11, please refer to Figure 3i A dielectric layer 14 is grown on the carbon nanotube array 11, part of the second source 12 and part of the second drain 13.

[0106] Specifically, HfO2 is deposited over a portion of the second source 12, a portion of the second drain 13, and the carbon nanotube array 11 using atomic layer deposition (ALD) to form a dielectric layer 14.

[0107] Step 12, please refer to Figure 3j The second gate region is photolithographically etched on the dielectric layer 14, and the second gate 15 is fabricated in the second gate region using an electron beam evaporation process, thereby completing the fabrication of the carbon nanotube device.

[0108] Step 13, please refer to Figure 3k A metal interconnect layer opening region is photolithographically etched on the passivation layer 9 of the first drain 8, and the passivation layer 9 of the metal interconnect layer opening region is etched away using ICP process.

[0109] Step 14, please continue reading Figure 3k The epitaxial substrate under the back of the first source electrode 7 is etched, and the back of the first source electrode 7 is connected to the ground terminal through the through hole 18, and the second source electrode 12 is connected to the power supply terminal.

[0110] Step 15: Connect the first drain 8 and the second drain 13 through the first interconnect metal 16, and connect the first gate 10 and the second gate 15 through the second interconnect metal 17.

[0111] Specifically, the interconnect metal is photolithographically etched and evaporated to connect the gate and drain of the two devices respectively, thus obtaining a monolithic CMOS integrated device.

[0112] To achieve the objective of this invention, the present invention first etches the epitaxial substrate down to the channel layer, then fabricates a high electron mobility transistor (HEMT) and carbon nanotubes with a barrier layer. Next, SiO2 grown by plasma-enhanced chemical vapor deposition (PECVD) or Al2O3 grown by plasma-enhanced atomic layer deposition (PEALD) is used to electrically isolate the two devices. Then, passivation layer openings are etched at the corresponding locations of the drain and gate of the HEMT, and a via is grounded on the back of the source. Finally, interconnect metal is evaporated to connect the gate and drain of the carbon nanotubes to the corresponding gate and drain of the HEMT, resulting in a CMOS device with both high switching speeds in the N-channel and P-channel configurations, achieving a more space-saving CMOS integrated circuit.

[0113] Example 3

[0114] Please see Figure 4 , Figure 4 This is a schematic flowchart illustrating a method for fabricating a monolithically integrated device structure combining a compound semiconductor and carbon nanotubes, as provided in an embodiment of the present invention. Based on Embodiment 2, the present invention further provides a specific method for fabricating a monolithically integrated device structure combining a compound semiconductor and carbon nanotubes, the method comprising:

[0115] Step 1: ICP etching is used on the epitaxial substrate to the GaN buffer layer to form a separation region.

[0116] The epitaxial substrate consists of, from bottom to top, a substrate layer, an AlN nucleation layer, a GaN buffer layer, a GaN channel layer, and an AlN barrier layer.

[0117] 1a) Using photoresist as a mask, the epitaxial substrate is etched down to the bottom of the GaN buffer layer using a dry etching process to form a separation region between the two device fabrication areas.

[0118] 1a1) The etching process conditions are: Cl2 flow rate of 15 sccm, reaction chamber pressure of 11 mTorr, and electrode power of 180 W.

[0119] Step 2: Fabricate the first source and the first drain on the AlN barrier layer of the epitaxial substrate.

[0120] 2a) Photolithographically etch the first source region and the first drain region on the AlN barrier layer.

[0121] 2a1) Place the epitaxial substrate on a hot plate at 200°C and bake for 5 minutes.

[0122] 2a2) Apply and spin the release adhesive onto the AlN barrier layer, and bake the sample on a hot plate at 200°C for 5 minutes.

[0123] 2a3) Apply photoresist to the release adhesive and spin it off, and bake the sample on a hot plate at 900℃ for 1 minute.

[0124] 2a4) The sample after coating and spin-coating is placed in the photolithography machine, the coated surface is exposed, and the exposed sample is placed in the developer to remove the photoresist and stripper. After rinsing with ultrapure water and blowing with nitrogen, the first source region and the first drain region are formed.

[0125] 2b) Evaporate the first source and the first drain on the AlN barrier layer in the first source region and the first drain region, and on the photoresist outside the first source region and the first drain region.

[0126] 2b1) The sample with the first source and first drain photolithography pattern is placed in a plasma stripper for bottom film treatment for 5 minutes.

[0127] 2b2) Place the sample into the electron beam evaporation stage, and wait until the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10 -6 After Torr, ohmic metal is evaporated on the AlN barrier layer in the first source region and the first drain region, as well as on the photoresist outside the first source region and the first drain region, to form the first source and the first drain. The ohmic metal is a metal stack structure composed of four metal layers, Ti, Al, Ni and Au, arranged sequentially from bottom to top.

[0128] 2b3) After the ohmic metal evaporates, the sample is subjected to a stripping process to remove the ohmic metal, photoresist and stripping adhesive outside the first source and first drain. The sample is then rinsed with ultrapure water and dried with nitrogen.

[0129] 2c) The sample after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing. The annealing process is carried out under nitrogen, the annealing temperature is 830℃, and the annealing time is 30s. This causes the ohmic metal of the AlN barrier layer in the first source and the first drain to extend down to the GaN channel layer, thereby forming an ohmic contact between the metal and the heterojunction channel.

[0130] Step 3: Photolithographically etch the electrically isolated region of the active region on the AlN barrier layer, and use ion implantation to fabricate the electrically isolated active region of the device.

[0131] 3a) Photolithographically lithographically isolated regions on the AlN barrier layer.

[0132] 3a1) Place the sample on a hot plate at 200℃ and bake for 5 minutes.

[0133] 3a2) Apply and spin the photoresist, and bake the sample on a hot plate at 900℃ for 1 minute.

[0134] 3a3) The sample is placed in the lithography machine to expose the photoresist in the electrically isolated area. After exposure, the sample is placed in the developer to remove the photoresist in the electrically isolated area, and then rinsed with ultrapure water and dried with nitrogen.

[0135] 3b) Create electrical isolation of the active region on the AlN barrier layer.

[0136] 3b1) Ion implantation was performed sequentially into the AlN barrier layer, GaN channel layer, and a partially deep GaN buffer layer in the electrically isolated region to achieve mesa isolation of the active region. The ion implantation depth was 100 nm.

[0137] 3b2) The sample was sequentially placed in acetone solution, stripping solution, acetone solution and isopropanol solution for cleaning to remove the photoresist outside the electrically isolated area. Finally, the sample was rinsed with ultrapure water and dried with nitrogen.

[0138] Step 4: On the AlN barrier layer of the first source, first drain and active region, grow a SiN passivation layer using PECVD process.

[0139] 4a) Perform surface cleaning on the sample after active region ion implantation / electrical isolation is completed.

[0140] 4a1) Place the sample in acetone solution and ultrasonically clean it for 3 minutes at an ultrasonic intensity of 2.5.

[0141] 4a2) Place the sample in a stripping solution at 60°C and heat in a water bath for 5 minutes.

[0142] 4a3) Place the samples in acetone solution sequentially and ultrasonically clean for 3 minutes with an ultrasonic intensity of 2.5.

[0143] 4a4) Place the samples sequentially into isopropanol solution and ultrasonically clean for 3 minutes with an ultrasonic intensity of 2.5.

[0144] 4a5) Rinse the sample with ultrapure water and dry it with nitrogen.

[0145] 4b) A 120 nm thick SiN passivation layer is grown on the AlN barrier layer of the first source, first drain and active region using PECVD process. The growth process conditions are as follows: NH3 and SiH4 are used as reaction gases, the substrate temperature is 250 °C, the reaction chamber pressure is 600 mTorr and the RF power is 22 W.

[0146] Step 5: Photolithographically pattern the gate trench region (i.e., the GRSS region) on the SiN passivation layer, and etch the SiN passivation layer in the gate trench region using the ICP process.

[0147] 5a) Photolithographically etch the GRSS region on the SiN passivation layer 10.

[0148] 5a1) Place the sample on a hot plate at 200°C and bake.

[0149] 5a2) Apply and spin the photoresist, and bake the sample on a hot plate at 900℃ for 1 minute.

[0150] 5a3) Place the sample into the lithography machine to expose the photoresist in the GRSS region.

[0151] 5a4) After exposure, the sample is placed in the developer to remove the photoresist in the GRSS area, and then rinsed with ultrapure water and dried with nitrogen.

[0152] 5b) The cleaned sample was then etched using an ICP process to remove the SiN passivation layer material in the GRSS region. The etching conditions for the SiN passivation layer were: reaction gases CF4 and O2, reaction chamber pressure 10 mTorr, RF power of the upper and lower electrodes 100 W and 10 W respectively, and etching depth 125 nm.

[0153] 5b1) The sample was washed sequentially in acetone solution, stripping solution, acetone solution and isopropanol solution.

[0154] Step 6: Photolithographically etch the first gate region on the AlN barrier layer and fabricate the first gate using an electron beam evaporation process.

[0155] 6a) Photolithographically etch the first gate region on the AlN barrier layer.

[0156] 6a1) Place the sample on a hot plate at 200°C and bake for 5 minutes.

[0157] 6a2) Coat the sample with the first layer of photoresist until the first layer of photoresist completely covers the upper surface of the SiN passivation layer.

[0158] 6a3) Then coat the sample with a second layer of photoresist so that the second layer of photoresist completely covers the first layer of photoresist.

[0159] 6a4) Expose the sample after the adhesive has been applied a second time.

[0160] (6a5) After exposure, the sample is placed in the developer to remove the photoresist in the first gate region, and then rinsed with ultrapure water and dried with nitrogen.

[0161] 6b) Using electron beam evaporation, metal is deposited to form a T-shaped first gate.

[0162] 6b1) The sample with the photolithographic pattern in the first gate region is placed in a plasma resist remover for bottom film treatment, which takes 5 minutes.

[0163] 6b2) Place the cleaned sample into the electron beam evaporation stage, and wait until the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10 -6 After Torr, gate metal is evaporated on the photoresist within and outside the first gate region. This gate metal is a metal stack structure composed of three layers of metal, Ni, Au, and Ni, arranged sequentially from bottom to top.

[0164] Step 7: Use PECVD process to grow a SiO2 isolation layer in the groove between the left and right devices.

[0165] 7a) Perform surface cleaning on the sample after active region ion implantation / electrical isolation is completed.

[0166] 7a1) Place the sample in acetone solution and ultrasonically clean it for 3 minutes with an ultrasonic intensity of 2.5.

[0167] 7a2) Place the sample in a stripping solution at 60°C and heat in a water bath for 5 minutes.

[0168] 7a3) Place the samples sequentially into acetone solution and ultrasonically clean for 3 minutes with an ultrasonic intensity of 2.5.

[0169] 7a4) Place the samples sequentially into isopropanol solution and ultrasonically clean for 3 minutes with an ultrasonic intensity of 2.5.

[0170] 7a5) Rinse the sample with ultrapure water and dry it with nitrogen.

[0171] 7b) On the AlN barrier layer and SiN passivation layer of the first source, first drain and active region, an 800nm ​​thick SiO2 isolation layer is grown using PECVD process. The growth process conditions are: N2O and SiN4 are used as reaction gases, the substrate temperature is 300℃, the reaction chamber pressure is 900mTorr, and the RF power is 70W.

[0172] Step 8: Separate semiconductor carbon nanotubes with a purity higher than 99%.

[0173] 8a) Single-walled carbon nanotubes were mixed with poly(1-octylnonyl)-9H-carbazole PCz in a 1:1 volume ratio to carry out catalytic activity.

[0174] 8a1) Add 25 ml of toluene solution to it, soak it in an ice-water bath at 0°C, and place it in a VCX500 cell disruptor for 30 min to fully contact it.

[0175] 8a2) Perform pre-ultracentrifugation at 20000g for 30 min at 4℃, and take 90% of the supernatant.

[0176] 8a3) The second step of centrifugation was carried out at 20000g for 2 hours at 4℃. 90% of the supernatant was taken to obtain carbon nanotubes free of impurities and amorphous carbon.

[0177] 8b) The obtained supernatant was used to prepare carbon nanotube films by immersion method.

[0178] Step 9: Prepare carbon nanotube arrays using electrophoresis.

[0179] 9a) Take the epitaxial substrate on the right side, clean it, and then use magnetron sputtering to plate Cr / Au.

[0180] 9a2) Place the sample on a hot plate at 200°C and bake for 5 minutes.

[0181] 9a3) Apply photoresist to the prepared sample under a yellow light lamp and spin it off, then bake the sample on a 900℃ hot plate for 1 minute.

[0182] 9a4) The sample after coating and spin coating is placed in a photolithography machine to expose the coated surface, and the exposed sample is placed in a developing solution to remove the photoresist and prepare an electrophoretic electrode.

[0183] 9b) Connect the electrode to the function generator and perform electrophoresis at 100 kHz and 10 V to fabricate a carbon nanotube array on the right-side epitaxial substrate. After electrophoresis, immerse the sample in BOE to etch the metal electrode used for electrophoresis.

[0184] Step 10: Fabricate the second source and second drain on the carbon nanotube array. For details on the fabrication method, please refer to the fabrication method for the first source and first drain in Step 2; it will not be repeated here.

[0185] Step 11: Growing H+ on the AlN barrier layer, the second source, and the second drain using ALD. f O2 dielectric layer.

[0186] 11a) Using thermal atomic layer deposition (ALD) technology, a 10 nm thick H layer is grown in the region between and above the second source and second drain. f The O2 high-k dielectric layer was grown under the following process conditions: the precursor sources were O3 and TEMAH, the substrate temperature was 300℃, and the reaction chamber pressure was 0.3 Torr.

[0187] Step 12, in H f The second gate region is photolithographically etched on the O2 dielectric layer, and the second gate is fabricated using an electron beam evaporation process.

[0188] 12a) In H f The second gate region is photolithographically etched on the O2 dielectric layer.

[0189] 12a1) Place the sample on a hot plate at 200°C and bake for 5 minutes.

[0190] 12a2) Spin-coat photoresist onto the sample and expose the coated sample.

[0191] 12a3) After exposure, the sample is placed in the developer to remove the photoresist in the second gate region, and then rinsed with ultrapure water and dried with nitrogen.

[0192] 12b) A second gate is formed by depositing metal using electron beam evaporation.

[0193] 12b1) The sample with the photolithographic pattern in the second gate region is placed in a plasma resist remover for bottom film treatment for 5 minutes.

[0194] 12b2) Place the cleaned sample into the electron beam evaporation stage, and wait until the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10 -6 After Torr, gate metal is evaporated onto the photoresist within the second gate region and outside the second gate region. This gate metal is a metal stack structure composed of three layers of metal, Ni, Au, and Ni, arranged sequentially from bottom to top. At this point, the fabrication of the device on the right is complete.

[0195] Step 13: Photolithographically pattern the metal interconnect opening area on the SiN passivation layer, and etch away the SiN passivation layer in the interconnect opening area using ICP process.

[0196] 13a) Photolithographically etch the opening region of the metal interconnect layer on the SiN passivation layer.

[0197] 13a1) Place the sample on a hot plate at 200°C and bake for 5 minutes.

[0198] 13a2) Apply and spin the photoresist, with a spin speed of 3500 rpm, and bake the sample on a hot plate at 90°C for 1 min.

[0199] 13a3) The sample is placed in a photolithography machine to expose the photoresist in the opening area of ​​the metal interconnect layer.

[0200] 13a4) After exposure, the sample is placed in the developer to remove the photoresist in the interconnect opening area, and then rinsed with ultrapure water and dried with nitrogen.

[0201] 13b) Using ICP etching, under the conditions of CF4 and O2 reaction gases, reaction chamber pressure of 10 mTorr, and RF power of 100 W and 10 W for the upper and lower electrodes, respectively, a 120 nm SiN passivation layer in the interconnect opening area is removed.

[0202] Step 14: Ground the source back via on the left HEMT device, and use ICP process to etch away the epitaxial layer in the interconnect opening area.

[0203] 14a) Photolithographic through-hole opening area.

[0204] 14a1) Place the sample on a hot plate at 200°C and bake for 5 minutes.

[0205] 14a2) Apply and spin the photoresist at a spin speed of 3500 rpm and bake the sample on a hot plate at 90°C for 1 min.

[0206] 14a3) The sample is placed in the lithography machine to expose the photoresist in the opening area.

[0207] 14a4) After exposure, the sample is placed in the developer to remove the photoresist in the opening area, and then rinsed with ultrapure water and dried with nitrogen.

[0208] 14b) Using ICP etching, with CF4 and O2 as the reaction gases, a reaction chamber pressure of 10 mTorr, and RF powers of 100 W and 10 W for the upper and lower electrodes, respectively, the epitaxial material in the interconnect opening area is removed to achieve back-side via grounding.

[0209] Step 15: Preparation of interconnect metals.

[0210] 15a) Photolithographically pattern the metal interconnect layer regions on the gate and drain of the metal interconnect layer opening region and on the SiN passivation layer without opening etching.

[0211] 15a1) Place the sample with the completed metal interconnect layer opening etching on a hot plate at 200°C and bake for 5 minutes.

[0212] 15a2) Apply and spin-spray the release adhesive to the gate and drain of the metal interconnect layer opening area and the SiN passivation layer without opening etching. The spin-spray thickness is 0.35μm, and the sample is baked on a hot plate at 200℃ for 5min.

[0213] 15a3) Photoresist was applied and spun onto the release adhesive, with a spun thickness of 0.77 μm, and the sample was baked on a hot plate at 90 °C for 1 min.

[0214] 15a4) The sample after coating and spin coating is placed in the photolithography machine to expose the photoresist in the metal interconnect area.

[0215] 15a5) Place the exposed sample into the developer to remove the photoresist and stripper in the metal interconnect layer area, and then rinse it with ultrapure water and dry it with nitrogen.

[0216] 15b) Evaporate metal on the electrodes and SiN passivation layer in the metal interconnect region and on the photoresist outside the metal interconnect region, so that the gate and drain of the left and right parts of the device are connected respectively.

[0217] 15b1) The sample with the metal interconnect photolithography pattern is placed in a plasma resist remover for bottom film treatment, which takes 5 minutes.

[0218] 15b2) Place the sample into the electron beam evaporation stage, and wait until the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10 -6 After Torr, interconnect metal is evaporated on the electrodes and SiN passivation layer in the interconnect metal region and on the photoresist outside the metal interconnect region. The interconnect metal is a metal stack structure consisting of two metal layers, Ti and Au, arranged sequentially from bottom to top.

[0219] 15b3) The sample after the interconnect metal evaporation is completed is stripped to remove the interconnect metal, photoresist and release adhesive outside the metal interconnect layer area.

[0220] 15b4) Rinse the sample with ultrapure water and dry it with nitrogen.

[0221] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0222] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0223] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0224] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A device structure integrating a compound semiconductor and a carbon nanotube monolithically, characterized in that, include: Substrate layer; A nucleation layer is disposed on the substrate layer; A buffer layer is disposed on the nucleation layer, and a groove is provided in the middle region of the buffer layer; A channel layer is disposed on the upper surface of the buffer layer, excluding the portion of the groove; A barrier layer is disposed on the upper surface of the channel layer, excluding the portion of the groove. An electrical isolation layer is disposed in the groove, and the upper surface of the electrical isolation layer is located above the barrier layer; A carbon nanotube device is disposed on the barrier layer and located on one side of the electrical isolation layer; A first source and a first drain are disposed at intervals on the barrier layer and located on the other side of the electrical isolation layer, and the sidewall of the first drain is in contact with the sidewall of the electrical isolation layer. A passivation layer is disposed on the first source, the first drain, and the barrier layer located on the other side of the electrical isolation layer; A first gate is disposed within the gate trench of the passivation layer and on a portion of the passivation layer.

2. The device structure according to claim 1, characterized in that, The carbon nanotube device includes: Carbon nanotube array; The second source and the second drain are disposed at intervals on the carbon nanotube array, and the sidewall of the second drain is in contact with the sidewall of the electrical isolation layer. A dielectric layer is disposed on the carbon nanotube array, a portion of the second source electrode, and a portion of the second drain electrode; A second gate is disposed on the dielectric layer.

3. The device structure according to claim 2, characterized in that, The first drain and the second drain are connected by a first interconnect metal, the first gate and the second gate are connected by a second interconnect metal, the first source is connected to the ground terminal through a through-hole on the back, and the second source is connected to the power supply terminal.

4. The device structure according to claim 2, characterized in that, The first source, the first drain, the second source, and the second drain are all extended to the channel layer through annealing, so that the first source, the first drain, the second source, the second drain and the heterojunction channel are in ohmic contact, wherein the channel layer and the barrier layer form a heterojunction channel.

5. The device structure according to claim 1, characterized in that, The materials of the buffer layer and the channel layer include group III-V compounds.

6. The device structure according to claim 5, characterized in that, The buffer layer and the channel layer are made of the same material, which includes any one of GaN, GaAs, and InP.

7. The device structure according to claim 1, characterized in that, It also includes electrical isolation of the active region, which is formed by ion implantation into the end barrier layer, the channel layer and a buffer layer to a certain depth.

8. A method for fabricating a device structure integrating a compound semiconductor and a carbon nanotube monolith, characterized in that, The method for preparing the device structure according to any one of claims 1 to 7 comprises: An epitaxial substrate is prepared, wherein the epitaxial substrate comprises, from bottom to top, a substrate layer, a nucleation layer, a buffer layer, a channel layer and a barrier layer; ICP etching is performed in the middle region of the epitaxial substrate to etch into the buffer layer, forming a groove; A first source and a first drain are fabricated on the barrier layer; Electrical isolation of the active region is formed by ion implantation into the barrier layer, channel layer and buffer layer at a certain depth at the end. A passivation layer is grown on the barrier layer of the first source, the first drain, and the active region; The gate trench region is photolithographically etched, and the gate trench region is etched to form the gate trench. The first gate region is photolithographically etched, and the first gate is fabricated in the first gate region and the gate trench using an electron beam evaporation process. An electrical isolation layer is grown within the groove, and the upper surface of the electrical isolation layer is located above the barrier layer; A carbon nanotube film is fabricated on the barrier layer, and the carbon nanotube film is then fabricated into a carbon nanotube array using electrophoresis. A second source and a second drain are fabricated on the carbon nanotube array; A dielectric layer is grown on the carbon nanotube array, a portion of the second source electrode, and a portion of the second drain electrode; A second gate region is photolithographically etched on the dielectric layer, and a second gate is fabricated in the second gate region using an electron beam evaporation process. Photolithographically etch the metal interconnect layer opening region on the passivation layer of the first drain electrode, and then etch away the passivation layer of the metal interconnect layer opening region using ICP process. The epitaxial substrate under the back of the first source electrode is etched, and the back of the first source electrode is connected to the ground terminal through a via, and the second source electrode is connected to the power supply terminal. The first drain and the second drain are connected by a first interconnect metal, and the first gate and the second gate are connected by a second interconnect metal.

9. The preparation method according to claim 8, characterized in that, The materials of the buffer layer and the channel layer include group III-V compounds.

10. The preparation method according to claim 8, characterized in that, The buffer layer and the channel layer are made of the same material, which includes any one of GaN, GaAs, and InP.

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