A GaN HEMT device with ESD protection

Abstract

The application belongs to the technical field of power semiconductors, and particularly relates to a GaN HEMT device with ESD resistance. Based on the characteristics of high threshold and high voltage resistance of GaN HEMT and a cascade diode, when the voltage applied to the gate of the GaN HEMT device reaches the ESD trigger voltage, the diode is turned on to form an electrostatic discharge channel, so that the voltage of the gate of the power device no longer rises, thereby protecting the gate of the power device from being broken down by high voltage. The application can effectively improve the ESD voltage level of the device, enhance the robustness of the device, and improve the reliability of the device. The cascade diode of the gate-source ESD electrostatic discharge path is the same as the GaN HEMT in the process steps, and is easy to realize integration.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically relating to a GaN HEMT device with ESD protection. Background Technology

[0002] GaN HEMT (High Electron Mobility Transistor) technology is maturing and gradually being adopted in the market. Electrostatic discharge (ESD) protection is essential for both discrete and integrated GaN HEMT devices. However, GaN HEMT devices lack an internal PN junction for auxiliary ESD discharge, and their predominantly biased gate structure results in a significantly lower ESD failure voltage between the gate and source compared to the gate and drain. Therefore, ESD protection structures compatible with power devices have become a key focus in the market. The turn-on voltage of the ESD discharge path should be slightly lower than the gate breakdown voltage to both protect the gate and accommodate its maximum rated voltage. Furthermore, the ESD structure requires sufficient area to ensure adequate ESD discharge capability. Summary of the Invention

[0003] To address the aforementioned problems, this invention proposes a GaN HEMT device with ESD protection based on GaN cascaded diodes.

[0004] To achieve the above-mentioned objectives, the technical solution of the present invention is as follows:

[0005] A GaN HEMT device with ESD protection includes a vertically arranged GaN HEMT device body and a GaN cascaded diode. The former performs the function of a power device, and the latter performs the function of electrostatic protection. It also includes an isolation region 11 that isolates the active region of the GaN HEMT device and the active region of the GaN cascaded diode along the vertical direction. The electrodes of the GaN HEMT device and the GaN cascaded diode are electrically connected through interconnecting metal.

[0006] The GaN HEMT device comprises, from bottom to top, the following layers stacked along the vertical direction of the device: a substrate 1, a buffer layer 2 with a grooved upper surface, a GaN channel layer 3, a barrier layer 4, and a dielectric passivation layer 6, the surface of which is grooved; along the lateral direction of the device, the device surface has a source 5, a gate 7, and a drain 8 sequentially from one side to the other, wherein the gate 7 is located inside the grooved structure, and its bottom and sidewalls are in contact with the dielectric layer 6, and the gate 7 covers the dielectric passivation layers 6 on both sides of the groove to form a gate field plate structure; the source 5 and the drain 8 both penetrate the dielectric passivation layer 6 along the vertical direction of the device and extend into the barrier layer 4, and their lower surfaces form an ohmic contact with the barrier layer 4;

[0007] The GaN cascaded diode comprises, from bottom to top, a substrate 1, a buffer layer 2 with multiple grooves on its upper surface, a GaN channel layer 3, a barrier layer 4, and a dielectric layer 6, arranged in a groove shape along the vertical direction of the device. Along the lateral direction of the device, the two end surfaces of the device are a cathode 9, a floating gate metal FG, and an anode 10, respectively, with two or more floating gate metal FGs disposed between the cathode 9 and the anode. The cathode 9 penetrates the dielectric layer 6 along the vertical direction of the device, extending into the barrier layer 4, and its lower surface forms an ohmic contact with the barrier layer 4. The floating gate metal FG and the anode 10 are located within the groove structure. The bottom and sidewalls of the floating gate metal FG and the anode 10 near the cathode contact the dielectric layer 6, while the bottom and sidewalls away from the cathode 5 penetrate the dielectric layer 6 and form an ohmic contact with the barrier layer 4.

[0008] Specifically, the gate 7 of the GaN HEMT device is connected to the anode 10 or cathode 9 of the GaN cascade diode, and the source 5 of the GaN HEMT device is connected to the cathode 9 or anode 10 of the GaN cascade diode.

[0009] Device Working Principle: GaN HEMT devices with ESD protection have non-polar or very weakly polar sidewalls in their groove-shaped channel layer 3 and barrier layer 4. Therefore, a two-dimensional electron gas cannot form or has an extremely low concentration at the heterojunction interface between channel layer 3 and barrier layer 4, resulting in an enhancement-mode device. The device's conduction mechanism involves applying a forward voltage to the metal electrode in the groove structure, causing electrons to accumulate in channel layer 3 or barrier layer 4, thus achieving conduction. Specifically, when the voltage applied to the gate of the GaN HEMT device reaches the ESD protection voltage, electrons accumulate on the bottom and sidewalls of the floating gate metal FG of the series diode and the anode 10 near the cathode, forming an electrostatic discharge channel. This prevents the gate voltage from rising further, thus protecting the gate from high-voltage breakdown.

[0010] The beneficial effects of this invention are that, based on the high threshold voltage and high withstand voltage characteristics of GaN HEMTs and cascaded diodes, this invention can effectively improve the ESD voltage resistance of devices, enhance device robustness, and improve device reliability. The gate breakdown voltage of insulated-gate GaN HEMT devices can typically reach over 15V. Compared with the low threshold voltage of traditional p-GaN gate enhancement-type HEMTs, the cascaded diodes in this invention can significantly reduce the area. The cascaded diodes in the gate-source ESD discharge path follow the same process steps as GaN HEMTs, facilitating integration. Attached Figure Description

[0011] Figure 1 This is a two-dimensional top view of Example 1;

[0012] Figure 2 This is a schematic diagram of the two-dimensional structure of a GaN HEMT device;

[0013] Figure 3 This is a schematic diagram of the two-dimensional structure of a GaN cascaded diode;

[0014] Figure 4 This is a schematic diagram of the equivalent circuit of Example 1;

[0015] Figure 5 This is a two-dimensional top view of Example 2;

[0016] Figure 6 This is a schematic diagram of the equivalent circuit of Example 2;

[0017] Figure 7 This is a schematic diagram of the equivalent circuit of Example 3; Detailed Implementation

[0018] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0019] Example 1

[0020] like Figure 1 To illustrate the top view of the application structure, from one side to the other, the bottom section shows the source 5, gate 7, dielectric layer 6, and drain 8 of the GaN HEMT device. Above, from one side to the other, are the cathode 9, floating metal FG, and anode 10 of the GaN cascaded diode. In the middle of the top view, from one side to the other, are interconnect metal 12-1, isolation region 11, and interconnect metal 12-2. Isolation region 11, located between the GaN HEMT device and the GaN cascaded diode, is formed as a high-resistivity region 11 through an isolation process, isolating the electrical connection between their active regions and dividing the top view into upper and lower parts. Interconnect metal 12-1 connects the source 5 of the GaN HEMT device and the cathode 9 of the GaN cascaded diode, and interconnect metal 12-2 connects the gate 7 of the GaN HEMT device and the anode 10 of the GaN cascaded diode. Its equivalent circuit diagram is shown below. Figure 4 As shown;

[0021] like Figure 2 The image shows along Figure 1 The cross-sectional view along the AA' direction shows a GaN HEMT device. From bottom to top, the device consists of: a substrate 1, a buffer layer 2 with a grooved upper surface, a GaN channel layer 3, a barrier layer 4, and a dielectric passivation layer 6, with the surface being grooved. Laterally, the device surface has a source 5, a gate 7, and a drain 8 sequentially from one side to the other. The gate 7 is located within the grooved structure, with its bottom and sidewalls in contact with the dielectric layer 6. The gate 7 covers the dielectric passivation layers 6 on both sides of the groove, forming a gate field plate structure. Both the source 5 and the drain 8 penetrate the dielectric passivation layer 6 along the vertical direction of the device, extending into the barrier layer 4, with their lower surfaces forming an ohmic contact with the barrier layer 4.

[0022] like Figure 3 It is along Figure 1 A cross-sectional view along the BB' direction shows a GaN cascaded diode. Vertically, the device comprises, from bottom to top, a substrate 1, a buffer layer 2 with multiple grooves on its upper surface, a GaN channel layer 3, a barrier layer 4, and a dielectric layer 6, with grooved surfaces. Laterally, the device has a cathode 9, a floating gate metal FG, and an anode 10 on its two ends, respectively. Two or more floating gate metal FGs are positioned between the cathode 9 and the anode. The cathode 9 extends vertically through the dielectric layer 6 into the barrier layer 4, with its lower surface forming an ohmic contact with the barrier layer 4. The floating gate metal FGs and anode 10 are located within the grooved structure. The bottom and sidewalls of the floating gate metal FGs and anode 10 near the cathode contact the dielectric layer 6, while their bottom and sidewalls away from the cathode 5 penetrate the dielectric layer 6 and form an ohmic contact with the barrier layer 4.

[0023] Device Operating Principle: GaN HEMT devices with ESD protection have non-polar or very weakly polar sidewalls in their groove-shaped channel layer 3 and barrier layer 4. Therefore, a two-dimensional electron gas cannot form or has an extremely low concentration at the heterojunction interface between channel layer 3 and barrier layer 4. The device's conduction mechanism involves applying a forward voltage to the metal electrode in the groove structure, causing electrons to accumulate within the channel layer 3 or barrier layer 4, thus achieving conduction. Specifically, when the voltage applied to the gate of the GaN HEMT device reaches the ESD protection voltage, electrons accumulate on the bottom and sidewalls of the floating gate metal FG of the series diode and the anode 10 near the cathode, forming an electrostatic discharge channel. This prevents the gate voltage from rising further, thus protecting the gate from high-voltage breakdown. Simultaneously, the forward voltage of the series diode is higher than the GaN HEMT device threshold, ensuring the normal operation of the GaN HEMT device.

[0024] The beneficial effects of this invention are that, based on the high threshold voltage and high withstand voltage characteristics of GaN HEMTs and cascaded diodes, this invention can effectively improve the ESD voltage resistance of devices, enhance device robustness, and improve device reliability. The gate breakdown voltage of insulated-gate GaN HEMT devices can typically reach over 15V. Compared with traditional p-GaN gate-enhanced low-threshold HEMTs, only a small number of cascaded diodes are needed to achieve the gate-source ESD voltage requirements of HEMT devices, significantly reducing the structural area. The cascaded diodes in the gate-source ESD discharge path follow the same process steps as GaN HEMTs, facilitating integration.

[0025] Example 2

[0026] The difference between this example and Example 1 is that in this example, the GaN cascaded diode is also connected between the source and gate of the GaN HEMT device body, but one end of the interconnect metal 12-1 is connected to the source 5 and the other end is connected to the anode 10, and the interconnect metal 12-2 connects the gate 7 and the cathode 9, as shown. Figure 5To apply the top view of the structure, its equivalent circuit diagram is as follows: Figure 6 As shown. Figure 2 and Figure 3 They are along Figure 5 Cross-sectional view along the AA' and BB' directions. Compared to Example 1, the advantage of this example is that source ESD protection can be achieved by optimizing the number of cascaded diodes and the threshold voltage of the HEMT device. Specifically, when the voltage applied to the source of the GaN HEMT device reaches the ESD protection voltage, the series diodes form an electrostatic discharge channel to protect the source and gate from high-voltage breakdown.

[0027] Example 3

[0028] The difference between this example and Example 1 is that in this example, multiple GaN cascaded diodes are connected in parallel between the source and gate of the GaN HEMT device body. Its equivalent circuit diagram is shown below. Figure 7 As shown. Compared to Example 1, the advantage of this example is that multiple GaN cascaded diodes connected in parallel increase the electrostatic discharge path, reduce the electrostatic discharge path resistance, improve the discharge current capability, reduce the electrostatic discharge time, and reduce ESD losses.

Claims

1. A GaN HEMT device with ESD protection, characterized in that, It includes a vertically arranged GaN HEMT device body and a GaN cascade diode, the former realizing the power device function and the latter realizing the electrostatic protection function, and also includes an isolation region (11) that isolates the active region of the GaN HEMT device and the active region of the GaN cascade diode along the vertical direction. The electrodes of the GaN HEMT device and the GaN cascade diode are electrically connected through an interconnecting metal. The GaN HEMT device is constructed as follows: along the vertical direction of the device, from bottom to top, a substrate (1), a buffer layer (2) with a groove structure on the upper surface, a GaN channel layer (3), a barrier layer (4), and a dielectric passivation layer (6) are stacked sequentially. The surface of the GaN HEMT device has a groove structure. Along the lateral direction of the device, the device surface has a source (5), a gate (7), and a drain (8) sequentially from one side to the other. Part of the gate (7) is located in the groove structure, and the bottom and sidewalls are in contact with the dielectric passivation layer (6). The part of the gate (7) covering the dielectric passivation layer (6) is a gate field plate structure. The source (5) and the drain (8) both penetrate the dielectric passivation layer (6) along the vertical direction of the device and extend into the barrier layer (4). The lower surface forms an ohmic contact with the barrier layer (4). The GaN cascaded diode comprises, from bottom to top, a substrate (1), a buffer layer (2) with multiple grooves on the upper surface, a GaN channel layer (3), a barrier layer (4), and a dielectric passivation layer (6), arranged in a vertical direction. The surface of the GaN cascaded diode has a groove structure. In the transverse direction of the device, the two ends of the device are a cathode (9) and an anode (10), respectively. Two or more floating gate metals (FG) are arranged between the cathode (9) and the anode. The cathode (9) penetrates the dielectric passivation layer (6) in the vertical direction of the device and extends into the barrier layer (4). The lower surface forms an ohmic contact with the barrier layer (4). The floating gate metals (FG) and the anode (10) are located in the groove structure. The bottom and sidewalls of the floating gate metals (FG) and the anode (10) near the cathode are in contact with the dielectric passivation layer (6), and the bottom and sidewalls away from the cathode (9) penetrate the dielectric passivation layer (6) and form an ohmic contact with the barrier layer (4).

2. A GaN HEMT device with ESD protection according to claim 1, characterized in that, The source (5) and cathode (9) are connected by interconnecting metal one (12-1), and the gate (7) and anode (10) are connected by interconnecting metal two (12-2).

3. A GaN HEMT device with ESD protection according to claim 1, characterized in that, The source (5) and anode (10) are connected by interconnecting metal one (12-1), and the gate (7) and cathode (9) are connected by interconnecting metal two (12-2).

4. The GaN HEMT device with ESD protection according to any one of claims 1 or 2, characterized in that, Multiple GaN cascaded diodes are connected in parallel between the source (5) and gate (7) of the GaN HEMT device.

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