一种VCSEL芯片的制备方法及VCSEL芯片
By adding a passivation layer to protect the epitaxial structure during the fabrication of VCSEL chips, the problem of epitaxial wafer damage caused by high-energy ion implantation is solved, and the optoelectronic properties and reliability of the chip are improved.
CN116885558BActive Publication Date: 2026-07-17ZHEJIANG RAYSEASC TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG RAYSEASC TECH CO LTD
- Filing Date
- 2023-06-08
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In the VCSEL process, high-energy ion implantation causes damage to the surface structure of the epitaxial wafer, affecting chip performance and the stability of optoelectronic properties.
Method used
A passivation layer is added to the epitaxial wafer to protect the epitaxial structure and isolate it from the influence of moisture. A passivation layer with a thickness of λ/4 to λ/2 is formed by depositing materials such as SiO2, SiN, Al2O3, and SiON through methods such as PECVD to protect the epitaxial structure from damage.
Benefits of technology
This improved the optoelectronic properties and reliability of VCSEL chips, reduced the number of dark defects, and increased the yield.
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Figure CN116885558B_ABST
Abstract
本申请属于半导体技术领域，具体为一种VCSEL芯片的制备方法，包括形成半导体的外延结构，且所述外延结构自下而上依次包括衬底层、N‑DBR层、有源区、P‑DBR层以及高掺杂层；在所述高掺杂层上沉积形成用以保护外延结构不受环境中水汽影响的钝化层；蚀刻部分钝化层以裸露出部分的高掺杂层，然后再沉积P型电接触层，所述P型电接触层形成电导通图案；氧化所述外延结构以形成出光孔；对外延结构进行研磨减薄，然后在衬底层底部沉积形成N型电接触层。
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