Flyback switching power supply with short circuit protection function

Abstract

The application relates to the field of switching power supplies, in particular to a flyback switching power supply with a short-circuit protection function. The power supply comprises a main circuit, a peripheral circuit and a detection circuit. The peripheral circuit is used for obtaining electric energy from a secondary side and supplying power to the main circuit. The detection circuit comprises a switch control unit, a reference unit and a mirror unit. The switch control unit controls the current passing through the reference unit based on the short-circuit working state of the secondary side of the flyback working circuit. The mirror unit copies the current of the reference unit and outputs the current to the main circuit to correspondingly generate a control signal. The main circuit controls the flyback working circuit to work or triggers the main circuit protection based on the control signal. The application has the advantage of realizing under-voltage protection in a low-voltage scene.

Description

Technical Field

[0001] This application relates to the field of switching power supplies, and in particular to a flyback switching power supply with short-circuit protection. Background Technology

[0002] Flyback switching power supplies, as a common power electronic device, are widely used in home appliances, communication power supplies, and laptop adapters, and are favored for their small size and low power consumption. However, with the continuous upgrading and improvement of electrical equipment, higher requirements are being placed on the short-circuit protection of switching power supplies.

[0003] To meet the needs of different product models, existing power protection modules need to be able to adapt and adjust quickly. Traditionally, undervoltage protection in switching power supplies is achieved by detecting when the output voltage falls below the design value, shutting off the switching signal, and entering protection mode. However, with the upgrading and improvement of electrical equipment, this traditional undervoltage protection circuit can no longer meet the requirements of certain specific applications.

[0004] For certain specialized applications, such as those requiring switching power supplies to operate normally at very low output voltages (e.g., 0.1V), traditional undervoltage protection circuits are ineffective. Without undervoltage protection, a short circuit triggers continuous conduction mode (CCM), increasing the output voltage and leading to excessive current in the output circuit, severe device losses, and overheating of power devices. Furthermore, the complex internal structure of the protection module necessitates adjustments to the parameters of multiple components when the product model changes, increasing development costs. Summary of the Invention

[0005] To achieve undervoltage protection in low-voltage scenarios, this application provides a flyback switching power supply with short-circuit protection.

[0006] This application provides a flyback switching power supply with short-circuit protection, which adopts the following technical solution: A flyback switching power supply with short-circuit protection includes: A flyback circuit is used to supply power to the primary side and output power to the secondary side. The control circuit includes a main circuit, peripheral circuits, and a detection circuit. The peripheral circuits are used to obtain induced electrical energy from the secondary side and supply power to the main circuit. The detection circuit includes a switch control unit, a reference unit, a first mirror unit, and a second mirror unit. The reference unit is used to generate a reference current. The switch control unit controls the current passing through the second mirror unit based on the operating state of the flyback circuit's secondary side. The first and second mirror units respectively replicate the current of the reference unit according to a preset ratio and output it to the main circuit to generate corresponding control signals. The main circuit controls the flyback circuit to operate or triggers main circuit protection based on the control signals.

[0007] Optionally, the flyback operating circuit includes a primary-side operating circuit and a secondary-side output circuit. The primary-side operating circuit is used to pass power current, and the secondary-side output circuit obtains electrical energy based on the intermittent conduction of the primary-side operating circuit.

[0008] Optionally, the main circuit is used to control the primary-side working circuit to periodically and intermittently conduct; the peripheral circuit is used to periodically and intermittently obtain induced electrical energy from the secondary-side output circuit and supply power to the main circuit, and the supply voltage to the main circuit gradually decreases during the half-cycle of the secondary-side power outage.

[0009] Optionally, the main circuit controls the primary working circuit to conduct when it detects that the control signal reaches the first threshold during the power-off half-cycle of the primary working circuit; during any power-off half-cycle of the peripheral circuit, when the moment when the control signal reaches the first threshold is no earlier than a preset time threshold relative to the moment when the power supply from the peripheral circuit to the main circuit is reduced to below the minimum operating voltage of the main circuit, the main circuit is powered off and no longer controls the primary working circuit to conduct.

[0010] Optionally, the peripheral circuit includes an auxiliary coil NA, a second resistor R2, a third resistor R3, a fifth diode D5, and a third capacitor C3. The auxiliary coil NA is coupled to the secondary coil NS. One end of the auxiliary coil NA is connected to ground and the third resistor R3, and the other end is connected to the second resistor R2. The end of the third resistor R3 away from ground is connected to the end of the second resistor R2 away from the auxiliary coil NA. The positive terminal of the fifth diode D5 is connected to the end of NA away from ground, and the negative terminal of the fifth diode D5 is connected to the power supply terminal of the main circuit. The positive terminal of the third capacitor C3 is connected to the negative terminal of the fifth diode D5, and the negative terminal of the third capacitor C3 is connected to ground. The connection node of the second resistor R2 and the third resistor R3 is used to output the feedback detection signal VS.

[0011] Optionally, the main circuit includes a first flip-flop DFFR1, a second flip-flop DFFR2, a third flip-flop DFFR3, a first AND gate AND1, a first comparator CMP1, a sixth capacitor C6, a third switch Q3, and a set signal output unit. A signal with an initial low level is set as the zero-crossing timing debounce signal. The first AND gate AND1 is used to input the inverted signal and the set signal of the zero-crossing timing debounce signal. The CLK1 pin of the first flip-flop DFFR1 is connected to the output of the first AND gate AND1, the D1 pin of the first flip-flop DFFR1 is connected to VDD, the RB1 pin of the first flip-flop DFFR1 is used to input a signal representing the on / off state of the primary-side working circuit, and the Q1 pin of the first flip-flop DFFR1 is used to output the switch signal SW. The CLK2 pin of the second flip-flop DFFR2 is used to input the switch signal. The reverse signal of SW is used to input the inverted signal of the zero-crossing timing debounce signal. The D2 pin of the second flip-flop DFFR2 is connected to VDD, and the RB2 pin of the second flip-flop DFFR2 is used to input the inverted signal of the zero-crossing timing debounce signal. The CLK3 pin of the third flip-flop DFFR3 is connected to the Q2 pin of the second flip-flop DFFR2, and the D3 pin of the third flip-flop DFFR3 is connected to VDD. The output signal of the Q3 pin of the third flip-flop DFFR3 is used as the new zero-crossing timing debounce signal. The control terminal of the third switch Q3 is used to input the inverted signal of the zero-crossing timing debounce signal. The input terminal is connected to the positive terminal of the sixth capacitor C6, and the output terminal is connected to the negative terminal of the sixth capacitor C6 and the ground. The positive terminal of the sixth capacitor C6 is used to obtain the output current of the mirror unit. The non-inverting input terminal of the first comparator CMP1 is used to input the reference voltage VREF1, and the inverting input terminal is connected to the positive terminal of the sixth capacitor C6. The set signal output unit is used to output a PWM set signal, and the switch signal SW is used to control the on / off state of the primary working circuit.

[0012] Optionally, one end of the secondary coil NS is connected to the positive terminal of the seventh diode D7, and the other end is connected to the negative terminal of the fifth capacitor C5 and serves as the negative output terminal of the secondary output circuit. The negative terminal of the seventh diode D7 is connected to the positive terminal of the fifth capacitor C5 and serves as the positive output terminal of the secondary output circuit.

[0013] Optionally, the switch control unit includes a second comparator CMP2. The non-inverting input of the second comparator CMP2 is used to acquire a feedback detection signal VS, the inverting input is used to acquire a reference voltage VREF21, and the output is used to connect to a second mirror unit to control the switching of the second mirror unit. The feedback detection signal VS is used to characterize the load condition of the secondary side of the flyback circuit.

[0014] Optionally, the first mirror unit includes several parallel twenty-second switching transistors Q22, and the current output by the first mirror unit is the sum of the currents flowing through each of the twenty-two switching transistors Q22.

[0015] Optionally, the second mirror unit includes several parallel twenty-third switches Q23 and a twenty-fourth switch Q24 connected in series with each of the twenty-third switches Q23. The twenty-fourth switch Q24 is the sum of the currents passing through each of the twenty-third switches Q23 and serves as the output current of the second mirror unit. The output terminal of the switch control unit is connected to the control terminal of the twenty-fourth switch Q24.

[0016] Optionally, the reference unit includes a 21st switch Q21, whose input is connected to VDD, and whose output and control terminals are connected to a constant current source; the 22nd switch Q22 of the first mirror unit has its input connected to VDD, and its output and control terminals are connected to the control terminal of the 21st switch; the 23rd switch Q23 of the second mirror unit has its input connected to VDD, its control terminal connected to the output of the 21st switch Q21, and its output connected to the input of the 24th switch Q24. The sum of the currents at the outputs of the 22nd switch Q22 and the 24th switch Q24 is the output supply current Ich.

[0017] In summary, this application includes at least one of the following beneficial technical effects: 1. The flyback switching power supply of this application is applicable to discontinuous mode. When a short circuit occurs in the secondary output circuit, it can detect the short circuit state and distinguish it from the discontinuous mode, thereby controlling the primary working circuit to extend the interruption duration in discontinuous mode and thus entering power protection. Compared with existing solutions, it is applicable to situations where the switching power supply output is very low.

[0018] 2. Since the requirements for circuit state vary in different practical scenarios, the low-voltage output threshold of the switching power supply also varies. Therefore, in this application, a detection circuit is used to control the short-circuit state. By adjusting the resistance value within the detection circuit, adjusting the number of current mirrors, or controlling the charging and discharging of the capacitor, the charging time can be directly adjusted, which effectively reduces the workload of adaptive adjustment required to apply the flyback switching power supply to different products. Attached Figure Description

[0019] Figure 1 A topology diagram of a flyback switching power supply with short-circuit protection function is shown in one embodiment of the present invention.

[0020] Figure 2 A partial circuit diagram of the main circuit in one embodiment of the present invention is shown.

[0021] Figure 3 A circuit diagram of the detection circuit in one embodiment of the present invention is shown.

[0022] Explanation of reference numerals in the attached figures: 1. Primary side working circuit; 2. Secondary side output circuit; 3. Main circuit; 4. Peripheral circuit; 5. Rectifier and filter circuit. Detailed Implementation

[0023] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0024] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the inventive concept. As part of this specification, some of the accompanying drawings of this disclosure are block diagrams illustrating structures and devices to avoid complicating the disclosed principles. For clarity, not all features of the actual embodiment need to be described. Furthermore, the language used in this disclosure has been primarily chosen for readability and instructional purposes and may not have been chosen to define or limit the subject matter of the invention, thus requiring the necessary claims to determine such inventive subject matter. References to “an embodiment” or “an embodiment” in this disclosure mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment, and multiple references to “an embodiment” or “an embodiment” should not be construed as necessarily referring to the same embodiment.

[0025] Unless explicitly defined, the terms “a,” “an,” and “the” are not intended to refer to a singular entity, but rather to include a general category whose specific examples can be used for illustration. Therefore, the use of the terms “a” or “an” can mean any number of at least one, including “a,” “one or more,” “at least one,” and “one or more.” The term “or” means any of the options and any combination of the options, including all options unless explicitly indicated that the options are mutually exclusive. The phrase “at least one of” when combined with a list of items refers to a single item in the list or any combination of items in the list. The phrase does not require all items listed unless explicitly defined as such.

[0026] This application discloses a flyback switching power supply with short-circuit protection function, referring to... Figure 1 The flyback switching power supply includes a flyback operating circuit and a control circuit. The flyback operating circuit is used to output electrical energy from the external power supply and through the conversion between the primary and secondary sides, while the control circuit is used to control the on / off state of the primary side. When a short circuit occurs on the secondary side, the operation of the primary side is interrupted and undervoltage protection is activated.

[0027] The flyback circuit includes a primary-side operating circuit 1 and a secondary-side output circuit 2. The primary-side operating circuit is used to pass power current, and the secondary-side output circuit obtains electrical energy based on the intermittent conduction of the primary-side operating circuit.

[0028] Specifically, in one embodiment, the primary-side operating circuit includes a primary-side coil NP, a second switch M2, and a fourth resistor R4. The two ends of the primary-side coil NP are respectively connected to the input terminal of the second switch M2 and one connection terminal of an external input. The two ends of the fourth resistor R4 are respectively connected to the output terminal of the second switch M2 and the other connection terminal of the external input. The control terminal of the second switch M2 is connected to a control circuit to obtain a switching signal SW. Of course, the arrangement order of the primary-side coil NP, the second switch M2, and the fourth resistor R4 can differ in different embodiments. For example, with the two connection terminals of the external input as positive and negative, the primary-side coil NP, the second switch M2, and the fourth resistor R4 can be connected sequentially from positive to negative, or sequentially from negative to positive, or other electronic components such as resistors can be added in between. The key is that the second switch M2 controls the on / off state of the circuit after receiving the switching signal SW, and that the current in the primary-side coil NP changes when the circuit is switched on or off, and that the voltage drop across the fourth resistor R4 changes in both the on and short-circuit states.

[0029] Furthermore, the second switch M2 can vary in different embodiments. For example, the second switch M2 can be a PMOS or an NMOS transistor, as long as it has low leakage current and can respond quickly to the switching signal SW at the input control terminal. As an example, in the above embodiment, the second switch M2 is an NMOS transistor. The two ends of the primary coil NP are connected to the drain of the second switch M2 and the positive terminal of the external input, respectively. The two ends of the fourth resistor R4 are connected to the source of the second switch M2 and the negative terminal of the external input, respectively. The negative terminal of the external input is connected to ground. The gate of the second switch M2 is connected to the control circuit to obtain the switching signal SW. When the second switch M2 receives a high-level switching signal SW, i.e., SW=1, the primary working circuit is turned on, which is referred to below as the conduction half-cycle of the primary working circuit. During the conduction half-cycle, the end of the fourth resistor R4 furthest from ground is used to output the working detection signal CS, and CS=1. When the second switch M2 receives a low-level switching signal SW, i.e., SW=0, the primary-side working circuit is disconnected, which is referred to below as the power-off half-cycle of the primary-side working circuit. During the power-off half-cycle, the end of the fourth resistor R4 furthest from the ground wire is used to output the working detection signal CS, and CS=0.

[0030] To reduce the adverse effects on circuit components caused by the rapid current change during the fast switching of the second switching transistor M2, and to improve the operating quality of the primary-side working circuit, in some embodiments, the primary-side working circuit further includes a spike pulse absorption unit. The spike pulse absorption unit includes a first resistor R1, a fourth capacitor C4, and a sixth diode D6. The anode of the sixth diode D6 is connected to the primary-side coil NP, and the cathode of the sixth diode D6 is connected to the cathode of the fourth capacitor C4 and the first resistor R1. The end of the first resistor R1 furthest from the sixth diode D6 is connected to the end of the primary-side coil NP furthest from the sixth diode D6, and the anode of the fourth capacitor C4 is connected to the end of the primary-side coil NP furthest from the sixth diode D6. In these embodiments, the connection methods of the first resistor R1, the fourth capacitor C4, and the sixth diode D6 can be different. As long as the fourth capacitor C4 can absorb the pulse generated by the primary coil NP, the first resistor R1 can dissipate the discharge of the primary coil NP and the fourth capacitor C4, the sixth diode D6 can unidirectionally conduct the current generated by the primary coil when the second switch M2 is turned off, and the first resistor R1 and the fourth capacitor C4 are prevented from short-circuiting the primary coil NP when the second switch M2 is turned on.

[0031] The secondary-side output circuit 2 includes a secondary-side coil NS, a seventh diode D7, and a fifth capacitor C5. The secondary-side coil NS is coupled to the primary-side coil NP, and its two ends are respectively connected to the two ends of the fifth capacitor C5. The seventh diode D7 is located on any connection line between the secondary-side coil NS and the fifth capacitor C5. The two ends of the fifth capacitor C5 serve as the output terminals of the secondary-side output circuit. Since the secondary-side coil NS is coupled to the primary-side coil NP, when the current in the primary-side coil NP changes, the secondary-side coil NS will generate a corresponding positive or reverse induced electromotive force. Similarly, in these embodiments, the connection methods of the secondary-side coil NS, the seventh diode D7, and the fifth capacitor C5 can differ, as long as the seventh diode D7 can prevent the secondary-side coil NS from outputting during half a cycle, and the fifth capacitor C5 can output during that half cycle. For example, one end of the secondary-side coil NS is connected to the positive terminal of the seventh diode D7, and the other end is connected to the negative terminal of the fifth capacitor C5, serving as the negative output terminal of the secondary-side output circuit. The negative terminal of the seventh diode D7 is connected to the positive terminal of the fifth capacitor C5, serving as the positive output terminal of the secondary-side output circuit. It should be noted that in this embodiment, the end of the primary coil NP that is furthest from the positive input and the end of the secondary coil NS that is connected to the positive terminal of the fifth capacitor C5 are the same-named ends.

[0032] The primary-side operating circuit can directly use DC input as external input, or it can process AC input to indirectly obtain DC input. Specifically, in some embodiments, the flyback operating circuit also includes a rectifier filter circuit 5, which includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first capacitor C1, and a second capacitor C2. The first diode D1, second diode D2, third diode D3, and fourth diode D4 form a rectifier bridge. For example, the positive and negative terminals of the first capacitor C1 are connected to the live wire and the neutral wire, respectively; the positive terminal of the first diode D1 and the negative terminal of the third diode D3 are connected to the live wire; the positive terminal of the second diode D2 and the negative terminal of the fourth diode D4 are connected to the neutral wire; the negative terminals of the first diode D1 and the second diode D2 are connected to the positive terminal of the second capacitor C2; the positive terminal of the second capacitor C2 serves as the positive output of the rectifier filter circuit; and the positive terminals of the third diode D3 and the fourth diode D4 are connected to the negative terminal of the second capacitor C2 and serve as the negative output of the rectifier filter circuit.

[0033] The control circuit includes a main circuit 3, a peripheral circuit 4, and a detection circuit. The main circuit outputs a switching signal SW to control the primary-side working circuit to periodically turn on and off. The peripheral circuit periodically and intermittently receives induced energy from the secondary-side output circuit and supplies power to the main circuit. During the half-cycle of power outage, the supply voltage to the main circuit gradually decreases. The duration of the half-cycle is variable, and the longer the duration, the lower the supply voltage from the peripheral circuit to the main circuit, until it falls below the minimum operating voltage of the main circuit. By setting the detection circuit, when the secondary-side output voltage is within the normal fluctuation range, the control signal generated by the detection circuit outputting current / voltage to the main circuit ensures that the peripheral circuit can still provide a sufficiently high supply voltage to the main circuit at the end of the half-cycle of power outage. In other words, when the main circuit detects that the control signal has reached the first threshold during the power-off half-cycle of the primary-side working circuit, it controls the primary-side working circuit to conduct. During any power-off half-cycle of the peripheral circuit, if the moment when the control signal reaches the first threshold is no earlier than a preset time threshold relative to the moment when the power supply from the peripheral circuit to the main circuit drops below the minimum operating voltage of the main circuit, the main circuit de-energizes and no longer controls the primary-side working circuit to conduct. It is important to note that due to the delay in signal transmission, the preset time threshold corresponds to this delay. For example, when the control signal reaches the first threshold, the primary-side working circuit will conduct after a series of signal transmissions and processing. During the process from the primary-side working circuit conducting to the main circuit starting to charge, there is still a series of signal transmissions and processing, which will incur time consumption. That is, there is a time difference between the control signal reaching the first threshold and the main circuit starting to charge; this time difference is the preset time threshold. In different embodiments, the implementation structure of the main circuit can vary. As an example, the main circuit includes a first flip-flop DFFR1, a second flip-flop DFFR2, a third flip-flop DFFR3, a first AND gate AND1, a first comparator CMP1, a sixth capacitor C6, a third switch Q3, and a set signal output unit. A signal with an initial low level is set as the zero-crossing timing debounce signal S_tdmin. The first AND gate AND1 is used to input the set signal and the inverted signal of the zero-crossing timing debounce signal S_tdmin. Specifically, one input of the first AND gate AND1 is connected to the set signal output unit to obtain the PWM set signal, and the other input of the first AND gate AND1 receives the zero-crossing timing debounce signal S_tdmin through a first NOT gate NOT1.

[0034] The CLK1 pin of the first flip-flop DFFR1 is connected to the output of the first AND gate AND1. The D1 pin of the first flip-flop DFFR1 is connected to VDD. The RB1 pin of the first flip-flop DFFR1 is used to input a signal representing the on / off state of the primary-side working circuit. The Q1 pin of the first flip-flop DFFR1 is used to output the switching signal SW. Specifically, the RB1 pin of the first flip-flop DFFR1 is used to input the inverted signal of the digital signal corresponding to the working detection signal CS. It should be noted that since the working detection signal CS itself is an analog signal, it needs to be converted into a digital signal through certain transformation and threshold judgment methods. This solution does not make specific limitations. In addition, in the embodiments given in this application, the first flip-flop DFFR1, the second flip-flop DFFR2, and the third flip-flop DFFR3 are all synchronous reset D flip-flops. In other embodiments, asynchronous reset D flip-flops can be used. It is only necessary to add an inverter to the RB pin compared to this solution. Alternatively, other types of flip-flops or electronic components can be used, as long as the functional implementation logic is the same as this solution.

[0035] It is important to note that, for Figure 2 The VDD of the main circuit is usually supplied by Figure 1 The voltage is derived from VCC in the circuit, therefore, if the input voltage of VCC is undervoltage, the voltage of VDD in the main circuit will also be undervoltage. Currently, a common practice during power-on is to design a high-voltage startup module for the switching power supply. There are many ways to implement a high-voltage startup module. For example, at the moment the power supply is powered on, the third capacitor C3 is charged through the primary coil. When the VCC voltage reaches the startup voltage of the main circuit, the various references of the main circuit are established. After the main circuit starts working, the high-voltage startup is completed, and the power supply for the third capacitor C3 is provided by the auxiliary coil NA, and the high-voltage startup module is disconnected.

[0036] The CLK2 pin of the second flip-flop DFFR2 is used to input the inverted signal of the switch signal SW. The D2 pin of the second flip-flop DFFR2 is connected to VDD. The RB2 pin of the second flip-flop DFFR2 is used to input the inverted signal of the zero-crossing timing debounce signal S_tdmin. Specifically, the CLK2 pin of the second flip-flop DFFR2 is connected to the Q1 pin of the first flip-flop DFFR1 through the second NOT gate of the inverter NOT2. The RB2 pin of the second flip-flop DFFR2 receives the zero-crossing timing debounce signal S_tdmin through the third NOT gate of the inverter NOT3.

[0037] The CLK3 pin of the third flip-flop DFFR3 is connected to the Q2 pin of the second flip-flop DFFR2, and the D3 pin of the third flip-flop DFFR3 is connected to VDD. The output signal of the Q3 pin of the third flip-flop DFFR3 serves as the new zero-crossing timing debounce signal S_tdmin. The control terminal of the third switch Q3 is used to input the inverted signal of the zero-crossing timing debounce signal S_tdmin. The input terminal is connected to the positive terminal of the sixth capacitor C6, and the output terminal is connected to the negative terminal of the sixth capacitor C6 and ground. The positive terminal of the sixth capacitor C6 is used to obtain the charging current Ich. The non-inverting input terminal of the first comparator CMP1 is used to input the reference voltage VREF1, and the inverting input terminal is connected to the positive terminal of the sixth capacitor C6. In addition, the third switch Q3 can be different in different embodiments. For example, the third switch Q3 can be a PMOS transistor or an NMOS transistor, as long as it has low leakage current and can respond quickly to the control signal of the input control terminal. As an example, in the above embodiment, the third switch Q3 is an NMOS transistor. The gate of the third switch Q3 is used to input the inverse signal of the zero-crossing timing anti-jitter signal S_tdmin. The drain is connected to the positive terminal of the sixth capacitor C6, and the source is connected to the negative terminal of the sixth capacitor C6 and the ground line.

[0038] The peripheral circuit includes an auxiliary coil NA, a second resistor R2, a third resistor R3, a fifth diode D5, and a third capacitor C3. The auxiliary coil NA is coupled to the secondary coil NS. One end of the auxiliary coil NA is connected to ground and the third resistor R3, and the other end is connected to the second resistor R2. The end of the third resistor R3 furthest from ground is connected to the end of the second resistor R2 furthest from the auxiliary coil NA. The anode of the fifth diode D5 is connected to the end of NA furthest from ground, and the cathode of the fifth diode D5 is connected to the power supply terminal of the main circuit. The anode of the third capacitor C3 is connected to the cathode of the fifth diode D5, and the cathode of the third capacitor C3 is connected to ground. The connection point of the second resistor R2 and the third resistor R3 is used to output a feedback detection signal VS. The feedback detection signal VS is used to characterize the secondary load condition. Capacitor C3 obtains energy from the auxiliary coil NA and supplies power to the main circuit during the half-cycle of the primary coil's conduction. Furthermore, the end of the auxiliary coil NA furthest from ground and the end of the primary coil NP furthest from the positive input are of the same name.

[0039] The working principles of the main circuit and peripheral circuits are as follows: Initially, S_tdmin is set to a low level (hereinafter, 0 represents low level and 1 represents high level; at this point, S_tdmin=0). S_tdmin outputs 1 through the first NOT gate (NOT1) and is input to the input of the first AND gate (AND1). When the set signal SET_SW output from the set signal output unit goes high, the output of the first AND gate goes high, meaning CLK1=1. Since the primary coil is not yet turned on, CS=0 and RB1=1. The output Q1 of the first flip-flop DFFR1 goes high, meaning SW=1. At this point, the primary working circuit is turned on, the power-off half-cycle ends, the primary coil current begins to rise, and the conducting half-cycle begins.

[0040] When the switching signal SW is input to the second NOT gate NOT2, CLK2 goes low, i.e., CLK2=0. When S_tdmin is input to the third NOT gate NOT3, the output goes high, and RB2 goes high, i.e., RB2=1. Therefore, the output Q2 of the second flip-flop DFFR2 is low, i.e., Q2=CLK3=0.

[0041] Since RB2=1, the third switch Q3 is turned on, and the sixth capacitor C6 discharges. Therefore, the voltage level VC6 at the end of the sixth capacitor C6 furthest from ground is less than VREF1, and the first comparator CMP1 outputs high, i.e., RB3=1. Since CLK3 does not have a rising edge, S_tdmin=0. Because the primary-side working circuit continues to conduct, i.e., the current through the primary coil NP continues to rise towards a stable value, until the current of the primary-side working circuit rises to the design value, then the working detection signal CS turns high, correspondingly, RB1=0. Due to the characteristics of the first flip-flop DFFR1, the output Q1 of the first flip-flop DFFR1 is reset to 0, i.e., SW=0. Therefore, the primary-side working circuit is turned off, the conducting half-cycle ends, and the de-energized half-cycle begins. At the instant the primary-side working circuit is turned off, the primary coil NP discharges rapidly through the spike pulse absorption unit. Correspondingly, the secondary coil NS generates an induced current and turns on, charging the fifth capacitor C5 and supplying power to the outside.

[0042] Correspondingly, the auxiliary coil NA generates an induced electromotive force and charges the third capacitor C3, while simultaneously supplying power to the main circuit. Since SW=0, CLK2 goes high, meaning a rising edge is input to CLK2. At this time, RB2=1, therefore the output Q2 of the second flip-flop DFFR2 goes high, meaning a rising edge is input to CLK3. At this time, RB3=1, therefore the output of the third flip-flop DFFR3, the third switch Q3, goes high, and S_tdmin goes high, meaning S_tdmin=1.

[0043] Since S_tdmin=1, S_tdmin outputs low after passing through the third NOT gate (NOT3), RB2=0, and the output Q2 of the second flip-flop DFFR2 is reset, i.e., Q2=0. It's important to note that because RB2=0, the third switch Q3 stops conducting, and Ich begins charging the sixth capacitor C6. During charging, VC6 continuously rises until it exceeds VREF1. When VC6>VREF1, RB3=0. Therefore, when VC6<VREF1, due to the reset of Q2, a falling edge is generated, so the output of the third flip-flop DFFR3, the third switch Q3, remains high, i.e., S_tdmin=1. After Ich continues charging the sixth capacitor C6 for a period of time, VC6>VREF1, RB3=0, and the output of the third flip-flop DFFR3, the third switch Q3, is reset, i.e., S_tdmin=0, until SW=1, completing the half-cycle of power-off. This completes the conduction half-cycle and de-energization half-cycle of a basic working circuit, and then enters the next cycle, repeating the above process.

[0044] In summary, the duration for which S_tdmin is high is determined by the charging duration of the sixth capacitor C6, and the charging duration of the sixth capacitor C6 depends on the value of Ich. Therefore, controlling the value of Ich can control the duration for which S_tdmin is high, which is the duration for which the second switch M2 is turned off.

[0045] In the embodiments of this application, the charging of Ich is performed by a detection circuit. In different embodiments, the detection circuit can control the magnitude of Ich, or control the charging duration of the sixth capacitor C6 by controlling whether Ich is output. Specifically, in the embodiments of this application, the detection circuit includes a switch control unit, a reference unit, a first mirror unit, and a second mirror unit. The switch control unit controls the current passing through the second mirror unit based on the operating state of the secondary side of the flyback circuit. The first mirror unit and the second mirror unit respectively replicate the current of the reference unit according to a preset ratio and output it to the sixth capacitor C6.

[0046] Specifically, the switch control unit includes a second comparator CMP2. The non-inverting input of the second comparator CMP2 is used to acquire the feedback detection signal VS, the inverting input is used to acquire the reference voltage VREF21, and the output is used to connect to the second mirror unit to control the switching of the second mirror unit. The reference voltage VREF21 is a fixed lower limit value, such as 0.1V. When VS is greater than VREF21, the signal output by the operational amplifier AMP is high, controlling the second mirror unit to turn on; when VS is less than VREF21, the signal output by the operational amplifier AMP is low, controlling the second mirror unit to turn off.

[0047] The first mirror unit includes several parallel-connected twenty-second switches Q22, and the output current of the first mirror unit is the sum of the currents flowing through each of the twenty-two switches Q22. The second mirror unit includes several parallel-connected twenty-third switches Q23 and a twenty-fourth switch Q24 connected in series with each of the twenty-third switches Q23. The twenty-fourth switch Q24 is the sum of the currents flowing through each of the twenty-third switches Q23 and serves as the output current of the second mirror unit. The output terminal of the switch control unit is connected to the control terminal of the twenty-fourth switch Q24. Since the first and second mirror units replicate the current of the reference unit, different implementation methods can be used. As an example, each branch of the first and second mirror units can form a current mirror with the reference unit, that is, each branch of the first and second mirror units will carry the same current as the reference unit when it is turned on.

[0048] Specifically, the reference unit includes a 21st switch Q21, whose input is connected to VDD, and whose output and control terminals are connected to a constant current source; the first mirror unit has a 22nd switch Q22 whose input is connected to VDD, and whose output and control terminals are connected to the control terminal of the 21st switch; the second mirror unit has a 23rd switch Q23 whose input is connected to VDD, whose control terminal is connected to the output of the 21st switch Q21, and whose output is connected to the input of the 24th switch Q24. The sum of the currents at the outputs of the 22nd switch Q22 and the 24th switch Q24 is the output supply current Ich.

[0049] It should be noted that the specific components used in the twenty-first switch Q21, twenty-second switch Q22, twenty-third switch Q23, and twenty-fourth switch Q24 can differ; for example, they can be PMOS or NMOS transistors. Any switch with low leakage current and a fast response to input control signals is acceptable. As an example, in the above embodiment, the twenty-first switch Q21, twenty-second switch Q22, twenty-third switch Q23, and twenty-fourth switch Q24 are all NMOS transistors, with the input terminal being the drain, the output terminal being the source, and the control terminal being the gate.

[0050] The working principle of the detection circuit is as follows: Switches Q21 (21), Q22 (22), and Q23 (23) act as current mirrors for each other. Different ratios of these switches can be used to obtain different currents. For example, if the current through the reference unit is I1, the current through the first mirror unit is I2, and the current through the third mirror unit is I3, and Q21:Q22:Q23 = 1:5:10, then I1:I2:I3 = 1:5:10. If the constant current source I1 is 1µA, then I2 = 5µA and I3 = 10µA. VREF21 is designed to be approximately greater than 0V (e.g., VREF21 = 0.1V). During the half-cycle of the primary-side circuit's power-off and without protection failure, VS is greater than VREF21, the second comparator CMP2 outputs high, switch Q24 (24) conducts, and capacitor C6 (6) charges with a current of I2 + I3. Figure 2 When VC6 rises and becomes greater than VREF1, the output of the first comparator CMP1 goes low, RB3 = 0, and the output of the third flip-flop DFRR1 goes low, i.e., S_tdmin is reset to low. At the same time, since S_tdmin = 0, the third switch Q3 turns on, and the sixth capacitor C6 discharges.

[0051] Since S_tdmin=0, after SET_SW goes high, the switch control signal SW goes high, and the primary-side working circuit enters the conduction half-cycle, storing energy in the primary-side coil NP. When the current in the primary-side working circuit exceeds the design value, CS goes high, RB1=0, the output of Q1 of the first flip-flop DFFR1=0, SW is reset to low, and the primary-side working circuit enters the power-off half-cycle. S_tdmin goes high, the third switch Q3 is turned off, and the sixth capacitor C6 is charged with I2+I3.

[0052] When a short circuit occurs in the secondary output circuit, the feedback detection signal VS=0. Since VS is less than VREF21, the output of the second comparator CMP2 goes low, the twenty-fourth switch Q24 is turned off, and the sixth capacitor C6 is charged with the current value of I2. It should be noted that the current I2 is relatively small, and it takes a long time to charge the sixth capacitor C6. That is to say, when the third capacitor C3 continues to discharge until VCC reaches the undervoltage value, the sixth capacitor C6 may not have been charged to VC6>VREF1, or the sixth capacitor C6 may have been charged to VC6>VREF1, but the related signal transmission has not yet caused the auxiliary coil NA to charge, which is sufficient to meet the design requirements.

[0053] Since VC6 is always less than VREF1, the output of the first comparator CMP1 is high, and RB3 is high. Therefore, S_tdmin will remain high and cannot be reset, and the switch control signal SW will remain low, so energy storage on the primary side will cease. When the energy of the secondary coil NS and the auxiliary coil NA is exhausted, the auxiliary coil NA no longer supplies power to VCC and the third capacitor C3. As a result, the VCC voltage drops. When it drops to the undervoltage protection point, the main circuit stops working, and the system activates protection.

[0054] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A flyback switching power supply with short-circuit protection, characterized in that, include: A flyback circuit is used to supply power to the primary side and output power to the secondary side. The control circuit includes a main circuit, peripheral circuits, and a detection circuit. The peripheral circuits are used to obtain induced electrical energy from the secondary side and supply power to the main circuit. The detection circuit includes a switch control unit, a reference unit, a first mirror unit, and a second mirror unit. The reference unit is used to generate a reference current. The switch control unit includes a comparator. The non-inverting input of the comparator is used to obtain a feedback detection signal characterizing the load condition of the secondary side of the flyback circuit. The inverting input of the comparator is used to obtain a reference voltage. The output of the comparator is connected to the second mirror unit to control the switching of the second mirror unit, so that the switch control unit controls the current passing through the second mirror unit based on the operating state of the secondary side of the flyback circuit. The first mirror unit and the second mirror unit respectively replicate the current of the reference unit according to a preset ratio and output it to the main circuit. The sum of the output current of the first mirror unit and the output current of the second mirror unit is used as the power supply current output to the main circuit. The main circuit generates a control signal based on the power supply current. The main circuit controls the flyback circuit to work or triggers the main circuit protection based on the control signal.

2. The flyback switching power supply with short-circuit protection function according to claim 1, characterized in that, The flyback operating circuit includes a primary-side operating circuit and a secondary-side output circuit. The primary-side operating circuit is used to pass power current, and the secondary-side output circuit obtains electrical energy based on the intermittent conduction of the primary-side operating circuit. The main circuit is used to control the primary side working circuit to periodically and intermittently conduct; the peripheral circuit is used to periodically and intermittently obtain induced electrical energy from the secondary side output circuit and supply power to the main circuit, and the supply voltage to the main circuit gradually decreases during the half-cycle of the secondary side being cut off.

3. The flyback switching power supply with short-circuit protection function according to claim 2, characterized in that, When the main circuit detects that the control signal reaches the first threshold during the power-off half-cycle of the primary working circuit, it controls the primary working circuit to conduct. During any power-off half-cycle of the peripheral circuit, when the moment when the control signal reaches the first threshold is no earlier than a preset time threshold relative to the moment when the power supply from the peripheral circuit to the main circuit drops below the minimum operating voltage of the main circuit, the main circuit is powered off and no longer controls the primary working circuit to conduct.

4. The flyback switching power supply with short-circuit protection function according to claim 3, characterized in that, The peripheral circuit includes an auxiliary coil NA, a second resistor R2, a third resistor R3, a fifth diode D5, and a third capacitor C3. The auxiliary coil NA is coupled to the secondary coil NS. One end of the auxiliary coil NA is connected to ground and the third resistor R3, and the other end is connected to the second resistor R2. The end of the third resistor R3 away from ground is connected to the end of the second resistor R2 away from the auxiliary coil NA. The positive terminal of the fifth diode D5 is connected to the end of NA away from ground, and the negative terminal of the fifth diode D5 is connected to the power supply terminal of the main circuit. The positive terminal of the third capacitor C3 is connected to the negative terminal of the fifth diode D5, and the negative terminal of the third capacitor C3 is connected to ground. The connection node of the second resistor R2 and the third resistor R3 is used to output the feedback detection signal VS.

5. The flyback switching power supply with short-circuit protection function according to claim 4, characterized in that, The main circuit includes a first flip-flop DFFR1, a second flip-flop DFFR2, a third flip-flop DFFR3, a first AND gate AND1, a first comparator CMP1, a sixth capacitor C6, a third switch Q3, and a set signal output unit. A signal with an initial value of low level is set as the zero-crossing timing debounce signal. The first AND gate AND1 is used to input the inverted signal and the set signal of the zero-crossing timing debounce signal. The CLK1 pin of the first flip-flop DFFR1 is connected to the output terminal of the first AND gate AND1, the D1 pin of the first flip-flop DFFR1 is connected to VDD, the RB1 pin of the first flip-flop DFFR1 is used to input a signal representing the on / off state of the primary side working circuit, and the Q1 pin of the first flip-flop DFFR1 is used to output the switch signal SW. The CLK2 pin of the second flip-flop DFFR2 is used to input the inverted signal of the switch signal SW, the D2 pin of the second flip-flop DFFR2 is connected to VDD, and the RB2 pin of the second flip-flop DFFR2 is used to input the inverted signal of the zero-crossing timing anti-jitter signal. The CLK3 pin of the third flip-flop DFFR3 is connected to the Q2 pin of the second flip-flop DFFR2, and the D3 pin of the third flip-flop DFFR3 is connected to VDD. The output signal of the Q3 pin of the third flip-flop DFFR3 serves as the new zero-crossing timing debounce signal. The control terminal of the third switch Q3 is used to input the inverted signal of the zero-crossing timing debounce signal. The input terminal is connected to the positive terminal of the sixth capacitor C6, and the output terminal is connected to the negative terminal of the sixth capacitor C6 and ground. The positive terminal of the sixth capacitor C6 is used to obtain the output current of the mirror unit. The non-inverting input terminal of the first comparator CMP1 is used to input the reference voltage VREF1, and the inverting input terminal is connected to the positive terminal of the sixth capacitor C6. The set signal output unit is used to output the PWM set signal, and the switching signal SW is used to control the on / off state of the primary-side working circuit.

6. The flyback switching power supply with short-circuit protection function according to claim 2, characterized in that, The primary-side working circuit includes a primary-side coil NP, a second switch M2, and a fourth resistor R4. The two ends of the primary-side coil NP are respectively connected to the input terminal of the second switch M2 and one connection terminal of an external input. The two ends of the fourth resistor R4 are respectively connected to the output terminal of the second switch M2 and another connection terminal of an external input. The control terminal of the second switch M2 is connected to the main circuit to obtain the switching signal SW.

7. The flyback switching power supply with short-circuit protection function according to claim 1, characterized in that, The first mirror unit includes several parallel-connected 22nd switching transistors Q22, and the current output by the first mirror unit is the sum of the currents flowing through each 22nd switching transistor Q22.

8. The flyback switching power supply with short-circuit protection function according to claim 1, characterized in that, The second mirror unit includes several parallel twenty-third switches Q23 and a twenty-fourth switch Q24 connected in series with each of the twenty-third switches Q23. The twenty-fourth switch Q24 is the sum of the currents passing through each of the twenty-third switches Q23 and serves as the output current of the second mirror unit. The output terminal of the switch control unit is connected to the control terminal of the twenty-fourth switch Q24.

9. The flyback switching power supply with short-circuit protection function according to claim 8, characterized in that, The reference unit includes a 21st switch Q21, whose input is connected to VDD, and whose output and control terminals are connected to a constant current source. The first mirror unit has a 22nd switch Q22 whose input is connected to VDD, and whose output and control terminals are connected to the control terminal of the 21st switch. The second mirror unit has a 23rd switch Q23 whose input is connected to VDD, whose control terminal is connected to the output of the 21st switch Q21, and whose output is connected to the input of the 24th switch Q24. The sum of the currents at the outputs of the 22nd switch Q22 and the 24th switch Q24 is the output supply current Ich.

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