A high speed multiple output latch circuit

Abstract

The application belongs to the technical field of analog-digital conversion, and particularly relates to a high-speed multi-output latch circuit which is suitable for a successive approximation type analog-digital converter circuit. The application fully utilizes the mutual relationship among various signals by respectively arranging PMOS transistors and NMOS transistors, simultaneously performs reset and latching, and only controls reset and latching by one clock signal compared with a traditional high-speed SAR logic latch architecture. In the case of slightly increasing delay, the size and complexity of the additional required logic circuit are greatly reduced. The application does not need a comparator to provide an additional reset or latching control signal, greatly simplifies the size and complexity of the circuit, can output four control signals, reduces the area of a chip, and solves the defects of a large logic circuit, multiple clock control signals and only two output control signals of the existing high-speed SAR logic latch circuit structure.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital conversion technology, specifically a high-speed multi-output latch circuit, suitable for successive approximation analog-to-digital converter circuits. Background Technology

[0002] Successive approximation (SAR) analog-to-digital converters (ADCs) have become a popular research area for medium-resolution and medium-bandwidth ADCs due to their low power consumption and small chip area. However, for traditional SAR ADC circuits, especially those using split capacitor array structures, the latching and shifting of traditional SAR logic module units using D flip-flop arrays are performed separately, resulting in slow speed and a large number of logic circuits. Furthermore, the need for numerous logic circuits to control the switching of the capacitor array also leads to relatively high power consumption.

[0003] Existing high-speed latch circuits employ a self-latching structure, enabling simultaneous data latching and retention. This significantly improves operating speed and reduces the required logic unit circuitry, thereby decreasing chip area.

[0004] However, traditional high-speed latch circuit structures still have problems and shortcomings when dealing with SARADC circuits that use capacitor arrays that require multiple switching during a single quantization, such as traditional split capacitor arrays. First, split capacitor arrays require at least four control bits to control the switching of the capacitor array after each comparison. Traditional latches can only provide two output states at a time; to output more control bits, more logic circuitry and longer operating delays are needed. Second, in traditional structures, latch control requires an additional EOL signal from the comparator to control its normal operation. Third, traditional high-speed latch circuit structures require a large number of logic circuits to generate at least three clock signals to control its normal operation, resulting in a larger logic circuit area and higher power consumption. Summary of the Invention

[0005] To address the aforementioned problems or shortcomings, and to overcome the drawbacks of existing high-speed SAR logic latch circuits, such as large logic circuit size, the need for multiple clock control signals, and the ability to output only two control signals, this invention proposes a high-speed multi-output latch circuit.

[0006] A high-speed multi-output latch circuit includes a latch execution circuit (such as...) Figure 1 As shown), the CLK signal logic circuit (such as...) Figure 2 (as shown) and READY signal logic circuit (such as Figure 3 (As shown).

[0007] The latching execution circuit is composed of MOSFET transistors for signal latching, specifically including PMOS transistors M6, M7, M8, M9, M14, and M15, and NMOS transistors M0, M1, M2, M3, M4, M5, M10, M11, M12, and M13; the input signals VIP and VIN are the latched signals, CLK is the clock control signal, and VONT, VOPT, VONB, and VOPB are the four output signal nodes.

[0008] Among them, the gates of M6, M0 and M14 are connected; the source of M14 is connected to the power supply port VDD, and the drain is connected to the drain of M0; the drain of M4 is connected to the drain of M6, the source of M4 is connected to the drain of M2, and the gate of M4 is connected to the input signal port VIP; the source of M2, the drain of M0, the drain of M14 and the gate of M11 are connected and serve as the output signal node VONB.

[0009] The gates of M7, M1, and M15 are connected; the source of M15 is connected to the power supply port VDD, and its drain is connected to the drain of M1; the drain of M5 is connected to the drain of M7, the source of M5 is connected to the drain of M3, and the gate of M5 is connected to the input signal port VIP; the source of M3, the drain of M1, the drain of M15, and the gate of M10 are connected and serve as the output signal node VOPB.

[0010] The source of M10 is connected to the drain of M12. The source of M12 is grounded to GND. The gate of M12 is connected to the clock control signal CLK. The gate of M8 is connected to the clock control signal CLK. The drains of M6, M8, M4, and M10, the gate of M7, the gate of M1, and the gate of M15 are connected and serve as the output signal node VONT.

[0011] The source of M11 is connected to the drain of M13. The source of M13 is grounded to GND. The gate of M13 is connected to the clock control signal CLK. The gate of M9 is connected to the clock control signal CLK. The drains of M7, M9, M5, and M11, the gate of M6, the gate of M0, and the gate of M14 are connected and serve as the output signal node VOPT.

[0012] The sources of M0 and M1 are both grounded; the sources of M6, M7, M8 and M9 are all connected to the power supply VDD.

[0013] In the latch execution circuit, M6 and M0, and M7 and M1 form a pair of inverters, and the gates of M6 and M7 are connected to the drain of the other, respectively, to directly control the output signal nodes VONT and VOPT to output the corresponding latch results.

[0014] M8 and M9 are used to reset the output signal nodes VONT and VOPT to a high level during the reset phase when the CLK signal is low.

[0015] M2 and M3 are switching transistors controlled by the clock signal CLK, while M4 and M5 are switching transistors controlled by the input signals VIN and VIP, respectively. During the latching phase, M2, M3, M4, and M5 control the latching execution circuit to perform latching operations. Furthermore, the gate of M6 is also connected to M14, which controls the output signal node VONB. When the input signal VIN is high, the gate of M14 is high, and M0 is turned on, causing the output signal node VONB to output a GND level signal. Conversely, if the VIP signal is low, the output signal node VONB outputs a VDD level signal.

[0016] Similarly, the gate of M7 is connected to M15, which can control the output signal node VOPT to output the latched result. Its function is the same as that of M14, and will not be described again here. In addition, the drains of M0 and M1 are connected to the gates of M11 and M10 respectively, and are used to control and accelerate the latching results of VONT and VOPT. The drains of M0 and M1 are connected to the gates of M10 and M11 respectively. During the latching stage, the CLK signal is high, which turns on M12 and M13. When the drain voltages of M0 and M1, that is, the output voltages of output signal nodes VONB and VOPB, are established, the conduction of M10 and M11 can be controlled. This creates a path from the output signal node VONT through M10 and M12 and from the output signal node VOPT through M11 and M13 to the GND potential, thereby increasing the speed at which the output voltage of the output signal node VONT or the output signal node VOPT establishes to the GND potential and shortening the latching time.

[0017] M12 and M13, whose gates are directly controlled by the clock signal CLK, are used to control the operation of M11 and M10. When the CLK signal is low, M12 and M13 are turned off, and M10 and M11 cannot conduct to operate normally. Since M10 and M11 can accelerate latching, and M4 and M5, controlled by the input signals VIP and VIN, can be directly connected to the output signal nodes VONT and VOPT via their drains to control the output latching results of the two ports, while M2 and M3 are separated from the output signal nodes VONB and VOPB, the output latching speed of the output signal nodes VONB and VOPB will be slightly slower than that of the output signal nodes VONT and VOPT.

[0018] The CLK signal logic circuit consists of a cascaded two-input AND gate and an inverter, used to generate the control clock signal CLK, which is divided into an enable signal EN and a reset signal RST, used to control the latch to reset and latch. The EN and RST signals are respectively connected to the two input ports of a two-input NAND gate, and the output of the NAND gate is connected to an inverter, and then output by the inverter.

[0019] The READY signal logic circuit consists of four NOR gates, used to generate the READY control signal. After the previous stage latch is completed, it is necessary to control the next stage latch to work, that is, to generate the READY control signal.

[0020] The four NOR gate input signal ports are connected to VIN, VIP, VONB, and VONP, respectively. VIN and VIP are connected to two input ports of NOR gate A, VONB and VOPB are connected to two input ports of NOR gate C, the output port of NOR gate A is connected to one input port of NOR gate B, and the other input port of NOR gate B is connected to the output READY signal port. The output ports of NOR gates B and C are connected to two input ports of NOR gate D, and the output signal of NOR gate D is directly connected to the READY signal port. Here, in addition to using the input signals VIP and VIN for control, signal control from nodes VONB and VONP is also required. This is because, among the four output nodes of the latch in this invention, VONB and VOPB nodes have relatively longer setup times. READY signal feedback control is used to ensure that the output control signal is generated after the previous latching is completed.

[0021] The specific operating steps of the above-mentioned high-speed multi-output latch circuit are as follows:

[0022] Step 1: Reset the latch.

[0023] During the reset phase, VIP and VIN are set low. The clock signal CLK then outputs a low signal, resetting output signal nodes VONT and VOPT to high. The other two output signal nodes, VONB and VOPB, are reset to ground.

[0024] Step 2: Latching the latch.

[0025] When the clock signal CLK goes high, the latching execution circuit begins latching. Here, if the voltage value of the input signal VIP is greater than VIN, the voltage value of the output signal node VONT is pulled low, and the voltage value of the output signal node VOPT is pulled high to the power supply voltage VDD. Then, the voltage value of the output signal node VOPB is pulled back to the power supply voltage VDD. The voltage value of the output signal node VNOB remains at ground potential.

[0026] Step 3: Output control logic, such as Figure 3 As shown, the READY signal is output, and after the current level latch is completed, it controls the next high-speed multi-output latch to start working.

[0027] Figure 4 (c) and Figure 4 Figure (d) illustrates the operation of the voltage signals of the four output signal nodes when the input signal VIP is assumed to be greater than VIN (the corresponding quantization bit controlled by CLK; the situation is similar for other quantization bits). It can be seen that during the reset phase, the voltage values ​​of VONB and VOPB are both reset to high level, while the voltage values ​​of VONT and VOPT are both reset to low level. After the latching operation begins, the four output signal nodes quickly latch the corresponding voltage values: VONB latches the high-level signal, VOPB latches the low-level signal, VONT latches the high-level signal, and VOPT latches the low-level signal.

[0028] If the input signal VIP is less than VIN, during the reset phase, the voltage values ​​of VONB and VOPB are both reset to high level, while the voltage values ​​of VONT and VOPT are both reset to low level. After the latching operation begins, the four output signal nodes quickly latch the corresponding voltage values: VONB latches the low-level signal, VOPB latches the high-level signal, VONT latches the low-level signal, and VOPT latches the high-level signal.

[0029] The signals from these output signal nodes are then used directly to control the state switching of the ADC capacitor array.

[0030] Compared to this invention, existing technologies require at least three clock signals for the circuit to reset and latch properly, thus necessitating the use of more logic circuit units. Furthermore, existing technologies only allow two output state values ​​to be latched and used to control the state switching of the capacitor array. This design is ill-suited for the requirement of at least four state control bits for state switching in split-type capacitor arrays. Consequently, more combinational logic circuitry is needed for the corresponding state switching control.

[0031] In summary, compared to traditional high-speed SAR logic latch architectures, this invention uses only a single clock signal to control reset and latching, significantly reducing the size and complexity of the additional logic circuitry required with only a slight increase in delay. Furthermore, by using separate PMOS and NMOS transistors for reset, the interrelationships between the various signals are fully utilized, enabling simultaneous latching and control of four state bits. Moreover, the structure of this invention does not require a comparator to provide additional reset or latching control signals, greatly simplifying the circuit size and complexity. Attached Figure Description

[0032] Figure 1 This is a structural diagram of the latch execution circuit of the present invention;

[0033] Figure 2 This is a structural diagram of the CLK signal logic circuit of the present invention;

[0034] Figure 3 This is a structural diagram of the READY signal logic circuit of the present invention;

[0035] Figure 4 This is a schematic diagram of the working signals of each input and output node of the latch execution circuit in an embodiment;

[0036] Figure 5 This is a timing diagram of each input and output node when the CLK signal logic circuit is working in the example;

[0037] Figure 6 The following is a timing diagram of each input and output node when the READY signal logic circuit is working as shown in the example. Detailed Implementation

[0038] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0039] A high-speed multi-output latch circuit includes a latch execution circuit (such as...) Figure 1 As shown), the CLK signal logic circuit (such as...) Figure 2 (as shown) and READY signal logic circuit (such as Figure 3 (As shown).

[0040] The structure shown requires only one input setting CLK signal to control reset and latching. Input signals VIP and VIN are used to input the comparison results of the comparator. The VONT, VOPT, VONB, and VOPB nodes output the latched results and control the capacitor array. The CLK signal logic circuit generates the clock signal controlling the latch operation, while the READY signal logic circuit generates the READY signal to control the next high-speed multi-output latch. Related timing instructions are provided in... Figures 4-6 The details are provided below. The specific steps are as follows:

[0041] Step 1: Reset the latch. Figure 4 The embodiment shows the working signals of each input and output node of the latch execution circuit; where (a) is a signal diagram of the clock signal CLK; (b) is a diagram of the input signals VIP and VIN, and VIP>VIN during latching; (c) and (d) are the working conditions of the four output signal nodes of module A of the present invention within one clock cycle.

[0042] During the reset phase, the clock signal CLK is low, and the latch input signals VIN and VIP are also low. Figure 5 The timing diagram of the clock signal CLK is given below: During the operation step analysis, the input enable port EN is kept at a high level. When the input reset port RST is low, the output clock port CLK is also low. This keeps the high-speed multi-output latch circuit of this invention in a reset state.

[0043] In the reset state, M8 and M9 are turned on, while M2 and M3 are turned off; simultaneously, M12 and M13 are also turned off. The circuit output signal nodes VONT and VOPT are reset to high level. Resetting output signal nodes VONT and VOPT to high level causes M0 and M1 to turn on, and the other two output signal nodes VONB and VOPB are reset to ground.

[0044] Step 2: Latching the latch. The reset port RST signal of the clock signal CLK logic circuit is converted to a high-level signal, causing the clock signal CLK to also become a high-level signal. Figure 5 The above is provided. This causes the high-speed multi-output latch of the present invention to enter the latching working state.

[0045] In the latching state, M2 and M3 are turned on, and the latching execution circuit begins latching. Here, if the input signal VIP is greater than the voltage value of VIN, the voltage value of the output signal node VONT is pulled low, and the conduction of M12 accelerates this process. Simultaneously, the voltage value of VIN is at ground potential. The decrease in the voltage value of the output signal node VONT causes M7 to turn on, while M13 is already off, thus the voltage value of the output signal node VOPT is pulled high to the power supply voltage VDD. Afterwards, since the voltage value of the output signal node VONT is at ground potential, M15 is turned on and M1 is turned off, and the voltage value of the output signal node VOPB is pulled to the power supply voltage VDD. Because the voltage value of the output signal node VOPT remains at the power supply voltage (high level), M14 cannot be turned on, but M0 is turned on, and the voltage value of the output signal node VNOB continues to remain at ground potential. Then, the high level of the output signal node VOPB causes M10 to turn on, further accelerating the discharge of the VONT node. With VONB at a low level, M11 remains off, and the output signal node VOPT remains at a high level.

[0046] It is worth noting that if the input signal VIP is less than the voltage value of VIN, the entire latching and output process is completely symmetrical to the circuit operation in the previous case, which will not be elaborated here.

[0047] Step 3: Output Control Logic. In the SAR ADC circuit structure, the quantization accuracy determines the number of SAR logic structure units required. Figure 3 The block diagram of the READY signal logic circuit has been given, and its timing diagram is shown in [the original text]. Figure 6 As shown in the diagram. When the previous READY signal is completed, the output ports of the READY signal logic circuit will show a high level followed by a low level after the VIP and VIN signals, as well as the output signal nodes VOPB and VONB, are established. Figure 6 During setup, VIP and VOPB are high while VIN and VONB are low, and vice versa. After setup is complete at the above nodes, the READY signal becomes a high-level output signal to control the next high-speed multi-output latch.

[0048] Compared with existing technologies, this invention achieves multi-output latching by setting four output signal nodes at the drains of M6, M7, M0, and M1 respectively in the latch circuit structure. Furthermore, among the four output signal nodes, the VONT node signal and the VOPT node signal can control each other (the VONT node signal controls the latching and reset of the VOPT output node through the on / off state of M7; the VOPT node signal controls the latching and reset of the VONT output node through the on / off state of M6). Similarly, the VONB and VOPB signal nodes can also control each other (the VONB node signal controls the latching and reset of the VOPT output node through the on / off state of M11; the VOPB node signal controls the latching and reset of the VONT output node through the on / off state of M10). This circuit structure with mutual control of output nodes not only improves the operating speed of the circuit latching and reset but also ensures that the high-speed latch of this invention can output four latching control signals. This mutually controlled circuit structure reduces the requirement for clock control signals, requiring only one clock signal to control the latching and reset operation.

[0049] As can be seen from the above embodiments, the present invention, while ensuring the latching and reset functions of traditional high-speed latch circuits, uses only a clock signal for operation control, which greatly reduces the use and consumption of logic unit circuits; and also proposes a circuit structure that performs four-terminal latching simultaneously, which reduces the complexity of the corresponding switching control logic circuit in ADC circuits such as those using split differential capacitor arrays, thereby reducing the chip area.

Claims

1. A high-speed multi-output latch circuit, characterized in that: This includes latch execution circuitry, CLK signal logic circuitry, and READY signal logic circuitry; The latching execution circuit is composed of MOSFET transistors, specifically including PMOS transistors M6, M7, M8, M9, M14, and M15, and NMOS transistors M0, M1, M2, M3, M4, M5, M10, M11, M12, and M13; the input signals VIP and VIN are the latched signals, CLK is the clock signal, and VONT, VOPT, VONB, and VOPB are the four output signal nodes; Among them, the gates of M6, M0 and M14 are connected; the source of M14 is connected to the power supply port VDD, and the drain is connected to the drain of M0; the drain of M4 is connected to the drain of M6, the source of M4 is connected to the drain of M2, and the gate of M4 is connected to the input signal port VIP; the source of M2, the drain of M0, the drain of M14 and the gate of M11 are connected and serve as the output signal node VONB. The gates of M7, M1, and M15 are connected; the source of M15 is connected to the power supply port VDD, and its drain is connected to the drain of M1; the drain of M5 is connected to the drain of M7, the source of M5 is connected to the drain of M3, and the gate of M5 is connected to the input signal port VIN; the source of M3, the drain of M1, the drain of M15, and the gate of M10 are connected and serve as the output signal node VOPB. The source of M10 is connected to the drain of M12. The source of M12 is grounded to GND. The gate of M12 is connected to the clock control signal CLK. The gate of M8 is connected to the clock control signal CLK. The drains of M6, M8, M4, M10, M7, M1, and M15 are connected and serve as the output signal node VONT. The source of M11 is connected to the drain of M13. The source of M13 is grounded to GND. The gate of M13 is connected to the clock control signal CLK. The gate of M9 is connected to the clock control signal CLK. The drains of M7, M9, M5, M11, M6, M0, and M14 are connected and serve as the output signal node VOPT. The sources of M0 and M1 are both grounded; the sources of M6, M7, M8 and M9 are all connected to the power supply VDD. In the latch execution circuit, M6 and M0, and M7 and M1 form a pair of inverters, and the gates of M6 and M7 are connected to the drain of the other, respectively, to directly control the output signal nodes VONT and VOPT to output the corresponding latch results. M8 and M9 are used to reset the output signal nodes VONT and VOPT to a high level during the reset phase when the CLK signal is low. M2 and M3 are switching transistors controlled by the clock signal CLK, while M4 and M5 are switching transistors controlled by the input signals VIN and VIP, respectively. During the latching phase, M2, M3, M4, and M5 control the latching execution circuit to perform latching operations. Furthermore, the gate of M6 is also connected to M14, which controls the output signal node VONB. When the input signal VIN is high, the gate of M14 is high, and M0 is turned on, causing the output signal node VONB to output a GND level signal. Conversely, if the VIP signal is low, the output signal node VONB outputs a VDD level signal. M12 and M13, whose gates are directly controlled by the clock signal CLK, are used to control the operation of M11 and M10. When the CLK signal is low, M12 and M13 are turned off, and M10 and M11 cannot be turned on to work normally. Since M10 and M11 can accelerate latching, and M4 and M5, which are controlled by the input signals VIP and VIN, can be directly connected to the output signal nodes VONT and VOPT with their drains to control the output latching results of the two ports, and M2 and M3 are separated from the output signal nodes VONB and VOPB, the output latching speed of the output signal nodes VONB and VOPB will be slower than that of the output signal nodes VONT and VOPT. The CLK signal logic circuit consists of a cascaded two-input NAND gate and an inverter, used to generate the control clock signal CLK, which is divided into an enable signal EN and a reset signal RST, used to control the latch to reset and latch. The EN and RST signals are respectively connected to the two input ports of a two-input NAND gate, and the output of the NAND gate is connected to an inverter, and then output by the inverter. The READY signal logic circuit consists of four NOR gates, which are used to generate the READY control signal. After the first-level latch is completed, it is necessary to control the next-level latch to work, that is, to generate the READY control signal. The four NOR gate input signal ports are connected to VIN, VIP, VONB, and VONP respectively. Among them, VIN and VIP are connected to two input ports of NOR gate A, VONB and VOPB are connected to two input ports of NOR gate C, the output port of NOR gate A is connected to one input port of NOR gate B, and the other input port of NOR gate B is connected to the output READY signal port. The output ports of NOR gate B and NOR gate C are connected to two input ports of NOR gate D respectively, and the output signal of NOR gate D is directly connected to the READY signal port. READY signal feedback control is used to ensure that the output control signal is generated after the previous latch is completed.

2. The high-speed multi-output latch circuit as described in claim 1, characterized in that, The specific work steps are as follows: Step 1: Reset the latch; During the reset phase, VIP and VIN are set to low level; the clock signal CLK will output a low level signal, and the output signal nodes VONT and VOPT will be reset to high level; the other two output signal nodes VONB and VOPB will be reset to ground potential. Step 2: Latching the latch; When the clock signal CLK goes high, the latching execution circuit starts latching. If the voltage value of the input signal VIP is greater than VIN, the voltage value of the output signal node VONT is pulled low, and the voltage value of the output signal node VOPT is pulled high to the power supply voltage VDD. Then the voltage value of the output signal node VOPB is pulled to the power supply voltage VDD, while the voltage value of the output signal node VNOB remains at ground potential. Step 3: Output control logic, output READY signal, after the current level latch is completed, control the next high-speed multi-output latch to work; If the input signal VIP is greater than VIN, during the reset phase, the voltage values ​​of VONB and VOPB are both reset to high level, while the voltage values ​​of VONT and VOPT are both reset to low level. After the latching operation begins, the four output signal nodes quickly latch the corresponding voltage values: VONB latches the high-level signal, VOPB latches the low-level signal, VONT latches the high-level signal, and VOPT latches the low-level signal. If the input signal VIP is less than VIN, during the reset phase, the voltage values ​​of VONB and VOPB are both reset to high level, while the voltage values ​​of VONT and VOPT are both reset to low level. After the latching operation begins, the four output signal nodes quickly latch the corresponding voltage values: VONB latches the low-level signal, VOPB latches the high-level signal, VONT latches the low-level signal, and VOPT latches the high-level signal. The signals from these output signal nodes are then used directly to control the state switching of the ADC capacitor array.

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