A near-sensor image encryption architecture based on memristor and polarity-adjustable transistor

Abstract

The application relates to a near-sensor image encryption architecture based on a memristor and a polarity-adjustable transistor, which comprises a plurality of parallel structures of the same unit, each unit comprising a sensing module, an encryption module and an encoding storage module, wherein the sensing module is used for collecting a photocurrent generated by light input and mapping image pixel values into voltages as original image information according to the photocurrent; the encryption module is used for generating a key based on a physical unclonable function of the memristor and performing encryption processing on the original image information and the key to obtain encrypted information; and the encoding storage module is used for encoding the encrypted information into conductance for storage and output to the cloud or mapping the encrypted information into a conductance form of a non-volatile transistor for in-memory calculation and transmitting the in-memory calculated information into the cloud. The architecture realizes image information encryption at the near-sensor end, avoids information leakage and attacks in the transmission process, and improves the security and reliability of the information transmission process.

Description

Technical Field

[0001] This invention belongs to the field of information processing technology, specifically relating to a proximity sensing image encryption architecture based on memristors and polarity-tunable transistors. Background Technology

[0002] With the rapid development of the emerging Internet of Things (IoT), sensors need to continuously collect and transmit massive amounts of information. Taking image sensing as an example, in traditional architectures, the vast amounts of information collected by image sensors must first be converted into digital data and then transmitted to the cloud for processing. This leads to bottlenecks in latency, energy consumption, and other aspects. This information is also increasingly vulnerable to theft during transmission. While state-of-the-art cryptographic systems offer robust security solutions based on complex encryption algorithms, these algorithms require extensive hardware accelerators for implementation, making them difficult to adopt for IoT edge sensors with limited hardware resources and low energy budgets.

[0003] Currently, keys used for information security are primarily based on software algorithms that employ pseudo-random numbers. In this regard, hardware-inherent security primitives are less vulnerable to attack than software implementations. Physically unclonable functions (PFCs) have been widely used as a hardware security primitive for key generation; however, traditional CMOS-based PFC technology has stringent process requirements and may not provide sufficient randomness, making it more susceptible to attacks. Therefore, developing on-chip cryptographic primitives that require less computational resources and can be integrated with IoT edge sensors is of great significance. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a proximity sensing image encryption architecture based on memristors and polarity-tunable transistors. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a proximity sensing image encryption architecture based on memristors and polarity-tunable transistors, comprising: multiple parallel-connected identical units, each unit corresponding to one pixel of the image, and each unit including: a sensing module, an encryption module, and an encoding storage module, wherein... The sensing module is used to collect the photocurrent generated by the light input, and to map the image pixel values ​​into voltage based on the photocurrent as the original image information; The encryption module is used to generate a key based on the memristor's physically unclonable function, and to encrypt the original image information with the key to obtain encrypted information; The encoding and storage module is used to encode the encrypted information into electrical conductance for storage and output it to the cloud, or to map the encrypted information into the electrical conductance of a non-volatile transistor for in-memory calculation and transmit the in-memory calculated information to the cloud.

[0005] In one embodiment of the present invention, the sensing module includes a phototransistor. The source of the phototransistor is input with a first voltage, the gate is input with a second voltage, and the drain is used as the output terminal of the sensing module.

[0006] In one embodiment of the present invention, the encryption module includes an XOR logic gate submodule and a key generation submodule, wherein, The key generation submodule is used to generate keys using the physically unclonable function of memristors; The XOR logic gate submodule is used to perform XOR logic operations to encrypt the original image information with the key to obtain encrypted information.

[0007] In one embodiment of the present invention, the key generation submodule includes a memristor and a first selection transistor, wherein, The top electrode of the memristor is input with a fifth voltage, and the bottom electrode is connected to the source of the selection transistor and serves as the output terminal of the key generation submodule. The gate of the first selection transistor is input with a fourth voltage, and the drain is connected to ground.

[0008] In one embodiment of the present invention, the threshold voltage of the memristors in the plurality of units, and the threshold voltage of each memristor in different periods, all follow a Gaussian distribution.

[0009] In one embodiment of the invention, during the key generation stage, the fifth voltage is the average of the threshold voltages of the plurality of memristors.

[0010] In one embodiment of the present invention, the XOR logic gate submodule includes a load transistor and a dual-gate controlled transistor, wherein the dual-gate controlled transistor is a polarity-adjustable transistor. The source of the load transistor receives a third voltage, and its gate is connected to the drain of the load transistor, the source of the dual-gate transistor, and serves as the output terminal of the encryption module. The top gate of the dual-gate transistor is connected to the output of the sensing module and serves as the first input of the XOR logic gate submodule; the back gate is connected to the output of the key generation submodule and serves as the second input of the XOR logic gate submodule; and the drain is connected to the ground terminal.

[0011] In one embodiment of the present invention, the encoding storage module includes storage transistors, all of which are non-volatile transistors. The source of the storage transistor is connected to a sixth voltage, the gate is connected to the output of the encryption module, and the drain is connected to ground.

[0012] In one embodiment of the present invention, the encoding storage module includes a second selection transistor and a storage transistor, wherein the storage transistors are all non-volatile transistors. The source of the second selection transistor is input with a sixth voltage, the gate is input with a bias voltage, and the drain is connected to the source of the storage transistor. The gate of the storage transistor is connected to the output terminal of the encryption module, and the drain is connected to the ground terminal.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The image encryption architecture of the present invention directly inputs the original image information obtained by the phototransistor collecting light input into the encryption module. In the encryption module, a key is generated based on the memristor's physical non-cloning function and the original image information is encrypted. This realizes the encryption of image information at the near sensor end. Thereafter, the image information is transmitted in the form of ciphertext, avoiding information leakage and attack during the transmission process, and improving the security and reliability of the information transmission process.

[0014] 2. In the image encryption architecture of the present invention, the XOR logic gate submodule includes a load transistor and a dual-gate control transistor. The dual-gate control transistor is a polarity-adjustable transistor with bipolar control behavior. The number of transistors used to construct the XOR logic gate is small, the structure is simple, and the problem of using a large number of transistors in the analog-to-digital converter, digital-to-analog converter and XOR logic gate in the traditional architecture is avoided, thereby reducing hardware resource consumption and time delay.

[0015] 3. In the image encryption architecture of the present invention, the key generation submodule uses the physical non-cloning function of the memristor to generate the key. Compared with the software-based pseudo-random number generator and the physical non-cloning function based on traditional CMOS to generate the key, it is not easily affected by side-channel and machine learning attacks, and the encryption effect has higher reliability and security.

[0016] 4. In the image encryption architecture of the present invention, the encoding and storage module can encode the encrypted information and transmit it directly to the cloud, or it can map the encrypted information into the form of conductivity for in-memory calculation. The in-memory calculation is performed directly at the near sensor end, which can further reduce power consumption and time delay. Attached Figure Description

[0017] Figure 1 A circuit diagram of a proximity sensing image encryption architecture based on memristors and polarity-tunable transistors provided in an embodiment of the present invention; Figure 2 The transfer characteristic curve of the dual-gate controlled transistor provided in the embodiment of the present invention; Figure 3 A schematic diagram of an encryption module provided in an embodiment of the present invention using dual-gate controlled transistors to form an XOR logic; Figure 4 A schematic diagram of another proximity sensing image encryption architecture based on memristors and polarity-tunable transistors provided in an embodiment of the present invention. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0019] Example 1 Please see Figure 1 , Figure 1 A circuit diagram of a proximity sensing image encryption architecture based on memristors and polarity-tunable transistors provided in an embodiment of the present invention.

[0020] The image encryption architecture consists of multiple parallel units with identical structures, each unit corresponding to a pixel of the image.

[0021] Specifically, in this image encryption architecture, multiple units are arranged in an array, the size of which is determined by the image size. Each unit processes one pixel of the image. For example, the image encryption architecture can consist of an N×N unit array to process an N×N pixel image, or it can consist of an N×M unit array to process an N×M pixel image. Furthermore, all units are parallel, and each unit has multiple voltage input ports. Except for the Vs voltage of each unit, which needs to be applied individually, the voltages of the other corresponding ports are the same. For example… Figure 1 In the N×N cell array, each cell has 7 voltage input ports. Except for Vs, the voltages input to the 6 ports are V1, V2, V3, V4, V5, and V6, respectively.

[0022] Each unit includes: a sensing module 1, an encryption module 2, and an encoding and storage module 3. The sensing module 1 collects the photocurrent generated by the light input and maps the image pixel values ​​to voltage based on the photocurrent as the original image information, which serves as an input to the encryption module 2. The encryption module 2 generates a key based on the memristor's physically non-cloning function and encrypts the original image information with the key to obtain encrypted information. The encoding and storage module 3 encodes the encrypted information as a current and outputs it to the cloud, or maps the encrypted information to the conductance of a non-volatile transistor for in-memory calculation and transmits the calculated information to the cloud.

[0023] In one specific embodiment, the sensing module 1 includes a phototransistor T1, the source of which is input with a first voltage V1, the gate of which is input with a second voltage V2, and the drain of which serves as the output terminal of the sensing module 1, outputting voltage data to the encryption module 2.

[0024] Specifically, phototransistor T1 generates photocurrent through illumination and converts each pixel's data into voltage data for encryption based on the photocurrent, which serves as the top gate input of encryption module transistor T3. The gate voltage V2 of phototransistor T1 is set to a threshold. When there is illumination, phototransistor T1 is turned on, meaning the top gate of transistor T3 is at a high level, representing logic "1". When there is no illumination, phototransistor T1 does not generate photocurrent, and the top gate of T3 is at a low level, representing logic "0".

[0025] In this embodiment, the phototransistor T1 generates a photoresponse current when illuminated, and converts each pixel data into voltage data for encryption based on the photoresponse current, without the need for analog-to-digital conversion, which facilitates direct processing of image pixels.

[0026] In one specific embodiment, the encryption module 2 includes a key generation submodule 22 and an XOR logic gate submodule 21. The key generation submodule 22 generates a key using the physically non-cloning function of a memristor. The XOR logic gate submodule 21 performs an XOR logic operation to encrypt the original image information with the key, obtaining encrypted information, i.e., the encrypted image pixels.

[0027] Specifically, the key generation submodule 22 generates a random key, which serves as an input for XOR logic encryption. The XOR logic gate submodule 21 then performs encryption processing to achieve the encryption effect.

[0028] Furthermore, the key generation submodule 22 includes a memristor R1 and a first selection transistor T4. The top electrode of the memristor R1 is input to the fifth voltage V5, and the bottom electrode is connected to the source of the selection transistor T4 and serves as the output terminal of the key generation submodule 22; the gate of the first selection transistor T4 is input to the fourth voltage V4, and the drain is connected to the ground terminal.

[0029] Specifically, the core of the key generation submodule 22 is the memristor R1, which generates the key based on the inherent randomness of the memristor as a physically unclonable function. Due to defects and randomness in the manufacturing process of the memristor R1, the memristor threshold voltage V... TH Due to the randomness between devices and between periods, the threshold voltage V of multiple memristors can be fitted after multiple measurements. TH Following a Gaussian distribution, the threshold voltage of each memristor in different cycles also follows a Gaussian distribution. Furthermore, the control voltage of memristor R1, i.e., the fifth voltage V5, is set as the threshold voltage V of multiple memristors. TH If the average value is not specified, then the memristor R1 will randomly be in a high-resistance state and a low-resistance state, corresponding to logic states "1" and "0" respectively.

[0030] Specifically, the key generation submodule 22 works in three main stages: During the key generation phase, the gate voltage V4 applied to the first selection transistor T4 turns T4 off, and the fifth voltage V5 is set to the mean of the Gaussian distribution of the threshold voltage of the memristor R1. TH0 If the threshold voltage of memristor R1 is lower than V at this time TH0 If the memristor R1 is in a low-resistance state, the voltage at point B is high, denoted as logic "1". Conversely, if the threshold voltage of memristor R1 is higher than V at this time... TH0 If the memristor R1 is in a high impedance state, the voltage at point B is low, which is recorded as logic "0".

[0031] During the key reading stage, it is only necessary to adjust the fourth voltage V4 to turn on the first selection transistor T4, read the current of the first selection transistor T4, if it is a high conduction current, the key of this pixel is "1", if the conduction current of the first selection transistor T4 is very low, the key is "0", and the read key is passed to the receiver for subsequent decryption.

[0032] During the key erasure phase, the fifth voltage V5 is set as the erasure voltage V of the memristor R1. RESET Restore R1 to its initial state.

[0033] Furthermore, the XOR logic gate submodule 21 includes a load transistor T2 and a dual-gate transistor T3, wherein the dual-gate transistor T3 is a polarity-adjustable transistor. The source of the load transistor T2 receives the third voltage V3, and its gate is connected to the drain of the load transistor T2. The source of the dual-gate transistor T3 serves as the output of the encryption module 2. The top gate of the dual-gate transistor T3 is connected to the output of the sensing module 1 and serves as the first input of the XOR logic gate submodule 21, while its back gate is connected to the output of the key generation submodule 22 and serves as the second input of the XOR logic gate submodule 21. Its drain is connected to ground.

[0034] The core of the XOR logic gate submodule 21 is a dual-gate controlled transistor T3 with bipolar control behavior. Nonlinear logic can be implemented using the dual-gate controlled transistor T3. T2 is a transistor operating in the saturation region, acting as a load. The load transistor T2 and the dual-gate controlled transistor T3 together form an XOR gate, which can perform the XOR operation used for encryption, mapping the encrypted image pixels to current. The two inputs to the XOR operation are the top gate and bottom gate of the dual-gate controlled transistor T3.

[0035] Please see Figure 2 , Figure 2 The diagram shows the transfer characteristic curves of a dual-gate controlled transistor with bipolar modulation behavior provided in an embodiment of the present invention. From... Figure 2 As can be seen from the diagram, by scanning the gate voltage of the dual-gate transistor T3, the transfer characteristics of the polarity-tunable transistor T3 can be obtained: as the bottom gate voltage V... BG Or the top gate voltage V TGAs V(0) increases to V(1), the transfer characteristic of T3 changes from P-type to N-type, with the critical point being V. O , less than V O The gate voltage is defined as a logic input of "0", which is greater than V. O The gate voltage is defined as the logic input "1".

[0036] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating the encryption module provided in an embodiment of the present invention, which utilizes dual-gate controlled transistors to construct an XOR logic. Figure 3 It can be seen that, taking the top gate and back gate of the dual-gate controlled transistor T3 as two input combinations, since the top gate and back gate compete with each other in regulating the channel current, when both inputs are "0" or "1", the transistor exhibits enhancement in one polarity, corresponding to the output current I at point C. ds For a large current, it is denoted as "1"; when the two inputs are combined as "(1,0)" or "(0,1)", the two gate voltages cancel each other out and suppress the channel regulation, thus the corresponding current I at point C is... ds The current is small, denoted as "0". The output is represented by a non-linear XNOR operation. Subsequently, transistor T2, operating in the saturation region, acts as a load and divides the voltage with the dual-gate transistor T3. Therefore, the voltage at point C will be related to I. ds It is inversely proportional, meaning that the output voltage at point C exhibits a non-linear logic XOR operation.

[0037] The XOR operation is commonly used in encryption because of its inherent characteristic: two consecutive XOR operations return the input itself. The specific expression is: A ⊕ B=C Its inverse operation is: B ⊕ C=A Where A is the plaintext information to be encrypted, B is the encryption key, and C is the encrypted ciphertext. In this embodiment, the plaintext information is the voltage at point A mapped to the pixel after the phototransistor T1 responds to light, and the key is the random key generated by the key generation module mapped to the voltage at point B. After XOR operation by the XOR logic gate module, the pixel of the output ciphertext is mapped to the voltage at point C.

[0038] Furthermore, during decryption, the decryptor only needs to know the encrypted ciphertext and the key transmitted from the sensor, and perform the inverse XOR operation (i.e., XOR the ciphertext and the key) to obtain the plaintext information. The decryptor, however, cannot obtain the original image information without the accurate key or the encryption algorithm used.

[0039] In one specific embodiment, the encoding storage module 3 includes storage transistors T6, all of which are non-volatile transistors. The source of each storage transistor T6 receives a sixth voltage V6, its gate is connected to the output of the encryption module 2, and its drain is connected to ground. Figure 4 As shown, Figure 4 A schematic diagram of another proximity sensing image encryption architecture based on memristors and polarity-tunable transistors provided in an embodiment of the present invention.

[0040] Specifically, due to its non-volatile nature, when the encrypted information Vc is applied to the gate of the storage transistor T6, the encrypted information is encoded into the conductance of the storage transistor T6 for storage. The encrypted information can be directly transmitted to the cloud for further image processing through the drain current of the storage transistor T6. After receiving the ciphertext, the cloud decrypts it with the key provided by the sensing end to obtain the original image information.

[0041] In one specific embodiment, the encoding storage module 3 includes a second selection transistor T5 and a storage transistor T6. The source of the second selection transistor T5 receives a sixth voltage V6, its gate receives a bias voltage Vs, and its drain is connected to the source of the storage transistor T6. The gate of the storage transistor T6 is connected to the output terminal of the encryption module 2, and its drain is connected to ground. Figure 1 As shown.

[0042] Specifically, due to its non-volatile nature, after the encrypted information Vc is applied to the gate of the storage transistor T6, the encrypted information is encoded into the conductance of the storage transistor T6 for storage. The encrypted information can be directly transmitted to the cloud for further image processing through the drain current of the storage transistor T6. At this time, the second selection transistor T5 can be turned on.

[0043] In addition, T5, as a selection transistor, is controlled to be turned on or off by Vs. Combined with the non-volatile transistor T6, it forms a 2T structure. By applying in-memory computation information to the gate of T6 and using the conductance of T6 as a weight, in-memory computation is performed directly on the chip to perform image processing on the encrypted text. This allows for data preprocessing computation on the encrypted information at the near-sensing end. The preprocessed information is then transmitted to the cloud for decryption, thereby achieving homomorphic encryption of the image.

[0044] The image encryption architecture of this embodiment directly inputs the original image information obtained by the phototransistor collecting light input into the encryption module. In the encryption module, a key is generated based on the memristor's physical non-cloning function and the original image information is encrypted. This realizes the encryption of image information at the near sensor end. Thereafter, the image information is transmitted in ciphertext form, avoiding information leakage and attack during transmission, and improving the security and reliability of information transmission.

[0045] In the image encryption architecture of this embodiment, the XOR logic gate submodule performs XOR operation for encryption. The encryption module includes a load transistor and a dual-gate control transistor. The dual-gate control transistor is a polarity-adjustable transistor with bipolar control behavior, which reduces the number of transistors used and simplifies the structure. This avoids the problem of using a large number of transistors in analog-to-digital converters, digital-to-analog converters and XOR logic gates in traditional architectures, thereby reducing hardware resource consumption and time delay.

[0046] In the image encryption architecture of this embodiment, the key generation submodule uses the physical non-cloning function of the memristor to generate the key. Compared with software-based pseudo-random number generators and physical non-cloning function-based key generation based on traditional CMOS, it is less susceptible to side-channel and machine learning attacks, and the encryption effect has higher reliability and security.

[0047] In the image encryption architecture of this embodiment, the encrypted information is encoded as current in the encoding and storage module. The encrypted information can be directly transmitted to the cloud for post-processing, or the encrypted information can be mapped to the conductance of a non-volatile transistor for in-memory calculation. The in-memory calculation is performed directly at the sensor end, which can further reduce power consumption and time delay.

[0048] It should be noted that, in this document, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0049] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A proximity sensing image encryption architecture based on memristors and polarity-tunable transistors, characterized in that, include: Multiple parallel units with identical structures, each unit corresponding to one pixel of the image, each unit includes: a sensing module (1), an encryption module (2), and an encoding storage module (3), wherein, The sensing module (1) is used to collect the photocurrent generated by the light input, and to map the image pixel value into voltage based on the photocurrent as the original image information; The encryption module (2) is used to generate a key based on the memristor's physical non-cloning function, and to encrypt the original image information with the key to obtain encrypted information; The encryption module (2) includes an XOR logic gate submodule (21) and a key generation submodule (22). The key generation submodule (22) is used to generate a key using the physical non-cloning function of a memristor. The XOR logic gate submodule (21) is used to perform an XOR logic operation to encrypt the original image information with the key to obtain encrypted information. The XOR logic gate submodule (21) includes a load transistor (T2) and a dual-gate transistor (T3). The dual-gate transistor (T3) is a polarity-adjustable transistor. The source of the load transistor (T2) is input with a third voltage (V3), and the drain is connected to the gate of the load transistor (T2) and the source of the dual-gate transistor (T3) and serves as the output of the encryption module (2). The top gate of the dual-gate transistor (T3) is connected to the output of the sensing module (1) and serves as the first input of the XOR logic gate submodule (21), the back gate is connected to the output of the key generation submodule (22) and serves as the second input of the XOR logic gate submodule (21), and the drain is connected to the ground terminal. The encoding storage module (3) is used to encode the encrypted information into electrical conductance for storage and output it to the cloud, or to map the encrypted information into the electrical conductance of a non-volatile transistor for in-memory calculation and transmit the in-memory calculation information to the cloud.

2. The proximity sensing image encryption architecture based on memristors and polarity-tunable transistors according to claim 1, characterized in that, The sensing module (1) includes a phototransistor (T1), The source of the phototransistor (T1) is input with a first voltage (V1), the gate is input with a second voltage (V2), and the drain is used as the output terminal of the sensing module (1).

3. The proximity sensing image encryption architecture based on memristors and polarity-tunable transistors according to claim 1, characterized in that, The threshold voltage of the memristor (R1) in the multiple units, and the threshold voltage of each memristor (R1) in different periods, all follow a Gaussian distribution.

4. The proximity sensing image encryption architecture based on memristors and polarity-tunable transistors according to claim 3, characterized in that, During the key generation phase, the fifth voltage (V5) is the average of the threshold voltages of the plurality of memristors (R1).

5. The proximity sensing image encryption architecture based on memristors and polarity-tunable transistors according to claim 1, characterized in that, The encoding storage module (3) includes storage transistors (T6), all of which are non-volatile transistors. The source of the storage transistor (T6) is input with a sixth voltage (V6), the gate is connected to the output terminal of the encryption module (2), and the drain is connected to the ground terminal.

6. The proximity sensing image encryption architecture based on memristors and polarity-tunable transistors according to claim 1, characterized in that, The encoding storage module (3) includes a second selection transistor (T5) and a storage transistor (T6), wherein the storage transistor (T6) is a non-volatile transistor. The source of the second selection transistor (T5) is input with a sixth voltage (V6), the gate is input with a bias voltage (Vs), and the drain is connected to the source of the storage transistor (T6). The gate of the storage transistor (T6) is connected to the output terminal of the encryption module (2), and the drain is connected to the ground terminal.

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