Circuit board and method of processing the same

Abstract

This application discloses a circuit board and its processing method. The circuit board processing method includes: obtaining a circuit board to be processed; drilling through holes at predetermined locations on the circuit board; wherein the through holes penetrate the ink layer of a core board; performing a first degreasing treatment on the through holes to remove at least a portion of the ink layer on the hole walls and forming at least one cavity on both sides of the hole walls, wherein the cavity communicates with the through holes; injecting colloidal palladium into the through holes after the first degreasing treatment, so that the colloidal palladium is adsorbed on the hole walls and the inner walls of the cavities; performing a second degreasing treatment on the hole walls and cavities with the colloidal palladium to remove all ink and the colloidal palladium, thereby obtaining a circuit board. This application achieves electrical disconnection of any layer of signal transmission vias through the colloidal palladium removal process, and the residual pins are zero, thereby improving the transmission speed and stability during transmission.

Description

Technical Field

[0001] This application belongs to the field of circuit board processing technology, and in particular relates to a circuit board and its processing method. Background Technology

[0002] With the widespread adoption of 5G mobile networks and the increase in signal transmission frequencies, signal integrity issues in PCBs (Printed Circuit Boards) are receiving increasing attention. In the design of multi-layer PCBs, not all layers need to be interconnected. During the fabrication of through-holes, excess copper pillars exist between non-interconnected layers; these pillars are called residual spikes. If these residual spikes are not addressed, signals will be transmitted through them.

[0003] Back drilling, as a current technology for controlling residual pile length, has limited ability to control residual pile length due to the changes in medium thickness during the pressure plate process and the limitation of drilling depth control. Excessive back drilling depth will lead to open circuit, while insufficient back drilling depth will result in excessively long residual piles, affecting electrical conductivity and signal integrity, and failing to achieve the ideal situation of zero residual piles. Summary of the Invention

[0004] This application provides a circuit board and its processing method to solve the problem of excessively long residual pillars affecting electrical conductivity and signal integrity, thereby improving transmission speed and stability during transmission. To solve the above technical problem, one technical solution adopted in this application is: a circuit board processing method, wherein the method includes: obtaining a circuit board to be processed; drilling through holes at predetermined positions on the circuit board; wherein the through holes penetrate the ink layer of the core board; performing a first degreasing treatment on the through holes to remove at least a portion of the ink layer from the hole walls and forming at least one cavity on both sides of the hole walls, wherein the cavity communicates with the through holes; injecting colloidal palladium into the through holes after the first degreasing treatment, so that the colloidal palladium is adsorbed onto the hole walls and the inner walls of the cavities; performing a second degreasing treatment on the hole walls and cavities with the colloidal palladium to remove all ink and the colloidal palladium, thereby obtaining the circuit board.

[0005] Optionally, the step of obtaining the circuit board to be processed and drilling through holes at predetermined positions on the circuit board, wherein before the step of the through holes penetrating the ink layer of the core board, includes: obtaining multiple core boards to be laminated, covering the two surfaces of the core boards with copper layers; performing pattern processing on the copper layers on the two surfaces of the core boards to form a circuit pattern; printing ink in each area of ​​the circuit pattern to form an ink layer; and laminating multiple core boards with the ink layer to obtain the circuit board to be processed.

[0006] Optionally, before the step of injecting colloidal palladium into the through hole after the first degreasing treatment so that the colloidal palladium is adsorbed on the hole wall and the inner wall of the cavity, the method further includes: performing degreasing and pre-impregnation treatment on the through hole after the first degreasing treatment.

[0007] Optionally, before the step of performing a second degreasing treatment on the walls of the through holes and the cavity with the colloidal palladium to remove all ink and the colloidal palladium to obtain the circuit board, the method further includes: performing a degumming treatment on the colloidal palladium to expose the palladium core of the colloidal palladium.

[0008] Optionally, the step of performing a first degreasing treatment on the through hole to remove at least a portion of the ink layer on the hole wall and form at least one cavity on both sides of the hole wall, wherein the cavity communicates with the through hole, includes: placing the core board in a solution for the first degreasing to remove a portion of the ink layer on the hole wall; wherein the solution is 20±3% sodium hydroxide by mass and the temperature is 85±10 degrees Celsius.

[0009] Optionally, the step of performing a second degreasing treatment on the walls of the through-holes and the cavities coated with the colloidal palladium to remove all ink and the colloidal palladium to obtain the circuit board includes: placing the core board with the adsorbed colloidal palladium in a solution for a second degreasing treatment to remove all ink layers from the walls of the through-holes to obtain the circuit board; wherein at least one cavity is formed on both sides of the through-hole walls, the length of the cavity along the axial direction of the through-hole is 30-50 micrometers, the length of the cavity perpendicular to the axial direction of the through-hole is 60-80 micrometers, the solution is 20±3% sodium hydroxide by mass, and the temperature is 85±10 degrees Celsius.

[0010] Optionally, after performing a second degreasing treatment on the through-hole walls and the cavity with the colloidal palladium to remove all ink and the colloidal palladium to obtain the circuit board, the method further includes: sequentially performing copper plating, copper immersion, and etching steps on the through-hole walls after the second degreasing treatment to obtain the circuit board.

[0011] To solve the above-mentioned technical problems, the second technical solution adopted in this application is to provide a circuit board, the circuit board comprising: a core board layer, wherein a through hole is formed on the core board layer, wherein the through hole penetrates the ink layer of the core board; wherein the core board layer comprises a plurality of stacked core boards, and the through hole penetrates each of the core boards; and the hole wall of the through hole is not covered by the ink layer; at least one cavity is formed on both sides of the hole wall of the through hole, wherein the cavity communicates with the through hole.

[0012] Optionally, a filler layer is provided, which is located between any two adjacent core boards, and the two surfaces of the filler layer are respectively bonded to the surface of the core board.

[0013] Optionally, the length of the cavity along the axial direction of the through hole is 30-50 micrometers, and the length of the cavity perpendicular to the axial direction of the through hole is 60-80 micrometers.

[0014] The beneficial effects of this application are as follows: Unlike traditional back-rotation control techniques for residual via length, this invention employs a novel ink rinsing process to achieve disconnection of signal transmission vias at any layer, with zero residual via length. The technology provided by this invention can reduce reflection and resonance during signal transmission, improve signal integrity, and promote the development of PCBs with higher transmission speeds. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0016] Figure 1 This is a flowchart of the first embodiment of the circuit board processing method of the present invention;

[0017] Figure 2 This is a schematic diagram of the circuit board structure in the circuit board processing method of the present invention;

[0018] Figure 3 yes Figure 2 Enlarged view of section A in the middle;

[0019] Figure 4 This is a schematic diagram of the core board structure after the first degreasing in the processing method of the circuit board of the present invention;

[0020] Figure 5 This is a schematic diagram of the core board structure after adsorption of colloidal palladium in the circuit board processing method of the present invention.

[0021] Figure 6 This is a schematic diagram of the core board structure after the second degreasing in the processing method of the circuit board of the present invention;

[0022] Figure 7 This is a flowchart of the second embodiment of the circuit board processing method of the present invention;

[0023] Figure 8 This is a schematic diagram of the core board structure after blanking in the processing method of the circuit board of the present invention;

[0024] Figure 9This is a schematic diagram of the core board structure after pattern transfer in the circuit board processing method of the present invention;

[0025] Figure 10 This is a schematic diagram of the core board structure after printing the ink layer in the circuit board processing method of the present invention;

[0026] Figure 11 This is a schematic diagram of the core board structure after copper plating in the circuit board processing method of the present invention;

[0027] Figure 12 This is a schematic diagram of the core board structure after etching in the circuit board processing method of the present invention;

[0028] Figure 13 This is a schematic diagram of the circuit board structure of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0031] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0032] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0033] First Embodiment

[0034] Please see Figure 1 , Figure 1 This is a flowchart of the first embodiment of the circuit board processing method of the present invention. It should be noted that if substantially the same result is achieved, the method of the present invention is not necessarily identical. Figure 1 The illustrated process sequence is limited. For example... Figure 1 As shown, the method includes the following steps:

[0035] S101: Obtain the circuit board to be processed, and drill through holes at the set positions on the circuit board; wherein the through holes penetrate the ink layer of the core board.

[0036] Please refer to Figure 2 , Figure 3 ,in, Figure 2 This is a schematic diagram of the circuit board structure in the circuit board processing method of the present invention; Figure 3 yes Figure 2 Enlarged view of section A. In this embodiment, a circuit board 5 of suitable size is first selected. Multiple ink layers 3 are laid on both sides of the circuit board 5 and inside the circuit board 5. Holes are drilled in the circuit board 5, with through holes 4 penetrating the ink layers 3, so that the cross-section of the ink layers 3 is exposed to the air, which facilitates subsequent processing.

[0037] S102: Perform a first degreasing treatment on the through hole to remove at least part of the ink layer on the hole wall and form at least one cavity on both sides of the hole wall, wherein the cavity is in communication with the through hole.

[0038] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the core board structure after the first degreasing process in the circuit board processing method of the present invention. In this embodiment, the circuit board 5 after drilling undergoes a first degreasing treatment, that is, the ink layer 3 exposed to the air is dissolved by chemical solution. After the first degreasing treatment, most of the ink in the ink layer 3 can be removed. Due to the dissolution and elimination of the ink, a cavity 301 is formed at the original ink layer 3.

[0039] S103: Inject colloidal palladium into the through hole after the first degreasing treatment, so that the colloidal palladium is adsorbed on the hole wall and the inner wall of the cavity.

[0040] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the core board structure after adsorbing colloidal palladium in the circuit board processing method of the present invention. In this embodiment, colloidal palladium 6 is adsorbed on the inner wall of the through hole 4 of the circuit board 5, including the inner wall of the cavity 301 formed by the dissolution of the ink layer 3, which facilitates subsequent copper plating.

[0041] S104: Perform a second degreasing treatment on the walls of the through holes and the cavity containing the colloidal palladium to remove all ink and the colloidal palladium, thereby obtaining a circuit board.

[0042] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the core board structure after the second degreasing process in the circuit board processing method of the present invention. In this embodiment, the through hole 4 containing colloidal palladium 6 is subjected to a second degreasing treatment. Since colloidal palladium 6 cannot form a dense film on the ink, the residual ink can continue to be dissolved during the second degreasing process, and the colloidal palladium 6 adsorbed on the ink can be carried away, thereby eliminating the presence of colloidal palladium 6 in the cavity 301 and completing the cleaning of the entire ink layer 3.

[0043] Second Embodiment

[0044] Please see Figure 7 , Figure 7 This is a flowchart of the second embodiment of the circuit board processing method of the present invention. It should be noted that if substantially the same result is achieved, the method of the present invention does not necessarily require further elaboration. Figure 12 The illustrated process sequence is limited. For example... Figure 12 As shown, the method includes the following steps:

[0045] S201: Obtain multiple core boards to be laminated, and cover the two surfaces of the core boards with copper layers.

[0046] Please see Figure 8 , Figure 8 This is a schematic diagram of the core board structure after blanking in the circuit board processing method of the present invention. In this embodiment, blanking is performed first, and a core board 1 of appropriate size is cut from the material board. A layer of copper 8 is deposited on both sides of the core board 1 so that the circuit pattern 2 can be processed later.

[0047] S202: The copper layers on both sides of the core board are patterned to form a circuit pattern.

[0048] Please see Figure 9 , Figure 9This is a schematic diagram of the core board structure after pattern transfer in the circuit board processing method of the present invention. In this embodiment, after a layer of copper 8 is wrapped on the core board 1, photosensitive dry films need to be attached to both sides of the board. The photosensitive dry films are sheet-like and parallel to the core board 1, and are located on both sides of the core board 1. After attaching the photosensitive dry films to the two sides of the core board 1, the photosensitive dry films need to be exposed to project the circuit diagram data to be processed onto the photosensitive dry films for exposure, thereby recording the circuit diagram data on the photosensitive dry films. During the processing, the photosensitive dry films attached to the copper-clad laminate undergo a polymerization reaction after being irradiated by ultraviolet light, thereby forming a stable substance that adheres to the copper clad laminate, thereby achieving the functions of blocking electroplating, etching, and via masking. Finally, the photosensitive dry films are removed, realizing the transfer of the circuit pattern 2 of the core board 1.

[0049] S203: Print ink in each area of ​​the circuit pattern to form an ink layer.

[0050] Please see Figure 10 , Figure 10 This is a schematic diagram of the core board structure after printing the ink layer in the circuit board processing method of the present invention. In this embodiment, after the circuit pattern 2 is transferred, ink needs to be printed on the circuit pattern 2. According to the prior design, the ink layer 3 is printed and laid in the corresponding position to form multiple ink layers.

[0051] S204: Laminating multiple core boards with the ink layer to obtain the circuit board to be processed.

[0052] Please combine Figure 2 , Figure 2 This is a schematic diagram of the circuit board structure in the circuit board processing method of the present invention. In this embodiment, the processed core board 1 is laminated so that multiple core boards 1 are stacked and bonded together to obtain a multilayer circuit board 5. After the connection is completed, through holes 4 that have no connection or transmission function are drilled out. Since the ink layer 3 is designed in advance, the through holes 4 are inserted through the ink layer 3, and the ink layer 3 is located on both sides of the through holes 4.

[0053] Specifically, since both excessively long and excessively short ink layer 3 will affect the final transmission quality of circuit board 5, if ink layer 3 is too long, the cavity will be larger in the later stage, and the upper and lower parts of the cavity will easily come into contact; if ink layer 3 is too short, the deposited copper 7 formed later will be too dense. Therefore, in this embodiment, the center position of the ink is aligned with the center position of the via 4, and the diameter of the ink is increased by 100-200 micrometers based on the diameter of the via 4. It can be 100 micrometers, 120 micrometers, 150 micrometers, 180 micrometers, 200 micrometers, etc. In this embodiment, it is preferred to increase the diameter of the via 4 by 150 micrometers. In other embodiments, it can also be increased by 0-100 micrometers or more than 200 micrometers based on the diameter of the via 4. No further limitation is made here.

[0054] Specifically, the thickness of the printing ink is controlled between 30 and 50 micrometers, with 30, 40, or 50 micrometers being optional. In this embodiment, 40 micrometers is preferred. In other embodiments, the thickness can be less than 30 micrometers or greater than 50 micrometers, such as 20 micrometers or 60 micrometers.

[0055] S205: Place the core board in a solution for the first degreasing process to remove part of the ink layer from the walls of the through holes.

[0056] Please combine Figure 4 , Figure 4 This is a schematic diagram of the core board structure after the first degreasing process in the circuit board processing method of the present invention. In this embodiment, the circuit board 5 after drilling the through hole 4 undergoes the first degreasing treatment, that is, the circuit board 5 is placed in a specific solution, thereby dissolving the ink layer 3. After the ink layer 3 is dissolved, the inner wall of the through hole 4 between the two ink layers 3 is disconnected, breaking the electrical connection between different areas.

[0057] Specifically, in this embodiment, the first degreasing treatment uses a sodium hydroxide solution of 20±3wt%, such as a sodium hydroxide solution of 17wt%, 20wt%, or 23wt%. In other embodiments, other concentrations of sodium hydroxide solution can also be used, which will not be elaborated on here.

[0058] Specifically, in this embodiment, the external temperature for the first degreasing treatment is preferably 85±10 degrees Celsius. For example, it can be 75 degrees Celsius, 85 degrees Celsius, 95 degrees Celsius, etc., all of which can achieve a high reaction rate. In other embodiments, other non-preferred temperatures can also be used, such as 70 degrees Celsius and 73 degrees Celsius, which will not be elaborated on here.

[0059] In this embodiment, the purpose of the first degreasing is to laterally etch the ink layer 3, forming a cavity 301 at the location of the ink layer 3. Specifically, considering structural stability and processing technology, in this embodiment, the cavity 301 formed by the first degreasing is preferably 60-80 micrometers, for example, it can be 60 micrometers, 70 micrometers, 80 micrometers, etc. In other embodiments, it can also be 55 micrometers or 85 micrometers, that is, a cavity 301 of a certain length can be formed, which will not be elaborated further here.

[0060] S206: After the first degreasing treatment, the through hole is degreased, shaped, and pre-impregnated.

[0061] In this embodiment, after the cavity 301 is machined on the ink layer 3, the inner wall of the through hole 4 is degreased and shaped. This involves cleaning the hole wall surface, removing oxides from the copper surface and ink from the cavity 301, adjusting the charge on the hole wall, and ensuring the cleanliness of the hole wall and the cavity 301. After the degreasing and shaped hole operation is completed, a pre-impregnation treatment is required to enhance the wettability of the inner wall of the through hole 4 and the cavity 301, making it easier for the subsequent adsorption of colloidal palladium 6.

[0062] S207: Inject colloidal palladium into the through hole after the first degreasing treatment, so that the colloidal palladium is adsorbed on the hole wall and the inner wall of the cavity.

[0063] Please combine Figure 5 , Figure 5 This is a schematic diagram of the core board structure after adsorbing colloidal palladium in the circuit board processing method of the present invention. In this embodiment, after cleaning, colloidal palladium 6 needs to be adsorbed on the inner wall of the through hole 4 of the circuit board 5, including the inner wall of the cavity 301 formed by the dissolution of the ink layer 3. The presence of the pit will reduce the amount of colloidal palladium 6 adsorbed at this position, thus facilitating the subsequent copper plating process.

[0064] S208: Degelatinize the colloidal palladium to expose the palladium core.

[0065] In this embodiment, colloidal palladium 6 is adsorbed on both the inner wall of the through hole 4 and the cavity 301. After adsorption, the colloidal palladium 6 needs to be degellated. After degelation, some of the basic stannate compounds around the palladium core are removed, thereby exposing the palladium core completely and enhancing the activity of the colloidal palladium 6.

[0066] S209: The core board with the adsorbed colloidal palladium is placed in a solution for a second degreasing process to remove all ink layers from the walls of the through holes, thereby obtaining the circuit board.

[0067] Please see Figure 6 , Figure 6 This is a schematic diagram of the core board structure after the second degreasing process in the circuit board processing method of the present invention. In this embodiment, the process parameters for the second degreasing treatment are the same as those for the first degreasing treatment, namely, using a 20±3wt% sodium hydroxide solution and processing at an environment of 85±10 degrees Celsius. Specific parameters can be found in step S203 for the first degreasing treatment, and will not be elaborated further here. Because colloidal palladium 6 cannot form a dense film like copper, the degreasing process can continue to laterally etch the ink, cleaning up any remaining ink in the cavity 301, allowing the ink to continue dissolving and carrying away the colloidal palladium 6 at that location. Consequently, in the subsequent copper plating process, due to the lack of colloidal palladium 6 catalysis, there is no copper deposition area at that location.

[0068] S210: The through-hole walls after the second degreasing treatment are sequentially subjected to copper plating, copper immersion, and etching steps to obtain the circuit board.

[0069] Please combine Figure 11 , Figure 12 ,in Figure 11 This is a schematic diagram of the core board structure after copper plating in the circuit board processing method of the present invention; Figure 12 This is a schematic diagram of the core board structure after etching in the circuit board processing method of the present invention. In this embodiment, the through-hole 4, which has undergone the second degreasing treatment, is subjected to copper deposition treatment. The activation of the palladium core induces the autocatalytic reaction of chemically deposited copper 7. The newly generated metallic copper and the reaction byproduct hydrogen can both act as reaction catalysts to catalyze the reaction, allowing the metallic copper reaction to proceed continuously. After this step, a layer of chemically deposited copper can be deposited on the area where colloidal palladium 6 is adsorbed. In the bath solution, normal air agitation should be maintained to oxidize the cuprous ions and copper powder in the bath solution, converting them into soluble divalent copper.

[0070] After the copper plating is completed, another copper plating is required on the basis of the deposited copper 7. During the thickening process, because the previous second degreasing process has broken the copper hole between the two ink layers 3 of the core board 1, the copper hole between the upper and lower ink layers 3 is also in a broken state. During the electroplating process, the copper hole at this position will not change much and will still be the thin copper when depositing copper 7. The other areas of the deposited copper 7 are electroplated to thicken.

[0071] After the electroplating thickening is completed, the inner wall of the through hole 4 is finally etched. This etching removes the thin copper layer 7 deposited between the upper and lower ink layers 3, ensuring a complete electrical break between the upper and lower ink layers, while the thickness of other electroplated copper layers remains largely unchanged. Specifically, this etching uses 3-8 wt% sulfuric acid; for example, 3 wt%, 5 wt%, or 8 wt% sulfuric acid can be used to etch the thin copper. This increases the distance of the copper break in the hole and also ensures the break in the electrical connection between different core board layers 1.

[0072] Third Embodiment

[0073] Please combine Figure 13 , Figure 13This is a schematic diagram of the circuit board structure of the present invention. In this embodiment, the circuit board 5 has multiple core board layers, each corresponding to a core board 1. In this embodiment, there are three core board layers. In other embodiments, it can also be composed of four or two core boards 1 stacked together, without further limitation. Each core board 1 has circuit patterns 2 laid on both sides of its surface. A fill layer 9 is provided between every two core boards 1. The opposite sides of the fill layer 9 connect the surface of different core boards 1 to the circuit patterns 2 on that surface.

[0074] In this embodiment, a through hole 4 is formed on the circuit board 5, penetrating the entire circuit board 5. The central axis of the through hole 4 is perpendicular to the surface of the circuit board 5. A plurality of cavities 301 are formed on the filling layer 9, with the extension direction of the cavities 301 perpendicular to the axis of the through hole 4. The cavities 301 are arranged in a ring along the axial direction of the through hole 4, i.e., the cavities 301 are annular cavities 301, and the cavities 301 are interconnected with the through hole 4. A copper deposition layer 7 is electroplated on the inner wall of the through hole 4. However, there is no copper deposition layer 7 on the inner wall of the through hole 4 between the two cavities 301. Because there is a copper deposition layer 7 on the inner wall of the through hole 4, the circuit patterns 2 on both sides of the core board 1 are connected. Furthermore, because there is no copper deposition layer 7 on the inner wall of the through hole 4 between the two cavities 301, the electrical connection between the upper and lower ink positions is completely disconnected, thus achieving no residual pins and minimizing the impact on signal integrity.

[0075] In this embodiment, if the cavity 301 is too large or too small, it will affect the reliability of the product. If the cavity 301 is too long, the upper and lower parts of the cavity will easily come into contact, causing the cavity to fail and even causing the layers to separate. If the cavity 301 is too short, it will serve as a partition.

[0076] Specifically, the diameter of the annular cavity 301 is 100-200 micrometers larger than the radius of the through hole 4, so that the structural strength of the circuit board 5 is not affected when the cavity 301 is formed. In this embodiment, it is preferably 150 micrometers, but in other embodiments it can also be 100 micrometers, 130 micrometers, 180 micrometers, or 200 micrometers, which will not be elaborated further.

[0077] Specifically, the thickness of cavity 301 is controlled between 30 and 50 micrometers, preferably 40 micrometers in this embodiment. In other embodiments, the thickness can also be 30 micrometers, 50 micrometers, etc., which will not be elaborated on here.

[0078] In this embodiment, no residual pillars are formed in the circuit board 5, which ensures the disconnection of the electrical connection between the two core boards 1 in the through hole 4. This can improve the stability of signal transmission during the use of the circuit board 5, reduce reflection and resonance during signal transmission, and improve signal integrity.

[0079] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method of processing a circuit board, characterized by, include: Obtain the circuit board to be processed, and drill through holes at predetermined positions on the circuit board; wherein the through holes penetrate the ink layer of the core board; The through hole is subjected to a first degreasing treatment to remove at least a portion of the ink layer from the hole wall and to form at least one cavity on both sides of the hole wall, wherein the cavity communicates with the through hole; Colloidal palladium is injected into the through hole after the first degreasing treatment, so that the colloidal palladium is adsorbed on the hole wall and the inner wall of the cavity; The colloidal palladium is subjected to a degellation treatment to expose the palladium core. A second degreasing treatment is performed on the walls of the through-holes containing the colloidal palladium and the cavity to remove all the ink and the colloidal palladium, resulting in a circuit board.

2. The method of processing a circuit board according to claim 1, wherein The step of obtaining the circuit board to be processed and drilling through holes at predetermined locations on the circuit board, wherein the through holes penetrate the ink layer of the core board, includes: Multiple core boards to be laminated are obtained, and copper layers are covered on both surfaces of the core boards; The copper layers on both sides of the core board are patterned to form a circuit pattern; Ink is printed in each area of ​​the circuit pattern to form an ink layer; Multiple core boards with the ink layer are laminated together to obtain the circuit board to be processed.

3. The method of processing a circuit board according to claim 1, wherein After the first degreasing treatment Prior to the step of injecting colloidal palladium into the through-hole to allow the colloidal palladium to be adsorbed onto the hole wall and the inner wall of the cavity, the method further includes: The through holes after the first degreasing treatment are then subjected to degreasing, hole straightening, and pre-impregnation treatment.

4. The method of processing a circuit board according to claim 1, wherein The step of performing a first degreasing treatment on the through-hole to remove at least a portion of the ink layer from the through-hole wall and forming at least one cavity on both sides of the through-hole wall, wherein the cavity communicates with the through-hole, includes: The core board is placed in a solution for the first degreasing process to remove part of the ink layer from the walls of the through holes; wherein the solution is 20±3% sodium hydroxide by mass and the temperature is 85±10 degrees Celsius.

5. The method of processing a circuit board according to claim 1, wherein The step of performing a second degreasing treatment on the walls of the through-holes coated with the colloidal palladium and the cavity to remove all ink and the colloidal palladium to obtain the circuit board includes: The core board with the adsorbed colloidal palladium is placed in a solution for a second degreasing process to remove all the ink layers from the walls of the through holes, thereby obtaining the circuit board. The hole wall has at least one cavity on each side, the cavity has a length of 30-50 micrometers along the axial direction of the through hole, and a length of 60-80 micrometers perpendicular to the axial direction of the through hole. The solution is sodium hydroxide of 20±3% by mass and the temperature is 85±10 degrees Celsius.

6. The method of processing a circuit board according to claim 1, wherein After the step of performing a second degreasing treatment on the walls of the through-holes coated with the colloidal palladium and the cavity to remove all ink and the colloidal palladium to obtain the circuit board, the method further includes: The through-hole walls after the second degreasing treatment are sequentially subjected to copper plating, copper immersion, and etching steps to obtain the circuit board.

Images