Light detection device and light detection system

Abstract

A light detection device according to the present disclosure includes: a light receiving section having a light receiving element, a first switch that connects the light receiving element to a first node in an on state, a second switch that applies a prescribed voltage to the first node in an on state, and a signal generator that generates a pulse signal in accordance with a voltage of the first node; a controller that controls operations of the first switch and the second switch; a detector that detects a timing at which the pulse signal changes based on the pulse signal; and an output section that outputs a detection signal corresponding to a detection result of the detector when the second switch is placed in the on state.

Description

Technical Field

[0001] This disclosure relates to an optical detection device and an optical detection system for detecting light. Background Technology

[0002] The Time-of-Flight (TOF) method is frequently used to measure distances to an object. In this TOF method, light is emitted, and the reflected light from the object is detected. The distance to the object is then measured by measuring the time difference between the timing of the emitted light and the timing of the detected reflected light. Some such distance measuring devices have a BIST (Built-in Self-Test) function. For example, Patent Document 1 discloses a technique for detecting malfunctions in a light receiver using light reflected within the housing.

[0003] List of citations

[0004] Patent documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2020-112501 Summary of the Invention

[0006] Therefore, in optical detection devices, it is desirable to perform self-diagnosis and diagnose the presence or absence of faults through the BIST function.

[0007] The goal is to provide a light detection device and light detection system capable of performing self-diagnosis.

[0008] The optical detection apparatus according to an embodiment of the present disclosure includes a light receiving unit, a controller, a detector, and an output unit. The light receiving unit is configured to include a light receiving element, a first switch, a second switch, and a signal generator. The first switch couples the light receiving element to a first node by being turned on. The second switch applies a predetermined voltage to the first node by being turned on. The signal generator generates a pulse signal based on the voltage at the first node. The controller is configured to control the operation of the first and second switches. The detector is configured to detect timing changes in the pulse signal based on the pulse signal. The output unit is configured to output a detection signal corresponding to the detection result of the detector when the second switch is turned on.

[0009] A light detection system according to an embodiment of the present disclosure includes a light-emitting unit and a light detector. The light-emitting unit is configured to emit light. The light detector is configured to detect light reflected by a measurement object from light emitted from the light-emitting unit. The light detector includes a light-receiving unit, a controller, a detector, and an output unit. The light-receiving unit is configured to include a light-receiving element, a first switch, a second switch, and a signal generator. The first switch couples the light-receiving element to a first node by being turned on. The second switch applies a predetermined voltage to the first node by being turned on. The signal generator generates a pulse signal based on the voltage at the first node. The controller is configured to control the operation of the first and second switches. The detector is configured to detect timing changes in the pulse signal based on the pulse signal. The output unit is configured to output a detection signal corresponding to the detection result of the detector when the second switch is turned on.

[0010] In the optical detection apparatus and optical detection system according to embodiments of the present disclosure, in the optical receiving unit, a first node is coupled to an optical receiving element by turning on a first switch, and a predetermined voltage is applied to the first node by turning on a second switch. A pulse signal is generated based on the voltage at the first node. The first and second switches are controlled by a controller. The detector detects the timing of changes in the pulse signal based on the pulse signal. Then, when the second switch is turned on, the output unit outputs a detection signal corresponding to the detection result of the detector. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a configuration example of a light detection system according to an embodiment of the present disclosure.

[0012] Figure 2 This is a block diagram illustrating a configuration example of a photodetector according to the first embodiment.

[0013] Figure 3 It is shown Figure 2 The circuit diagram shows an example of the configuration of the optical receiver.

[0014] Figure 4 It is shown Figure 2 The circuit diagram shows an example of a pixel array configuration.

[0015] Figure 5 It is shown Figure 2 The circuit diagram shows an example of the configuration of the trigger section.

[0016] Figure 6 It is an instruction Figure 1 The diagram illustrates an operational example of the optical detection system.

[0017] Figure 7 It is shown Figure 2 The diagram illustrates an example of the operation of a pixel array.

[0018] Figure 8 It is shown Figure 3 The diagram illustrates the operating status of the distance measurement operation of the light receiving unit.

[0019] Figure 9 It is an instruction Figure 1 The timing waveform diagram shows an example of the distance measurement operation of the optical detection system.

[0020] Figure 10 It is shown Figure 2 The diagram illustrates an example of the distance measurement operation of a histogram generator.

[0021] Figure 11 It is shown Figure 3 The diagram illustrates the operating status of the optical receiver during its self-diagnostic operation.

[0022] Figure 12 It shows Figure 3 The timing waveform diagram shows an example of the self-diagnostic operation of the optical receiver shown.

[0023] Figure 13 It is shown Figure 2 The diagram illustrates an example of the self-diagnostic operation of the histogram generator shown.

[0024] Figure 14A It is shown Figure 3 Another timing waveform diagram of an example of the self-diagnostic operation of the optical receiver shown.

[0025] Figure 14B It is shown Figure 2 Another illustrative diagram of an example of the self-diagnostic operation of the histogram generator shown.

[0026] Figure 15A It is shown Figure 3 Another timing waveform diagram of an example of the self-diagnostic operation of the optical receiver shown.

[0027] Figure 15B It is shown Figure 2 Another illustrative diagram of an example of the self-diagnostic operation of the histogram generator shown.

[0028] Figure 16A It is shown Figure 3 Another timing waveform diagram of an example of the self-diagnostic operation of the optical receiver shown.

[0029] Figure 16B It is shown Figure 2 Another illustrative diagram of an example of the self-diagnostic operation of the histogram generator shown.

[0030] Figure 17A It is shown Figure 3Another timing waveform diagram of an example of the self-diagnostic operation of the optical receiver shown.

[0031] Figure 17B It is shown Figure 2 Another illustrative diagram of an example of the self-diagnostic operation of the histogram generator shown.

[0032] Figure 18 It is shown Figure 3 This diagram illustrates another operating state of the self-diagnostic operation of the light receiver shown.

[0033] Figure 19A It is shown Figure 3 Another timing waveform diagram of an example of the self-diagnostic operation of the optical receiver shown.

[0034] Figure 19B It is shown Figure 2 Another illustrative diagram of an example of the self-diagnostic operation of the histogram generator shown.

[0035] Figure 20 This is a block diagram illustrating a configuration example of a photodetector according to a variation of the first embodiment.

[0036] Figure 21 It is shown Figure 20 The circuit diagram shows an example configuration of the TDC unit.

[0037] Figure 22 It is shown Figure 20 The illustration shows an example of the distance measurement operation of the histogram generator.

[0038] Figure 23 It is shown Figure 20 The diagram illustrates an example of the self-diagnostic operation of the histogram generator shown.

[0039] Figure 24 This is an explanatory diagram showing an operational example of a light detection system according to another variation of the first embodiment.

[0040] Figure 25 This is an explanatory diagram showing the operation state of the light receiving unit according to another variation of the first embodiment.

[0041] Figure 26 This is a timing waveform diagram illustrating an operational example of an optical detection system according to another variation of the first embodiment.

[0042] Figure 27 This is an explanatory diagram showing the operation state of the light receiving unit according to another variation of the first embodiment.

[0043] Figure 28This is a circuit diagram illustrating a configuration example of the light receiving section according to another variation of the first embodiment.

[0044] Figure 29 This is an explanatory diagram showing an example of the installation of a photodetector according to another variation of the first embodiment.

[0045] Figure 30 This is a block diagram illustrating a configuration example of a photodetector according to the second embodiment.

[0046] Figure 31 It is shown Figure 30 The circuit diagram shows an example of the configuration of the trigger section.

[0047] Figure 32 It is shown Figure 30 The diagram illustrates an example of the self-diagnostic operation of the histogram generator shown.

[0048] Figure 33 It is shown Figure 30 The diagram illustrates an example of the self-diagnostic operation of a histogram generator.

[0049] Figure 34 This is a circuit diagram showing a configuration example of the trigger section according to a modified example of the second embodiment.

[0050] Figure 35 This is an explanatory diagram illustrating an example of the self-diagnostic operation of a histogram generator according to a modified example of the second embodiment.

[0051] Figure 36 This is another illustrative diagram showing an example of the self-diagnostic operation of a histogram generator according to a variation of the second embodiment.

[0052] Figure 37 This is a circuit diagram showing a configuration example of the TDC unit according to another variation of the second embodiment.

[0053] Figure 38 This is a circuit diagram illustrating a configuration example of the light receiving section and the trigger section according to another variation of the second embodiment.

[0054] Figure 39 This is a circuit diagram illustrating a configuration example of the light receiving section and the trigger section according to another variation of the second embodiment.

[0055] Figure 40 This is a circuit diagram illustrating a configuration example of the light receiving section and the trigger section according to another variation of the second embodiment.

[0056] Figure 41 This is a circuit diagram illustrating a configuration example of the light receiving section and the trigger section according to another variation of the second embodiment.

[0057] Figure 42 This is a block diagram illustrating a configuration example of a photodetector according to a third embodiment.

[0058] Figure 43 It is shown Figure 42 The circuit diagram shows an example of the configuration of the trigger section.

[0059] Figure 44 It is shown Figure 43 The circuit diagram shows an example configuration of the adder.

[0060] Figure 45 It is shown Figure 42 The diagram illustrates the self-diagnostic operation of the histogram generator.

[0061] Figure 46 It is shown Figure 42 Another illustrative diagram of an example of the self-diagnostic operation of the histogram generator shown.

[0062] Figure 47 It is shown Figure 42 Another illustrative diagram of an example of the self-diagnostic operation of the histogram generator shown.

[0063] Figure 48 It is shown Figure 42 Another illustrative diagram of an example of the self-diagnostic operation of the histogram generator shown.

[0064] Figure 49 This is a block diagram illustrating a configuration example of a photodetector according to the fourth embodiment.

[0065] Figure 50 It shows Figure 49 The circuit diagram shows an example of the configuration of the optical receiver.

[0066] Figure 51 This is a timing waveform diagram illustrating an example of the distance measurement operation of the optical detection system according to the fourth embodiment.

[0067] Figure 52 It is shown Figure 50 The timing waveform diagram shows an example of the self-diagnostic operation of the optical receiver shown.

[0068] Figure 53 It is shown Figure 50 Another timing waveform diagram of an example of the self-diagnostic operation of the optical receiver shown.

[0069] Figure 54 It is shown Figure 50 Another timing waveform diagram of an example of the self-diagnostic operation of the optical receiver shown.

[0070] Figure 55It is shown Figure 50 Another timing waveform diagram of an example of the self-diagnostic operation of the optical receiver shown.

[0071] Figure 56 It is shown Figure 50 Another timing waveform diagram of an example of the self-diagnostic operation of the optical receiver shown.

[0072] Figure 57 This is a flowchart illustrating an example of self-diagnostic operation in a light detection system according to the fourth embodiment.

[0073] Figure 58 It is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0074] Figure 59 This is an illustration showing an example of the installation location of the vehicle exterior information detection unit and the imaging unit.

[0075] Figure 60 This is a block diagram illustrating a configuration example of a vehicle based on an application example.

[0076] Figure 61 This is another block diagram showing a configuration example of a vehicle based on an application example.

[0077] Figure 62 It is a flowchart indicating the operation of a vehicle in a real-world application example. Detailed Implementation

[0078] In the following description, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0079] 1. First Embodiment

[0080] 2. Second Embodiment

[0081] 3. Third embodiment

[0082] 4. Fourth Embodiment

[0083] 5. Examples of applications to moving bodies

[0084] 6. Specific application examples of vehicles

[0085] <1. First Embodiment>

[0086] [Configuration Example]

[0087] Figure 1 An example configuration of a light detection system (light detection system 1) according to an embodiment is shown. Light detection system 1 is a ToF sensor and is configured to emit light and detect reflected light reflected by the object being measured (OBJ). Light detection system 1 includes a light-emitting unit 11, an optical system 12, a photodetector 20, and a controller 14.

[0088] The light-emitting unit 11 is configured to emit light pulses L0 toward the measurement object OBJ based on instructions from the controller 14. The light-emitting unit 11 emits light pulses L0 by performing alternating and repetitive light emission and non-emission operations based on instructions from the controller 14. The light-emitting unit 11 includes a light source that emits, for example, infrared light. This light source may be constructed using, for example, a laser light source, an LED (light-emitting diode), or the like.

[0089] The optical system 12 includes a lens that forms an image on the light-receiving surface of the photodetector 20. A light pulse (reflected light pulse L1) emitted from the light-emitting unit 11 and reflected by the measurement object OBJ enters the optical system 12.

[0090] The photodetector 20 is configured to detect the reflected light pulse L1 based on instructions from the controller 14. The photodetector 20 then generates a distance image based on the detection result and outputs the image data of the generated distance image as a distance image signal S1. Furthermore, as described later, the photodetector 20 has the function of performing a self-diagnostic operation and outputs the diagnostic result as a diagnostic result signal S2.

[0091] The controller 14 is configured to provide control signals to the light-emitting unit 11 and the photodetector 20, and to control the operation of the light-emitting unit 11 and the photodetector 20, thereby controlling the operation of the light detection system 1.

[0092] Figure 2 An example configuration of the light detector 20 is shown. The light detector 20 includes a pixel array 21, a trigger unit 22, a histogram generator 23, a distance calculator 24, an output unit 25, a diagnostic unit 26, an output unit 27, and a distance measurement controller 28.

[0093] The pixel array 21 includes a plurality of light receivers P arranged in a matrix. Each light receiver P is configured to detect light, thereby generating a pulse signal having a pulse corresponding to the detection light. In addition, when the light detection system 1 performs self-diagnostic operation, the light receiver P can generate the pulse signal based on the supplied control signals (control signals ENBIST and XACT described later).

[0094] Figure 3 An example configuration of the light receiver P is shown. The light receiver P includes a photodiode PD, transistors MN1, MP1, MP2, MP3 and MN2, an inverter IV1, an AND circuit AND1 and an OR circuit OR1. Transistors MN1 and MN2 are N-type MOS (metal-oxide-semiconductor) transistors, and transistors MP1 to MP3 are P-type MOS transistors.

[0095] A photodiode (PD) is a photoelectric conversion element that converts light into electrical charge. A PD has an anode supplied with a power supply voltage VNEG and a cathode coupled to the drains of transistors MN1 and MP1. For example, a single-photon avalanche diode (SPAD) can be used for a PD.

[0096] Transistor MN1 has a gate supplied with the control signal ENBIST, a drain coupled to the cathode of photodiode PD and the drain of transistor MP1, and a source grounded. Transistor MP1 has a gate supplied with the control signal ENBIST, a drain coupled to the cathode of photodiode PD and the drain of transistor MN1, and a source coupled to node N1 and a back gate. With this configuration, when the control signal ENBIST is low, transistor MP1 is turned on and transistor MN1 is turned off. Therefore, in the light receiver P, the cathode of photodiode PD is coupled to node N1 through transistor MP1. Conversely, when the control signal ENBIST is high, transistor MN1 is turned on and transistor MP1 is turned off. Therefore, in the light receiver P, the cathode of photodiode PD and node N1 are separated from each other, and the cathode of photodiode PD is grounded through transistor MN1.

[0097] Transistor MP2 has a gate supplied with a bias voltage Vbias, a source supplied with a power supply voltage VDDH, and a drain coupled to the source of transistor MP3. Transistor MP2 operates as a constant current source (constant current source CUR, described later) that transfers current from the power node for the power supply voltage VDDH to node N1. Transistor MP3 has a gate supplied with a control signal XACT, a source coupled to the drain of transistor MP2, and a drain coupled to node N1. Transistor MN2 has a gate supplied with the control signal XACT, a drain coupled to node N1, and a grounded source. With this configuration, when the control signal XACT is low, transistor MP3 is turned on and transistor MN2 is turned off. Therefore, in the optical receiver P, the drain of transistor MP2, which serves as a constant current source, is coupled to node N1 through transistor MP3. Conversely, when the control signal XACT is high, transistor MN2 is turned on and transistor MP3 is turned off. Therefore, in the light receiving section P, the drain of the transistor MP2, which serves as a constant current source, and node N1 are separated from each other, and node N1 is grounded through transistor MN2.

[0098] Inverter IV1 is configured to generate an inverted voltage at node N1, thereby generating a pulse signal PLS1. Inverter IV1 is supplied with a power supply voltage VDDH.

[0099] The AND circuit AND1 is configured to generate the pulse signal PLS2 by performing a logical AND operation on the pulse signal PLS1 and the control signal SEL. The AND circuit AND1 is supplied with a power supply voltage VDDL that is lower than the power supply voltage VDDH.

[0100] OR circuit OR1 is configured to generate pulse signal PLS3 (pulse signal PLS3B) by performing a logical OR operation on pulse signal PLS2 and pulse signal PLS3 (pulse signal PLS3A) provided from another optical receiver P. OR circuit OR1 is supplied with a power supply voltage VDDL.

[0101] Figure 4 An example configuration of pixel array 21 is shown. For ease of explanation, Figure 4 The light receiver P is shown in a simplified manner. Specifically, the photodiode PD and transistors MN1, MP1, MP2, and MP3 are not shown. Furthermore, transistor MN2 is shown using the symbol for a switch.

[0102] In this example, Figure 4 Multiple optical receivers P arranged side-by-side in a horizontal direction are coupled one to one of their respective fourth optical receivers P. Specifically, the output terminal of the OR1 of a certain optical receiver P (optical receiver P1) is coupled to the input terminal of the OR1 of the fourth optical receiver P (optical receiver P5) to the right of optical receiver P1. The output terminal of the OR1 of the OR1 of the optical receiver P (optical receiver P2) to the right of optical receiver P1 is coupled to the input terminal of the OR1 of the fourth optical receiver P (optical receiver P6) to the right of optical receiver P2. The output terminal of the OR1 of the OR1 of the optical receiver P (optical receiver P3) to the right of optical receiver P2 is coupled to the input terminal of the OR1 of the fourth optical receiver P (optical receiver P7) to the right of optical receiver P3. The output terminal of the OR circuit OR1 of the light receiver P (light receiver P4) to the right of light receiver P3 is coupled to the input terminal of the OR circuit OR1 of the fourth light receiver P (light receiver P8) to the right of light receiver P4. In this example, eight light receivers P1 to P8 in a certain row have been described as an example. This also applies to multiple light receivers P in other rows. Therefore, in pixel array 21, multiple light receivers P are coupled in a so-called daisy-chain coupling manner. Then, in the multiple light receivers P coupled in this daisy-chain manner, the OR circuit OR1 of the final stage light receiver P each outputs a pulse signal PLS, such as... Figure 2 As shown.

[0103] Trigger section 22 ( Figure 2 It is configured to sample multiple pulse signals PLS provided from pixel array 21 based on clock signal CLK.

[0104] Figure 5 An example configuration of the trigger unit 22 is shown. The trigger unit 22 includes a plurality of triggers 29. The triggers 29 are configured to correspond one-to-one with a plurality of pulse signals PLS provided from the pixel array 21. Each of the plurality of triggers 29 is a D-type trigger and is configured to sample the corresponding pulse signal PLS based on the clock signal CLK, thereby generating a pulse signal PLSA.

[0105] Histogram generator 23 ( Figure 2 The histogram generator 23 is configured to generate a histogram indicating the generation timing of the pulse signal PLS based on each of the plurality of pulse signals PLSA provided from the trigger unit 22. Specifically, in distance measurement operation, the photodetector 20 generates the pulse signal PLS by detecting the reflected light pulse L1, which causes the histogram generator 23 to generate a histogram indicating the light reception timing of each of the plurality of light receivers P based on the plurality of pulse signals PLSA. Furthermore, in self-diagnostic operation, the photodetector 20 generates the pulse signal PLS based on the control signal XACT, which causes the histogram generator 23 to generate a histogram indicating the generation timing of the pulse signal PLS based on the control signal XACT in each of the plurality of light receivers P based on the plurality of pulse signals PLSA.

[0106] The distance calculator 24 is configured to generate a distance image by calculating the distance value to the measured object OBJ based on data from the light receiving timing of each of the plurality of light receivers P. Data is provided from the histogram generator 23.

[0107] The output unit 25 is configured to output the image data of the distance image generated by the distance calculator 24 as the distance image signal S1.

[0108] The diagnostic unit 26 is configured to perform diagnostic processing on multiple light receiving units P in the pixel array 21 based on data from the generation timing of the pulse signal PLS based on the control signal XACT. Data is provided from the histogram generator 23.

[0109] Output unit 27 is configured to output the result of the diagnostic processing performed by diagnostic unit 26 as a diagnostic result signal S2. Diagnostic result signal S2 includes a flag signal indicating whether any one of the plurality of optical receivers P is faulty. Furthermore, if any one of the plurality of optical receivers P is faulty, diagnostic result signal S2 includes a signal indicating details of the fault. Output unit 27 outputs diagnostic result signal S2 including this information.

[0110] Distance measurement controller 28 is configured to be based on data from controller 14 ( Figure 1The instructions control the operation of the pixel array 21, the trigger unit 22, the histogram generator 23, the distance calculator 24 and the diagnostic unit 26, thereby controlling the operation of the photodetector 20.

[0111] Here, the photodiode PD corresponds to a specific example of the "light receiving element" in this disclosure. Node N1 corresponds to a specific example of the "first node" in this disclosure. Transistor MP1 corresponds to a specific example of the "first switch" in this disclosure. Transistor MN2 corresponds to a specific example of the "second switch" in this disclosure. Pulse signal PLS1 corresponds to a specific example of the "pulse signal" in this disclosure. Inverter IV1 corresponds to a specific example of the "signal generator" in this disclosure. Distance measurement controller 28 corresponds to a specific example of the "controller" in this disclosure. Trigger unit 22 and histogram generator 23 correspond to specific examples of the "detector" in this disclosure. Output unit 27 corresponds to a specific example of the "output unit" in this disclosure. Diagnostic unit 26 corresponds to a specific example of the "diagnostic unit" in this disclosure.

[0112] [Operation and Work]

[0113] Next, the operation and function of the light detection system 1 according to this embodiment will be described.

[0114] (Overview of the overall operation)

[0115] First, refer to Figure 1 and Figure 2 An overview of the overall operation of the optical detection system 1 is described below. The light-emitting unit 11 emits a light pulse L0 toward the object being measured OBJ. The optical system 12 forms an image on the light-receiving surface of the photodetector 20. The photodetector 20 detects the light pulse (reflected light pulse L1) reflected by the object being measured OBJ. The controller 14 provides control signals to the light-emitting unit 11 and the photodetector 20, and controls their operation, thereby controlling the distance measurement operation of the optical detection system 1.

[0116] In the photodetector 20, the pixel array 21 generates multiple pulse signals PLS corresponding to the light reception results of multiple light receiving units P. The trigger unit 22 samples the multiple pulse signals PLS provided from the pixel array 21 based on the clock signal CLK, thereby generating each of the multiple pulse signals PLSA. The histogram generator 23 generates a histogram indicating the light reception timing of each of the multiple light receiving units P based on each of the multiple pulse signals PLSA provided from the trigger unit 22. The distance calculator 24 calculates the distance value to the measurement object OBJ based on the light reception timing data of each of the multiple light receiving units P provided from the histogram generator 23, thereby generating a distance image. The output unit 25 outputs the image data of this distance image as a distance image signal S1.

[0117] In the self-diagnostic operation, pixel array 21 generates multiple pulse signals PLS based on control signal XACT. Trigger unit 22 samples the multiple pulse signals PLS provided from pixel array 21 based on clock signal CLK, thereby generating each of the multiple pulse signals PLSA. Histogram generator 23 generates a histogram indicating the generation timing of the pulses of the pulse signals PLS based on control signal XACT, based on each of the multiple pulse signals PLSA provided from trigger unit 22. Diagnostic unit 26 performs diagnostic processing on multiple light receiving units P in pixel array 21 based on the pulse generation timing data of the pulse signals PLS based on control signal XACT. Data is provided from histogram generator 23. Output unit 27 outputs the diagnostic processing result of diagnostic unit 26 as a diagnostic result signal S2.

[0118] Based on instructions from controller 14, distance measurement controller 28 controls the operation of pixel array 21, trigger unit 22, histogram generator 23, distance calculator 24 and diagnostic unit 26, thereby controlling the operation of photodetector 20.

[0119] (Detailed instructions)

[0120] Next, the operation of the light detection system 1 will be described in detail.

[0121] Figure 6 An operational example of the light detection system 1 is shown. In the light detection system 1, a distance measurement time period T1 and a blanking time period P2 are alternately set. During the distance measurement time period T1, the light detection system 1 performs a distance measurement operation. Therefore, the light detection system 1 repeatedly performs the distance measurement operation. During the blanking time period T2, the light detection system 1 performs a self-diagnostic operation on the multiple light receiving units P in the pixel array 21. Here, the distance measurement time period T1 corresponds to a specific example of the "first time period" in this disclosure. The blanking time period T2 corresponds to a specific example of the "second time period" in this disclosure.

[0122] (Distance measurement operation)

[0123] First, a description of the distance measurement operation is given. In the distance measurement operation, the photodetector 20 sequentially selects multiple photodetectors P from multiple photodetectors P in the pixel array 21 as detection targets during a distance measurement time period T1, and calculates the distance value based on the light receiving timing of the selected multiple photodetectors P.

[0124] Figure 7 An example of the operation of selecting multiple light receiving units P as detection targets in the photodetector 20 is shown. Figure 7In the diagram, the shaded areas schematically indicate the positions of multiple light receivers P selected in the pixel array 21. In this example, during a distance measurement time period T1, multiple light receivers P are sequentially selected from the left end of the pixel array 21.

[0125] Specifically, in Figure 4 In this process, the distance measurement controller 28 uses the control signal SEL to select multiple optical receivers P as detection targets. For example, the distance measurement controller 28 changes the control signal SEL to a high level for the optical receivers P in four columns, including optical receivers P1, P2, P3, and P4, and changes the control signal SEL to a low level for the optical receivers P in other columns. Therefore, the optical receivers P in the four columns, including optical receivers P1, P2, P3, and P4, are selected as detection targets.

[0126] In each selected light receiver P, such as Figure 3 As shown, the AND circuit AND1 generates a pulse signal PLS2 corresponding to pulse signal PLS1 by performing a logical AND operation on the pulse signal PLS1 generated by inverter IV1 and the high-level control signal SEL. In each unselected optical receiver P, as in... Figure 3 As shown, circuit AND1 holds pulse signal PLS2 at a low level based on control signal SEL, which is at a low level. As a result, pulse signal PLS2 generated by the selected light receiver P is provided as pulse signal PLS to trigger unit 22.

[0127] Figure 8 The selected optical receiver P and the trigger 29 that performs the operation based on the pulse signal PLS1 generated by the selected optical receiver P are shown. For ease of explanation, Figure 8 The circuit is shown in a simplified manner. Specifically, in Figure 8 In the diagram, transistor MP2 is shown using a constant current source CUR, and AND circuit AND1 and OR circuit OR1 in the light receiver P, as well as OR circuit OR1 of one or more light receivers P downstream of the light receiver P, are shown using a buffer BUF. Furthermore, transistors MN1, MN2, MP1, and MP3 are each indicated using symbols representing switches indicating the on / off states of the transistors.

[0128] Figure 9An operational example of the light receiver P and trigger 29 in distance measurement operation is shown, wherein (A) indicates the waveform of the control signal ENBIST, (B) indicates the waveform of the control signal XACT, (C) indicates the waveform of the light emitted from the light-emitting unit 11, (D) indicates the waveform of the light incident on the photodetector 20, (E) indicates the waveform of the voltage VN1 at node N1, (F) indicates the waveform of the pulse signal PLS1 (pulse signal PLS), (G) indicates the waveform of the clock signal CLK, and (H) indicates the waveform of the pulse signal PLSA.

[0129] During distance measurement operation, the distance measurement controller 28 changes the control signals ENBIST and XACT to a low level. Figure 9 (A) and (B)). Therefore, in the light receiving section P, as Figure 8 As shown, transistors MP1 and MP3 are turned on, while transistors MN1 and MN2 are turned off. As a result, the cathode of photodiode PD is coupled to node N1, and the constant current source CUR is coupled to node N1.

[0130] At time t11, the light-emitting unit 11 emits a light pulse L0 based on the command from the controller 14. Figure 9 (C)). The light pulse L0 is reflected by the object being measured OBJ. The light pulse reflected by the object being measured OBJ (reflected light pulse L1) enters the light receiving section P of the photodetector 20 at time t12. The time from the time t11 when the emitted light pulse L0 is emitted to the time t12 when the reflected light pulse L1 enters the light receiving section P is the time of flight Ttof of the light pulse detected by the light receiving section P.

[0131] In the light receiver P, the photodiode PD induces avalanche amplification by detecting light, which reduces the voltage VN1 at node N1. Figure 9 (E)). Then, at time t13, when the voltage VN1 at node N1 becomes lower than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from low to high. Figure 9 (F)). In the subsequent timing t14, the flip-flop 29 samples the pulse signal PLS corresponding to the pulse signal PLS1 based on the rising edge of the clock signal CLK, so as to change the pulse signal PLSA from low level to high level. Figure 9 (G) and (H)).

[0132] Subsequently, current flows into node N1 through the constant current source CUR to increase the voltage VN1 at node N1. Figure 9 (E)). Then, at time t15, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS from high to low. Figure 9 (F)). In the subsequent timing t16, the flip-flop 29 samples the pulse signal PLS corresponding to the pulse signal PLS1 based on the rising edge of the clock signal CLK, so as to change the pulse signal PLSA from high level to low level. Figure 9 (G) and (H)).

[0133] As described above, in the optical detection system 1, an optical pulse L0 is emitted once to generate a pulse signal PLSA. The pulse signal PLSA includes a pulse that begins at a timing corresponding to the light reception timing of the reflected optical pulse L1. In this example, the pulse width of this pulse is corresponding to... Figure 9 The time length of the four clock pulses in the clock signal CLK shown in (H).

[0134] The optical detection system 1 repeatedly emits light pulses L1 multiple times within a distance measurement time period T1 to achieve the desired result. Figure 9 The operation shown is as follows. The optical detection system 1 performs this operation on each selected optical receiver P.

[0135] Figure 10 An operational example of the histogram generator 23 in a distance measurement operation is shown. (A) indicates the histogram of a light receiver P obtained when light pulse L0 is emitted once, and (B) indicates the histogram of a light receiver P obtained when light pulse L0 is emitted multiple times.

[0136] like Figure 9 As shown in (H), the optical detection system 1 generates a pulse signal PLSA by emitting an optical pulse L0 once. The pulse signal PLSA includes a pulse that begins at a timing corresponding to the optical reception timing of the reflected optical pulse L1. In this example, the pulse width of this pulse is the time length corresponding to four clock pulses in the clock signal CLK. Therefore, the histogram generator 23 generates... Figure 10 The histogram shown in (A) is shown. The width W of the histogram corresponds to the pulse period of the clock signal CLK. In this example, the light pulse L0 is emitted once; therefore, the frequency is "1". The left end of the histogram corresponds to the light reception timing of the reflected light pulse L1, and the width of the histogram distribution corresponds to the pulse width of the pulse signal PLS.

[0137] The optical detection system 1 repeatedly emits light pulses L0 multiple times within a distance measurement time period T1. Therefore, the cumulative effect of these multiple pulses is as follows: Figure 10 The data shown in (A). Therefore, histogram generator 23 generates... Figure 10 The histogram shown in (B) is used as an example. The optical detection system 1 can calculate the optical reception timing based on the position of the left end of the histogram, and can calculate the time of flight Ttof based on the optical reception timing.

[0138] Histogram generator 23 generates histograms for each of the multiple optical receivers P. Figure 10 The histogram shown in (B) is used to calculate the optical receiving timing in each of the plurality of optical receiving units P.

[0139] The distance calculator 24 calculates the distance value to the measurement object OBJ based on the light reception timing data from each of the plurality of light receiving units P provided by the histogram generator 23, thereby generating a distance image. Then, the output unit 25 outputs the image data of the distance image as a distance image signal S1.

[0140] (Self-diagnostic procedure)

[0141] Next, the self-diagnostic operation will be described. In the self-diagnostic operation, the photodetector 20 sequentially selects multiple photoreceivers P from multiple photoreceivers P in the pixel array 21 as detection targets during a blanking time period T2, as in the distance measurement operation ( Figure 7 In the case of ), the photodetector 20 then performs self-diagnosis by changing the control signal XACT in the selected plurality of photoreceiving units P.

[0142] Figure 11 The selected optical receiver P and the trigger 29 that performs operation based on the pulse signal PLS1 generated by the selected optical receiver P are shown. For ease of explanation, [the following is a description of the process]. Figure 8 Same, Figure 11 The circuit is shown in a simplified manner.

[0143] Figure 12 An operational example of the optical receiver P and trigger 29 in self-diagnostic operation is shown. (A) indicates the waveform of the control signal ENBIST, (B) indicates the waveform of the control signal XACT, (C) indicates the waveform of the voltage VN1 at node N1, (D) indicates the waveform of the pulse signal PLS1 (pulse signal PLS), (E) indicates the waveform of the clock signal CLK, and (F) indicates the waveform of the pulse signal PLSA.

[0144] During self-diagnostic operation, the distance measurement controller 28 changes the control signal ENBIST to a high level. Figure 12 (A)). Therefore, in the light receiving section P, as Figure 11 As shown, transistor MP1 is off and transistor MN1 is on. As a result, the cathode of photodiode PD is disconnected from node N1 and grounded. Furthermore, the distance measurement controller 28 changes the control signal XACT to a high level during the time period prior to timing t21. Figure 12(B) Therefore, in the light receiver P, transistor MN2 is turned on and transistor MP3 is turned off. As a result, the constant current source CUR is disconnected from node N1, and node N1 is grounded.

[0145] At time t21, the distance measurement controller 28 changes the control signal XACT from high level to low level. Figure 12 (B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. As a result, node N1 is separated from the ground node and connected to the constant current source CUR.

[0146] Subsequently, current flows into node N1 through the constant current source CUR to increase the voltage VN1 at node N1. Figure 12 (C)). Then, at time t22, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS from high to low. Figure 12 (D)). In the subsequent timing t23, the flip-flop 29 samples the pulse signal PLS corresponding to the pulse signal PLS1 based on the rising edge of the clock signal CLK, so as to change the pulse signal PLSA from high level to low level. Figure 12 (E) and (F)). Voltage VN1 then reaches a high level, thus completing the preparation.

[0147] At time t24 after voltage VN1 reaches a high level, distance measurement controller 28 changes control signal XACT from low level to high level. Figure 12 (B) Therefore, in the light receiver P, transistor MN2 is turned on and transistor MP3 is turned off. As a result, node N1 is disconnected from the constant current source CUR and grounded, which changes the voltage VN1 at node N1 from a high level to a low level. Figure 12 (C) The voltage VN1 at node N1 becomes lower than the logic threshold TH of inverter IV1, causing inverter IV1 to change the pulse signal PLS1 from low to high. Figure 12 (D)). In the subsequent timing t25, the flip-flop 29 samples the pulse signal PLS corresponding to the pulse signal PLS1 based on the rising edge of the clock signal CLK, so as to change the pulse signal PLSA from low level to high level. Figure 12 (E) and (F)).

[0148] Next, at time t26, the distance measurement controller 28 changes the control signal XACT from high level to low level. Figure 12 (B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. As a result, node N1 is separated from the ground node and connected to the constant current source CUR.

[0149] Subsequently, current flows into node N1 through the constant current source CUR to increase the voltage VN1 at node N1. Figure 12 (C)). Then, at time t27, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS from high to low. Figure 12 (D)). In the subsequent timing t28, the flip-flop 29 samples the pulse signal PLS corresponding to the pulse signal PLS1 based on the rising edge of the clock signal CLK, so as to change the pulse signal PLSA from high level to low level. Figure 12 (E) and (F)).

[0150] Figure 13 An operational example of histogram generator 23 in the self-diagnostic process is shown. Figure 12 In the process, the optical detection system 1 changes the control signal XACT to a high level during timings t24 to t26 to generate a pulse signal PLSA containing pulses starting from the timing corresponding to the rising timing of the control signal XACT, such as... Figure 12 As shown in (F). In this example, the pulse width of the pulse is the time length corresponding to four clock pulses in the clock signal CLK. Therefore, the histogram generator 23 generates... Figure 13 The histogram shown is illustrated here. In this example, the control signal XACT goes high once; therefore, the frequency is "1". The left end of the histogram corresponds to the timing of the pulse generation of the pulse signal PLS, and the width of the histogram distribution corresponds to the pulse width of the pulse signal PLS.

[0151] The diagnostic unit 26 diagnoses the pulse generation timing and pulse width of the pulse signal PLS based on data from each of the plurality of light receivers P provided by the histogram generator 23, thereby performing diagnostic processing on the plurality of light receivers P in the pixel array 21.

[0152] Next, the self-diagnostic operation will be described in detail with reference to some examples of faults. In the optical receiver P, various faults may occur due to initial faults, degradation over time, etc. Figure 8Examples of faults may include cases where the current applied by the constant current source CUR is large (case C1) and cases where the current applied by the constant current source CUR is small (case C2). Examples of faults may include cases where the voltage VN1 at node N1 is stuck at a high level (case C3) and cases where the voltage VN1 at node N1 is stuck at a low level (case C4). Examples of faults may further include cases where the cathode of the photodiode PD is stuck at a low level or where the anode and cathode of the photodiode PD are short-circuited to each other (case C5). The diagnostic unit 26 is capable of diagnosing these various faults in the light receiving unit P.

[0153] (Case C1)

[0154] First, we describe the case where the constant current source CUR needs to apply a large current (case C1).

[0155] Figure 14A An operational example of the optical receiver P in case C1 is shown, where (A) indicates the waveform of the control signal ENBIST, (B) indicates the waveform of the control signal XACT, (C) indicates the waveform of the voltage VN1 at node N1, and (D) indicates the waveform of the pulse signal PLS1. Figure 14A In (C) and (D), the dashed line indicates the waveform when there is no fault, and the solid line indicates the waveform when there is a fault. Figure 14A (A) to (D) respectively correspond to Figure 12 (A) to (D). In Figure 14A The waveforms of the clock signal CLK and the pulse signal PLSA are not shown in the diagram; however, they are not shown in the diagram. Figure 12 Like (E) and (F), flip-flop 29 samples the pulse signal PLS based on the rising edge of the clock signal CLK to generate the pulse signal PLSA.

[0156] At time t31, the distance measurement controller 28 changes the control signal XACT from high level to low level. Figure 14A (B) Therefore, node N1 is disconnected from the ground node and connected to the constant current source CUR. Then, current flows into node N1 through the constant current source CUR to increase the voltage VN1 at node N1 ((C) of Figure 14). In the case of C1, the current applied by the constant current source CUR is large, and the voltage VN1 rises in a short time compared to the case without a fault. Then, at timing t32, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high level to low level ( Figure 14A (D)). Voltage VN1 then reaches a high level, thus completing the preparation.

[0157] Then, at time t33 after voltage VN1 reaches a high level, distance measurement controller 28 changes control signal XACT from low level to high level. Figure 14A (B) Therefore, node N1 is disconnected from the constant current source CUR and grounded, and the voltage VN1 at node N1 changes from high level to low level. Figure 14A (C)). The voltage VN1 at node N1 becomes lower than the logic threshold TH of inverter IV1, causing inverter IV1 to change the pulse signal PLS1 from low to high. Figure 14A (D)).

[0158] Next, at time t34, the distance measurement controller 28 changes the control signal XACT from high level to low level. Figure 14A (B) Therefore, node N1 is disconnected from the ground node and connected to the constant current source CUR. Current then flows into node N1 through the constant current source CUR to increase the voltage VN1 at node N1. Figure 14A (C)). In case C1, the current applied by the constant current source CUR is large, and the voltage VN1 rises rapidly in a short time compared to the case without a fault. Then, at time t35, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high to low. Figure 14A (D)).

[0159] Therefore, in case C1, the current applied by the constant current source CUR is large, which increases the voltage VN1 forward from timing t34 in a short time compared to the case without a fault. Consequently, the pulse end timing of pulse signal PLS1 becomes earlier, and the pulse width of pulse signal PLS1 becomes shorter. Therefore, the pulse width of pulse signal PLSA generated by trigger 29 also becomes shorter.

[0160] Figure 14B This illustrates an operational example of histogram generator 23 in case C1, where (A) indicates the case without a fault, and (B) indicates the case with a fault associated with case C1. Figure 14A As shown in (D), in case C1, the pulse width of the pulse signal PLS1 becomes shorter. Therefore, as Figure 14B As shown in (B), compared to the case where there is no fault ( Figure 14B Compared to (A), the right end of the histogram shifts to the left, which narrows the width of the histogram distribution.

[0161] When the right end of the histogram moves to the left end, thus narrowing the width of the histogram distribution, the diagnostic unit 26 diagnoses the light receiver P as having the following fault: the current applied by the constant current source CUR increases.

[0162] (Case C2)

[0163] Next, we will describe the case where the current applied by the constant current source CUR is small (case C2).

[0164] Figure 15A This illustrates an operational example of the optical receiver P in scenario C2. At timing t41, the distance measurement controller 28 changes the control signal XACT from high to low. Figure 15A (B) Therefore, node N1 is disconnected from the ground node and connected to the constant current source CUR. Then, current flows into node N1 through the constant current source CUR to increase the voltage VN1 at node N1 ((C) of Figure 15). In case C2, the current applied by the constant current source CUR is small, and the voltage VN1 rises for a longer time compared to the case without a fault. Then, at timing t42, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high level to low level ( Figure 15A (D)). Voltage VN1 then reaches a high level, thus completing the preparation.

[0165] Then, after the voltage VN1 reaches a high level, the distance measurement controller 28 changes the control signal XACT from a low level to a high level. Figure 15A (B) Therefore, node N1 is disconnected from the constant current source CUR and grounded, and the voltage VN1 at node N1 changes from high level to low level. Figure 15A (C)). The voltage VN1 at node N1 becomes lower than the logic threshold TH of inverter IV1, causing inverter IV1 to change the pulse signal PLS1 from low to high. Figure 15A (D)).

[0166] Next, at time t44, the distance measurement controller 28 changes the control signal XACT from high level to low level. Figure 15A (B) Therefore, node N1 is disconnected from the ground node and connected to the constant current source CUR. Then, current flows into node N1 through the constant current source CUR to increase the voltage VN1 at node N1 ((C) of Figure 15). In case C2, the current applied by the constant current source CUR is small, and the voltage VN1 rises for a longer time compared to the case without a fault. Then, at timing t45, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high level to low level ( Figure 15A (D)).

[0167] Therefore, in case C2, the current applied by the constant current source CUR is small, which increases the voltage VN1 a long time ahead of timing t44 compared to the case without a fault. Consequently, the timing of the end of the pulse of pulse signal PLS1 becomes later, and the pulse width of pulse signal PLS1 becomes longer. Therefore, the pulse width of pulse signal PLSA generated by trigger 29 also becomes longer.

[0168] Figure 15B An operational example of histogram generator 23 in case C2 is shown, where (A) indicates the case where no fault exists, and (B) indicates the case where a fault associated with case C2 exists. Figure 15A As shown in (D), in case C2, the pulse width of the pulse signal PLS1 becomes longer; therefore, the pulse width of the pulse signal PLSA generated by trigger 29 also becomes longer. Thus, as... Figure 15B As shown in (B), compared to the case where there is no fault ( Figure 15B Compared to (A), the right end of the histogram shifts to the right, which widens the distribution of the histogram.

[0169] When the right end of the histogram is shifted to the right, thereby widening the width of the histogram distribution, the diagnostic unit 26 diagnoses the fault of the light receiving unit P having a reduced current applied by the constant current source CUR.

[0170] (Case C3)

[0171] Next, we will describe the case where the voltage VN1 at node N1 is stuck at a high level (case C3).

[0172] Figure 16A This illustrates an operational example of the optical receiver P in scenario C3. At timing t51, the distance measurement controller 28 changes the control signal XACT from high to low. Figure 16A (B)). Additionally, the distance measurement controller 28 changes the control signal XACT from low to high at time t52 and from high to low at time t53. In case C3, the voltage VN1 at node N1 is held at a high level ( Figure 16A (C)). Therefore, inverter IV1 keeps the pulse signal PLS1 at a low level ( Figure 16A (D)).

[0173] Therefore, in case C3, the voltage VN1 at node N1 is held high; consequently, the pulse signal PLS1 remains low. Consequently, the pulse signal PLSA generated by flip-flop 29 also remains low.

[0174] Figure 16BAn operational example of histogram generator 23 in case D3 is shown, where (A) indicates the case without a fault, and (B) indicates the case with a fault associated with case C3. Figure 16A As shown in (D), in case C3, the pulse signal PLS1 remains low; therefore, the pulse signal PLSA generated by flip-flop 29 also remains low. Thus, as... Figure 16B As shown in (B), the frequency in the histogram is “0” across all warehouses.

[0175] In this manner, when the frequency in all compartments is "0", the diagnostic unit 26 diagnoses a fault in which the voltage VN1 at node N1 of the optical receiver P is stuck at a high level.

[0176] (Case C4)

[0177] Next, we will describe the case where the voltage VN1 at node N1 is stuck at a low level (case C4).

[0178] Figure 17A An operational example of the optical receiver P in case C4 is shown. At timing t61, the distance measurement controller 28 changes the control signal XACT from high level to low level. Figure 17A (B)). Additionally, the distance measurement controller 28 changes the control signal XACT from low to high at time t62 and from high to low at time t63. In case C4, the voltage VN1 at node N1 is held at a low level ( Figure 17A (C)). Therefore, inverter IV1 holds the pulse signal PLS1 at a high level ( Figure 17A (D)).

[0179] Therefore, in case C4, the voltage VN1 at node N1 is held low; therefore, the pulse signal PLS1 remains high. Consequently, the pulse signal PLSA generated by flip-flop 29 also remains high.

[0180] Figure 17B An operational example of histogram generator 23 in case C4 is shown, where (A) indicates the case where no fault exists, and (B) indicates the case where a fault associated with case C4 exists. Figure 17A As shown in (D), in case C4, the pulse signal PLS1 remains high; therefore, the pulse signal PLSA generated by flip-flop 29 also remains high. Thus, as Figure 17B As shown in (B), the frequency of "1" in all warehouses is in the histogram.

[0181] In this manner, when the frequency in all compartments is "1", the diagnostic unit 26 diagnoses a fault in which the voltage VN1 at node N1 of the optical receiver P is stuck at a low level.

[0182] (Case C5)

[0183] Next, we will describe the situation where the cathode of the photodiode PD is stuck at a low level or the anode and cathode of the photodiode are short-circuited to each other (case C5).

[0184] Figure 18 The selected optical receiver P and the trigger 29 that performs operation based on the pulse signal PLS1 generated by the selected optical receiver P are shown. For ease of explanation, [the following is a description of the process]. Figure 8 Same, Figure 18 The circuit is shown in a simplified manner.

[0185] Figure 19A An operational example of the optical receiver P in case C5 is shown, wherein (A) indicates the waveform of the control signal ENBIST, (B) indicates the waveform of the control signal XACT, (C) indicates the waveform of the voltage VN1 at node N1, and (D) indicates the waveform of the pulse signal PLS1 (pulse signal PLS).

[0186] In this self-diagnostic operation, the distance measurement controller 28 changes the control signal ENBIST to a low level. Figure 19A (A)). Therefore, in the light receiving section P, as Figure 18 As shown, transistor MP1 is turned on, and transistor MN1 is turned off. As a result, the cathode of photodiode PD is disconnected from the ground node and coupled to node N1. Furthermore, as... Figure 18 As shown, the distance measurement controller 28 changes the power supply voltage VNEG to be applied to the anode of the photodiode PD to "0V". It should be noted that in this example, the power supply voltage VNEG becomes "0V", but this is not limiting. Voltages that prevent the photodiode PD (single-photon avalanche diode) from operating can be applied. For example, in distance measurement operation where the power supply voltage VNEG is changed to "-20V", the power supply voltage VNEG can be changed to "-10V" in this self-diagnostic operation. Therefore, the photodiode PD is disconnected, and the anode and cathode of the photodiode PD are electrically insulated. In other words, in Figure 11 In the example, transistor MP1 is off; however, in Figure 18 In this example, transistor MP1 is turned on, and photodiode PD is turned off. Therefore, a self-diagnosis of the cathode of photodiode PD can be performed, as described below. It should be noted that even in this case, the same procedures as described above for C1 to C4 can be performed. Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is similar to the self-diagnostic operation in [the context of the original text].

[0187] At time t71, the distance measurement controller 28 changes the control signal XACT from high level to low level. Figure 19A (B)). Additionally, the distance measurement controller 28 changes the control signal XACT from low to high at time t72 and from high to low at time t73. In the absence of a fault, with Figure 12 Similarly, in case C5, the voltage VN1 at node N1 changes according to the control signal XACT, and the pulse signal PLS1 changes according to this voltage VN1. Meanwhile, in case C5, the cathode of the photodiode PD is stuck at a low level, or the anode and cathode of the photodiode PD are short-circuited. Therefore, the voltage VN1 remains at a low level. Figure 19A (C)). Therefore, inverter IV1 holds the pulse signal PLS1 at a high level ( Figure 19A (D)).

[0188] Figure 19B An operational example of histogram generator 23 in case C5 is shown, where (A) indicates the case where no fault exists, and (B) indicates the case where a fault associated with case C5 exists. Figure 19A As shown in (D), in case C5, the pulse signal PLS1 remains high; therefore, the pulse signal PLSA generated by flip-flop 29 also remains high. Thus, as Figure 19B As shown in (B), the frequency of all warehouses in the histogram is "1".

[0189] When the control signal ENBIST goes low and the power supply voltage VNEG becomes “0V”, and the frequency in all compartments is “1”, the diagnostic unit 26 diagnoses the optical receiver P for the following fault: the cathode of the photodiode PD is stuck at a low level or the cathode and anode of the photodiode PD are short-circuited to each other.

[0190] Therefore, the diagnostic unit 26 performs diagnostic processing on the faults in the optical receiver P described in cases C1 to C5. Then, the output unit 27 outputs the diagnostic processing result of the diagnostic unit 26 as a diagnostic result signal S2.

[0191] Therefore, in the optical detection system 1, a light receiver P is provided, which includes a photodiode PD; a first switch (transistor MP1) that couples the photodiode PD and node N1 when turned on; a second switch (transistor MN2) that applies a predetermined voltage (ground voltage in this example) to node N1 when turned on; and a signal generator (inverter IV1) that generates a pulse signal PLS1 based on the voltage VN1 at node N1. A detector (trigger unit 22 and histogram generator 23) is provided, which detects the timing of changes in the pulse signal PLS1 based on the pulse signal PLS1. An output unit 27 is configured to output a diagnostic result signal S2 corresponding to the detection result of the detector when the second switch (transistor MN2) is turned on. Therefore, in the optical detection system 1, it is possible to confirm whether the light receiver P should perform the desired operation when the transistor MN2 is turned on, which allows for self-diagnosis of the light receiver P.

[0192] In optical detection system 1, such as Figure 6 As shown, the distance measurement operation is performed during the distance measurement time period T1, and the self-diagnosis operation is performed during the blanking time period T2. Therefore, the distance measurement operation can continue and the light receiving unit P can be self-diagnosed.

[0193] [Effect]

[0194] As described above, in this embodiment, a light receiver is provided, which includes a photodiode, a first switch that couples the photodiode to node N1 when switched on, a second switch that applies a predetermined voltage to node N1 when switched on, and a signal generator that generates a pulse signal based on the voltage at node N1. The detector is configured to detect changes in the pulse signal based on the pulse signal timing. The output unit is configured to output a diagnostic result signal corresponding to the detector's detection result when the second switch is switched on. Thus, self-diagnosis is possible.

[0195] [Variation Example 1-1]

[0196] In the above embodiment, the trigger unit 22 samples the pulse signal PLS, and the histogram generator 23 generates a histogram based on the sampling result, but this is not limiting. The light detection system 1A according to this modified example will be described in detail below.

[0197] Compared with the light detection system 1 in the above embodiment ( Figure 1 The same applies to the optical detection system 1A, which includes a photodetector 20A.

[0198] Figure 20 An example configuration of the photodetector 20A is shown. The photodetector 20A includes a TDC (time-to-digital converter) unit 22A, a histogram generator 23A, and a diagnostic unit 26A.

[0199] The TDC unit 22A is configured to generate multiple timing codes TCODE by detecting the rising timing of multiple pulse signals PLS provided from the pixel array 21.

[0200] Figure 21 A configuration example of TDC unit 22A is shown. TDC unit 22A includes a plurality of TDCs 29A. The plurality of TDCs 29A are configured to correspond one-to-one with a plurality of pulse signals PLS provided from pixel array 21. Each of the plurality of TDCs 29A is configured to perform a counting operation based on clock signal CLK and latch the count value based on the rising edge of pulse signal PLS, thereby generating a timing code TCODE. TDC unit 22A then provides the timing code TCODE generated by the plurality of TDCs 29A to histogram generator 23A.

[0201] Histogram generator 23A is configured to generate a histogram indicating the generation timing of the pulse of pulse signal PLS based on each of the plurality of timing codes TCODEs provided from TDC unit 22A. Specifically, in distance measurement operation, photodetector 20A generates pulse signal PLS by detecting reflected light pulse L1, which causes histogram generator 23A to generate a histogram indicating the light reception timing in each of the plurality of light receiving units P based on the plurality of pulse signals PLSA. Furthermore, in self-diagnostic operation, photodetector 20A generates pulse signal PLS based on control signal XACT, which causes histogram generator 23A to generate a histogram indicating the generation timing of the pulse of pulse signal PLS based on control signal XACT in each of the plurality of light receiving units P based on the plurality of pulse signals PLSA.

[0202] The diagnostic unit 26A is configured to perform diagnostic processing on multiple light receiving units P in the pixel array 21 based on data from the generation timing of the pulse signal PLS based on the control signal XACT. Data is provided from the histogram generator 23A.

[0203] Here, TDC unit 22A and histogram generator 23A correspond to specific instances of the "detector" in this disclosure.

[0204] Figure 22 An operational example of the histogram generator 23A in a distance measurement operation is shown, wherein (A) indicates the histogram of a light receiver P obtained when a single light pulse L0 is emitted, and (B) indicates the histogram of a light receiver P obtained when multiple light pulses L0 are emitted.

[0205] The optical detection system 1A generates a timing code TCODE corresponding to the optical reception timing of the reflected optical pulse L1 by emitting a single optical pulse L0. Therefore, the histogram generator 23A generates... Figure 22The histogram shown in (A) is shown. In this example, light pulse L0 is emitted once; therefore, the frequency is "1".

[0206] The optical detection system 1A repeatedly emits light pulses L0 multiple times within a distance measurement time period T1. Therefore, the accumulated pulses... Figure 22 The data shown in (A). Therefore, histogram generator 23A generates... Figure 22 The histogram shown in (B) is used to calculate the light receiving timing, for example, based on the centroid position of the histogram.

[0207] Histogram generator 23A generates Figure 22 The histogram of each of the plurality of optical receivers P shown in (B) is used to calculate the optical receiving timing of each of the plurality of optical receivers P.

[0208] During self-diagnostic operation, the diagnostic unit 26A is able to diagnose faults such as those described above, including C3 to C5.

[0209] When the voltage VN1 at node N1 is held high (case C3), such as Figure 16A As shown, the optical receiver P holds the pulse signal PLS1 at a low level. Figure 16A (D)).

[0210] Figure 23 An operational example of histogram generator 23A is shown, where (A) indicates the case where no fault exists, and (B) indicates the case where a fault associated with case C3 exists. In the case where no fault exists, such as... Figure 23 As shown in (A), the frequency in the timing code TCODE corresponding to the rising timing of the pulse signal PLS is "1".

[0211] In case C3, the pulse signal PLS1 remains low; therefore, the pulse signal PLS has no rising edge and does not cause the TDC 29A to generate the timing code TCODE. Therefore, in the histogram, as shown... Figure 23 As shown in (B), the frequency in all compartments is "0". Thus, when the frequency in all compartments is "0", the diagnostic unit 26A diagnoses a malfunction in the optical receiver P.

[0212] When the voltage VN1 at node N1 is stuck at a low level (case C4), such as Figure 17A As shown, the optical receiver P holds the pulse signal PLS at a high level. Figure 17A (D)).

[0213] In case C4, pulse signal PLS1 remains high; therefore, pulse signal PLS has no rising edge and does not cause TDC 29A to generate timing code TCODE, as shown below. Figure 23 As shown in the diagram. Therefore, in the histogram, the frequency in all compartments is "0". Thus, when the frequency in all compartments is "0", the diagnostic unit 26A diagnoses a malfunction in the optical receiver P.

[0214] When the cathode of the photodiode PD is stuck at a low level or the anode and cathode of the photodiode PD are short-circuited (case C5), such as Figure 19A As shown, the optical receiver P holds the pulse signal PLS1 at a high level. Figure 19A (D)).

[0215] In case C5, the pulse signal PLS1 remains high; therefore, the pulse signal PLS has no rising edge and does not cause the TDC 29A to generate the timing code TCODE. Therefore, in the histogram, as shown... Figure 23 As shown in (B), the frequency in all compartments is "0". Thus, when the frequency in all compartments is "0", the diagnostic unit 26A diagnoses a malfunction in the optical receiver P.

[0216] [Variations 1-2]

[0217] In the above embodiment, during a blanking time period T2, multiple light receivers P are sequentially selected as detection targets from a plurality of light receivers P in the pixel array 21, but this is not limiting. Instead, for example, as... Figure 24 As shown, during multiple (two in this example) blanking time periods T2, multiple light receivers P can be sequentially selected as detection targets from multiple light receivers P in the pixel array 21. In this example, during the first blanking time period T2 of the two blanking time periods T2, multiple light receivers P are sequentially selected as detection targets from multiple light receivers P in the left half of the pixel array 21, and during the subsequent blanking time period T2, multiple light receivers P are sequentially selected as detection targets from multiple light receivers P in the right half of the pixel array 21. This allows for a shorter blanking time period T2, which in turn allows for an increase in the frequency of distance measurement operations, for example, per unit time.

[0218] [Variations 1-3]

[0219] In the above embodiments, during the distance measurement operation, such as Figure 8 As shown, transistor MN2 remains off, but this is not limiting. Instead, for example, as... Figure 25 As shown, the transistor MN2 can be turned on or off. Therefore, for example, as described below, in distance measurement operations, by turning on the transistor MN2 during the time period when the light-emitting unit 11 emits the light pulse L0, false detection by the photodetector 20 can be prevented.

[0220] Figure 26 An operational example of the light detection system 1 before and after the timing transition from the blanking time period T2 to the distance measurement time period T1 is shown, wherein (A) indicates the waveform of the control signal ENBIST, (B) indicates the waveform of the control signal XACT, (C) indicates the waveform of the light emitted from the light-emitting unit 11, (D) indicates the waveform of the light incident on the photodetector 20, (E) indicates the waveform of the voltage VN1 at node N1, and (F) indicates the waveform of the pulse signal PLS1.

[0221] During the blanking time period T2, the optical detection system 1 performs self-diagnosis. In this example, the distance measurement controller 28 changes the control signal XACT to a high level during the time period from timing t81 to timing t82, and the voltage VN1 at node N1 and the pulse signal PLS1 change according to the control signal XACT. Figure 26 (B), (E) and (F)).

[0222] Then, at time t83, the distance measurement controller 28 changes the control signal ENBIST from high level to low level. Figure 26 (A) Therefore, transistor MP1 is turned on, transistor MN1 is turned off, and the cathode of photodiode PD is disconnected from the ground node and coupled to node N1.

[0223] Furthermore, at this timing t83, the distance measurement controller 28 changes the control signal XACT from low to high. Figure 26 (B) Therefore, transistor MN2 is turned on, and transistor MP3 is turned off. Thus, node N1 is disconnected from the constant current source CUR and grounded. Voltage VN1 changes from high to low in this way ( Figure 26 (E)), which causes inverter IV1 to change the pulse signal PLS1 from low level to high level. Figure 26 (F)).

[0224] Then, at time t84, the blanking period T2 ends, and the distance measurement period T1 begins. At this time t84, the light-emitting unit 11 emits a light pulse L0 based on a command from the controller 14. Figure 26 (C)). At this time, the control signal XACT is at a high level ( Figure 26 (B)); therefore, transistor MN2 is turned on. Consequently, the voltage VN1 at node N1 remains low.

[0225] Then, at the subsequent timing t85, the distance measurement controller 28 changes the control signal XACT from high level to low level. Figure 26(B) Therefore, transistor MP3 is turned on, and transistor MN2 is turned off. As a result, node N1 is disconnected from the ground node and connected to the constant current source CUR. Current flows into node N1 through the constant current source CUR to increase the voltage VN1 at node N1. Figure 26 (E)). Then, at time t86, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high to low. Figure 26 (F)).

[0226] Subsequent operations are similar to the above embodiments ( Figure 9 The operations in ).

[0227] Therefore, in this modified example, the transistor MN2 is turned on during the time period when the light-emitting part 11 emits the light pulse L0. Thus, for example, even if the light pulse L0 emitted from the light-emitting part 11 is reflected by the inner wall of the housing of the light detection system 1 and enters the photodetector 20, the photodetector 20 will not generate a pulse signal PLS1 based on that light. As a result, the photodetector 20 is able to prevent false detection.

[0228] In this example, such as Figure 25 As shown, a single transistor MN2 is used, but this is not limiting. (As...) Figure 27 As shown, in addition to transistor MN2, transistor MN3 can be provided to be turned on or off during the distance measurement time period T1.

[0229] [Variations 1-4]

[0230] In the above embodiments, the light receivers P are coupled via a daisy-chain coupling, but this is not limiting. Instead, for example, multiple triggers 29 can be provided, each corresponding one-to-one with a plurality of light receivers P in the pixel array 21, and the light receivers P can be coupled one-to-one with each trigger 29. This is similar to the light detection system 1 according to the above embodiments. Figure 1 Similar to the light detection system 1D according to this modification, it includes a light detector 20D. The light detector 20D is similar to that according to the above embodiment. Figure 2 Similarly, the photodetector 20D includes a pixel array 21D and a trigger unit 22D. The pixel array 21D includes a plurality of light receiving units P arranged in a matrix. The trigger unit 22D includes a plurality of triggers 29 corresponding to the plurality of light receiving units P.

[0231] Figure 28An example configuration of the light receiver P and trigger 29 according to this modification is shown. The light receiver P includes a photodiode PD, transistors MN1, MP1, MP2, MP3 and MN2, and an inverter IV1. The light receiver P according to this modification is similar to the light receiver P according to the above embodiment, which omits the AND circuit AND1 and / or the OR circuit OR1. Figure 3 Corresponding to this modification, in the optical receiver P, the inverter IV1 is configured to generate the inverted voltage of the voltage VN1 at node N1, thereby generating a pulse signal PLS. The trigger 29 operates based on the pulse signal PLS output from the inverter IV1.

[0232] Figure 29 An example of mounting a photodetector 20D is shown. In this example, the photodetector 20D is formed on two semiconductor substrates 101 and 102. Semiconductor substrate 101 is disposed on the light-receiving surface side of the photodetector 20D, and semiconductor substrate 102 is disposed on the side opposite to the light-receiving surface of the photodetector 20D. Semiconductor substrates 101 and 102 are stacked on top of each other. The wiring of semiconductor substrate 101 and the wiring of semiconductor substrate 102 are coupled to each other via wiring 103. Wiring 103 can be metal-based, for example, using Cu-Cu bonding or bump bonding. Figure 28 The photodiode PD of the light receiver P shown is disposed on the semiconductor substrate 101, and the components of the light receiver P other than the photodiode PD and the trigger 29 coupled to the light receiver P are disposed on the semiconductor substrate 102. The photodiode PD of the light receiver P, the components of the light receiver P other than the photodiode PD, and the trigger 29 coupled to the light receiver P are disposed in corresponding regions of the semiconductor substrates 101 and 102.

[0233] [Other variations]

[0234] Furthermore, two or more of these variations can be combined.

[0235] <2. Second Embodiment>

[0236] Next, the optical detection system 2 according to the second embodiment will be described. This embodiment is configured to perform self-diagnosis on a plurality of optical receivers P uniformly. It should be noted that components that are substantially the same as those in the optical detection system 1 according to the first embodiment described above are indicated by the same reference numerals, and their descriptions are appropriately omitted.

[0237] The optical detection system 2 according to this embodiment and the optical detection system 1 according to the first embodiment ( Figure 1 Similarly, it includes a photodetector 30.

[0238] Figure 30An example configuration of the photodetector 30 is shown. The photodetector 30 includes a trigger unit 32, a histogram generator 33, and a diagnostic unit 36.

[0239] Figure 31 An example configuration of the trigger unit 32 is shown. The trigger unit 32 includes a plurality of triggers 29, a plurality of AND circuits 37, and a plurality of triggers 38.

[0240] Each of the multiple AND circuits 37 is configured to perform a logical AND operation on four pulse signals PLS. It should be noted that in this example, AND circuit 37 performs a logical AND operation on four pulse signals PLS, but this is not limiting. For example, AND circuit 37 may perform a logical AND operation on two or three pulse signals PLS, or it may perform a logical AND operation on five or more pulse signals PLS.

[0241] Multiple flip-flops 38 are provided, each corresponding one-to-one with a plurality of AND circuits 37. Each of the multiple flip-flops 38 is configured to sample the output signal of the corresponding AND circuit 37 based on the clock signal CLK to generate a pulse signal PLSB. This pulse signal PLSB is used for diagnostic processing operations. That is, the optical detection system 2 uniformly diagnoses the four optical receivers P during the diagnostic processing operations.

[0242] In distance measurement operation, histogram generator 33 generates a histogram based on multiple pulse signals PLSA, indicating the optical reception timing of each of the multiple optical receivers P. Furthermore, in self-diagnostic operation, histogram generator 33 generates a histogram based on multiple pulse signals PLSB, which indicates the generation timing of the pulses of the pulse signal PLS based on the control signal XACT in each of the multiple optical receivers P.

[0243] The diagnostic unit 36 ​​is configured to perform diagnostic processing on multiple light receivers P in the pixel array 21 based on pulse generation timing data of the pulse signal PLS. The pulse generation timing of the pulse signal PLS is based on the control signal XACT provided from the histogram generator 33. This diagnostic unit 36 ​​performs diagnostic processing on multiple light receivers P by uniformly diagnosing four light receivers P.

[0244] Here, the trigger unit 32 and the histogram generator 33 correspond to a specific instance of the "detector" in this disclosure.

[0245] Compared with the light detection system 1 according to the first embodiment ( Figure 6 Similar to the first embodiment, the light detection system 2 performs distance measurement during the distance measurement time period T1 and performs self-diagnosis on the plurality of light receiving units P in the pixel array 21 during the blanking time period T2. The distance measurement operation in the light detection system 2 is the same as that in the light detection system 1 according to the first embodiment. Figures 7 to 10 )resemblance.

[0246] During self-diagnostic operation, the diagnostic unit 36 ​​is able to diagnose faults such as those described above, C1 and C3.

[0247] (Case C1)

[0248] When the current applied by the constant current source CUR is large (case C1), such as Figure 14A As shown, compared to the case without a fault, the pulse width of the pulse signal PLS1 becomes shorter. Figure 14A (D)).

[0249] Figure 32 An operational example of the histogram generator 33 is shown, where (A) indicates the case where there is no fault in any of the four optical receivers P, and (B) indicates the case where a fault associated with case C1 exists in at least one of the four optical receivers P. In the case where there is no fault in any of the four optical receivers P, the four pulse signals PLS generated by the four optical receivers P have substantially the same waveform. The AND circuit 37 of the trigger unit 32 obtains the logical AND of the pulse signals PLS provided from the four optical receivers P. The output signal of the AND circuit 37 has a waveform substantially the same as these four pulse signals PLS. Therefore, as... Figure 32 As shown in (A), a histogram with a frequency of "1" is obtained. The left end of the histogram corresponds to the pulse generation timing of the pulse signal PLS, and the width of the histogram distribution corresponds to the pulse width of the pulse signal PLS.

[0250] In the case where the fault associated with condition C1 exists in at least one of the four optical receivers P, such as Figure 14A As shown, in the faulty optical receiver P, the timing of the pulse end of the pulse signal PLS1 becomes earlier, which shortens the pulse width. Figure 14A (D)). The AND circuit 37 of the trigger section 32 obtains the logical AND of the pulse signals PLS provided by the four optical receivers P. The output signal of the AND circuit 37 becomes a signal with a shorter pulse width, similar to the pulse signal PLS1 generated by the faulty optical receiver P. As a result, as Figure 32 As shown in (B), compared to the case where there is no fault ( Figure 32 Compared to (A), the right end of the histogram shifts to the left, which narrows the width of the histogram distribution.

[0251] When the right end of the histogram is moved to the left end, thus narrowing the width of the histogram distribution, the diagnostic unit 36 ​​diagnoses at least one of the four optical receivers P as having a fault where the current applied by the constant current source CUR increases.

[0252] (Case C3)

[0253] When the voltage VN1 at node N1 is held high (case C3), such as Figure 16A As shown, the optical receiver P holds the pulse signal PLS1 at a low level. Figure 16A (D)).

[0254] Figure 33 An operational example of histogram generator 33 is shown, wherein (A) indicates the case where there is no fault in all four optical receivers P, and (B) indicates the case where a fault associated with case C3 exists in at least one of the four optical receivers P. In the case where the fault associated with case C3 exists in at least one of the four optical receivers P, in the optical receiver P with the fault, as... Figure 16A As shown, the pulse signal PLS1 remains at a low level. Figure 16A (D)). The AND circuit 37 of the flip-flop section 32 obtains the logic AND of the pulse signals provided from the four optical receivers P. Therefore, the output signal of the AND circuit 37 remains at a low level. Therefore, as Figure 33 As shown in (B), the frequency in the histogram is “0” across all warehouses.

[0255] In the case where the frequency in all compartments is “0” in this manner, the diagnostic unit 36 ​​diagnoses at least one of the four optical receivers P as having a fault where the voltage VN1 at node N1 is stuck at a high level.

[0256] Therefore, in the optical detection system 3, a composite pulse signal (pulse signal PLSB) is generated based on the pulse signals PLS generated by multiple (four in this example) optical receivers P, and diagnostic processing can be performed by detecting the timing of changes in the composite pulse signal.

[0257] As described above, in this embodiment, a synthesized pulse signal is generated based on pulse signals generated by multiple optical receivers, and the timing of changes in the synthesized pulse signal is detected, which enables diagnostic processing to be performed.

[0258] [Variation Example 2-1]

[0259] In the above embodiments, such as Figure 31 As shown, the logical AND of the four pulse signals PLS is obtained by circuit 37, thereby performing a unified self-diagnosis on the four optical receivers P, but this is not limiting. Alternatively, the logical OR of the four pulse signals PLS can be used to perform a unified self-diagnosis on the four optical receivers P. The optical detection system 2A according to this modified example will be described in detail below.

[0260] The optical detection system 2A according to this embodiment and the optical detection system 1 according to the first embodiment ( Figure 1 Similarly, it includes a photodetector 30A. This is similar to the photodetector 30A according to the second embodiment. Figure 30 Like the photodetector 30A, the photodetector 30A includes a trigger section 32A and a diagnostic section 36A.

[0261] Figure 34 An example configuration of the trigger section 32A is shown. The trigger section 32A includes multiple OR circuits 37A.

[0262] Each of the multiple OR circuits 37A is configured to perform a logical OR of four pulse signals PLS. Each of the multiple flip-flops 38 samples the output signal of the corresponding OR circuit 37A based on the clock signal CLK, thereby generating the pulse signal PLSB.

[0263] The diagnostic unit 36A is configured to perform diagnostic processing on multiple light receivers P in the pixel array 21 based on pulse generation timing data of the pulse signal PLS, where the pulse generation timing of the pulse signal PLS is based on the control signal XACT provided from the histogram generator 33. This diagnostic unit 36A performs diagnostic processing on multiple light receivers P by uniformly diagnosing four light receivers P.

[0264] During self-diagnostic operation, the diagnostic unit 36A is able to diagnose faults such as those described above, including C2, C4, and C5.

[0265] When the current applied by the constant current source CUR is small (case C2), such as Figure 15A As shown, the pulse width of pulse signal PLS1 becomes longer than in the case where there is no fault. Figure 15A (D)).

[0266] Figure 35 An operational example of the histogram generator 33A is shown, wherein (A) indicates the case where there is no fault in all four optical receivers P, and (B) indicates the case where a fault associated with case C2 exists in at least one of the four optical receivers P. In the case where a fault associated with case C2 exists in at least one of the four optical receivers P, in the optical receiver P with the fault, as... Figure 15A As shown, the timing of the pulse end of the pulse signal PLS1 becomes later, which makes the pulse width longer. Figure 15A (D)). The OR circuit 37A of the trigger section 32A calculates the logical OR of the pulse signals PLS provided from the four optical receivers P. Therefore, the output signal of the OR circuit 37A is a long pulse width signal similar to the pulse signal PLS1 generated by the faulty optical receiver P. As a result, as Figure 35 As shown in (B), compared to the case where there is no fault ( Figure 35 Compared to (A), the right end of the histogram shifts to the right, which widens the distribution of the histogram.

[0267] When the right end of the histogram is moved to the right, thereby widening the width of the histogram distribution, the diagnostic unit 36A diagnoses a fault in at least one of the four optical receivers P where the current applied by the constant current source CUR is reduced.

[0268] When the voltage VN1 at node N1 is stuck at a low level (case C4), such as Figure 17A As shown, the optical receiver P holds the pulse signal PLS1 at a high level. Figure 17A (D)).

[0269] Figure 36 An operational example of histogram generator 33A is shown, wherein (A) indicates that there is no fault in all of the four optical receivers P, and (B) indicates that there is a fault associated with case C4 in at least one of the four optical receivers P.

[0270] In the case where the fault associated with condition C4 exists in at least one of the four optical receivers P, in the optical receiver P with the fault, such as Figure 17A As shown, the pulse signal PLS1 remains at a high level. Figure 17A (D)). The OR circuit 37A of the trigger section 32A calculates the logic OR of the pulse signals PLS provided from the four optical receivers P. Therefore, the output signal of the OR circuit 37A remains at a high level. Therefore, as Figure 36 As shown in (B), the frequency of all warehouses in the histogram is "1".

[0271] In this manner, when the frequency in all compartments is "1", the diagnostic unit 36A diagnoses a fault in which at least one of the four optical receivers P has a voltage VN1 at node N1 stuck at a low level.

[0272] When the cathode of the photodiode PD is stuck at a low level or the anode and cathode are short-circuited (case C5), as shown in Figure 19, the light receiver P holds the pulse signal PLS1 at a high level. Figure 19A (D)). It should be noted that, in the case of performing the self-diagnosis associated with case C5, as described above, the control signal ENBIST becomes low, and the power supply voltage VNEG applied to the anode of the photodiode PD becomes "0V". Therefore, in the case where the fault associated with case C5 exists in at least one of the four photoreceiving sections P, as in case C4 ( Figure 36 In the histogram, the frequency of all warehouses is "1".

[0273] When the control signal ENBIST goes low and the power supply voltage VNEG goes "0V", and the frequency in all compartments is "1", the diagnostic unit 36A diagnoses a fault in which at least one of the four photoreceivers P has a photodiode PD whose cathode is stuck at a low level or whose cathode and anode are short-circuited to each other.

[0274] [Variation Example 2-2]

[0275] In the above embodiments, triggers 29 and 38 are provided, but this is not limiting. Instead, for example, as... Figure 37 As shown, a Time Control Unit (TDC) can be provided, such as in Variation 1-1. The TDC unit 32B includes a plurality of TDCs 29B, a plurality of AND circuits 37, and a plurality of TDCs 38B. Each of the plurality of TDCs 29B is configured to perform a counting operation based on a clock signal CLK and latch the count value based on the rising edge of a pulse signal PLS, thereby generating a time code TCODE. Each of the plurality of TDCs 38B is configured to perform a counting operation based on a clock signal CLK and latch the count value based on the rising edge of the output signal of the AND circuit 37, thereby generating a time code TCODE.

[0276] [Variations 2-3]

[0277] In the above embodiments, the light receivers P are coupled via a daisy-chain coupling, but this is not limiting. Instead, as in variations 1-4, for example, multiple triggers 29 can be provided, each corresponding one-to-one with a plurality of light receivers P in the pixel array 21, and the light receivers P can be coupled one-to-one with each trigger 29. The light detection system 2C according to this variation, like the light detection system 2 according to the second embodiment, includes a photodetector 30C. The photodetector 30C according to the second embodiment... Figure 30 Similarly, the photodetector 30C includes a pixel array 21C and a trigger unit 32C. The pixel array 21C includes a plurality of light receiving units P disposed in a matrix. The trigger unit 32C includes a plurality of triggers 29, a plurality of AND circuits 37, and a plurality of triggers 38 corresponding to the plurality of light receiving units P.

[0278] Figure 38 An example configuration of four light receivers P, four flip-flops 29, circuit 37, and flip-flop 38 according to this modification is shown. Each light receiver P includes a photodiode PD, transistors MN1, MP1, MP2, MP3, and MN2, and an inverter IV1. The light receivers P according to this modification correspond to the light receiver P according to the above embodiment. Figure 3The AND circuit AND1 and OR circuit OR1 are omitted from the optical receiver P. In each optical receiver P according to this modification, the inverter IV1 is configured to generate the inverted voltage of the voltage VN1 at node N1, thereby generating a pulse signal PLS. Each of the four flip-flops 29 operates based on the pulse signal PLS output from the inverter IV1 of the corresponding optical receiver P. The AND circuit 37 obtains the logical AND of the four pulse signals PLS. The flip-flop 38 operates based on the output signal of the AND circuit 37. It should be noted that in this example, a flip-flop section 32C including multiple AND circuits 37 is used, but this is not limiting. Figure 39 As shown, a flip-flop section 32D including multiple OR circuits 37A can be used.

[0279] In addition, Figure 38 In this example, the four triggers 29 are configured to correspond one-to-one with the four optical receivers P, but this is not limiting. For example, with Figure 40 Similar to the trigger section 32E shown, a trigger 29 can be configured corresponding to each of the four optical receivers P. The trigger section 32E includes an OR circuit 37E, an AND circuit 37F, a selector 38E, and a trigger 29. The OR circuit 37E is configured to perform a logical OR of the four pulse signals PLS. The AND circuit 37F is configured to perform a logical AND of the four pulse signals PLS. The selector 38E is configured to select the output signal of the OR circuit 37E during distance measurement operation and to select the output signal of the AND circuit 37F during self-diagnostic operation. The trigger 29 is configured to sample the output signal of the selector 38E based on the rising edge of the clock signal CLK, thereby generating a pulse signal PLSA. During distance measurement operation, the OR circuit 37E performs a logical OR of the four pulse signals PLS, and the trigger 29 generates the pulse signal PLSA based on the output signal of the OR circuit 37E. Therefore, the AND circuit... Figure 38 Compared to the example in the previous example, the number of flip-flops 29 can be reduced, which allows for a reduction in circuit area and power consumption.

[0280] Similarly, in Figure 39 In the example, the four triggers 29 are configured to correspond one-to-one with the four optical receivers P, but this is not limiting. For example, with Figure 41 Similar to the trigger section 32F shown, a trigger 29 can be configured corresponding to each of the four optical receivers P. The trigger section 32F includes an OR circuit 37E and a trigger 29. The OR circuit 37E is configured to perform a logical OR operation on four pulse signals PLS. The trigger 29 is configured to sample the output signal of the OR circuit 37E based on the rising edge of the clock signal CLK, thereby generating the pulse signal PLSA. In this example, the OR circuit 37E is used for both distance measurement and self-diagnostic operations. Therefore, with... Figure 39Compared to the example in the previous example, the number of flip-flops 29 can be reduced, which allows for a reduction in circuit area and power consumption.

[0281] The photodetector according to this modification can, for example, be formed on two semiconductor substrates, and is compatible with the photodetector 20D according to modifications 1-4. Figure 29 )Same.

[0282] <3. Third Embodiment>

[0283] Next, the optical detection system 3 according to the third embodiment will be described. This embodiment is configured to perform a unified self-diagnosis of multiple optical receivers P using an adder. It should be noted that components that are substantially the same as those in the optical detection system 1 according to the first embodiment described above are indicated by the same reference numerals, and their descriptions are appropriately omitted.

[0284] The optical detection system 3 according to this embodiment and the optical detection system 1 according to the first embodiment ( Figure 1 Similarly, it includes a photodetector 40.

[0285] Figure 42 An example configuration of the photodetector 40 is shown. The photodetector 40 includes a trigger unit 42, a histogram generator 43, and a diagnostic unit 46.

[0286] Figure 43 An example configuration of the trigger unit 42 is shown. The trigger unit 42 includes a plurality of triggers 29 and a plurality of adders 47.

[0287] Each of the multiple adders 47 is configured to perform addition based on four pulse signals PLSA, thereby generating a code CODE. Specifically, each adder 47 generates a code CODE indicating the number of signals at high levels in the four pulse signals PLSA. The number of signals at high levels can be 0 or greater and 4 or less. Thus, the adder 47 generates a 3-bit code CODE.

[0288] Figure 44An example configuration of adder 47 is shown. Adder 47 includes half adders 51 and 52 and full adders 53 and 54. Half adder 51 has input terminals A and B that receive two of the four pulse signals PLSA, an output terminal S coupled to input terminal A of full adder 54, and a carry output terminal Cout coupled to input terminal A of full adder 53. Half adder 52 has input terminals A and B that receive the remaining two of the four pulse signals PLSA, an output terminal S coupled to input terminal B of full adder 54, and a carry output terminal Cout coupled to input terminal B of full adder 53. Full adder 53 has an input terminal A coupled to the carry output terminal Cout of half adder 51, an input terminal B coupled to the carry output terminal Cout of half adder 52, and a carry input terminal Cin coupled to the carry output terminal Cout of full adder 54. Full adder 53 outputs the signal of bit B2 of indicator code CODE from the carry output terminal Cout, and outputs the signal of bit B1 of indicator code CODE from the output terminal S. Input terminal A of full adder 54 is coupled to the output terminal S of half adder 51, input terminal B is coupled to the output terminal S of half adder 52, the carry input terminal Cin is grounded, and the carry output terminal Cout is coupled to the carry input terminal Cin of full adder 53. Full adder 54 outputs the signal of bit B0 of indicator code CODE from the output terminal S. Bit B2 is the most significant bit of code CODE, and bit B0 is the least significant bit of code CODE.

[0289] Histogram generator 43 ( Figure 42 In distance measurement operations, a histogram is generated based on multiple pulse signals PLSA to indicate the optical reception timing of each of the multiple optical receivers P. Furthermore, in self-diagnostic operations, the histogram generator 43 generates a histogram based on a code CODE, which indicates the generation timing of the pulses of the pulse signal PLS based on the control signal XACT in each of the multiple optical receivers P.

[0290] The diagnostic unit 46 is configured to perform diagnostic processing on multiple light receivers P in the pixel array 21 based on the pulse generation timing data of the pulse signal PLS. The pulse generation timing of the pulse signal PLS is based on the control signal XACT provided from the histogram generator 43. This diagnostic unit 46 performs diagnostic processing on multiple light receivers P by uniformly diagnosing four light receivers P.

[0291] Here, the trigger unit 42 and the histogram generator 43 correspond to a specific instance of the "detector" in this disclosure.

[0292] Compared with the light detection system 1 according to the first embodiment ( Figure 6Similar to the first embodiment, the light detection system 3 performs distance measurement during the distance measurement time period T1 and performs self-diagnosis on the plurality of light receivers P in the pixel array 21 during the blanking time period T2. The distance measurement operation of the light detection system 3 is the same as that of the light detection system 1 according to the first embodiment. Figures 7 to 10 )same.

[0293] During self-diagnostic operation, the diagnostic unit 36 ​​is able to diagnose faults such as those described above, C1 to C5.

[0294] (Case C1)

[0295] When the current applied by the constant current source CUR is large (case C1), such as Figure 14A As shown, compared to the case without a fault, the pulse width of the pulse signal PLS1 becomes shorter. Figure 14A (D)).

[0296] Figure 45 An operational example of the histogram generator 43 is shown, wherein (A) indicates the case where there is no fault in all four optical receivers P, and (B) indicates the case where there is a fault associated with case C1 in one of the four optical receivers P. In the case where there is no fault in all four optical receivers P, the pulse widths of the four pulse signals PLS are the same; therefore, around the pulse of the pulse signal PLS, the value indicated by the code CODE becomes "0", "4", "4", "4", "4", and "0" or an instance. Therefore, as... Figure 45 As shown in (A), a flat histogram with a frequency of "4" is obtained. The left end of the histogram corresponds to the pulse generation timing of the pulse signal PLS, and the width of the histogram distribution corresponds to the pulse width of the pulse signal PLS.

[0297] If the fault associated with case C1 exists in one of the four optical receivers P, then in the optical receiver P with the fault, as follows: Figure 14A As shown, the timing of the pulse end of the pulse signal PLS1 becomes earlier, which shortens the pulse width. Figure 14A (D) Therefore, for example, around the pulse of the pulse signal PLS, the value indicated by the code CODE changes to "0", "4", "4", "4", "3", and "0". As a result, as Figure 45 As shown in (B), compared to the case without a fault, a portion of the right end of the histogram is missing. Figure 45 (A)).

[0298] In the event that a portion of the right end of the histogram is missing in this manner, the diagnostic unit 46 diagnoses at least one of the four optical receivers P for a fault caused by an increase in current applied by the constant current source CUR.

[0299] (Case C2)

[0300] When the current applied by the constant current source CUR is small (case C2), such as Figure 15A As shown, compared to the case without faults ( Figure 15A (D)), the pulse width of the pulse signal PLS1 becomes longer.

[0301] Figure 46 An operational example of the histogram generator 43 is shown, wherein (A) indicates the case where there is no fault in all four optical receivers P, and (B) indicates the case where a fault associated with case C2 exists in one of the four optical receivers P. In the case where a fault associated with case C2 exists in one of the four optical receivers P, in the optical receiver P with the fault, as... Figure 15A As shown, the timing of the pulse end of pulse signal PLS1 becomes later, which makes the pulse width of pulse signal PLS1 longer. Figure 15A (D)). Therefore, for example, around the pulse of the pulse signal PLS, the value indicated by the code CODE changes to "0", "4", "4", "4", "4", "1", and "0". As a result, Figure 46 As shown in (B), compared to the case without a fault, a portion of the right end of the histogram extends ( Figure 46 (A)).

[0302] If a portion of the right end of the histogram extends in this manner, the diagnostic unit 46 will diagnose at least one of the four optical receivers P as having a fault such as a reduction in current applied by the constant current source CUR.

[0303] (Case C3)

[0304] When the voltage VN1 at node N1 is held high (case C3), such as Figure 16A As shown, the optical receiver P holds the pulse signal PLS1 at a low level. Figure 16A (D)).

[0305] Figure 47 An operational example of the histogram generator 43 is shown, wherein (A) indicates the case where there is no fault in all four optical receivers P, and (B) indicates the case where a fault associated with condition C3 exists in one of the four optical receivers P. In the case where a fault associated with condition C3 exists in one of the four optical receivers P, in the optical receiver P with the fault, as... Figure 16A As shown, the pulse signal PLS1 remains at a low level. Figure 16A(D) Therefore, for example, around the pulse of the pulse signal PLS, the value indicated by the code CODE changes to "0", "3", "3", "3" and "0". As a result, as Figure 47 As shown in (B), compared to the case where there is no fault ( Figure 47 Compared to (A), the height of the histogram becomes lower.

[0306] When the height of the histogram decreases, the diagnostic unit 46 diagnoses at least one of the four optical receivers P as having a fault where the voltage VN1 at node N1 is stuck at a high level.

[0307] (Case C4)

[0308] When the voltage VN1 at node N1 is stuck at a low level (case C4), such as Figure 17A As shown, the optical receiver P holds the pulse signal PLS1 at a high level. Figure 17A (D)).

[0309] Figure 48 An operational example of the histogram generator 43 is shown, wherein (A) indicates the case where there is no fault in all four optical receivers P, and (B) indicates the case where a fault associated with case C4 exists in one of the four optical receivers P. In the case where a fault associated with case C4 exists in one of the four optical receivers P, in the optical receiver P with the fault, as... Figure 17A As shown, the pulse signal PLS1 remains at a high level. Figure 17A (D)). Therefore, for example, the value indicated by the code becomes "1", ..., "1", "4", "4", "4", "4", "1" and .... Therefore, as Figure 48 As shown in (B), in the histogram, the frequency of "1" or greater is in all warehouses.

[0310] In this manner, if the frequency in all compartments is 1 or greater, the diagnostic unit 46 will diagnose at least one of the four optical receivers P as having a fault where the voltage VN1 at node N1 is stuck at a high level.

[0311] (Case C5)

[0312] When the cathode of the photodiode PD is stuck at a low level or the anode and cathode of the photodiode PD are short-circuited (case C5), such as Figure 19A As shown, the optical receiver P holds the pulse signal PLS1 at a high level. Figure 19A(D)). It should be noted that when performing the self-diagnostic procedure associated with case C5, as described above, for example, the control signal ENBIST goes low, and the power supply voltage VNEG applied to the anode of the photodiode PD becomes “0V”. Therefore, in the case where the fault associated with case C5 exists in one of the four photoreceiving sections P, the frequency in all sections is “1” or greater in the histogram, as in case C4. Figure 48 ).

[0313] When the control signal ENBIST goes low and the power supply voltage VNEG becomes “0V”, and the frequency in all compartments is “1” or greater, the diagnostic unit 46 diagnoses at least one of the four photoreceiving units P with the following fault: the cathode of the photodiode PD is stuck at a low level or the cathode and anode of the photodiode PD are short-circuited to each other.

[0314] Therefore, in the optical detection system 3, addition processing is performed based on the pulse signals PLS generated by each of the multiple (four in this example) optical receivers P to generate a code CODE, and the timing of changing the code CODE is detected, which enables diagnostic processing to be performed.

[0315] As described above, in this embodiment, addition processing is performed based on the pulse signal generated by each of the plurality of optical receivers to generate a code, and the timing of the code change is detected, which enables diagnostic processing to be performed.

[0316] [Variation Example 3-1]

[0317] In the above embodiment, trigger 29 is provided, but this is not limiting. Instead, as in variant 2-2, TDC can be provided.

[0318] [Variation Example 3-2]

[0319] In the above embodiments, the optical receiver P is coupled via a daisy-chain connection, but this is not limiting. Instead, for example, as in variations 2-3, the optical receiver P can be coupled one-to-one to the trigger 29.

[0320] <4. Fourth Embodiment>

[0321] Next, the light detection system 4 according to the fourth embodiment will be described. In this embodiment, the configuration of the light receiver P is the same as that of the light receiver P according to the first embodiment. Figure 3 The configurations differ. It should be noted that components substantially the same as those in the optical detection system 1 according to the first embodiment described above are indicated by the same reference numerals, and their descriptions are appropriately omitted.

[0322] As with the light detection system 1 according to the first embodiment ( Figure 1According to this embodiment, the light detection system 4 includes a light detector 60.

[0323] Figure 49 An example configuration of the light detector 60 is shown. The light detector 60 includes a pixel array 61 and a diagnostic unit 66.

[0324] The pixel array 61 includes a plurality of light receivers P arranged in a matrix. Each light receiver P is configured to detect light, thereby generating a pulse signal having a pulse corresponding to the detected light. In addition, when the light detection system 1 performs self-diagnostic operation, the light receiver P can generate the pulse signal based on the provided control signals (control signals ENBIST, XACT, XENAR described later).

[0325] Figure 50 An example configuration of the optical receiver P is shown. The optical receiver P includes a photodiode PD, transistors MN1, MP1, MP2, MP3 and MN2, an inverter IV1, a NOR circuit NOR1, a NAND circuit NAND1, a delay circuit DEL1, a transistor MP4, an AND circuit AND1 and an OR circuit OR1. Transistor MP4 is a P-type MOS transistor.

[0326] The NOR circuit NOR1 is configured to determine the NOR of the control signal XACT and the control signal XENAR. The NOR circuit NOR1 is supplied with a power supply voltage VDDH.

[0327] The NAND circuit NAND1 is configured to perform a NAND operation on the output signal of the NOR circuit NOR1 and the pulse signal PLS1. The NAND circuit NAND1 is supplied with a power supply voltage VDDH.

[0328] Delay circuit DEL1 is configured to delay the output signal of NAND circuit NAND1. Delay circuit DEL1 is supplied with a power supply voltage VDDH.

[0329] The transistor MP4 has a gate that supplies the output signal of the delay circuit DEL1, a source that supplies the power supply voltage VDDH, and a drain that is coupled to node N1.

[0330] Diagnostic Department 66 ( Figure 49 The system is configured to perform diagnostic processing on multiple light receivers P in the pixel array 61 based on pulse generation timing data from the pulse signal PLS based on the control signal XACT. Data is provided from the histogram generator 23.

[0331] The distance measurement controller 68 is configured to control the operation of the pixel array 61, the trigger unit 22, the histogram generator 23, the distance calculator 24 and the diagnostic unit 66 based on instructions from the controller 14, thereby controlling the operation of the photodetector 60.

[0332] Figure 51 An operational example of the light receiver P in distance measurement is shown, wherein (A) indicates the waveform of the control signal ENBIST, (B) indicates the waveform of the control signal XACT, (C) indicates the waveform of the control signal XENAR, (D) indicates the waveform of the light emitted from the light-emitting unit 11, (E) indicates the waveform of the light incident on the photodetector 60, (F) indicates the waveform of the voltage AR at the gate of transistor MP4, (G) indicates the waveform of the voltage VN1 at node N1, and (H) indicates the waveform of the pulse signal PLS1 (pulse signal PLS). Figure 51 The waveforms of the clock signal CLK and the pulse signal PLSA are not shown in the diagram, but they are similar to those in the first embodiment described above. Figure 9 The waveforms are similar to those in the original text.

[0333] During distance measurement operation, the distance measurement controller 68 changes the control signals ENBIST and XACT to a low level. Figure 51 (A) and (B)). Therefore, in the light receiver P, transistors MP1 and MP3 are turned on, and transistors MN1 and MN2 are turned off. As a result, the cathode of the photodiode PD is coupled to node N1, and the constant current source CUR (transistor MP2) is coupled to node N1. In addition, the distance measurement controller 68 changes the control signal XENAR to a low level ( Figure 51 (C)). Therefore, the output signal of the NOR1 circuit is high.

[0334] At time t91, the light-emitting unit 11 emits a light pulse L0 based on the command from the controller 14. Figure 51 (D)). The light pulse L0 is reflected by the object being measured OBJ. The light pulse reflected by the object being measured OBJ (reflected light pulse L1) enters the light receiving section P of the photodetector 20 at timing t92. The time from the timing t91 of the emitted light pulse L0 to the timing t92 of the reflected light pulse L1 entering the light receiving section P is the time of flight Ttof of the light pulse detected by the light receiving section P.

[0335] In the light receiver P, the photodiode PD causes avalanche amplification by detecting light, which reduces the voltage VN1 at node N1. Figure 51 (G)). Then, at time t93, when the voltage VN1 at node N1 becomes lower than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from low to high. Figure 51 (H)).

[0336] The NAND circuit NAND1 changes its output signal from high to low based on the change in the pulse signal PLS1. At timing t94, which is a delay time of the delay circuit DEL1 delayed from timing t93, the delay circuit DEL1 changes the voltage AR at the gate of transistor MP4 from high to low. Figure 51 (F)). Therefore, transistor MP4 is turned on, and the voltage VN1 at node N1 increases (F). Figure 51 (G)). Then, at time t95, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high to low. Figure 51 (H)).

[0337] Then, the NAND circuit NAND1 changes the output signal from low to high according to the change in the pulse signal PLS1. At timing t96, which is a delay time of the delay circuit DEL1 delayed from timing t95, the delay circuit DEL1 changes the voltage AR at the gate of transistor MP4 from low to high. Figure 51 (F)).

[0338] Figure 52 An operational example of the optical receiver P in self-diagnostic operation is shown, wherein (A) indicates the waveform of the control signal ENBIST, (B) indicates the waveform of the control signal XACT, (C) indicates the waveform of the control signal XENAR, (D) indicates the waveform of the voltage AR at the gate of transistor MP4, (E) indicates the waveform of the voltage VN1 at node N1, and (F) indicates the waveform of the pulse signal PLS1 (pulse signal PLS). Figure 52 The waveforms of the clock signal CLK and the pulse signal PLSA are not shown in the diagram, but they are similar to those in the first embodiment described above. Figure 12 The waveforms are similar to those in (etc.).

[0339] During self-diagnostic operation, the distance measurement controller 68 changes the control signal ENBIST to a high level. Figure 52 (A)). Therefore, in the light receiver P, transistor MP1 is turned off and transistor MN1 is turned on. As a result, the cathode of photodiode PD is separated from node N1 and grounded. In addition, the distance measurement controller 68 changes the control signal XACT to a high level during the time period before timing t101. Figure 52 (B) Therefore, in the light receiver P, transistor MN2 is turned on and transistor MP3 is turned off. As a result, the constant current source CUR is disconnected from node N1, and node N1 is grounded. Furthermore, the distance measurement controller 68 changes the control signal XENAR to a low level (B). Figure 52(C)). The control signal XACT is high for a period of time before timing t101; therefore, the NOR circuit NOR1 will change the output signal to low. Therefore, the delay circuit DEL1 will change the voltage AR to high. Figure 52 (D)).

[0340] At time t101, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 52 (B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. As a result, node N1 is separated from the ground node and connected to the constant current source CUR. Therefore, although not shown, current flows into node N1 through the constant current source CUR, and the voltage VN1 at node N1 gradually increases.

[0341] Next, at time t102, after the delay time of delay circuit DEL1 has elapsed since timer t101, delay circuit DEL1 changes the voltage AR at the gate of transistor MP4 from high level to low level. Figure 52 (D)). Therefore, transistor MP4 is turned on, and the voltage VN1 at node N1 increases ( Figure 52 (E)). Then, at time t103, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high to low. Figure 52 (F)). Then, after the delay time of the delay circuit DEL1 has elapsed since the timing t103, the delay circuit DEL1 changes the voltage AR from low level to high level. Figure 52 (D)). Thus, preparation is complete.

[0342] Then, at time t104, the distance measurement controller 68 changes the control signal XACT from low level to high level. Figure 52 (B) Therefore, in the light receiver P, transistor MN2 is turned on and transistor MP3 is turned off. As a result, node N1 is disconnected from the constant current source CUR and grounded, and the voltage VN1 at node N1 changes from high level to low level. Figure 52 (E)). The voltage VN1 at node N1 becomes lower than the logic threshold TH of inverter IV1, causing inverter IV1 to change the pulse signal PLS1 from low to high. Figure 52 (F)).

[0343] Next, at time t105, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 52(B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. As a result, node N1 is separated from the ground node and connected to the constant current source CUR. Therefore, although not shown, current flows into node N1 through the constant current source CUR, causing the voltage VN1 at node N1 to gradually increase.

[0344] Next, at time t106, after the delay time of delay circuit DEL1 has elapsed since timer t105, delay circuit DEL1 changes voltage AR from high level to low level. Figure 52 (D)). Therefore, transistor MP4 is turned on, and the voltage VN1 at node N1 increases ( Figure 52 (E)). Then, at time t107, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high to low. Figure 52 (F)). Then, after the delay time of the delay circuit DEL1 has elapsed since timer t107, the delay circuit DEL1 changes the voltage AR from low level to high level. Figure 52 (D)).

[0345] Next, the self-diagnostic operation will be described in detail with reference to some examples of faults. In the optical receiver P, various faults may occur due to initial faults, degradation over time, etc. Examples of faults may include the case where transistor MP4 fails to change the voltage at node N1 (case C11) and the case where transistors MP2 and MP3 fail to supply current to node N1. Examples of faults may include the case where cases C11 and C12 occur simultaneously (case C13). The diagnostic unit 66 is capable of diagnosing these various faults in the optical receiver P.

[0346] (Case C11)

[0347] First, the case where transistor MP4 cannot change the voltage at node N1 (case C11) is described. It should be noted that this example describes an instance where a fault exists in transistor MP4, but the same applies to cases where a fault exists anywhere in the path of NAND1, delay circuit DEL1, and transistor MP4.

[0348] Figure 53 An operational example of the optical receiver P under condition C11 is shown, wherein (A) indicates the waveform of the control signal ENBIST, (B) indicates the waveform of the control signal XACT, (C) indicates the waveform of the control signal XENAR, (D) indicates the waveform of the voltage AR at the gate of transistor MP4, (E) indicates the waveform of the voltage VN1 at node N1, and (F) indicates the waveform of the pulse signal PLS1 (pulse signal PLS). Figure 53 In (E) and (F), the dashed line indicates the waveform when there is no fault, and the solid line indicates the waveform when there is a fault. Figure 53 (A) to (F) respectively correspond to Figure 52 (A) to (F).

[0349] At time t111, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 53 (B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. As a result, node N1 is separated from the ground node and connected to the constant current source CUR. Therefore, current flows into node N1 through the constant current source CUR, causing the voltage VN1 at node N1 to gradually increase (B). Figure 53 (E)).

[0350] Next, at time t112, after the delay time of delay circuit DEL1 since timer t111, delay circuit DEL1 changes the voltage AR at the gate of transistor MP4 from high level to low level. Figure 53 (D)). In the case of C11, transistor MP4 cannot change the voltage VN1 at node N1, because the voltage VN1 increases as is based on the current supplied from the constant current source CUR. Figure 53 (E)). Subsequently, the delay circuit DEL1 changes the voltage AR from low to high level. Figure 53 (D)). At time t113, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high to low. Figure 53 (F)).

[0351] Then, at time t114, the distance measurement controller 68 changes the control signal XACT from low level to high level. Figure 53 (B) Therefore, in the light receiver P, transistor MN2 is turned on and transistor MP3 is turned off. As a result, node N1 is disconnected from the constant current source CUR and grounded, causing the voltage VN1 at node N1 to change from a high level to a low level. Figure 53 (E)). The voltage VN1 at node N1 becomes lower than the logic threshold TH of inverter IV1, causing inverter IV1 to change the pulse signal PLS1 from low to high. Figure 53 (F)).

[0352] Next, at time t115, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 53(B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. As a result, node N1 is separated from the ground node and connected to the constant current source CUR. Therefore, current flows into node N1 through the constant current source CUR, gradually increasing the voltage VN1 at node N1. Figure 53 (E)).

[0353] Next, at time t116, after the delay time of delay circuit DEL1 has elapsed since timer t115, delay circuit DEL1 changes voltage AR from high level to low level. Figure 53 (D)). In the case of C11, transistor MP4 cannot change the voltage VN1 at node N1, because the voltage VN1 increases as is based on the current supplied from the constant current source CUR. Figure 53 (E)). Subsequently, the delay circuit DEL1 changes the voltage AR from low to high level. Figure 53 (D)). At time t117, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high to low. Figure 53 (F)).

[0354] Therefore, in the case of C11, transistor MP4 cannot change the voltage VN1 at node N1, which causes current to flow into node N1 through the paths of transistors MP2 and MP3, increasing the voltage VN1 at node N1. Consequently, compared to the case without a fault, the timing of the pulse end of pulse signal PLS1 becomes later, and the pulse width of pulse signal PLS1 becomes longer. Therefore, in the histogram generated by histogram generator 23, the right end of the histogram shifts to the right, which widens the width of the histogram distribution.

[0355] When the width of the histogram distribution is widened by moving the right end of the histogram to the right, the diagnostic unit 66 diagnoses the light receiver P as having a fault where the transistor MP4 cannot change the voltage at node N1.

[0356] (Case C13)

[0357] Next, we describe the case where transistor MP4 cannot change the voltage VN1 at node N1 and transistors MP2 and MP3 cannot provide current to node N1 (case C13).

[0358] Figure 54 An operational example of the optical receiver P in case C13 is shown.

[0359] At time t121, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 54(B)). Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. In the case of C13, transistors MP2 and MP3 cannot supply current to node N1, which keeps the voltage VN1 at node N1 at a low level. Figure 54 (E)).

[0360] Next, at time t122, after the delay time of delay circuit DEL1 has elapsed since timer t121, delay circuit DEL1 changes the voltage AR at the gate of transistor MP4 from high level to low level. Figure 54 (D)). In case C13, transistor MP4 cannot change the voltage VN1 at node N1, which keeps the voltage VN1 at a low level. Figure 54 (E)). Subsequently, the delay circuit DEL1 changes the voltage AR from low to high level. Figure 54 (D)).

[0361] Then, at time t123, the distance measurement controller 68 changes the control signal XACT from low level to high level. Figure 54 (B) Therefore, in the light receiver P, transistor MN2 is turned on and transistor MP3 is turned off. As a result, node N1 is grounded, which keeps the voltage VN1 at node N1 at a low level. Figure 54 (E)).

[0362] Next, at time t124, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 54 (B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. In case C13, transistors MP2 and MP3 cannot supply current to node N1, which keeps the voltage VN1 at node N1 at a low level. Figure 54 (E)).

[0363] Next, at time t125, after the delay time of delay circuit DEL1 has elapsed since timer t124, delay circuit DEL1 changes the voltage AR from high level to low level. Figure 54 (D)). In case C13, transistor MP4 cannot change the voltage VN1 at node N1, which keeps the voltage VN1 at a low level. Figure 54 (E)). Subsequently, the delay circuit DEL1 changes the voltage AR from low to high level. Figure 54 (D)).

[0364] Therefore, transistor MP4 cannot change the voltage VN1 at node N1, and transistors MP2 and MP3 cannot supply current to node N1, which keeps the voltage VN1 at node N1 at a low level. Therefore, inverter IV1 keeps the pulse signal PLS1 at a high level. Therefore, in the histogram generated by histogram generator 23, the frequency in all bins is "1".

[0365] In this case, where the frequency in all compartments is "1", the diagnostic unit 66 diagnoses the optical receiver P as having a fault where transistor MP4 cannot change the voltage VN1 at node N1 and transistors MP2 and MP3 cannot supply current to node N1.

[0366] (Case C12)

[0367] Next, the case where transistors MP2 and MP3 cannot supply current to node N1 (case C12) is described. The self-diagnostic operation in case C12 is performed by setting transistor MP4 to not change the voltage VN1 at node N1. First, the case where the fault in case C12 does not occur is described. Then, the case where the fault in case C12 occurs is described.

[0368] Figure 55 An example of the operation of the optical receiver P during self-diagnostic operation is shown in the absence of a fault in condition C12. In this self-diagnostic operation, the distance measurement controller 68 changes the control signal XENAR to a high level. Figure 55 (C) Therefore, the NOR circuit NOR1 keeps the output signal low, and the delay circuit DEL1 keeps the gate voltage AR of transistor MP4 high. In this self-diagnostic operation, transistor MP4 remains off in this way.

[0369] At time t131, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 55 (B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. As a result, node N1 is separated from the ground node and connected to the constant current source CUR. Consequently, current flows into node N1 through the constant current source CUR, causing the voltage VN1 at node N1 to gradually increase (B). Figure 55 (E)). Then, at time t132, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high to low. Figure 55 (F)). Thus, preparation is complete.

[0370] Then, at time t133, the distance measurement controller 68 changes the control signal XACT from low level to high level. Figure 55 (B) Therefore, in the light receiver P, transistor MN2 is turned on and transistor MP3 is turned off. As a result, node N1 is disconnected from the constant current source CUR and grounded, causing the voltage VN1 at node N1 to change from a high level to a low level. Figure 55 (E)). The voltage VN1 at node N1 becomes lower than the logic threshold TH of inverter IV1, causing inverter IV1 to change the pulse signal PLS1 from low to high. Figure 55 (F)).

[0371] Next, at time t134, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 55 (B) Therefore, in the optical receiver P, transistor MP3 is turned on and transistor MN2 is turned off. As a result, node N1 is separated from the ground node and connected to the constant current source CUR. Therefore, current flows into node N1 through the constant current source CUR, which causes the voltage VN1 at node N1 to gradually increase. Then, at timing t135, when the voltage VN1 at node N1 becomes higher than the logic threshold TH of inverter IV1, inverter IV1 changes the pulse signal PLS1 from high level to low level ( Figure 55 (F)).

[0372] Figure 56 An example of the operation of the optical receiver P during self-diagnostic operation in the event of a fault in condition C12 is shown. Figure 56 In (E) and (F), the dashed line indicates the waveform when there is no fault, and the solid line indicates the waveform when there is a fault. Figure 56 (A) to (F) respectively correspond to Figure 55 (A) to (F).

[0373] At time t141, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 56 (B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. In case C12, transistors MP2 and MP3 cannot supply current to node N1, which keeps the voltage VN1 at node N1 at a low level. Figure 56 (E)).

[0374] Then, at time t142, the distance measurement controller 68 changes the control signal XACT from low level to high level. Figure 56 (B) Therefore, in the light receiver P, transistor MN2 is turned on and transistor MP3 is turned off. As a result, node N1 is grounded, which keeps the voltage VN1 at node N1 at a low level. Figure 56 (E)).

[0375] Next, at time t143, the distance measurement controller 68 changes the control signal XACT from high level to low level. Figure 56 (B) Therefore, in the light receiver P, transistor MP3 is turned on and transistor MN2 is turned off. In case C12, transistors MP2 and MP3 cannot supply current to node N1, which keeps the voltage VN1 at node N1 at a low level. Figure 56 (E)).

[0376] Transistors MP2 and MP3 cannot supply current to node N1 in this manner, which keeps the voltage VN1 at node N1 low. Therefore, inverter IV1 keeps the pulse signal PLS1 high. Consequently, in the histogram generated by histogram generator 23, the frequency in all bins is "1".

[0377] When the control signal XENAR becomes high in this manner, and the frequency in all compartments is "1", the diagnostic unit 66 diagnoses the optical receiver P as having a fault where transistors MP2 and MP3 cannot supply current to node N1.

[0378] Figure 57 An example of the self-diagnostic operation in the optical detection system 4 is shown.

[0379] First, the optical detection system 4 changes the control signal XENAR to a low level and performs a self-diagnostic operation (step S101). This operation corresponds to... Figures 52 to 54 .

[0380] Next, the diagnostic unit 66 confirms whether the pulse signal PLS remains at a high level (step S102). Specifically, the diagnostic unit 66 confirms whether the pulse signal PLS remains at a high level, such as... Figure 54 As shown in (F). With the pulse signal PLS held high ("Yes" in step S102), the diagnostic unit 66 diagnoses the fault as corresponding to case C13 (step S103). In other words, the diagnostic unit 66 diagnoses the optical receiver P as having a fault where transistor MP4 cannot change the voltage VN1 at node N1 and transistors MP2 and MP3 cannot supply current to node N1. Then, the process ends.

[0381] If the pulse signal PLS is not held at a high level (No in step S102), the diagnostic unit 66 checks whether the pulse width of the pulse signal PLS is wide (step S104). Specifically, the diagnostic unit 66 checks whether the pulse width of the pulse signal PLS is wide, such as... Figure 53As shown in (F). When the pulse width of the pulse signal PLS is wide ("Yes" in step S104), the diagnostic unit 66 diagnoses the fault as corresponding to case C11 (step S105). In other words, the diagnostic unit 66 diagnoses the optical receiver P as having a fault where the transistor MP4 cannot change the voltage VN1 at node N1. Then, the process ends.

[0382] If the pulse width of the pulse signal PLS is not wide (No in step S104), the photodetector 4 changes the control signal XENAR to a high level and performs a self-diagnostic operation (step S106). This operation corresponds to... Figure 55 and Figure 56 .

[0383] Next, the diagnostic unit 66 confirms whether the pulse signal PLS remains at a high level (step S107). Specifically, the diagnostic unit 66 confirms whether the pulse signal PLS remains at a high level, such as... Figure 56 As shown in (F). With the pulse signal PLS held high ("Yes" in step S107), the diagnostic unit 66 diagnoses the fault as corresponding to case C12 (step S108). In other words, the diagnostic unit 66 diagnoses the optical receiver P as having a fault where transistors MP2 and MP3 cannot supply current to node N1. Then, the process ends.

[0384] If the pulse signal PLS is not held at a high level (No in step S107), the diagnostic unit 66 diagnoses the optical receiver P as fault-free and normal (step S109). Thus, the process ends.

[0385] As described above, in the optical detection system 4, it is possible to detect... Figure 50 The light receiving unit P shown is used for diagnostic processing.

[0386] [Variation Example 4]

[0387] Any of the variations of the first to third embodiments described above can be applied to the optical detection system 4 according to the fourth embodiment described above.

[0388] <5. Examples of applications of moving bodies>

[0389] The technology disclosed herein (the Technology) is applicable to a variety of products. For example, the Technology disclosed herein can be implemented as a device mounted on any type of mobile body, such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, aircraft, drone, ship, or robot.

[0390] Figure 58This is a block diagram depicting an example of a schematic configuration of a vehicle control system, which serves as an example of a mobile body control system to which the technology according to embodiments of this disclosure can be applied.

[0391] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 58 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 1205. Furthermore, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0392] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for the following devices: a drive force generating device for generating the vehicle's driving force, such as an internal combustion engine or a drive electric motor; a drive force transmission mechanism for transmitting driving force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating the vehicle's braking force.

[0393] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves emitted from a mobile device can be input to the body system control unit 12020 as signals for key replacement or various switches. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0394] The exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform processing such as detecting objects like people, vehicles, obstacles, signs, and text on the road surface, or performing processing to detect the distance to them.

[0395] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0396] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. The in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, or it can determine whether the driver is dozing off.

[0397] The microcomputer 12051 can calculate control target values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption, distance-based following, maintaining vehicle speed, collision warning, lane departure warning, etc.

[0398] Furthermore, the microcomputer 12051 can control the drive force generation device, steering mechanism, braking device, etc., based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, to perform cooperative control intended for autonomous driving, which enables the vehicle to drive automatically without relying on the driver's operation.

[0399] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the exterior of the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control to prevent glare by controlling the headlights to switch from high beam to low beam based on the position of the vehicle ahead or oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0400] The sound / image output unit 12052 transmits at least one of sound and image output signals to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle. Figure 58In this example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. For example, display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0401] Figure 59 This is an illustration showing an example of the mounting position of the imaging unit 12031.

[0402] exist Figure 59 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0403] Imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, located on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, and on the upper part of the windshield inside the vehicle. Imaging unit 12101 on the front nose and imaging unit 12105 on the upper part of the windshield inside the vehicle primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0404] Incidentally, Figure 59 Examples of the imaging ranges of imaging units 12101 to 12104 are depicted. Imaging range 12111 indicates the imaging range of imaging unit 12101 located at the front nose. Imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located at the side mirrors, respectively. Imaging range 12114 indicates the imaging range of imaging unit 12104 located at the rear bumper or rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by superimposing image data captured by imaging units 12101 to 12104.

[0405] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0406] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the vehicle ahead, which specifically exists on the driving path of the vehicle 12100 and is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can preset the following distance to be maintained with the vehicle ahead and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Thus, cooperative control for autonomous driving, which aims to enable the vehicle to drive automatically, can be performed without relying on the driver's operation.

[0407] For example, the microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and a collision is possible, the microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering via drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0408] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the imaging images of the imaging units 12101 to 12104. For example, pedestrian identification is performed by a process of extracting feature points from the imaging images of the imaging units 12101 to 12104, which are infrared cameras, and by a process of determining whether an object is a pedestrian by performing pattern matching processing on a series of feature points of the outline of the indicated object. When the microcomputer 12051 determines that a pedestrian exists in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon indicating the pedestrian is displayed at a desired location.

[0409] An example of a vehicle control system to which the technology according to this disclosure can be applied has been described above. The technology according to this disclosure can be applied to the imaging unit 12031 in the above-described components. This allows the vehicle control system 12000 to diagnose whether the imaging unit 12031 is operating normally by performing self-diagnosis. Therefore, in the vehicle control system 12000, for example, in the event of a malfunction, appropriate actions such as warning the driver can be performed, which improves reliability.

[0410] <6. Specific Application Examples of Vehicles>

[0411] Next, specific examples of applying the optical detection system according to this disclosure to a vehicle will be described in detail.

[0412] Figure 60 and Figure 61 A configuration example of a vehicle 200 applying this technology is shown. Figure 61 In the vehicle 200, an ECU (Electronic Control Unit) 208, a front camera module 201, a steering system 202, headlights 203, an engine 204, an electric motor 205, a brake system 206, and a display and operation unit 207 are connected via a bus 209. Figure 61 As shown.

[0413] ECU 208 is configured to perform vehicle 200 control by communicating with various blocks in vehicle 200 via bus 209. In driver assistance mode, ECU 208 performs vehicle 200 control based on information provided by front camera module 201. ECU 208 includes one or more ECUs.

[0414] The front camera module 201 is configured to detect the lane in which the vehicle 200 is traveling, vehicles traveling in front of the vehicle 200, pedestrians walking in front of the vehicle 200, etc. The front camera module 201 includes an image sensor 211, a distance measurement sensor 212, and a front camera ECU 213, such as... Figure 61 As shown.

[0415] Image sensor 211 includes, for example, a CMOS (Complementary MOS) image sensor and is configured to capture an image of an area in front of vehicle 200 by performing an imaging operation. In this example, image sensor 211 also has the function of performing a self-diagnostic operation. It should be noted that this is not limiting, and image sensor 211 may not have the function of performing a self-diagnostic operation.

[0416] The distance measurement sensor 212 includes a light detection system according to any of the above embodiments and is configured to measure the distance to an object in front of the vehicle 200 by performing a distance measurement operation. The distance measurement sensor 212 also has the function of performing a self-diagnostic operation.

[0417] The front camera ECU 213 is configured to perform various detection processes, such as lane detection, vehicle detection, pedestrian detection, and headlight detection, based on the captured image generated by the image sensor 211 and the distance image generated by the distance measurement sensor 212. The front camera ECU 213 then notifies the ECU 208 of the results of the detection processes. Furthermore, the front camera ECU 213 also has the function of notifying the ECU 208 of any fault detected in either the image sensor 211 or the distance measurement sensor 212.

[0418] Steering 202 is configured to control the direction of travel of vehicle 200. Steering 202 is operated, for example, by the driver. Furthermore, in driver assistance mode, steering 202 is controlled, for example, by ECU 208. Specifically, for example, in driver assistance mode, ECU 208 controls steering 202 based on information provided from front camera module 201 to avoid collisions with vehicles or pedestrians along the lane in front of vehicle 200.

[0419] The headlights 203 are configured to illuminate an area in front of the vehicle 200. The headlights 203 are operated, for example, by the driver. Furthermore, in driver assistance mode, the headlights 203 are controlled, for example, by the ECU 208. Specifically, for example, in driver assistance mode, the ECU 208 performs control based on information provided from the front camera module 201 to switch from high beam to low beam when an oncoming vehicle is traveling, and from low beam to high beam when no oncoming vehicle is traveling.

[0420] Engine 204 and electric motor 205 are the power sources that allow vehicle 200 to move. Engine 204 and electric motor 205 are controlled by ECU 208. For example, ECU 208 operates electric motor 205 when engine 204 is inefficient (such as when starting vehicle 200). Furthermore, ECU 208 operates engine 204 when engine 204 is efficient. Additionally, for example, in driver assistance mode, ECU 208 controls the operation of engine 204 and electric motor 205 based on information provided from front camera module 201.

[0421] Brake 206 is configured to brake vehicle 200. Brake 206 is operated, for example, by the driver. Additionally, brake 206 is controlled, for example, by ECU 208 in driver assistance mode. Specifically, for example, in driver assistance mode, ECU 208 controls brake 206 based on information provided from front camera module 201 to avoid collisions with vehicles or pedestrians in front of vehicle 200.

[0422] The display operation unit 207 includes, for example, an LCD display, a touch panel, etc., and is configured to display the driving status of the vehicle 200. Furthermore, the display operation unit 207 has the function of performing route navigation to a destination based on information from, for example, a GPS (Global Positioning System) device (not shown). For example, if the front camera module 201 malfunctions and the ECU 208 terminates driver assistance mode, the display operation unit 207 will display this information.

[0423] Figure 62 An example of driver assistance processing for vehicle 200 is shown.

[0424] The ECU 208 checks whether the driving assistance mode is set by operating the display unit 207 (step S201). If the driving assistance mode is not set ("No" in step S201), step S201 is repeated until the driving assistance mode is set.

[0425] With the driver assistance mode set ("Yes" in step S201), the ECU 208 obtains the results of the self-diagnostic operation in the front camera module 201 (step S202). Then, the ECU 208 checks whether there is a fault in the front camera module 201 (step S203).

[0426] In step S203, if there is no fault in the front camera module 201 (No in step S203), the front camera module 201 performs imaging and distance measurement operations (step S204). Specifically, the image sensor 211 generates a captured image by capturing an image of the area in front of the vehicle 200. Furthermore, the distance measurement sensor 212 generates a distance image by measuring the distance to objects in front of the vehicle 200.

[0427] Next, the front camera ECU 213 analyzes the captured image and the distance image (step S205). Specifically, for example, the front camera ECU 213 performs various detection processes such as lane detection, vehicle detection, pedestrian detection, and headlight detection based on the captured image generated by the image sensor 211 and the distance image generated by the distance measurement sensor 212.

[0428] Next, the ECU 208 performs driver assistance processing based on the analysis results of the front camera ECU 213 (step S206). Specifically, the ECU 208 performs driver assistance processing by controlling the operation of the steering gear 202, headlights 203, engine 204, electric motor 205, brakes 206 and display operation unit 207.

[0429] Then, ECU 208 confirms whether driving is complete (step S207). If driving is not complete ("No" in step S207), the process returns to step S202. If driving is complete ("Yes" in step S207), the process ends.

[0430] In step S203, if a fault exists in the front camera module 201 (Yes in step S203), the ECU 208 terminates the driving assistance mode (step S208). Then, the display operation unit 207 displays a notification that the driving assistance mode has ended (step S209).

[0431] Therefore, the process is complete.

[0432] Although the present technology has been described above with reference to some embodiments, variations and specific application examples, the present technology is not limited to these embodiments and can be modified in various ways.

[0433] For example, in the above embodiments, for example, Figure 3 The light receiver P is shown in the figure. However, the circuit configuration of the light receiver P is not limited to this, and any of various circuit configurations can be applied.

[0434] It should be noted that the effects described herein are illustrative and non-limiting only, and may include other effects.

[0435] It should be noted that this technology can have the following configurations. With this technology having the following configurations, self-diagnosis can be performed.

[0436] (1) A light detection device, comprising:

[0437] An optical receiver includes an optical receiving element, a first switch, a second switch, and a signal generator. The first switch couples the optical receiving element to a first node by turning it on. The second switch applies a predetermined voltage to the first node by turning it on. The signal generator generates a pulse signal based on the voltage at the first node.

[0438] The controller controls the operation of the first and second switches;

[0439] The detector, based on the timing of pulse signal changes, detects pulse signals; and

[0440] The output unit outputs a detection signal corresponding to the detection result of the detector when the second switch is turned on.

[0441] (2) The optical detection device according to (1) further includes a diagnostic unit, wherein when the second switch is turned on, the diagnostic unit performs diagnostic processing based on the detection result of the detector, wherein

[0442] The detection signal includes a signal corresponding to the diagnostic result of the diagnostic unit.

[0443] (3) The optical detection device according to (2), wherein the detection signal includes a signal indicating whether there is a fault in the optical receiver.

[0444] (4) The optical detection device according to (2) or (3), wherein the detection signal includes a signal indicating details of a fault in the optical receiver.

[0445] (5) The light detection device according to any one of (2) to (4), wherein,

[0446] During multiple first time periods, the controller turns on the first switch.

[0447] During a second time period between two adjacent first time periods, the controller disconnects the first switch and connects or disconnects the second switch.

[0448] The diagnostic unit performs the diagnostic process based on the detection results of the detector during the second time period.

[0449] (6) The light detection device according to any one of (2) to (4), wherein,

[0450] During multiple first time periods, the controller turns on the first switch.

[0451] In a second time period between two adjacent first time periods of the plurality of first time periods, the controller turns on the first switch and turns on or off the second switch, and

[0452] The diagnostic unit performs the diagnostic process based on the detection results of the detector during the second time period.

[0453] (7) The optical detection device according to (5) or (6), wherein,

[0454] During the second time period, the signal generator generates a pulse signal corresponding to the on / off state of the second switch, and

[0455] The detector detects the timing of changes in the pulse signal during the second time period.

[0456] (8) The optical detection device according to (7), wherein the diagnostic unit performs the diagnostic process based on the timing of the change of the pulse signal.

[0457] (9) The optical detection device according to (7) or (8), wherein the diagnostic unit performs the diagnostic processing based on the presence or absence of a change in the pulse signal.

[0458] (10) The optical detection device according to (5) or (6), wherein,

[0459] During the first time period, the signal generator generates a pulse signal corresponding to the light reception result of the light receiving element, and

[0460] The detector detects the timing of the change in the pulse signal during the first time period to detect the optical receiving timing in the optical receiving element.

[0461] (11) The light detection apparatus according to any one of (1) to (10), wherein,

[0462] The optical detection device includes multiple optical receivers.

[0463] The controller controls the operation of the first switch and the second switch of each of the plurality of optical receivers, and

[0464] The detector generates a composite pulse signal based on multiple pulse signals generated by multiple optical receivers, and detects the timing of changes in the composite pulse signal.

[0465] (12) The light detection apparatus according to any one of (1) to (10), wherein,

[0466] The optical detection device includes multiple optical receivers.

[0467] The controller controls the operation of the first switch and the second switch of each of the plurality of optical receivers, and

[0468] The detector generates a code by performing addition processing based on multiple pulse signals generated by the multiple optical receivers, and detects the timing of changes in the code.

[0469] (13) The light detection device according to any one of (1) to (12), wherein the light detection device is mounted on a vehicle.

[0470] (14) A light detection system, comprising:

[0471] The light-emitting part emits light; and

[0472] A photodetector detects the light reflected by the object being measured from the light emitted from the light source, wherein...

[0473] The photodetector includes:

[0474] An optical receiver includes an optical receiving element, a first switch, a second switch, and a signal generator. The first switch couples the optical receiving element to a first node by turning it on. The second switch applies a predetermined voltage to the first node by turning it on. The signal generator generates a pulse signal based on the voltage at the first node.

[0475] The controller controls the operation of the first switch and the second switch.

[0476] The detector detects changes in the pulse signal based on the timing of the pulse signal changes.

[0477] The output unit outputs a detection signal corresponding to the detection result of the detector when the second switch is turned on.

[0478] This application claims priority to Japanese Patent Application No. 2021-029082, filed with the Japan Patent Office on February 25, 2021, the entire contents of which are incorporated herein by reference.

[0479] Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations can be made depending on design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A light detection device, comprising: An optical receiver includes an optical receiving element, a first switch, a second switch, and a signal generator. The first switch couples the optical receiving element to a first node by turning it on. The second switch applies a predetermined voltage to the first node by turning it on. The signal generator generates a pulse signal based on the voltage at the first node. The controller controls the operation of the first switch and the second switch; A detector that detects timing changes in the pulse signal based on the pulse signal; The output unit outputs a detection signal corresponding to the detection result of the detector when the second switch is turned on. as well as The diagnostic unit, when the second switch is turned on, performs diagnostic processing based on the detection result of the detector, wherein... The detection signal includes a signal corresponding to the diagnostic result of the diagnostic unit. During multiple first time periods, the controller turns on the first switch. During a second time period between two adjacent first time periods, the controller disconnects the first switch and connects or disconnects the second switch. The diagnostic unit performs the diagnostic process based on the detection results of the detector during the second time period.

2. A light detection device, comprising: An optical receiver includes an optical receiving element, a first switch, a second switch, and a signal generator. The first switch couples the optical receiving element to a first node by turning it on. The second switch applies a predetermined voltage to the first node by turning it on. The signal generator generates a pulse signal based on the voltage at the first node. The controller controls the operation of the first switch and the second switch; A detector that detects timing changes in the pulse signal based on the pulse signal; The output unit outputs a detection signal corresponding to the detection result of the detector when the second switch is turned on. as well as The diagnostic unit, when the second switch is turned on, performs diagnostic processing based on the detection result of the detector, wherein... The detection signal includes a signal corresponding to the diagnostic result of the diagnostic unit. in: During multiple first time periods, the controller turns on the first switch. In a second time period between two adjacent first time periods of the plurality of first time periods, the controller turns on the first switch and turns on or off the second switch, and The diagnostic unit performs the diagnostic process based on the detection results of the detector during the second time period.

3. The optical detection device according to claim 1 or 2, wherein, The detection signal includes a signal indicating whether there is a fault in the optical receiver.

4. The optical detection device according to claim 1 or 2, wherein, The detection signal includes a signal indicating details of a fault in the optical receiver.

5. The optical detection device according to claim 1, wherein, During the second time period, the signal generator generates a pulse signal corresponding to the on / off state of the second switch, and The detector detects the timing of changes in the pulse signal during the second time period.

6. The optical detection device according to claim 5, wherein, The diagnostic unit performs the diagnostic process based on the timing of the pulse signal change.

7. The optical detection device according to claim 5, wherein, The diagnostic unit performs the diagnostic process based on whether or not the pulse signal changes.

8. The optical detection device according to claim 1, wherein, During the first time period, the signal generator generates a pulse signal corresponding to the light reception result of the light receiving element, and The detector detects the timing of the change in the pulse signal during the first time period to detect the optical receiving timing in the optical receiving element.

9. The optical detection device according to claim 1 or 2, wherein, The optical detection device includes multiple optical receivers. The controller controls the operation of the first switch and the second switch of each of the plurality of optical receivers, and The detector generates a composite pulse signal based on multiple pulse signals generated by multiple optical receivers, and detects the timing of changes in the composite pulse signal.

10. The optical detection device according to claim 1 or 2, wherein, The optical detection device includes multiple optical receivers. The controller controls the operation of the first switch and the second switch of each of the plurality of optical receivers, and The detector generates a code by performing addition processing based on multiple pulse signals generated by multiple optical receivers, and detects the timing of changes in the code.

11. The optical detection device according to claim 1 or 2, wherein, The optical detection device is installed in the vehicle.

12. A light detection system, comprising: The light-emitting part emits light; as well as A photodetector detects light reflected by the object being measured from light emitted from the light-emitting part, wherein The photodetector includes: An optical receiver includes an optical receiving element, a first switch, a second switch, and a signal generator. The first switch couples the optical receiving element to a first node by turning it on. The second switch applies a predetermined voltage to the first node by turning it on. The signal generator generates a pulse signal based on the voltage at the first node. The controller controls the operation of the first switch and the second switch. The detector detects changes in the pulse signal based on the timing of the pulse signal. The output unit, when the second switch is turned on, outputs a detection signal corresponding to the detection result of the detector, and The diagnostic unit, when the second switch is turned on, performs diagnostic processing based on the detection result of the detector, wherein... The detection signal includes a signal corresponding to the diagnostic result of the diagnostic unit. During multiple first time periods, the controller turns on the first switch. During a second time period between two adjacent first time periods, the controller disconnects the first switch and connects or disconnects the second switch. The diagnostic unit performs the diagnostic process based on the detection results of the detector during the second time period.

13. A light detection system, comprising: The light-emitting part emits light; as well as A photodetector detects light reflected by the object being measured from light emitted from the light-emitting part, wherein The photodetector includes: An optical receiver includes an optical receiving element, a first switch, a second switch, and a signal generator. The first switch couples the optical receiving element to a first node by turning it on. The second switch applies a predetermined voltage to the first node by turning it on. The signal generator generates a pulse signal based on the voltage at the first node. The controller controls the operation of the first switch and the second switch. The detector detects changes in the pulse signal based on the timing of the pulse signal. The output unit, when the second switch is turned on, outputs a detection signal corresponding to the detection result of the detector, and The diagnostic unit, when the second switch is turned on, performs diagnostic processing based on the detection result of the detector, wherein... The detection signal includes a signal corresponding to the diagnostic result of the diagnostic unit. in: During multiple first time periods, the controller turns on the first switch. In a second time period between two adjacent first time periods of the plurality of first time periods, the controller turns on the first switch and turns on or off the second switch, and The diagnostic unit performs the diagnostic process based on the detection results of the detector during the second time period.

Images