Serial / Deserial Circuit, Serial Data Receiving Method and Chip

Abstract

A serial / parallel circuit, a serial data receiving method and a chip relate to the field of inter-chip communication and are used for shortening the link-up time of a multi-channel serial / parallel circuit. The serial / parallel circuit (40) comprises a first receiving channel (41) and a second receiving channel (42); the first receiving channel (41) comprises a clock data recovery circuit (412) and a first serial-parallel conversion circuit (411); the second receiving channel (42) comprises a second serial-parallel conversion circuit (421); the first serial-parallel conversion circuit (411) receives first serial data, performs analog-to-digital conversion and serial-parallel conversion; the second serial-parallel conversion circuit (421) receives second serial data, performs analog-to-digital conversion and serial-parallel conversion; and the clock data recovery circuit (412) obtains a first clock signal from the first serial data and outputs the first clock signal to the first serial-parallel conversion circuit (411) and the second serial-parallel conversion circuit (421).

Description

Technical Field

[0001] This application relates to the field of chip-to-chip communication, and more particularly to a serial / deserialization circuit, a serial data receiving method, and a chip. Background Technology

[0002] Serializing / deserializing (SerDes) technology is a high-speed interface technology used for inter-chip communication. Some devices employ multi-lane serializing / deserializing circuits to increase transmission bandwidth.

[0003] During the switching from single-channel transmission to multi-channel transmission, the receiving end first needs to recover the clock signals of each channel from the serial data of multi-channel transmission in order to complete the link establishment of each channel. This takes a long time, thus affecting the working efficiency of the entire system under high transmission bandwidth. Summary of the Invention

[0004] This application provides a serial / deserialization circuit, a serial data receiving method, and a chip to shorten the connection establishment time of a multi-channel serial / deserialization circuit.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a serial / deserialization circuit is provided, including a first receiving channel and a second receiving channel; the first receiving channel includes a clock data recovery circuit and a first serial-to-parallel conversion circuit; the second receiving channel includes a second serial-to-parallel conversion circuit; the first serial-to-parallel conversion circuit is used to receive first serial data and perform analog-to-digital conversion and serial-to-parallel conversion; the second serial-to-parallel conversion circuit is used to receive second serial data and perform analog-to-digital conversion and serial-to-parallel conversion; the clock data recovery circuit is used to obtain a first clock signal from the first serial data and output the first clock signal to the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit.

[0007] The serial / deserialization circuit provided in this application embodiment uses the first clock signal recovered by the clock data recovery circuit of the first receiving channel through the second receiving channel. As long as there is always serial data in the first receiving channel, the second receiving channel can perform analog-to-digital conversion and serial-to-parallel conversion on the received second serial data without having to establish a link. Therefore, the link establishment time of the multi-channel serial / deserialization circuit can be shortened.

[0008] In one possible implementation, the first clock signal serves as the sampling clock for the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit during analog-to-digital conversion. That is, multiple receiving channels can share the clock signal of a single receiving channel for analog-to-digital conversion.

[0009] In one possible implementation, the second receiving channel further includes a clock skew cancellation circuit. This circuit detects the clock skew between the clock signal of the second serial data and the first clock signal, and delays the first clock signal based on the clock skew to output a first clock signal with the clock skew eliminated to the second serial-to-parallel conversion circuit. Using a clock skew cancellation circuit allows the second serial-to-parallel conversion circuit to obtain a more accurate first clock signal.

[0010] In one possible implementation, the clock skew cancellation circuit includes a phase detector and a delay chain circuit. The phase detector is used to detect the clock skew between the clock signal of the second serial data and the first clock signal, and the delay chain circuit is used to delay the first clock signal according to the clock skew. This application does not limit the structure of the delay chain circuit; for example, it can be a delay chain circuit composed of gate circuits or a delay chain circuit composed of D flip-flops, etc.

[0011] In one possible implementation, the second serial-to-parallel conversion circuit includes: an analog front-end equalizer, a comparator, and a deserializer; the analog front-end equalizer is used to equalize the high and low frequency energy of the second serial data; the comparator is used to sample the equalized second serial data according to a first clock signal to perform analog-to-digital conversion on the second serial data to obtain digital second serial data; the deserializer is used to perform serial-to-parallel conversion on the digital second serial data to obtain second parallel data. That is, the second receiving channel may only include the second serial-to-parallel conversion circuit.

[0012] In one possible implementation, the data transmission rates of the first and second receiving channels are the same. To prevent clock asynchrony, the two receiving channels must share the same clock signal when their data transmission rates are identical.

[0013] In one possible implementation, there are multiple second receiving channels, the number of which is determined by the transmission bandwidth. This aims to meet the transmission bandwidth requirements while minimizing power consumption.

[0014] In a second aspect, a serial data receiving method is provided, applied to a serial / deserialization circuit as described in the first aspect. The method includes: a first serial-to-parallel conversion circuit of a first receiving channel receiving first serial data and performing analog-to-digital conversion and serial-to-parallel conversion; a second serial-to-parallel conversion circuit of a second receiving channel receiving second serial data and performing analog-to-digital conversion and serial-to-parallel conversion; and a clock data recovery circuit of the first receiving channel obtaining a first clock signal from the first serial data and outputting the first clock signal to the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit.

[0015] In one possible implementation, the first clock signal serves as the sampling clock for analog-to-digital conversion when the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit perform analog-to-digital conversion.

[0016] In one possible implementation, the method further includes: a clock deviation elimination circuit of the second receiving channel detects the clock deviation between the clock signal of the second serial data and the first clock signal, and delays the first clock signal according to the clock deviation, so as to output the first clock signal after eliminating the clock deviation to the second serial-to-parallel conversion circuit.

[0017] In one possible implementation, the second serial-to-parallel conversion circuit of the second receiving channel receives the second serial data, performs analog-to-digital conversion and serial-to-parallel conversion to output the second parallel data, including: an analog front-end equalizer of the second serial-to-parallel conversion circuit equalizes the high and low frequency energy of the second serial data; a comparator of the second serial-to-parallel conversion circuit samples the equalized second serial data according to a first clock signal to perform analog-to-digital conversion on the second serial data to obtain the second serial data in digital form; and a deserializer of the second serial-to-parallel conversion circuit performs serial-to-parallel conversion on the digital second serial data to obtain the second parallel data.

[0018] Thirdly, a chip is provided, including a serial / deserialization circuit and a data receiving module as described in the first aspect and any embodiment thereof. The serial / deserialization circuit is used to receive serial data and then send parallel data to the data receiving module. Depending on the application scenario of the chip, the data receiving module also has different functions. For example, when the chip is used as a system-on-chip (SOC) of a terminal device (e.g., a mobile phone), the data receiving module can be a core; when the chip is used as a storage chip, the data module can be a cache or a storage array; when the chip is used as a transceiver chip, the data receiving module can be a baseband, etc.

[0019] The technical effects of the second and third aspects refer to the technical effects of the first aspect and any of its embodiments. Attached Figure Description

[0020] Figure 1 A schematic diagram of a multi-channel SerDes provided in an embodiment of this application;

[0021] Figure 2 A schematic diagram of the structure of a receiving end of a receiving channel provided in an embodiment of this application. Figure 1 ;

[0022] Figure 3 A schematic diagram of the structure of a receiving end of a receiving channel provided in an embodiment of this application. Figure 2 ;

[0023] Figure 4 A schematic diagram of a serial / deserialization circuit provided in this application embodiment. Figure 1 ;

[0024] Figure 5A schematic diagram of a serial / deserialization circuit provided in this application embodiment. Figure 2 ;

[0025] Figure 6 A schematic diagram of a serial / deserialization circuit provided in this application embodiment. Figure 3 ;

[0026] Figure 7 A schematic diagram of a serial / deserialization circuit provided in this application embodiment. Figure 4 ;

[0027] Figure 8 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0028] As used herein, the terms “component,” “module,” “system,” etc., are intended to refer to a computer-related entity, which may be hardware, firmware, a combination of hardware and software, software, or running software. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a running thread, a program, and / or a computer. As an example, an application running on a computing device and the computing device itself can both be components. One or more components may reside in a running process and / or thread, and components may be located in a single computer and / or distributed among two or more computers. Furthermore, these components are capable of execution from various computer-readable media having various data structures thereon. These components may communicate locally and / or remotely via signals, such as based on one or more data packets (e.g., data from a component that interacts with a local system, another component in a distributed system, and / or signals that interact with other systems via a network such as the Internet).

[0029] First, some concepts related to serialization / deserialization that may be involved in this application will be described:

[0030] Serial / deserialization technology is a high-speed interface technology used for inter-chip communication. The transmitting end converts parallel data into serial data for transmission, and the receiving end converts the received serial data back into parallel data. The path that serial data travels from the transmitting end to the receiving end is called the channel, which can be implemented through components or structures such as chip packaging, printed circuit board (PCB) traces, vias, cables, and connectors.

[0031] Serial / deserial transmission does not have a separate clock line; the clock signal is embedded in the transition edges of the serial data. When the receiver receives serial data, its clock data recovery (CDR) circuit captures the frequency of the serial data's transition edges to recover the clock signal. If the data does not transition for a long time, the CDR circuit cannot be accurately trained, and the CDR's sampling time will drift, potentially sampling more "0"s or "1"s than the actual data. Therefore, the transmitter can use 8b / 10b encoding or scrambling when sending serial data to avoid excessively long consecutive "0"s or "1"s in the serial data, ensuring that transition edges appear quickly.

[0032] The receiving end takes a long time to recover the clock signal embedded in the transition edge of the serial data stream. In order to speed up the recovery process, the transmitting end can send a training sequence in a specific format according to the protocol before sending valid data. This allows the receiving end's CDR circuit to quickly recover the clock signal based on the training sequence. When subsequent serial data is received, the CDR circuit can continuously output the clock signal by locking the transition edge of the serial data.

[0033] After recovering the clock signal, the receiving end aligns the recovered clock signal with the transition edge of the serial data, and then samples the serial data in the middle of the transition edge to realize the analog-to-digital conversion of the serial data to obtain the digital serial data. Then, the digital serial data is converted from serial to parallel to obtain the digital parallel data.

[0034] As mentioned earlier, in a multi-channel serial / deserial circuit, during the switch from single-channel to multi-channel transmission, the receiving end first needs to recover the clock signals of each channel from the data transmitted from multiple channels to establish the link between them. Therefore, the first step is to combine... Figures 1-3 This will explain the clock recovery principle of a multi-channel serial / deserial circuit.

[0035] Figure 1 A serial / deserialization circuit is illustrated, in which a first chip 11 and a second chip 12 transmit data through N channels at the physical layer. Each channel of the chips includes a transmitter (TX) and a receiver (RX). For a single channel, the transmitter of one chip is connected to the receiver of another chip. Data transmission in each channel is independent, and the transmission and reception of a single channel are also independent. N channels represent N times the transmission bandwidth.

[0036] like Figure 2 and Figure 3As shown, the receiver RX of a channel includes an analog front end (AFE) equalizer 21, a slicer 22, a demultiplexer (DMUX) 23, and a clock data recovery (CDR) circuit 24.

[0037] The AFE equalizer 21 is used to equalize the high and low frequency energy of the input analog serial data and amplify the effective signal, thereby improving the signal-to-noise ratio (SNR).

[0038] Comparator 22 is used to sample the equalized analog serial data according to the level segment based on the clock signal output by CDR circuit 24, thereby converting the analog serial data into digital serial data.

[0039] The DMUX 23 is used to perform serial-to-parallel conversion on digital serial data, thereby converting digital serial data into digital parallel data.

[0040] Since serial / deserial communication lacks an accompanying clock, during the initial link establishment process, the CDR circuit 24 recovers the clock signal from the serial data by tracking and locking the phase deviation of the serial data. This clock signal serves as the sampling clock for comparator 22 to sample the analog serial data. Additionally, if there is a frequency deviation between the clock sources of the two chips, the CDR circuit 24 is also used to track and lock the frequency deviation of the serial data. Therefore, the locking time during the link establishment process is relatively long.

[0041] CDR circuit 24 can be implemented in multiple ways:

[0042] like Figure 2 As shown, in one possible implementation, the CDR circuit 24 includes a phase detector (PD) 241, a digital low-pass filter (DLPF) 242, and a clock generator (CKG) 243.

[0043] Specifically, PD 241 detects the phase of serial data by detecting its transition edges, which indicates the direction of clock signal adjustment, such as forward or backward. DLPF 242 slows down the transitions of serial data through integration (filtering) to prevent feedback loop jitter; adjusting the parameters of DLPF 242 allows for rapid phase locking of the serial data within the channel. CKG 243 adjusts the phase of the clock signal according to its adjustment direction; the clock signals generated by CKG 243 for each channel are independent.

[0044] like Figure 3 As shown, in another possible implementation, the CDR circuit 24 includes a phase detector (PD) 241, a digital low-pass filter (DLPF) 242, and a phase interpolator (PI) 244.

[0045] The functions of PD 241 and DLPF 242 are described above. PI 244 is used to adjust the phase of the clock signal according to the adjustment direction. The PI 244 of each channel generates the clock signal based on the same global phase-locked loop (PLL), relative to... Figure 2 Using independent CKG 243 for each channel can reduce the power consumption of multi-channel transmission.

[0046] This serial / deserialization circuit can change the number of data transmission channels according to different transmission bandwidths. For example, in the default low transmission bandwidth scenario, the two chips can communicate using a single channel; when a burst of high transmission bandwidth is required, the two chips can switch to multi-channel communication. The total number of channels can be determined based on the maximum transmission bandwidth; for example, four channels are typically used.

[0047] Since the demand for high transmission bandwidth is sudden and usually short-lived, during the switching from single-channel to multi-channel, the receiving end must first recover the clock signals of each channel from the serial data transmitted by the multi-channel in order to complete the link establishment of each channel. Therefore, the time spent recovering the clock signals of each channel (or the channel with the slowest clock signal recovery) will affect the efficiency of the entire system under high transmission bandwidth.

[0048] In addition, electronic devices (such as mobile phones) are very sensitive to power consumption, and the power consumption of multi-channel transmission will increase accordingly. Therefore, it is also crucial to reduce the power consumption during multi-channel transmission.

[0049] Therefore, embodiments of this application provide a serial / deserialization circuit and chip that enables rapid recovery of the clock signals of each receiving channel by having multiple receiving channels share the clock signal output by the CDR of a single receiving channel, and can reduce the power consumption of multi-channel transmission.

[0050] like Figure 4 and Figure 5As shown, the serial / deserialization circuit 40 in the chip includes: a first receiving channel 41 and a second receiving channel 42. The first receiving channel 41 includes a first serial-to-parallel conversion circuit 411 and a CDR circuit 412. The second receiving channel 42 includes a second serial-to-parallel conversion circuit 421, optionally, as... Figure 6 and Figure 7 As shown, the second receiving channel 42 may further include a clock skew cancellation circuit 422. The serial / deserialization circuit 40 is used to perform the following serial data receiving method:

[0051] The first serial-to-parallel conversion circuit 411 receives first serial data in analog form, performs analog-to-digital conversion and serial-to-parallel conversion to output first parallel data in digital form.

[0052] The second serial-to-parallel conversion circuit 421 receives the second serial data in analog form, performs analog-to-digital conversion and serial-to-parallel conversion to output the second parallel data in digital form.

[0053] The CDR circuit 412 locks and recovers a stable first clock signal from the first serial data by tracking the phase and frequency deviations, and outputs the first clock signal to the first serial-to-parallel conversion circuit 411 and the second serial-to-parallel conversion circuit 421. That is, the CDR circuit 412 outputs the first clock signal to the first comparator 4112 of the first serial-to-parallel conversion circuit 411 and the second comparator 4212 of the second serial-to-parallel conversion circuit 421. The first clock signal serves as the sampling clock when the first comparator 4112 of the first serial-to-parallel conversion circuit 411 performs analog-to-digital conversion on the first serial data; the first clock signal also serves as the sampling clock when the second comparator 4212 of the second serial-to-parallel conversion circuit 421 performs analog-to-digital conversion on the second serial data.

[0054] like Figure 4 and Figure 5 As shown, the first serial-to-parallel conversion circuit 411 includes a coupled first AFE equalizer 4111, a first comparator 4112, and a first deserializer (DMUX) 4113.

[0055] The first AFE equalizer 4111 is used to equalize the high and low frequency energy of the analog first serial data, amplifying the effective signal without amplifying the noise, thereby improving the SNR. The first comparator 4112 is used to sample the analog first serial data according to the first clock signal output by the CDR circuit 412, thereby performing analog-to-digital conversion on the analog first serial data to obtain digital first serial data. The first deserializer 4113 is used to perform serial-to-parallel conversion on the digital first serial data, thereby converting the digital first serial data into digital first parallel data.

[0056] like Figure 4As shown, the CDR circuit 412 includes PD 4121, DLPF 4122, CKG 4123, or, as... Figure 5 As shown, the CDR circuit 412 includes PD 4121, DLPF 4122 and PI 4124.

[0057] PD 4121 is used to detect the phase of the first serial data by detecting the transition edge of the first serial data. This phase can indicate the adjustment direction of the first clock signal, such as forward or backward. DLPF 4122 is used to slow down the transition of the first serial data through integration (filtering) to prevent feedback loop jitter. By adjusting the parameters of DLPF 242, the phase of the first serial data in this channel can be quickly locked. CKG 4123 is used to adjust the phase of the first clock signal according to the adjustment direction of the first clock signal's phase. PI 4124 is used to adjust the phase of the first clock signal according to the adjustment direction of the first clock signal's phase. CDR circuit 412 can generate the first clock signal independently through CKG 4123, or it can generate the first clock signal based on PLL through PI 4124.

[0058] like Figure 4 and Figure 5 As shown, the second serial-to-parallel conversion circuit 421 includes a coupled second AFE equalizer 4211, a second comparator 4212, and a second deserializer (DMUX) 4213.

[0059] The second AFE equalizer 4211 is used to equalize the high and low frequency energy of the analog second serial data, amplifying the effective signal without amplifying noise, thereby improving the SNR. The second comparator 4212 is used to sample the analog second serial data according to the first clock signal output by the CDR circuit 412, thereby performing analog-to-digital conversion on the analog second serial data to obtain digital second serial data. The second deserializer 4213 is used to perform serial-to-parallel conversion on the digital second serial data, thereby converting the digital second serial data into digital second parallel data.

[0060] The data transmission rates of the first receiving channel 41 and the second receiving channel 42 are the same. The first receiving channel 41 serves as a reference receiving channel and has a complete CDR circuit. Since the phase and frequency deviations generated by the peer TX and the transmission channel have been tracked and locked by the CDR circuit of the first receiving channel 41, the second receiving channel 42 serves as a slave receiving channel and does not need to have a CDR circuit. Instead, it reuses the first clock signal output by the CDR circuit of the first receiving channel 41 to sample the received second serial data.

[0061] It should be noted that the second receiving channel 42 is not limited to one; there can be multiple channels, meaning that multiple second receiving channels can use the clock signal output by the CDR circuit in the first receiving channel.

[0062] The clock skew cancellation circuit 422 is used to detect the clock skew between the clock signal of the second serial data and the first clock signal, and delays the first clock signal according to the clock skew to output the first clock signal after clock skew cancellation to the second comparator 4212 of the second serial-to-parallel conversion circuit 421. Since the physical distance and wiring between the communication pins of the two chips are similar, and the transmission channels of different channels between the two chips are similar, the clock skew between the two receiving channels is very small. Therefore, the clock skew cancellation circuit 422 is optional, and using the clock skew cancellation circuit 422 can enable the second serial-to-parallel conversion circuit 421 to obtain a more accurate first clock signal.

[0063] like Figure 6 and Figure 7 As shown, the clock skew elimination circuit 422 includes a phase detector 4221 and a delay chain circuit 4222. The phase detector 4221 detects the clock skew between the clock signal of the second serial data and the first clock signal. The delay chain circuit 4222 delays the first clock signal according to the clock skew, so as to output the first clock signal after clock skew elimination to the second comparator 4212 of the second serial-to-parallel conversion circuit 421. This application does not limit the structure of the delay chain circuit; for example, it can be a delay chain circuit composed of gate circuits or a delay chain circuit composed of D flip-flops, etc.

[0064] The working principle of the serial / deserialization circuit 40 is as follows:

[0065] By default, the system enters single-channel mode. The serial / deserialization circuit 40 receives the first serial data through the first receiving channel 41 and obtains (locks and recovers) the first clock signal from the first serial data. Unless there is a sudden demand for high transmission bandwidth, the first receiving channel 41 remains operational.

[0066] If there is a sudden demand for high transmission bandwidth, the serial / deserialization circuit 40 keeps the first receiving channel 41 operating and starts the second receiving channel 42. This allows the first receiving channel 41 to receive the first serial data, lock and recover the first clock signal, and the second comparator 422 in the second receiving channel 42 to directly sample the received second serial data based on the first clock signal to obtain a digital signal, without first locking and recovering the clock signal of the second receiving channel from the second serial data. The number of second receiving channels 42 that can be started can be determined according to the transmission bandwidth, such as starting one, two, or three second receiving channels 42, etc., to meet the transmission bandwidth requirements while minimizing power consumption.

[0067] like Figure 8 As shown, this application embodiment also provides a chip 80, including the serial / deserialization circuit 81 and the data receiving module 82 described above. The serial / deserialization circuit 81 is used to receive serial data and then send parallel data to the data receiving module 82. Depending on the application scenario of the chip, the data receiving module 82 also has different functions. For example, when the chip is used as a system-on-chip (SOC) of a terminal device (e.g., a mobile phone), the data receiving module 82 can be the core; when the chip is used as a storage chip, the data module 82 can be a cache or storage array; when the chip is used as a transceiver chip, the data receiving module 82 can be a baseband, etc.

[0068] The serial / deserialization circuit, serial data receiving method, and chip provided in this application embodiment reuse the first clock signal recovered by the CDR circuit of the first receiving channel through the second receiving channel. As long as there is always serial data in the first receiving channel, the second receiving channel can perform analog-to-digital conversion and serial-to-parallel conversion on the received second serial data without having to establish a link. Therefore, the link establishment time of the multi-channel serial / deserialization circuit can be shortened.

[0069] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A serial / deserialization circuit, characterized in that, It includes a first receiving channel and a second receiving channel; the first receiving channel includes a clock data recovery circuit and a first serial-to-parallel conversion circuit; the second receiving channel includes a second serial-to-parallel conversion circuit. The first serial-to-parallel conversion circuit is used to receive the first serial data and perform analog-to-digital conversion and serial-to-parallel conversion; The second serial-to-parallel conversion circuit is used to receive the second serial data and perform analog-to-digital conversion and serial-to-parallel conversion; The clock data recovery circuit is used to obtain a first clock signal from the first serial data and output the first clock signal to the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit. The second receiving channel further includes a clock skew elimination circuit, which is used to detect the clock skew between the clock signal of the second serial data and the first clock signal, and delay the first clock signal according to the clock skew, so as to output the first clock signal after eliminating the clock skew to the second serial-to-parallel conversion circuit.

2. The circuit according to claim 1, characterized in that, The clock skew elimination circuit includes a phase detector and a delay chain circuit. The phase detector is used to detect the clock skew between the clock signal of the second serial data and the first clock signal. The delay chain circuit is used to delay the first clock signal according to the clock skew.

3. The circuit according to claim 2, characterized in that, The delay chain circuit is a delay chain circuit composed of gate circuits or a delay chain circuit composed of D flip-flops.

4. The circuit according to claim 1, characterized in that, The second serial-to-parallel conversion circuit includes: an analog front-end equalizer, a comparator, and a deserializer; the analog front-end equalizer is used to equalize the high and low frequency energy of the second serial data; the comparator is used to sample the equalized second serial data according to the first clock signal to perform analog-to-digital conversion on the second serial data to obtain digital second serial data; the deserializer is used to perform serial-to-parallel conversion on the digital second serial data to obtain second parallel data.

5. The circuit according to claim 1, characterized in that, The data transmission rates of the first receiving channel and the second receiving channel are the same.

6. The circuit according to claim 1, characterized in that, There are multiple second receiving channels, and the number of second receiving channels is determined by the transmission bandwidth.

7. The circuit according to claim 1, characterized in that, The first clock signal serves as the sampling clock for analog-to-digital conversion when the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit perform analog-to-digital conversion.

8. A serial data receiving method, characterized in that, Applied to the circuit as described in any one of claims 1-7, the method comprises: The first serial-to-parallel conversion circuit of the first receiving channel receives the first serial data and performs analog-to-digital conversion and serial-to-parallel conversion. The second serial-to-parallel conversion circuit of the second receiving channel receives the second serial data and performs analog-to-digital conversion and serial-to-parallel conversion. The clock data recovery circuit of the first receiving channel obtains the first clock signal from the first serial data and outputs the first clock signal to the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit; The clock deviation elimination circuit of the second receiving channel detects the clock deviation between the clock signal of the second serial data and the first clock signal, and delays the first clock signal according to the clock deviation, so as to output the first clock signal after eliminating the clock deviation to the second serial-to-parallel conversion circuit.

9. The method according to claim 8, characterized in that, The second serial-to-parallel conversion circuit of the second receiving channel receives the second serial data, performs analog-to-digital conversion and serial-to-parallel conversion to output the second parallel data, including: The analog front-end equalizer of the second serial-to-parallel conversion circuit equalizes the high and low frequency energy of the second serial data; The comparator of the second serial-to-parallel conversion circuit samples the equalized second serial data according to the first clock signal to perform analog-to-digital conversion on the second serial data to obtain the second serial data in digital form; The deserializer of the second serial-to-parallel conversion circuit performs serial-to-parallel conversion on the second serial data in digital form to obtain the second parallel data.

10. The method according to claim 8 or 9, characterized in that, The first clock signal serves as the sampling clock for analog-to-digital conversion when the first serial-to-parallel conversion circuit and the second serial-to-parallel conversion circuit perform analog-to-digital conversion.

11. A chip, characterized in that, It includes a serial / deserialization circuit and a data receiving module as described in any one of claims 1-7, wherein the serial / deserialization circuit is used to receive serial data and then send parallel data to the data receiving module.

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