Methods for adjusting equalizer parameters, methods and devices for sending training sequences.

Abstract

This application provides a method for adjusting equalizer parameters, a method for transmitting training sequences, and an apparatus, belonging to the field of communication technology. This application adds fixed code pattern data to the training sequence. Because the fixed code pattern data amplifies and superimposes the inter-symbol interference (ISI) at the trailing point, it reduces the technical difficulty of measuring ISI at the trailing point, thus determining the ISI at the trailing point with higher accuracy. Therefore, adjusting the equalizer parameters based on the ISI can effectively improve the accuracy of parameter adjustment.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method for adjusting equalizer parameters, a method for transmitting training sequences, and an apparatus. Background Technology

[0002] An equalizer is a parameter-adjustable filter used in a communication system. A typical function of an equalizer is to reduce inter-symbol interference (ISI). Adaptive equalization is a technique that automatically adjusts the equalizer's parameters based on channel characteristics. By adjusting the equalizer's parameters based on adaptive equalization, the equalizer can adapt to dynamic changes in channel characteristics, thereby improving its performance.

[0003] A typical method for adjusting equalizer parameters using adaptive equalization technology is as follows: The transmitter sends a training sequence, which is a string of random data, to the receiver. After processing the training sequence using the equalizer, the receiver measures the interference level of each data signal in the training sequence on each subsequent data signal. The receiver then adjusts the equalizer parameters based on the magnitude of the interference.

[0004] When using the above method, the accuracy of equalizer parameter adjustment is poor. Summary of the Invention

[0005] This application provides a method for adjusting equalizer parameters, a method for sending training sequences, and an apparatus, which can improve the accuracy of equalizer parameter adjustment. The technical solution is as follows.

[0006] Firstly, a method for adjusting equalizer parameters is provided. This method, for example, is applied at the receiving end of a training sequence. Specifically, the method includes: acquiring a training sequence processed by a first equalizer; determining a first position of fixed-code data in the training sequence; determining inter-symbol interference (ISI) generated by the fixed-code data at a second position; and adjusting the parameters of the first equalizer based on the ISI. The training sequence includes fixed-code data, and the second position is a position following the first position in the training sequence.

[0007] The above method adds fixed code pattern data to the training sequence. Since the fixed code pattern data amplifies and superimposes the inter-symbol interference at the trailing point, it reduces the technical difficulty of measuring the inter-symbol interference at the trailing point. Therefore, the accuracy of the inter-symbol interference at the trailing point is higher. Thus, adjusting the equalizer parameters according to the inter-symbol interference can effectively improve the accuracy of parameter adjustment.

[0008] The principle behind using fixed-code data to amplify and superimpose inter-symbol interference at the tail is based on the principle of linear systems: the signal received by the receiver is the convolution of the signal transmitted by the transmitter and the channel impulse response. After the flat portion (i.e., the low-frequency portion) of the channel impulse response is convolved with the transmitted signal, the high-frequency portion of the transmitted signal is filtered out, while the low-frequency portion is preserved. In classic training sequences, the signal strength (probability) at various frequencies is essentially the same. If the proportion of low-frequency signals is increased in the training sequence, the low-frequency response of the channel in the received signal will be enhanced, thus amplifying the error caused by the channel impulse response tail.

[0009] Fixed-pattern data refers to data whose pattern remains unchanged over multiple unit time periods. The waveform of a signal carrying fixed-pattern data is similar to that of direct current, approximating a straight line. Here, the unit time period is, for example, a unit interval (UI), where one UI represents the time length corresponding to one bit. For example, fixed-pattern data can be a string of consecutive 1s or a string of consecutive 0s.

[0010] Optionally, the second position mentioned above is not a position within the fixed code pattern data. For example, the second position mentioned above is a position within random data. For example, the first position is the position of the last bit of the fixed code pattern data, after which random data begins, and the second position is one bit within the random data.

[0011] Optionally, the fixed pattern data includes at least four consecutive identical data units (UIs). For example, the fixed pattern data is at least four consecutive 0 bits, or at least four consecutive 1 bits.

[0012] Optionally, fixed-code pattern data and random data alternate in the training sequence. In one possible implementation, the training sequence sequentially includes a first data segment of fixed-code pattern data, random data, a second data segment of fixed-code pattern data, and random data. For example, the training sequence includes at least 4 bits of consecutive 1-random data followed by at least 4 bits of consecutive 0-random data.

[0013] Optionally, the position (first position) of the fixed code pattern data in the training sequence is determined by searching the training sequence once or multiple times to identify the position with the highest probability of containing the fixed code pattern data, which is then used as the first position. In one possible implementation, template matching is used to determine the first position. Specifically, each consecutive symbol segment in the training sequence is compared with pre-saved fixed code pattern data to obtain the probability that each consecutive symbol segment contains the fixed code pattern data, and the segment with the highest probability is used as the first position. In another possible implementation, a method similar to binary search is used to determine the first position. Specifically, the training sequence is divided into multiple subsequences, and the number of consecutive 1s (or 0s) in each subsequence is counted. It is then determined whether the number of consecutive 1s (or 0s) in each subsequence exceeds a set number. If the number of consecutive 1s (or 0s) in a subsequence exceeds the set number, the fixed code pattern data is determined to belong to that subsequence. The subsequence is then further divided, and the number of consecutive 1s (or 0s) is counted again. This process is repeated until the first position is finally located.

[0014] The parameters of the first equalizer are, for example, the degeneration resistor (Rs) or the degeneration capacitor (Cs).

[0015] Optionally, the method for determining the inter-symbol interference generated by the fixed code pattern data at the second position, that is, the method for determining the tailing error caused by the fixed code pattern data, includes: determining the inter-symbol interference based on the correlation between the voltage of the data at the second position and the reference voltage.

[0016] The above method can convert the voltage of the data from an analog signal to a digital decision result, which is convenient for statistical analysis using counters, thus greatly reducing the difficulty of statistical analysis of inter-symbol interference and reducing the complexity of implementation.

[0017] Optionally, the reference voltage includes a first reference voltage and a second reference voltage, the voltage values ​​of the first reference voltage and the second reference voltage are not equal, and the tailing error caused by the fixed code pattern data is determined in the following way: using the first reference voltage as a decision threshold, the data at the second position is compared to obtain a first decision result; using the second reference voltage as a decision threshold, the data at the second position is compared to obtain a second decision result; the total number of identical values ​​in the first decision result and the second decision result is taken as the first total number; the total number of non-identical values ​​in the first decision result and the second decision result is taken as the second total number; inter-symbol interference is determined based on the first total number and the second total number, wherein inter-symbol interference is positively correlated with the first total number and negatively correlated with the second total number.

[0018] The above method can accurately determine the inter-symbol interference at the tail, effectively solving the problem of the inability to effectively measure the noise intensity of inter-symbol interference.

[0019] Optionally, the parameters of the first equalizer can be adjusted as follows: if the inter-symbol interference is less than a set interference threshold, decrease the parameters of the first equalizer; if the inter-symbol interference is greater than the set interference threshold, increase the parameters of the first equalizer; if the inter-symbol interference is equal to the set interference threshold, keep the parameters of the first equalizer unchanged.

[0020] The above methods help to solve the problems of insufficient or excessive equalization by the equalizer and improve the channel equalization performance of the equalizer.

[0021] Optionally, the training sequence is obtained by processing the first equalizer and the second equalizer. The training sequence also includes random data. The receiving end also adjusts the parameters of the second equalizer according to the error corresponding to one or more sign bits in the random data.

[0022] Random data can be, for example, a pseudo-random sequence. For instance, random data can be 56 bits of random 0s or 1s.

[0023] In the above method, the error brought by random data is used to adjust the parameters of the second equalizer, and the error brought by fixed code pattern data is used to adjust the parameters of the first equalizer. This ensures that the parameter adjustment processes of the first and second equalizers do not interfere with each other, supports the coexistence of the first and second equalizers, and facilitates the simultaneous parameter adjustment of the two equalizers.

[0024] Optionally, one or more sign bits in the random data include a first sign bit, and the adjustment method of the parameters of the second equalizer includes: adjusting the parameters of the second equalizer according to the correlation between the error corresponding to the first sign bit and the sign value, wherein the sign value is the value of the sign bit before the first sign bit in the random data, and the parameters of the second equalizer are negatively correlated with the correlation.

[0025] The above method can decouple the functions of the first equalizer and the second equalizer, avoiding mutual interference between them, and thus allowing for more precise adjustment of the parameters of the first equalizer and the second equalizer.

[0026] Optionally, the parameters of the second equalizer are adjusted by adjusting the parameters of the m-th tap of the second equalizer according to the correlation between the error corresponding to the i-th sign bit and the sign value at the (im)-th sign bit, where i and m are both positive integers.

[0027] Optionally, the distance between the second position and the first position is greater than N symbols, where N is the number of taps in the second equalizer.

[0028] In the above method, the second equalizer is responsible for eliminating the inter-symbol interference generated by the fixed code pattern data on the subsequent N symbol bits, while the first equalizer is responsible for eliminating the inter-symbol interference generated by the fixed code pattern data starting from the N+1th symbol on the subsequent symbol bits. This decouples the functions of the first equalizer and the second equalizer. Since the influence of the channel equalization of the second equalizer is hardly introduced when adjusting the parameters, the parameters of the first equalizer can be adjusted more accurately.

[0029] Optionally, the second position is the (N+1)th sign bit after the first position.

[0030] The above method can ensure the accuracy of parameter adjustment, while avoiding the huge computational overhead caused by detecting inter-symbol interference at a large number of locations.

[0031] Optionally, the length ratio between fixed code pattern data and random data in the training sequence is 1:7.

[0032] For example, in a typical training frame of 128 bits, there are 8 bits of 11111111 (fixed pattern data), followed by 56 bits of random 0 or 1 (random data), followed by 8 bits of 00000000 (fixed pattern data), and finally 56 bits of random 0 or 1 (random data).

[0033] The above method ensures a reasonable ratio of fixed code pattern data to random data, avoiding an excessively small proportion of fixed code pattern data that would increase training time, while also avoiding an excessively large proportion of fixed code pattern data that would weaken the randomness of the training sequence.

[0034] Optionally, the length of the fixed code pattern data is between 4 bits and 16 bits.

[0035] By using the above length for fixed pattern data, it is helpful to avoid the effect of fixed pattern data being weakened due to excessively short fixed pattern data length, while avoiding the impact of excessively long fixed pattern data on data randomness and the convergence of clock data recovery (CDR).

[0036] Optionally, the fixed code pattern data includes a first data segment and a second data segment, wherein the second data segment is the data obtained by inverting each bit in the first data segment.

[0037] The first data segment is, for example, a data segment consisting of at least four consecutive 1s, and the second data segment is, for example, a data segment consisting of at least four consecutive 0s. Optionally, the content of the first data segment includes one 0, and the rest of the content of the first data segment is 1; the content of the second data segment includes one 1, and the rest of the content of the second data segment is 0. Alternatively, the content of the first data segment includes two 1s, and the rest of the content of the first data segment is 0; the content of the second data segment includes two 0s, and the rest of the content of the second data segment is 1.

[0038] The above method balances the number of 0s and 1s, that is, makes the number of 0s and 1s in the fixed code data approximately the same, thereby eliminating the direct current (DC) offset of the signal.

[0039] Optionally, the second equalizer mentioned above is a decision feedback equalizer (DFE).

[0040] Optionally, the first equalizer mentioned above is a continuous-time linear equalizer (CTLE).

[0041] The above method can support application scenarios of serializers and deserializers (SERDES).

[0042] Secondly, a method for transmitting a training sequence is provided. In this method, a training sequence is generated, which includes fixed code pattern data. The fixed code pattern data is located at a first position in the training sequence. Inter-symbol interference generated by the fixed code pattern data at a second position is used to adjust the parameters of a first equalizer. The second position is the position after the first position in the training sequence. The first equalizer is the equalizer set in the receiving end of the training sequence. The training sequence is then transmitted.

[0043] The above method adds fixed code pattern data to the training sequence. Since the fixed code pattern data amplifies and superimposes the inter-symbol interference at the trailing point, it reduces the technical difficulty of measuring the inter-symbol interference at the trailing point. Therefore, the accuracy of the inter-symbol interference at the trailing point is higher. Thus, adjusting the equalizer parameters according to the inter-symbol interference can effectively improve the accuracy of parameter adjustment.

[0044] Optionally, the first position is the position of the last bit of the fixed code pattern data, and the second position is the position of the random data in the training sequence.

[0045] Optionally, the training sequence also includes random data, where the error corresponding to one or more sign bits in the random data is used to adjust the parameters of the second equalizer, which is the equalizer set at the receiving end of the training sequence.

[0046] In the above method, the error brought by random data is used to adjust the parameters of the second equalizer, and the error brought by fixed code pattern data is used to adjust the parameters of the first equalizer. This ensures that the parameter adjustment processes of the first and second equalizers do not interfere with each other, supports the coexistence of the first and second equalizers, and facilitates the simultaneous parameter adjustment of the two equalizers.

[0047] Optionally, the length ratio between fixed code pattern data and random data in the training sequence is 1:7.

[0048] The above length ratio can better balance training time and data randomness, and has wider applicability.

[0049] Optionally, the length of the fixed code pattern data is between 4 bits and 16 bits.

[0050] By using the above length for fixed pattern data, it is helpful to avoid the effect of fixed pattern data being weakened due to excessively short fixed pattern data length, while avoiding the impact of excessively long fixed pattern data on data randomness and the convergence of clock data recovery (CDR).

[0051] Optionally, the fixed code pattern data includes a first data segment and a second data segment, wherein the second data segment is the data obtained by inverting each bit in the first data segment.

[0052] The above method balances the number of 0s and 1s, that is, makes the number of 0s and 1s in the fixed code data approximately the same, thereby eliminating the direct current (DC) offset of the signal.

[0053] Thirdly, an equalizer parameter adjustment device is provided, which has the function of implementing the first aspect or any optional method of the first aspect. The equalizer parameter adjustment device includes at least one unit, which is used to implement the method provided by the first aspect or any optional method of the first aspect.

[0054] Fourthly, a training sequence transmitting apparatus is provided, which has the function of implementing the second aspect or any optional method of the second aspect described above. The training sequence transmitting apparatus includes at least one unit for implementing the method provided by the second aspect or any optional method of the second aspect.

[0055] In some embodiments, the units in the training sequence transmitting device are implemented in software, and the units in the training sequence transmitting device are program modules. In other embodiments, the units in the training sequence transmitting device are implemented in hardware or firmware. Specific details of the training sequence transmitting device provided in the fourth aspect can be found in the second aspect or any alternative to the second aspect described above, and will not be repeated here.

[0056] Fifthly, an electronic device is provided, comprising a processor and a first equalizer, the processor being configured to execute instructions causing the electronic device to perform the method provided in the first aspect or any alternative method of the first aspect, and the first equalizer being configured to process a training sequence.

[0057] Optionally, the electronic device also includes a second equalizer. The second equalizer works in conjunction with the first equalizer to process the obtained training sequence.

[0058] Specific details of the electronic equipment provided in the fifth aspect can be found in the first aspect or any alternative to the first aspect mentioned above, and will not be repeated here.

[0059] In a sixth aspect, an electronic device is provided, comprising a processor and a communication interface. The processor is configured to execute instructions causing the electronic device to perform the method provided in the second aspect or any alternative method thereof, and the communication interface is configured to transmit training sequences. Specific details of the electronic device provided in the sixth aspect can be found in the second aspect or any alternative method thereof, and will not be repeated here.

[0060] In a seventh aspect, a computer-readable storage medium is provided, the storage medium storing at least one instruction that, when executed on a computer, causes the computer to perform the method provided in the first aspect or any alternative method of the first aspect.

[0061] Eighthly, a computer-readable storage medium is provided, the storage medium storing at least one instruction that, when executed on a computer, causes the computer to perform the method provided in the second aspect or any alternative method of the second aspect.

[0062] Ninthly, a computer program product is provided, comprising one or more computer program instructions that, when loaded and executed by a computer, cause the computer to perform the method provided in the first aspect or any alternative method of the first aspect.

[0063] In a tenth aspect, a computer program product is provided, comprising one or more computer program instructions that, when loaded and executed by a computer, cause the computer to perform the method provided in the second aspect or any alternative method of the second aspect.

[0064] Eleventhly, a chip is provided, including a memory and a processor, the memory for storing computer instructions, and the processor for calling and executing the computer instructions from the memory to perform the methods of the first aspect and any possible implementation thereof.

[0065] In a twelfth aspect, a chip is provided, including a memory and a processor, the memory for storing computer instructions and the processor for retrieving and executing the computer instructions from the memory to perform the method provided in the second aspect or any alternative method of the second aspect.

[0066] In a thirteenth aspect, a communication system is provided, which includes an equalizer parameter adjustment device (as described in the third aspect) and a training sequence transmission device (as described in the fourth aspect).

[0067] In the fourteenth aspect, a communication system is provided, which includes electronic devices from the fifth aspect and electronic devices from the sixth aspect.

[0068] In a fifteenth aspect, an equalizer parameter adjustment device is provided, which can be provided as a receiver for training sequences, such as a SERDES receiver. The equalizer parameter adjustment device includes: a first equalizer, a fixed-code data positioning circuit, an error detection circuit, and an equalizer parameter adjustment circuit. Each piece of hardware in the equalizer parameter adjustment device is used to implement the method provided in the first aspect or any optional embodiment of the first aspect. Optionally, the equalizer parameter adjustment device further includes a second equalizer and a least mean square (LMS) adjustment circuit.

[0069] In a sixteenth aspect, a training sequence transmitting apparatus is provided, which can be provided as a transmitter of training sequences, such as a SERDES transmitter. The training sequence transmitting apparatus includes a training sequence generator and a transmitting circuit. The hardware components in this apparatus are used to implement the method provided in the first aspect or any alternative method of the first aspect.

[0070] In a seventeenth aspect, a communication system is provided, comprising the means of the fifteenth aspect and the means of the sixteenth aspect, the communication system being provided as SERDES. Attached Figure Description

[0071] Figure 1 This is a schematic diagram of an inter-symbol interference phenomenon provided in an embodiment of this application;

[0072] Figure 2 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application;

[0073] Figure 3 This is a flowchart of a method for adjusting equalizer parameters provided in an embodiment of this application;

[0074] Figure 4 This is a schematic diagram of a training sequence format provided in an embodiment of this application;

[0075] Figure 5 This is an architecture diagram of a SERDES system provided in an embodiment of this application;

[0076] Figure 6 This is a schematic diagram of a data positioning waveform provided in an embodiment of this application;

[0077] Figure 7 This is a schematic diagram of the structure of a training sequence sending device provided in an embodiment of this application;

[0078] Figure 8 This is a schematic diagram of the structure of an equalizer parameter adjustment device provided in an embodiment of this application. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0080] The following explains some terms and concepts involved in the embodiments of this application.

[0081] (1) Training sequence

[0082] A training sequence is a data sequence used to adjust the parameters of the equalizer at the receiver. The training sequence is carried in the data frames transmitted by the transmitter. For example, in a data frame transmitted by the transmitter, the frame header carries the training sequence, followed by the service data. The training sequence occupies one or more consecutive symbols in the data frame. The functions of the training sequence include, but are not limited to, training at the receiver (i.e., adjusting the equalizer parameters), channel estimation, etc.

[0083] (2) Code pattern

[0084] A code pattern refers to the waveform of a signal that represents data. This signal includes, but is not limited to, radio frequency signals in wireless communication, electrical signals or optical signals in wired communication, etc. For example, a high level represents data "1", and a low level represents data "0". Such waveforms of high and low levels constitute a code pattern.

[0085] (3) Fixed code pattern data

[0086] Fixed-pattern data refers to data whose pattern remains unchanged over multiple unit time periods. This unit time period is, for example, a unit interval (UI), where one UI represents the time length corresponding to one bit. Optionally, fixed-pattern data is binary data.

[0087] From the perspective of data content, fixed-code data has multiple consecutive bits whose values ​​remain unchanged. For example, fixed-code data has N consecutive bits whose values ​​are all 1, or N consecutive bits whose values ​​are all 0, where N is a positive integer greater than or equal to 2.

[0088] Optionally, each bit in the fixed-pattern data has the same value. For example, the fixed-pattern data is a string of consecutive 1s; or the fixed-pattern data is a string of consecutive 0s. As a specific example, the fixed-pattern data is 11111111. Alternatively, most bits in the fixed-pattern data have the same value, and a small number of bits with different values ​​are allowed. For example, there may be 1 or 2 bits with different values ​​in the fixed-pattern data, while the remaining bits have the same value. As a specific example, the fixed-pattern data is 11111101.

[0089] From the perspective of signal waveforms, the waveform of a signal carrying fixed-code data is similar to that of direct current, approximating a straight line over multiple time units. For example, the waveform of a signal carrying fixed-code data may be at a high level for multiple time units; conversely, it may be at a low level for multiple time units.

[0090] Optionally, the fixed pattern data includes at least four consecutive identical data units (UIs). For example, the fixed pattern data is at least four consecutive 0 bits, or at least four consecutive 1 bits.

[0091] (4) Inter-symbol interference (ISI)

[0092] Inter-symbol interference (ISI) refers to the distortion and broadening of symbol waveforms caused by suboptimal channel characteristics. This distortion results in long tails in the waveforms of previous symbols that extend to the sampling time of the current symbol, thus interfering with the decision-making process for that symbol. For example, ... Figure 1 As shown, when the transmitting end sends a high-level signal (digital signal 1), it will continuously pull the subsequent signal level higher after passing through the channel; conversely, when the transmitting end sends a low-level signal (digital signal 0), it will pull the subsequent signal level lower after passing through the channel.

[0093] (5) Equalizer

[0094] An equalizer is a filter with adjustable parameters. Equalizers are typically placed at the receiver end of a communication system, usually operating within the baseband signal processing unit or intermediate frequency (IF) signal processing unit. The typical function of an equalizer is to reduce or even eliminate inter-symbol interference (ISI). The basic principle behind this ISI reduction is that the equalizer produces characteristics approximately opposite to the channel characteristics, thereby compensating for channel distortion and correcting warped waveforms. These characteristics are manifested through the equalizer's parameters.

[0095] (6) Judgments and Judgment Thresholds

[0096] Decision-making is a process of comparing the voltage of data with a decision threshold. A typical implementation of decision-making is to compare the voltage of the data with the decision threshold; if the voltage is greater than the decision threshold, the decision result is set to 1; if the voltage is less than or equal to the decision threshold, the decision result is set to 0. The decision threshold refers to the reference voltage used in the decision-making process. The decision threshold is also called the decision limit.

[0097] (7) Continuous-time linear equalizer (CTLE)

[0098] A CTLE is an analog equalizer. CTLEs can be implemented using active or passive circuitry. The function of a CTLE is equivalent to a combination of a high-pass filter and an amplifier. The basic principle of a CTLE is that when a signal is received from a channel, the CTLE first amplifies the entire signal proportionally, and then filters the amplified signal through a high-pass filter. When the signal passes through the CTLE, low-frequency components are attenuated more, while high-frequency components are attenuated less, thus compensating for the loss of high-frequency components.

[0099] (8) Decision Feedback Equalizer (DFE)

[0100] A DFE (Digital Equalizer) is a type of digital equalizer. A DFE consists of a finite impulse response (FIR) filter, an adder, and a decision unit. The typical function of a DFE is to enhance high-frequency components, increasing the energy ratio between high-frequency and low-frequency components.

[0101] (9) Serializer / deserializer (SERDES)

[0102] SERDES is a high-speed serial interface in a chip. SERDES is used in serial wired communication systems. SERDES consists of two components: a transmitter and a receiver. The transmitter and receiver of a SERDES are typically located in two separate physical devices. The transmitter of a SERDES includes a feed-forward equalizer (FFE). The receiver of a SERDES includes a CTLE and a DFE. Typically, when the receiver of a SERDES receives a signal, it first processes the signal through the CTLE, then processes the signal output from the CTLE through the DFE, and finally samples and decides on the signal output from the DFE to obtain the data carried by the signal.

[0103] In SERDES systems, data signals typically attenuate during transmission through the channel. In the frequency domain, this attenuation follows a pattern: higher frequency signals attenuate more, while lower frequency signals attenuate less. In the time domain, this attenuation means that a standard digital pulse signal transmitted by the transmitter is received as a broadened signal after passing through the channel. For example, see attached... Figure 1 As shown, attached Figure 1 It is a signal waveform diagram. (Attached) Figure 1 In the two waveforms shown, one represents the digital pulse signal transmitted by the transmitter, and the other represents the signal received by the receiver. This channel-widened signal can interfere with adjacent signals; this noise generated by interference between transmitted data is called inter-symbol interference (ISI). The technique for eliminating ISI is called channel equalization, which adjusts the intensity of high-frequency and low-frequency signals to be consistent.

[0104] In a SERDES system, commonly used modules for channel equalization include FFE, DFE, and CTLE. FFE and DFE are digital circuit-based equalization filters, while CTLE is an analog circuit-based equalization filter. As the data transmission rate of SERDES continues to increase, channel attenuation and inter-symbol interference also increase. Therefore, all three equalization methods appear in mainstream SERDES systems. Among the three equalization methods, CTLE typically plays a key equalization role in SERDES systems due to its simple implementation, low power consumption, and strong equalization capabilities. However, because CTLE is a purely analog circuit-based equalizer, compared to digital equalizers like FFE and DFE, CTLE currently lacks an effective automatic adjustment algorithm and strategy to adapt to channel characteristics. This problem has long been a challenge and pain point for SERDES systems.

[0105] In view of this, this embodiment proposes a new and effective method for adjusting the CTLE equalizer parameters in a SERDES system. Alternatively, this method can be applied to scenarios where parameters of equalizers other than CTLE are adjusted. Alternatively, this method can be applied to wired or wireless communication systems other than SERDES systems.

[0106] The following are examples illustrating the application scenarios of embodiments of this application.

[0107] Appendix Figure 2 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application. (Attached) Figure 2 The application scenarios shown include the first device 200 and the second device 210. These application scenarios include, for example, wireless network communication scenarios or wired network communication scenarios. The typical product forms, internal components, and connection relationships of the first device 200 and the second device 210 are illustrated below.

[0108] (1) First equipment 200

[0109] The first device 200 can be any device with wireless or wired communication capabilities. The product form of the first device 200 includes many variations. Optionally, the first device 200 can be a user device. For example, the first device 200 can be a tablet computer, desktop computer, laptop computer, notebook computer, Ultra-mobile Personal Computer (UMPC), handheld computer, netbook, Personal Digital Assistant (PDA), mobile phone, or other internet-connected user device. Alternatively, the first device 200 can be an IoT node in the Internet of Things (IoT) or an in-vehicle communication device in the Internet of Vehicles (IoV). Optionally, the first device 200 can be a communication server, router, switch, bridge, or other communication entity. Alternatively, the first device 200 can include various forms of macro base stations, micro base stations, relay stations, etc. The first device 200 can optionally be a complete device, or a chip or processing system installed in a complete device. Devices with these chips or processing systems installed can implement the methods and functions of the embodiments of this application under the control of these chips or processing systems.

[0110] The first device 200 includes at least one processor 201, a memory 202, and a communication interface 203.

[0111] Processor 201 may be, for example, a general-purpose central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the embodiments of this application. For example, processor 201 may include an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. A PLD may be, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0112] Memory 202 may be, for example, read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; electrically erasable programmable read-only memory (EEPROM); compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.); magnetic disk storage media or other magnetic storage devices; or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Optionally, memory 202 exists independently and is connected to processor 201 via internal connection 204. Alternatively, memory 202 and processor 201 may be integrated together.

[0113] Optionally, the memory 202 stores program code 206 related to the method for transmitting the training sequence provided in the embodiments of this application. Optionally, the memory 202 is used to store fixed code pattern data.

[0114] Communication interface 203 uses any transceiver-like device for communicating with other devices or communication networks. Communication interface 203 includes, for example, at least one of a wired communication interface or a wireless communication interface. The wired communication interface is, for example, an Ethernet interface. The Ethernet interface is, for example, an optical interface, an electrical interface, or a combination thereof. The wireless communication interface is, for example, a wireless local area network (WLAN) interface, a cellular communication interface, or a combination thereof.

[0115] (2) Second equipment

[0116] The second device 210 can be any device with wired or wireless communication capabilities. The product form of the second device 210 includes many variations. Optionally, the second device 210 can be a user device. For example, the second device 210 can be a tablet computer, desktop computer, laptop computer, ultra-mobile personal computer (UMPC), handheld computer, netbook, personal digital assistant (PDA), mobile phone, or other internet-connected user device. Alternatively, the second device 210 can be an IoT node in the Internet of Things (IoT) or an in-vehicle communication device in the Internet of Vehicles (IoV). Optionally, the second device 210 can be a communication server, router, switch, bridge, or other communication entity. Alternatively, the second device 210 can include various forms of macro base stations, micro base stations, relay stations, etc. The second device 210 can optionally be a complete device, or a chip or processing system installed in a complete device. Devices with these chips or processing systems installed can implement the methods and functions of the embodiments of this application under the control of these chips or processing systems.

[0117] The second device 210 includes at least one processor 211, a memory 212, and a communication interface 213.

[0118] Processor 211 may be, for example, a general-purpose central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the embodiments of this application. For example, processor 211 may include an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. A PLD may be, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0119] Memory 212 may be, for example, read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; electrically erasable programmable read-only memory (EEPROM); compact disc read-only memory (CD-ROM) or other optical disc storage; optical disc storage (including compressed discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.); magnetic disk storage media or other magnetic storage devices; or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Optionally, memory 212 exists independently and is connected to processor 211 via internal connection 214. Alternatively, memory 212 and processor 211 may be integrated together.

[0120] Optionally, the memory 212 stores program code 216 related to the method for adjusting equalizer parameters provided in the embodiments of this application.

[0121] The communication interface 213 includes a first equalizer 2131. Optionally, the communication interface 213 also includes a second equalizer 2132. Both the first equalizer 2131 and the second equalizer 2132 are used for channel equalization to eliminate or reduce the effects of inter-symbol interference. Optionally, the first equalizer 2131 is an equalizer implemented using analog circuitry. Optionally, the second equalizer 2132 is an equalizer implemented using digital circuitry. The first equalizer 2131 or the second equalizer 2132 includes, but is not limited to, a time-domain equalizer or a frequency-domain equalizer. The first equalizer 2131 or the second equalizer 2132 includes, but is not limited to, a linear equalizer or a nonlinear equalizer. The first equalizer 2131 or the second equalizer 2132 includes, but is not limited to, a linear transverse equalizer, a linear character equalizer, a decision feedback equalizer, or a fractional interval equalizer.

[0122] Communication interface 213 uses any transceiver-like device for communicating with other devices or communication networks. Communication interface 213 includes, for example, at least one of a wired communication interface or a wireless communication interface. The wired communication interface is, for example, an Ethernet interface. The Ethernet interface is, for example, an optical interface, an electrical interface, or a combination thereof. The wireless communication interface is, for example, a wireless local area network (WLAN) interface, a cellular communication interface, or a combination thereof.

[0123] (3) Connection relationship between the first device and the second device

[0124] The first device and the second device are connected via a path. This path is implemented through a wired network and / or a wireless network. A wired network may be, for example, a network based on electrical signal communication or a network based on optical signal communication. A wireless network may be, for example, a network based on radio frequency signal communication.

[0125] Optional, attached Figure 2 The application scenario shown is specifically a SERDES system. The first device acts as the transmitter in the SERDES system; it is also called the serializer. The second device acts as the receiver in the SERDES system; it is also called the deserializer. The first device includes an FFE or other equalizer. The first equalizer 2131 in the second device is a CTLE. The second equalizer in the second device is a DFE.

[0126] The method flow of the embodiments of this application is illustrated below.

[0127] Appendix Figure 3 This is a flowchart illustrating a method for adjusting equalizer parameters according to an embodiment of this application. (Attached) Figure 3 The method shown includes the following steps S301 to S307.

[0128] Appendix Figure 3 The method illustrated involves interaction between multiple devices. To distinguish between the different devices, they are described as "first device," "second device," etc. (Appendix) Figure 3 The method shown mainly concerns how the second device adjusts the parameters of the equalizer using the training sequence sent by the first device.

[0129] Appendix Figure 3 The embodiment shown does not limit the order of the various steps (S303 to S306) executed by the receiving end. In other words, S303 to S306 are not necessarily executed in sequence, and the execution order of S303 to S306 can also be interchanged.

[0130] Appendix Figure 3 The scenarios on which the method shown is based may optionally be as follows: Figure 2 As shown. For example, in conjunction with the appendix Figure 2 Let's take a look, attached Figure 3 The first device in the method shown is an attachment Figure 2 The first device in the middle, 200, attached Figure 3 The second device in the method shown is an accessory. Figure 2 The second device 210. (Attached) Figure 3 The first equalizer in the method shown is an auxiliary equalizer. Figure 2 The first equalizer 2131 in the middle, with Figure 3 The second equalizer in the method shown is an auxiliary equalizer. Figure 2 The second equalizer 2132 in the system.

[0131] Appendix Figure 3 The method shown can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. In one possible implementation, the processor 211 in the second device implements the auxiliary... Figure 3 In the method shown, steps S303 to S307, or the processor 211 implements the attached program code through internal storage. Figure 3 Steps S303 to S307 in the method shown. In another possible implementation, the physical structure of the processor 211 is designed using hardware-based algorithm implementation, making the processor 211 a dedicated hardware accelerator for adjusting equalizer parameters. The processor 211 independently completes steps S303 to S307, or the processor 211 cooperates with the CPU to complete steps S303 to S307. For example, the processor 211 executes steps S303 to S305 according to the CPU's instructions and sends the determined inter-symbol interference to the CPU. The CPU is responsible for executing step S306.

[0132] Step S301: The first device generates a training sequence, which includes fixed code pattern data.

[0133] There are multiple ways for the first device to obtain fixed code data. The following examples illustrate how implementation method a and implementation method b can be used.

[0134] Implementation method a. The fixed code pattern data is preset.

[0135] For example, administrators can configure fixed code pattern data for the first device via command line, user interface, or other means, and the first device can generate training sequences based on the pre-configured fixed code pattern data.

[0136] Implementation method b. Fixed code pattern data is determined through negotiation.

[0137] For example, the first device pre-sends multiple candidate fixed-code pattern data to the second device. The second device selects one fixed-code pattern data from the multiple candidate fixed-code pattern data and sends the selected fixed-code pattern data back to the first device. The first device generates the aforementioned training sequence based on the fixed-code pattern data selected by the second device. As another example, when the second device needs to train an equalizer, the second device actively sends fixed-code pattern data to the first device, and the first device generates the aforementioned training sequence based on the fixed-code pattern data sent by the second device.

[0138] The above describes how to obtain fixed code pattern data. The following section provides examples of the specific data structure for fixed code pattern data.

[0139] In some embodiments, the fixed-code data includes a first data segment and a second data segment. The second data segment is the data obtained by inverting each bit in the first data segment. In other words, the first data segment and the second data segment are inverted versions of each other. Specifically, if the value of the i-th bit in the first data segment is 0, the value of the i-th bit in the second data segment is 1; if the value of the i-th bit in the first data segment is 1, the value of the i-th bit in the second data segment is 0. By setting the first data segment and the second data segment, the number of 0s and 1s is balanced, that is, the number of 0s and 1s in the fixed-code data is approximately equal, thereby eliminating the direct current (DC) offset of the signal.

[0140] Optionally, each bit in the first data segment is equal to 1, and each bit in the second data segment is equal to 0. For example, please refer to the appendix. Figure 4 , attached Figure 4 P_DC_SEG (positive direct current segment) is a specific example of the first data segment. (See attached image.) Figure 4 N_DC_PATTERN (negative direct current segment) is a specific example of the second data segment. (See attached image.) Figure 4 RANDOM_SEG in the example is a specific instance of random data. P_DC_SEG is eight 11111111, N_DC_SEG is eight 00000000, and 00000000 is the data obtained by inverting each bit of 11111111.

[0141] Optionally, the fixed-code pattern data is located at the beginning of the training frame. In one possible implementation, the first data segment in the fixed-code pattern data is located from the 1st bit to the nth bit in the training frame, where n is the length of the first data segment. For example, please refer to the appendix. Figure 4A training frame's header contains eight 11111111 (the first data segment in the fixed-pattern data). By using this method, the receiver, upon receiving the training frame, can more quickly locate the fixed-pattern data starting from the first bit of the training frame. Alternatively, the fixed-pattern data can be located at the end of the training frame. Alternatively, the fixed-pattern data can be located at the center of the training frame. Alternatively, the fixed-pattern data can be located at a predetermined position in the training frame, such as the position sent from the receiver to the transmitter, or a position pre-configured by administrators at both the receiver and transmitter. For example, the receiver announces the identifier of position i to the transmitter, and after receiving the identifier of position i, the transmitter sets the bits starting from the i-th bit in the training frame as the fixed-pattern data.

[0142] Alternatively, the first data segment primarily contains 1s, with a small number of 0s allowed. The second data segment primarily contains 0s, with a small number of 1s allowed. In one possible implementation, the first data segment contains one 0, and the rest of the first data segment contains 1s; the second data segment contains one 1, and the rest of the second data segment contains 0s. For example, the first data segment is 11111101, and the second data segment is 00000010. Another example is the first data segment being 11111011, and the second data segment being 00000100.

[0143] In another possible implementation, the first data segment contains two 1s, and the rest of the content is 0; the second data segment contains two 0s, and the rest of the content is 1. For example, the first data segment is 11110101, and the second data segment is 00001010. By including a small number of 0s in the first data segment and a small number of 1s in the second data segment, it is helpful to train the sequence matching channel for cases with reflection points, thus helping the scheme support more scenarios.

[0144] Optionally, the training sequence also includes random data. In some embodiments, the random data is a pseudo-random sequence. In some embodiments, the random data is binary data. For example, please refer to the appendix. Figure 4 , attached Figure 4 RANDOM_SEG in the example is a specific instance of random data, consisting of 56 bits of random 0s or 1s. Since the intensity of random data signals is the same at all frequencies in the spectrum, the signals of random data are closer to the data signals in actual business operations. By setting random data in the training sequence, the data transmission scenarios in actual business operations can be effectively simulated, ensuring that the equalizer parameter adjustments are more closely matched to the actual business scenario, thereby helping to improve the adjustment effect of the parameters.

[0145] There are several ways for the first device to generate random data. Two examples are given below.

[0146] Implementation Method 1: The first device contains a pseudo-random code training sequence generator, which generates random data.

[0147] Method 2: The first device shuffles the business data to obtain random data. Shuffling, for example, involves changing the order of different values ​​in the business data.

[0148] Optionally, after receiving the random data sent by the first device, the second device restores the random data to obtain the service data before it was shuffled.

[0149] Optionally, random data and fixed-code data alternate in the training sequence. In one possible implementation, random data is located between the first and second data segments in the training sequence. For example, please refer to the appendix. Figure 6 The training sequence includes the following data structure: P_DC_SEG (the first data segment in the fixed code pattern data) — RANDOM_SEG (random data) — N_DC_SEG (the second data segment in the fixed code pattern data) — RANDOM_SEG (random data).

[0150] Optionally, the length of the fixed pattern data is between 4 bits and 16 bits. Alternatively, the length of the fixed pattern data can be 4 bits, 8 bits, or 16 bits. For example, in a typical 128-bit training frame, it contains 8 bits of 11111111 (fixed pattern data), followed by 56 bits of random 0 or 1 (random data), then 8 bits of 00000000 (fixed pattern data), and finally 56 bits of random 0 or 1 (random data). Using these lengths helps avoid the fixed pattern data being too short, which would weaken its effectiveness, while also preventing the fixed pattern data from being too long, which would affect the randomness of the data and the convergence of the clock data recovery (CDR) circuit.

[0151] There are several ways to determine the length of the aforementioned fixed-code data. In one possible implementation, the administrator configures the length of the fixed-code data in the first device. In another possible implementation, the first device (sender) and the second device (receiver) determine the length of the fixed-code data through negotiation.

[0152] Optionally, the length ratio between fixed-code data and random data in the training sequence is 1:7. For example, the fixed-code data is 8 bits long, while the random data is 56 bits long. This length ratio better balances training time and data randomness, and has wider applicability.

[0153] Optionally, the random data and fixed-code pattern data are sent cyclically in units of training frames (TFs). Specifically, the training sequence includes one or more consecutive TFs, each TF including random data and fixed-code pattern data. Optionally, the fixed-code pattern data is the same in all TFs within the same training sequence. For example, please refer to the appendix. Figure 4 The training sequence consists of N training frames, namely training frame 1, training frame 2, ..., training frame N. Each training frame in training frame 1, training frame 2, ..., training frame N contains the same P_DC_SEG, and each training frame in training frame 1, training frame 2, ..., training frame N contains the same N_DC_SEG.

[0154] There are several ways to determine the length of the Training Token (TF). In one possible implementation, the administrator configures the TF length in the first device. Alternatively, the first device (transmitter) and the second device (receiver) negotiate to determine the TF length. Optionally, a TF length is 128 bits. By using the above-mentioned length for the TF, the reasonableness of the TF length is ensured, avoiding the situation where an excessively long TF reduces the frequency of fixed-pattern data occurrence, thus increasing training time, while avoiding the situation where an excessively short TF weakens the randomness of the training data.

[0155] Step S302: The first device sends the training sequence.

[0156] Step S303: The second device acquires the training sequence obtained by the first equalizer.

[0157] Step S304: The second device determines the first position of the fixed code pattern data in the training sequence.

[0158] This embodiment involves multiple positions in the training sequence. For clarity, "first position" and "second position" are used to distinguish the different positions in the training sequence. The first position refers to the location of the fixed code pattern data within the training sequence. There are multiple ways to determine this first position. Specifically, since the fixed code pattern data is a low-frequency code pattern, the channel attenuation is minimal, and a stable periodicity occurs. Therefore, by periodically detecting the data, the position of the fixed code pattern data can be locked. The following examples, using implementation methods A and B, illustrate specific methods for determining the first position.

[0159] Implementation method A: Template matching.

[0160] Specifically, the second device pre-stores fixed code pattern data, which can be understood as a template. After acquiring the training sequence, the second device compares each consecutive symbol segment in the training sequence with the pre-stored fixed code pattern data. Through this comparison, the second device obtains the probability that each consecutive symbol segment in the training sequence belongs to the fixed code pattern data. From the training sequence, the second device determines the position with the highest probability and uses this position as the position of the fixed code pattern data (the first position).

[0161] Implementation method B is similar to binary search.

[0162] Specifically, the second device divides the training sequence into multiple subsequences. The second device counts the number of consecutive 1s in each subsequence and determines if this number exceeds a set threshold. If the number of consecutive 1s in a subsequence exceeds the threshold, the fixed-pattern data is identified as belonging to that subsequence. This subsequence is then further divided, and the count of consecutive 1s continues. This process is repeated, narrowing the scope of the count until the fixed-pattern data is identified. Alternatively, the count can be changed from 1s to 0s, for example, counting the number of consecutive 0s in each subsequence of the training sequence.

[0163] By performing the above step S304, the position of the fixed code pattern data is locked. The position of the fixed code pattern data can serve as a reference position, making it easier to locate the position of subsequent data statistics (second position), and thus making it easier to determine inter-symbol interference.

[0164] Step S305: The second device determines the inter-symbol interference generated by the fixed code pattern data at the second position.

[0165] The second position is the position after the fixed code pattern data in the training sequence, that is, the position after the first position mentioned above. The second position is the position where the receiving end (second device) performs error detection.

[0166] Optionally, the distance between the second position and the first position is greater than N symbols. For example, the training sequence includes a total of M symbols, with fixed code pattern data located between the a-th and b-th symbols, and the second position being the position between the (b+N)-th and M-th symbol bits in the training sequence. N is a positive integer. Optionally, N is a positive integer greater than or equal to 2. Optionally, N is the number of taps in the second equalizer.

[0167] The relationship between the position of the fixed code pattern data (first position) and the position of the error statistics (second position) allows the scheme to support a system where the first and second equalizers coexist, improving the overall parameter adjustment effect of both equalizers. The technical principle behind this is that since the first and second equalizers simultaneously equalize the signal, their parameter adjustment processes often interfere with each other, making simultaneous parameter adjustment a technical challenge. In this embodiment, if the second equalizer has N taps, during the reception of the training sequence, the second equalizer is responsible for eliminating inter-symbol interference (ISI) caused by the fixed code pattern data on the subsequent N symbols, while the first equalizer is responsible for eliminating ISI caused by the fixed code pattern data starting from the N+1th symbol on subsequent symbols, thus decoupling the functions of the first and second equalizers. Therefore, during parameter adjustment, the influence of the first and second equalizers can be distinguished. By adjusting the parameters of the first equalizer based on the inter-symbol interference on the subsequent symbol bits starting from N+1 symbols, the parameters of the first equalizer can be adjusted more precisely since the influence of the channel equalization of the second equalizer is hardly introduced during parameter adjustment.

[0168] Optionally, the second position is the (N+1)th symbol bit after the first position. For example, if the fixed code pattern data is located between the a-th and b-th symbols, the second position is the (b+N+1)-th symbol bit in the training sequence. By adopting this method, the computational complexity of the scheme is reduced while almost without reducing the accuracy of parameter adjustment. The technical principle behind this effect is that the inter-symbol interference of the fixed code pattern data to subsequent symbol bits gradually decreases. Among each symbol bit starting from the (N+1)-th symbol bit, the inter-symbol interference on the (N+1)-th symbol bit is the largest and best represents the impact of the overall noise at the tail. Therefore, adjusting the parameters of the first equalizer based on the inter-symbol interference on the (N+1)-th symbol bit can ensure the accuracy of parameter adjustment while avoiding the huge computational overhead caused by detecting inter-symbol interference at a large number of positions.

[0169] Alternatively, the second position includes not only the (N+1)th symbol bit after the first position, but also the symbol bits after the (N+1)th symbol bit. For example, the second device determines the inter-symbol interference of the (N+1)th and (N+2)th symbol bits after the first position, performs an average or summation operation on the two inter-symbol interferences, and adjusts the parameters of the first equalizer based on the operation result.

[0170] In some embodiments, the second device determines inter-symbol interference at the second location based on the correlation between the voltage of the data at the second location and the reference voltage.

[0171] The reference voltage value can optionally be preset. The reference voltage is pre-stored in a second device. Optionally, the reference voltage acts as a decision threshold when determining inter-symbol interference at the second position. In other words, the correlation between the voltage of the data and the reference voltage specifically refers to the numerical relationship between the data voltage and the reference voltage. By adopting the above method, the difficulty of statistically analyzing inter-symbol interference is reduced, and the implementation complexity is decreased. Specifically, the voltage of the data at the second position is an analog signal, and analog signals are difficult to statistically analyze and calculate. However, by using the reference voltage as a decision threshold, the voltage of the data can be converted from an analog signal into a digital decision result, and the digital decision result is easily statistically analyzed using counters, thus greatly reducing the implementation complexity.

[0172] In some embodiments, the reference voltage includes a first reference voltage and a second reference voltage. The voltage values ​​of the first reference voltage and the second reference voltage are not equal. Optionally, the first reference voltage and the second reference voltage may have preset voltage values. Optionally, the functions of the first reference voltage and the second reference voltage may differ. The first reference voltage is used to determine the value of the data at the second position. The first reference voltage is sometimes also referred to as the center level or the "0" level. The function of the first reference voltage is similar to the zero point of a coordinate system; other voltage values ​​within the receiver are relative to the first reference voltage. The second reference voltage is used to determine the positive or negative sign of the data at the second position. The second reference voltage is sometimes also referred to as the desired level or the target level.

[0173] Determining inter-symbol interference (ISI) using the aforementioned first and second reference voltages includes, for example: comparing data at the second position using the first reference voltage as a decision threshold to obtain a first decision result; comparing data at the second position using the second reference voltage as a decision threshold to obtain a second decision result; taking the total number of identical values ​​in the first and second decision results as the first total number; taking the total number of non-identical values ​​in the first and second decision results as the second total number; and determining ISI based on the first and second total numbers. ISI is positively correlated with the first total number and negatively correlated with the second total number. The first decision result indicates the numerical relationship between the voltage of the data at the second position and the first reference voltage. The second decision result indicates the numerical relationship between the data at the second position and the second reference voltage.

[0174] The following example illustrates the process of determining intersymbol interference (ISI) using a formula. Formula 1 below is a concrete example of determining ISI using a first reference voltage and a second reference voltage.

[0175] tail_err=∑M(p_tail_i)*C(p_tail_i)-∑M(n_tail_i)*C(n_tail_i); Formula 1;

[0176] In Formula 1 above, `tail_err` refers to the inter-symbol interference (ISI) generated at the second position of the fixed-pattern data. The physical meaning of `tail_err` is the error caused by the channel impulse response (ISI) tailing noise. `tail` literally means "tail," referring to the second position mentioned above. `err` means "error," referring to the ISI. In `p_tail`, `p` represents P_DC_SEG (the first data segment in the fixed-pattern data). `p_tail` indicates the position where the P_DC_SEG produces the tailing phenomenon; specifically, `p_tail` is the (N+1)th symbol bit after the first data segment. Due to the influence of the channel's ISI, P_DC_SEG will cause the voltage of the data at `p_tail` to be higher than expected. `p_tail_i` represents `p_tail` in the i-th training frame of a training sequence. In `n_tail`, `n` represents N_DC_SEG (the second data segment in the fixed-pattern data). `n_tail` indicates the position where the N_DC_SEG produces the tailing phenomenon; specifically, `n_tail` is the (N+1)th symbol bit after the second data segment. `n_tail_i` represents the `n_tail` in the `i`th training frame of a training sequence. Due to the influence of ISI in the channel, `N_DC_SEG` will cause the data voltage on `n_tail` to be lower than expected. `C` represents the decision result at the center level, i.e., the first decision result mentioned above. In one possible implementation, the process of determining `C` is as follows: determine whether the equalized signal voltage value is greater than 0. If the equalized signal voltage value is greater than 0, then `C = 1`. If the equalized signal voltage value is less than or equal to 0, then `C = -1`. `M` represents the decision result at the desired level, i.e., the second decision result mentioned above. In one possible implementation, `M` is the expected value of the equalized signal voltage when `C = 1` or `C = -1`. Specifically, the signal voltage that is usually decided as `C = 1` or `C = -1` is usually a Gaussian distribution. If the expected mean voltage of this distribution is `v`, then if the equalized signal voltage is greater than `v`, then `M = 1`; if the equalized signal voltage is less than or equal to `v`, then `M = -1`. `*` indicates multiplication. The physical meaning of multiplying `C` and `M` is to calculate the total number of identical values ​​in `M` and `C` minus the total number of different values ​​in `M` and `C`. Specifically, the reference voltage for M is the expected mean of the signal voltage distribution when C = 1 (or C = -1). Therefore, the goal of the above formula is to ensure that the number of M = 1 and M = -1 are the same when C = 1 (or C = -1). ∑ is the summation symbol, and the range of the summation can be optionally set according to requirements, for example, the range of the summation can be an integer multiple of the training frames.

[0177] Step S306: The second device adjusts the parameters of the first equalizer based on the inter-symbol interference generated at the second position according to the fixed code pattern data.

[0178] Optionally, the aforementioned inter-symbol interference is specifically used in scenarios where the degeneration resistor (Rs) and degeneration capacitor (Cs) are adjusted as equalizer parameters.

[0179] In some embodiments, the equalizer parameters are adjusted by setting a threshold for inter-symbol interference (ISI). Specifically, the second device compares the ISI generated at the second location with the set interference threshold. If the ISI is less than the set interference threshold, the second device decreases the parameters of the first equalizer; if the ISI is greater than the set interference threshold, the second device increases the parameters of the first equalizer; if the ISI is equal to the set interference threshold, the second device keeps the parameters of the first equalizer unchanged.

[0180] The aforementioned interference threshold is sometimes referred to as the target error value, expected error value, or anticipated error value. The interference threshold is, for example, a small positive number. The interference threshold can be optionally set based on the specific circuit characteristics of the first equalizer and the second device.

[0181] Adjusting the parameters of the first equalizer using the above method helps improve its channel equalization performance. The principle behind this is that when the first equalizer is under-equalized, the inter-symbol interference (ISI) counted at the second position will be a very large positive number. Therefore, increasing the equalization parameters of the first equalizer—that is, increasing the gain in the high-frequency portion or increasing the attenuation in the low-frequency portion—solves the under-equalization problem. Conversely, when the first equalizer is over-equalized, the ISI counted at the second position will be a random number near 0 with a very small absolute value. In this case, decreasing the equalization parameters of the first equalizer—that is, decreasing the gain in the high-frequency portion or decreasing the attenuation in the low-frequency portion—solves the over-equalization problem.

[0182] Optionally, this embodiment also involves the parameter adjustment process of the second equalizer. Specifically, the training sequence is obtained by processing the first equalizer and the second equalizer. For example, the second device not only uses the fixed code pattern data in the training sequence obtained by the first equalizer and the second equalizer to perform the parameter adjustment process of the first equalizer, but also uses the random data in the training sequence obtained by the first equalizer and the second equalizer to adjust the parameters of the second equalizer. For the specific implementation method, please refer to step S307 below.

[0183] Step S307: The second device adjusts the parameters of the second equalizer according to the error corresponding to one or more sign bits in the random data.

[0184] In some embodiments, the second device determines the parameters of the second equalizer by statistically analyzing the correlation between the error of each received sign bit and the value of each preceding sign bit. For example, the second device adjusts the parameters of the second equalizer based on the correlation between the error corresponding to the first sign bit in the random data and the sign value. Here, the first sign bit is a sign bit in the random data. The sign value is the value of one or more sign bits preceding the first sign bit in the random data. The parameters of the second equalizer are negatively correlated with the correlation.

[0185] In some embodiments, the parameter determination process of the second equalizer specifically includes: the second device adjusting the parameter of the m-th tap of the second equalizer based on the correlation between the error corresponding to the i-th symbol bit and the symbol value at the (im)-th symbol bit. Here, i and m are both positive integers. The principle behind this method is that the product S(in)*E(i) is inversely proportional to the coefficient of the n-th tap of the second equalizer. Here, E(i) is the error of the symbol at the i-th position measured by the receiver, and S(in) represents the symbol value S(in) at the in-th position. Therefore, through the statistical value ∑ of random data... i S(in)E(i) can adaptively adjust the coefficients of the nth tap of the second equalizer.

[0186] In some embodiments, the parameter adjustment process of the second equalizer is implemented using the least mean square (LMS) algorithm. The LMS algorithm is an adaptive equalization algorithm that uses the minimum mean square error as its criterion.

[0187] Optionally, after determining the inter-symbol interference generated by the fixed code pattern data at the second position, the second device also uses the inter-symbol interference at the second position as the noise margin of the system and outputs the noise margin of the system.

[0188] Appendix Figure 3 The illustrated embodiment does not limit the timing of S306 and S307. In some embodiments, S306 and S307 are executed sequentially. For example, S306 is executed first, followed by S307; or S307 is executed first, followed by S306. In other embodiments, S306 and S307 are executed in parallel, that is, the second device executes S306 and S307 simultaneously.

[0189] The method provided in this embodiment adds fixed code pattern data to the training sequence. The fixed code pattern data can amplify and superimpose the inter-symbol interference at the trailing point, thereby reducing the technical difficulty of measuring the inter-symbol interference at the trailing point. Therefore, the accuracy of the determined inter-symbol interference at the trailing point is higher. Thus, adjusting the equalizer parameters according to the inter-symbol interference can effectively improve the accuracy of parameter adjustment.

[0190] The following section will provide a detailed explanation of the technical principles behind improving the accuracy of equalizer parameter adjustment when adding fixed code pattern data to the training sequence.

[0191] When the training sequence consists of random sequences and does not contain fixed code pattern data, the noise intensity of inter-symbol interference (ISI) at each position cannot be effectively measured due to the accuracy of the receiver's decision unit. This is because the ISI at the tail position manifests as the superposition of many small noises; that is, the ISI value of each tap is small, but the sum is very large. Over a large range, the equalizer will cause the ISI at the tail position to be a random number close to zero, making it difficult to obtain accurate equalizer parameters.

[0192] By adding fixed code pattern data to the training sequence, the inter-symbol interference at the tail of the channel impulse response is amplified and superimposed. Specifically, according to the principle of linear systems, the signal received by the receiver is the convolution of the signal transmitted by the transmitter and the channel impulse response. After the flat part of the channel impulse response (i.e., the low-frequency part) is convolved with the transmitted signal, the high-frequency part of the transmitted signal is filtered out, while the low-frequency part is preserved. In a classic training sequence, the signal strength (probability) of various frequency points in the transmitted signal is basically the same. If the proportion of low-frequency signal is increased in the training sequence, the low-frequency response of the channel in the received signal will be enhanced, thus amplifying the error caused by the tail of the channel impulse response.

[0193] Since the inter-symbol interference at the trailing point is amplified, the inter-symbol interference at the trailing point is basically greater than the accuracy of the decision detector, and the inter-symbol interference at the trailing point can be determined more accurately. Therefore, using more accurate inter-symbol interference can obviously adjust the equalizer parameters more accurately.

[0194] The following example illustrates this point. Figure 2 The application scenarios shown and the appendix Figure 3 The method shown is illustrated with an example.

[0195] Please refer to the attached document. Figure 5 , attached Figure 5 This is an architecture diagram of a SERDES system, with attached... Figure 5 It is attached Figure 2 Specific examples.

[0196] Appendix Figure 5 This includes a SERDES system transmitter 500 and a SERDES system receiver 510. The SERDES system transmitter 500 is a specific example of a first device. The SERDES system receiver 510 is a specific example of a second device.

[0197] The transmitter 500 includes a training sequence generator 501. The training sequence generator 501 is an appendix... Figure 2A specific example of processor 201 is provided. (See attached image.) Figure 3 Step S301 in the method shown is implemented, for example, by training the sequence generator 501.

[0198] The training sequence generator 501 is used to generate training sequences. Specifically, the training sequence generator 501 includes a random data generator 5011, a fixed code pattern data memory 5021, and a fixed code pattern data memory 5022.

[0199] The 5011 random code generator is used to generate random data.

[0200] The fixed-code data memory 5021 is used to store the configured fixed-code data P_DC_CODE (positive DC data segment, i.e., the first data segment). The fixed-code data memory 5021 can be, for example, a configurable register, or other memory such as memory, cache, or flash memory.

[0201] Fixed-code data memory 5022 is used to store the configured fixed-code data N_DC_CODE (negative DC data segment, i.e., the second data segment). Fixed-code data memory 5022 and fixed-code data memory 5021 may be different or the same memory. Fixed-code data memory 5022 may be, for example, a configurable register, or other memory such as main memory, cache, or flash memory.

[0202] The receiver 510 includes a receiving circuit 5110, a CTLE 5131, a DFE 5132, an LMS adaptation circuit 5113, a fixed code pattern data positioning circuit 5111, an error detection circuit 5112, and an equalization parameter adjustment circuit 5114.

[0203] The receiving circuit 5110 is used to provide the received data signal to CTLE 5131 and DFE 5132.

[0204] Both CTLE 5131 and DFE 5132 are used for channel equalization. Specifically, the data signal provided by the receiving circuit 5110 is processed by CTLE 5131 and DFE 5132, and then a decision and sampling are performed to obtain a training sequence.

[0205] The fixed-pattern data localization circuit 5111 is used to locate fixed-pattern data in the training sequence, that is, to determine the first position of the fixed-pattern data in the training sequence. For example, combined with the attached... Figure 4 As can be seen, the fixed-code data positioning circuit 5111 realizes the detection and positioning of P_DC_CODE and N_DC_CODE in the training bitstream. (See attached diagram) Figure 3In the method shown, step S304 is implemented, for example, by a fixed code pattern data positioning circuit 5111.

[0206] Error detection circuit 5112 is used to determine the inter-symbol interference generated by the fixed code pattern data at the second position, that is, to determine the error at the tailing point caused by the fixed code pattern data. For example, combined with the attached... Figure 4 The error detection circuit 5112 is used to detect errors caused by interference from P_DC_CODE or N_DC_CODE to adjacent random codes. The error detection circuit 5112 also provides the detected error to the equalization parameter adjustment circuit. (See appendix.) Figure 3 In the method shown, step S305 is implemented, for example, by error detection circuit 5112.

[0207] The equalization parameter adjustment circuit 5114 is used to adjust the parameters of the first equalizer according to intersymbol interference. For example, the equalization parameter adjustment circuit 5114 is used to adjust the CTLE coefficient.

[0208] The LMS adjustment circuit 5113 is used to adjust the parameters of the second equalizer based on the error corresponding to one or more sign bits in the random data. For example, the LMS adjustment circuit 5113 adjusts the DFE coefficient using the classic LMS algorithm. (See appendix) Figure 3 In the method shown, step S307 is implemented, for example, by the LMS adjustment circuit 5113.

[0209] The following describes the method for adjusting the equalizer parameters in the SERDES system. This method includes the following steps (1) to (4).

[0210] Step (1) When the SERDES system is initialized and the equalization parameters are trained, the sending end sends the training sequence.

[0211] The training sequence consists of consecutive training sequences (TFs). Each TF comprises three parts: P_DC_SEG, N_DC_SEG, and RANDOM_SEG. Within a training sequence, all TFs have the same P_DC_SEG and N_DC_SEG.

[0212] The code value of P_DC_SEG is either preset or a code value that needs to be sent as feedback from the receiving end.

[0213] N_DC_SEG is the sequence obtained by inverting each bit of P_DC_CODE.

[0214] RANDOM_SEG is a pseudo-random sequence. RANDOM_SEG can optionally be a pseudo-random sequence generated by a pseudo-random code generator. Alternatively, RANDOM_SEG is a pseudo-random data sequence generated by shuffling some valid data sent to the receiver. In a training data sequence, the data in the RANDOM_SEG of a TF are either pseudo-randomly generated or randomly shuffled data.

[0215] Step (2) The receiver locks the P_DC_SEG position and the N_DC_SEG position.

[0216] Because the data sent by the transmitting end is transmitted cyclically in TF (Folded Array of Numbers), the receiving end periodically detects the received data according to the length of TF. The receiving end performs the following steps S302 to S304 on the received equalized data to adjust the equalization parameters of the CTLE. The equalized data, for example, is obtained by sampling the received signal after it has passed through the CTLE and then through the DFE (Digital Front-End).

[0217] Specifically, because both P_DC_SEG and N_DC_SEG are low-frequency code types, the channel attenuation is minimal, and they exhibit stable periods. Periodic cyclic detection is sufficient to easily lock onto P_DC_SEG / N_DC_SEG. For example, the receiver can use template matching to compare each consecutive symbol segment with P_DC_SEG / N_DC_SEG to find the position with the highest probability. Alternatively, the receiver can count the number of 1s and 0s; sequences containing P_DC_SEG tend to have more 1s, while sequences containing N_DC_SEG tend to have more 0s. By reducing the length of the statistical sequence, the range is narrowed down to ultimately determine the positions of P_DC_SEG and N_DC_SEG. After locking is complete, the receiver obtains the following result: Figure 6 The waveform shown can be used to locate the position of each received bit within the current TF. (Appendix) Figure 6 The waveform of a digital control signal is shown. The horizontal axis is in units of UI or time, and the vertical axis is 0 and 1, with 0 for low voltage and 1 for high voltage.

[0218] The receiving end determines the positions of P_DC_SEG and N_DC_SEG to facilitate the determination of the positions of p_tail and n_tail in step S304, so as to calculate tail_err based on the positions of p_tail and n_tail. Simultaneously, P_DC_SEG / N_DC_SEG can be avoided during DFE coefficient adjustment. This is because P_DC_SEG / N_DC_SEG is non-random data. Although theoretically it has no impact on the adaptive adjustment of DFE coefficients, RANDOM_SEG data is closer to the actual application data because it differs from the actual application data. Therefore, a more suitable approach is to use only RANDOM_SEG for DFE coefficient adjustment, avoiding the influence of P_DC_SEG / N_DC_SEG data.

[0219] Step (3) The receiver adaptively adjusts the parameters of the DFE.

[0220] The data in RANDOM_SEG is a relatively long random sequence. The receiver uses the LMS algorithm to adaptively adjust the parameters of the DFE by statistically analyzing the data in RANDOM_SEG. The LMS algorithm estimates the coefficients of the DFE by statistically analyzing the correlation between the error of each received symbol and the value of each preceding symbol. The principle is that the product of the error (E(i)) of the symbol at the i-th position measured by the receiver and the value S(in) of the symbol at the in-th position, S(in)*E(i), is inversely proportional to the coefficient of the n-th tap of the DFE. Therefore, the coefficients are obtained by statistically analyzing the random sequence ∑... i S(in)E(i) can perform adaptive adjustment of the coefficients of the nth tap of the DFE.

[0221] Step (4) The receiver adaptively adjusts the parameters of CTLE.

[0222] If the DFE has N taps, it can eliminate the interference (ISI) caused by the preceding N symbols in the training bitstream received by the receiver for each symbol. Since the DFE has already eliminated the ISI caused by P_DC_SEG and N_DC_SEG for the subsequent N symbols, the goal of CTLE is to eliminate the ISI impact of P_DC_SEG and N_DC_SEG on subsequent symbol positions starting from position N+1. Because this impact gradually decreases with the trend, the focus is on detecting the error at position N+1. The N+1 position after P_DC_SEG and N_DC_SEG is called p_tail and n_tail. The tail_err is obtained by statistically analyzing the tail data using the above formula.

[0223] After obtaining `tail_err`, considering the influence of channel ISI, `P_DC_SEG` will cause the voltage of the data on `p_tail` to be higher than expected, while `N_DC_SEG` will cause the voltage of the data on `n_tail` to be lower. When CTLE equalization is insufficient, the statistically obtained `tail_err` will be a very large positive number, requiring an increase in the CTLE equalization parameters, i.e., increasing the gain of the high-frequency part or increasing the attenuation of the low-frequency part. When CTLE equalization is excessive, `tail_err` will be a random number near 0 with a very small absolute value, in which case it is necessary to decrease the gain of the high-frequency part or decrease the attenuation of the low-frequency part. When `tail_err` is a stable negative number, it indicates that CTLE equalization is severely excessive. Based on the specific CTLE and the characteristics of the receiver circuit and the number of statistical TFs, a small positive number is set as the target value of `tail_err` for adaptive adjustment of the CTLE equalization parameters.

[0224] Alternatively, the methods provided in the above examples can be applied to SERDES systems where the DFE is off or there is no DFE.

[0225] The method described above provides a novel SERDES training sequence containing both fixed-pattern data and random data. The fixed-pattern data amplifies and superimposes the ISI at the trailing point, effectively amplifying the noise at the ISI tail. Therefore, it solves the technical problems of difficult and inaccurate adaptive adjustment of CTLE parameters. This method not only reduces CTLE training time but also finds the optimal CTLE parameters more accurately, thus effectively improving the adaptive performance of CTLE and enhancing the equalization performance of the SERDES system.

[0226] Appendix Figure 7 This is a schematic diagram of the structure of a training sequence sending device provided in an embodiment of this application.

[0227] Optionally, in conjunction with the appendix Figure 2 Let's take a look, attached Figure 7 The device 700 shown is an accessory. Figure 2 The first piece of equipment is 200. Optionally, in conjunction with the attached... Figure 3 Let's take a look, attached Figure 7 The device 700 shown is used to implement the attached Figure 3 The function of the first device in the method shown. Optionally, in conjunction with the appendix... Figure 5 As you can see, device 700 achieves attached... Figure 5 The function of the 500 transmitter.

[0228] Please refer to the attached document. Figure 7The apparatus 700 includes a generation unit 701 and a transmission unit 702. The generation unit 701 is used to support the apparatus 700 in executing S301. The transmission unit 702 is used to support the apparatus 700 in executing S302.

[0229] Each unit in device 700 is implemented, wholly or partially, through software, hardware, firmware, or any combination thereof. (Appendix) Figure 7 The described device embodiments are merely illustrative. For example, the division of the units described above is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. Appendix Figure 7 The above-mentioned units can be implemented in either hardware or software functional units.

[0230] Optionally, in conjunction with the appendix Figure 5 As can be seen, the generation unit 701 uses the attached... Figure 5 The random code generator 5011, configurable register 5021 and configurable register 5021 are implemented.

[0231] Optionally, in conjunction with the appendix Figure 2 From this perspective, when implemented in software, the aforementioned generation unit 701 can be derived from an attached... Figure 2 The software functional units generated by at least one processor 201 of the first device 200 after reading the program code stored in the memory 202 are implemented. (Appendix) Figure 7 The above-mentioned units can also be attached. Figure 2 Different hardware components are implemented separately, for example, generation unit 701 is attached. Figure 2 A portion of the processing resources (e.g., one or two cores of a multi-core processor) in at least one processor 201 of the first device 200 is used for processing, or by an auxiliary processor. Figure 2 The remaining processing resources of at least one processor 201 in the first device 200 (e.g., other cores in a multi-core processor), or programmable devices such as field-programmable gate arrays (FPGAs) or coprocessors, are used to complete the process. The transmitting unit 702 is attached... Figure 2 The communication interface 203 of the first device 200 is implemented. Obviously, the above functional units can also be implemented by a combination of software and hardware. For example, the sending unit 702 is implemented by a hardware programmable device, while the generating unit 701 is a software functional unit generated by the CPU after reading the program code stored in the memory.

[0232] Appendix Figure 8 This is a schematic diagram of the structure of an equalizer parameter adjustment device provided in an embodiment of this application.

[0233] Optionally, in conjunction with the appendix Figure 2 Let's take a look, attached Figure 7 The device 800 shown is an accessory. Figure 2 The second device 210. Optionally, in conjunction with the attached... Figure 3 Let's take a look, attached Figure 7 The device 800 shown is used to implement the attached Figure 3 The function of the second device in the method shown. Optionally, in conjunction with the appendix... Figure 5 Let's take a look. Device 800 achieves attached... Figure 5 The functions of the receiver 510.

[0234] Please refer to the attached document. Figure 8 The device 800 includes an acquisition unit 801, a determination unit 802, and an adjustment unit 803. The acquisition unit 801 supports the device 800 in executing S303. The determination unit 802 supports the device 800 in executing S304 to S305. The adjustment unit 803 supports the device 800 in executing S306. Optionally, the adjustment unit 803 also supports the device 800 in executing S307.

[0235] Each unit in device 800 is implemented, wholly or partially, through software, hardware, firmware, or any combination thereof. (Appendix) Figure 8 The described device embodiments are merely illustrative. For example, the division of the units described above is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. Appendix Figure 8 The above-mentioned units can be implemented in either hardware or software functional units.

[0236] Optionally, in conjunction with the appendix Figure 5 As you can see, the acquisition unit 801 obtains information through the attached... Figure 5 Implemented by CTLE 5131 and DFE 5132, the determination unit 802 is determined through the attached Figure 5 The detection module 5111 for P_DC_CODE or N_DC_CODE is implemented, and the adjustment unit 803 is connected via an attached... Figure 5 The error detection module 5112 and the LMS adjustment module 5113 at the mid-trailing point are implemented.

[0237] Optionally, in conjunction with the appendix Figure 2From this perspective, when implemented in software, the aforementioned acquisition unit 801, determination unit 802, and adjustment unit 803 can be derived from an attached unit. Figure 2 The software functional units generated by at least one processor 211 of the second device 210 after reading the program code stored in the memory 212 are implemented. Figure 8 The above-mentioned units can also be attached. Figure 2 Different hardware components in the second device 210 are implemented separately; for example, the determining unit 802 is attached. Figure 2 At least a portion of the processing resources of at least one processor 211 (e.g., one or two cores of a multi-core processor) are used for processing, while the adjustment unit 803 is attached by... Figure 2 The remaining processing resources in at least one processor 211 (e.g., other cores in a multi-core processor) are used, or programmable devices such as field-programmable gate arrays (FPGAs) or coprocessors are employed. The acquisition unit 801 may optionally be provided by an attached... Figure 2 The first and second equalizers are implemented in the communication interface 213. Clearly, the above functional units can also be implemented using a combination of software and hardware. For example, the determining unit 802 can be implemented using a hardware programmable device, while the adjusting unit 803 is a software functional unit generated by the CPU after reading the program code stored in memory.

[0238] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. Wherein, "A refers to B" means that A is the same as B or A is a simple variation of B.

[0239] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects, and should not be construed as indicating or implying relative importance. For example, "first equalizer" and "second equalizer" are used to distinguish different equalizers, not to describe a specific order of equalizers, and should not be construed as the first equalizer being more important than the second equalizer.

[0240] In this application, unless otherwise stated, "at least one" means one or more, and "multiple" means two or more. For example, multiple sign bits refer to two or more sign bits.

[0241] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0242] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for adjusting equalizer parameters, characterized in that, The method includes: Obtain a training sequence processed by a first equalizer and a second equalizer, wherein the training sequence includes fixed code pattern data and random data; Determine the first position of the fixed code pattern data in the training sequence; The inter-symbol interference generated by the fixed code pattern data at the second position is determined, where the second position is the position following the first position in the training sequence; Adjust the parameters of the first equalizer according to the inter-symbol interference; The parameters of the second equalizer are adjusted based on the error corresponding to one or more sign bits in the random data.

2. The method according to claim 1, characterized in that, Determining the inter-symbol interference generated by the fixed code pattern data at the second position includes: The inter-symbol interference is determined based on the correlation between the voltage of the data at the second position and the reference voltage.

3. The method according to claim 2, characterized in that, The reference voltage includes a first reference voltage and a second reference voltage, the voltage values ​​of the first reference voltage and the second reference voltage are not equal, and determining the inter-symbol interference based on the correlation between the voltage of the data at the second position and the reference voltage includes: Using the first reference voltage as a decision threshold, the data at the second position is compared to obtain a first decision result; Using the second reference voltage as the decision threshold, the data at the second position is compared to obtain the second decision result; The total number of cases where the median values ​​of the first judgment result and the second judgment result are the same is taken as the first total number; The total number of cases where the values ​​of the first judgment result and the second judgment result are different is taken as the second total number; The inter-symbol interference (ISI) is determined based on the first total number and the second total number, wherein the ISI is positively correlated with the first total number and negatively correlated with the second total number.

4. The method according to claim 1, characterized in that, The step of adjusting the parameters of the first equalizer according to the inter-symbol interference includes: If the inter-symbol interference is less than the set interference threshold, decrease the parameters of the first equalizer; If the inter-symbol interference is greater than the set interference threshold, increase the parameters of the first equalizer; If the inter-symbol interference is equal to the set interference threshold, the parameters of the first equalizer remain unchanged.

5. The method according to claim 1, characterized in that, The random data includes one or more sign bits, including a first sign bit. Adjusting the parameters of the second equalizer based on the error corresponding to one or more sign bits in the random data includes: Based on the correlation between the error corresponding to the first sign bit and the sign value, the parameters of the second equalizer are adjusted, where the sign value is the value of the sign bit before the first sign bit in the random data, and the parameters of the second equalizer are negatively correlated with the correlation.

6. The method according to claim 5, characterized in that, The step of adjusting the parameters of the second equalizer based on the correlation between the error corresponding to the first sign bit and the sign value includes: Based on the correlation between the error corresponding to the i-th sign bit and the sign value at the (im)-th sign bit, adjust the parameter of the m-th tap of the second equalizer, where i and m are both positive integers.

7. The method according to any one of claims 1 to 6, characterized in that, The distance between the second position and the first position is greater than N symbols, where N is the number of taps in the second equalizer.

8. The method according to claim 7, characterized in that, The second position is the (N+1)th sign bit after the first position.

9. The method according to any one of claims 1 to 8, characterized in that, The length ratio between the fixed code pattern data and the random data in the training sequence is 1:

7.

10. The method according to any one of claims 1 to 8, characterized in that, The length of the fixed code pattern data is between 4 bits and 16 bits.

11. The method according to any one of claims 1 to 10, characterized in that, The fixed code pattern data includes a first data segment and a second data segment, wherein the second data segment is the data obtained by inverting each bit in the first data segment.

12. The method according to any one of claims 1 to 9, characterized in that, The second equalizer is a decision feedback equalizer (DFE).

13. The method according to any one of claims 1 to 12, characterized in that, The first equalizer is a continuous-time linear equalizer (CTLE).

14. A method for transmitting a training sequence, characterized in that, The method includes: A training sequence is generated, comprising fixed code pattern data and random data. The fixed code pattern data is located at a first position in the training sequence. Inter-symbol interference generated by the fixed code pattern data at a second position is used to adjust the parameters of a first equalizer. The second position is the position after the first position in the training sequence. The first equalizer is an equalizer set at the receiving end of the training sequence. The error corresponding to one or more sign bits in the random data is used to adjust the parameters of a second equalizer. The second equalizer is an equalizer set at the receiving end of the training sequence. Send the training sequence.

15. The method according to claim 14, characterized in that, The length ratio between the fixed code pattern data and the random data in the training sequence is 1:

7.

16. The method according to any one of claims 14 to 15, characterized in that, The length of the fixed code pattern data is between 4 bits and 16 bits.

17. The method according to any one of claims 14 to 16, characterized in that, The fixed code pattern data includes a first data segment and a second data segment, wherein the second data segment is the data obtained by inverting each bit in the first data segment.

18. The method according to claim 14, characterized in that, The generation of training sequences includes: The training sequence is generated based on the pre-set fixed code pattern data; or, The training sequence is generated based on the fixed code pattern data sent by the receiving end.

19. A device for adjusting equalizer parameters, characterized in that, The device includes: A first equalizer and a second equalizer are used to process the obtained training sequence, which includes fixed code pattern data and random data. A fixed-pattern data positioning circuit is used to determine the first position of the fixed-pattern data in the training sequence; An error detection circuit is used to determine the inter-symbol interference generated by the fixed code pattern data at a second position, where the second position is the position after the first position in the training sequence. An equalization parameter adjustment circuit is used to adjust the parameters of the first equalizer according to the inter-symbol interference. The Least Mean Square (LMS) adjustment circuit is used to adjust the parameters of the second equalizer based on the error corresponding to one or more sign bits in the random data.

20. The apparatus according to claim 19, characterized in that, The error detection circuit is used to determine the inter-symbol interference based on the correlation between the voltage of the data at the second position and the reference voltage.

21. The apparatus according to claim 20, characterized in that, The reference voltage includes a first reference voltage and a second reference voltage, the voltage values ​​of the first reference voltage and the second reference voltage are not equal, and the error detection circuit is used to compare the data at the second position with the first reference voltage as a decision threshold, based on the correlation between the voltage of the data at the second position and the reference voltage, to obtain a first decision result; Using the second reference voltage as the decision threshold, the data at the second position is compared to obtain the second decision result; The total number of cases where the median values ​​of the first judgment result and the second judgment result are the same is taken as the first total number; The total number of cases where the values ​​of the first judgment result and the second judgment result are different is taken as the second total number; The inter-symbol interference (ISI) is determined based on the first total number and the second total number, wherein the ISI is positively correlated with the first total number and negatively correlated with the second total number.

22. The apparatus according to claim 19, characterized in that, The equalization parameter adjustment circuit is used to decrease the parameters of the first equalizer if the inter-symbol interference is less than a set interference threshold; increase the parameters of the first equalizer if the inter-symbol interference is greater than the set interference threshold; and keep the parameters of the first equalizer unchanged if the inter-symbol interference is equal to the set interference threshold.

23. The apparatus according to claim 19, characterized in that, The random data includes one or more sign bits, including a first sign bit. The equalization parameter adjustment circuit is used to adjust the parameters of the second equalizer according to the correlation between the error corresponding to the first sign bit and the sign value. The sign value is the value of the sign bit before the first sign bit in the random data. The parameters of the second equalizer are negatively correlated with the correlation.

24. The apparatus according to claim 23, characterized in that, The equalization parameter adjustment circuit is used to adjust the parameter of the m-th tap of the second equalizer according to the correlation between the error corresponding to the i-th sign bit and the sign value on the (im)-th sign bit, where i and m are both positive integers.

25. The apparatus according to any one of claims 19 to 24, characterized in that, The distance between the second position and the first position is greater than N symbols, where N is the number of taps in the second equalizer.

26. The apparatus according to claim 25, characterized in that, The second position is the (N+20)th sign bit after the first position.

27. The apparatus according to any one of claims 19 to 26, characterized in that, The length ratio between the fixed code pattern data and the random data in the training sequence is 1:

7.

28. The apparatus according to any one of claims 19 to 26, characterized in that, The length of the fixed code pattern data is between 4 bits and 16 bits.

29. The apparatus according to any one of claims 19 to 28, characterized in that, The fixed code pattern data includes a first data segment and a second data segment, wherein the second data segment is the data obtained by inverting each bit in the first data segment.

30. The apparatus according to any one of claims 23 to 28, characterized in that, The second equalizer is a decision feedback equalizer (DFE).

31. The apparatus according to any one of claims 19 to 30, characterized in that, The first equalizer is a continuous-time linear equalizer (CTLE).

32. A device for transmitting training sequences, characterized in that, The device includes: A random code generator is used to generate random data. A training sequence generator is used to generate a training sequence, which includes fixed code pattern data and random data. The fixed code pattern data is located at a first position in the training sequence. Inter-symbol interference generated by the fixed code pattern data at a second position is used to adjust the parameters of a first equalizer. The second position is a position after the first position in the training sequence. The first equalizer is an equalizer set at the receiving end of the training sequence. Errors corresponding to one or more sign bits in the random data are used to adjust the parameters of a second equalizer. The second equalizer is an equalizer set at the receiving end of the training sequence. A transmitting circuit for transmitting the training sequence.

33. The apparatus according to claim 32, characterized in that, The length ratio between the fixed code pattern data and the random data in the training sequence is 1:

7.

34. The apparatus according to any one of claims 32 to 33, characterized in that, The length of the fixed code pattern data is between 4 bits and 16 bits.

35. The apparatus according to any one of claims 32 to 34, characterized in that, The fixed code pattern data includes a first data segment and a second data segment, wherein the second data segment is the data obtained by inverting each bit in the first data segment.

36. The apparatus according to claim 32, characterized in that, The training sequence generator is used to generate the training sequence based on the pre-set fixed code pattern data; or, to generate the training sequence based on the fixed code pattern data sent by the receiving end.

37. An electronic device, characterized in that, The electronic device includes a processor and a first equalizer, the processor being configured to execute instructions causing the electronic device to perform the method as described in any one of claims 1 to 3, and the first equalizer being configured to process a training sequence.

38. An electronic device, characterized in that, The electronic device includes a processor and a communication interface, the processor being configured to execute instructions causing the electronic device to perform the method as described in any one of claims 14 to 18, and the communication interface being configured to transmit training sequences.

39. A communication system, characterized in that, The system includes the electronic device as claimed in claim 37 and the electronic device as claimed in claim 38; or, the system includes the device as claimed in any one of claims 19 to 31 and the device as claimed in any one of claims 32 to 36.

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