Interface device and computing system comprising the same

Abstract

Embodiments of the present invention relate to an interface device and a computing system including the same. An interface device includes a plurality of ports to form a plurality of lanes, and a link controller to set a speed of a link by a manner of determining the speed of the link based on a cause of entering a configuration state of the link including the plurality of lanes.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0040881, filed on April 1, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to an electronic device, and more specifically, to an interface device and a computing system including the interface device. Background Technology

[0004] Peripheral Component Interconnect (PCI) defines a bus protocol for connecting input / output devices to host devices. PCI Fast (PCIe) is used to define the physical communication layer as a high-speed serial interface, while also incorporating programming concepts defined in the PCI standard.

[0005] A storage device is a device that stores data under the control of a host device (such as a computer or smartphone). A storage device can include a memory device for storing data and a memory controller for controlling that memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0006] Volatile memory devices are memory devices that store data only while power is supplied and lose the stored data when the power supply is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0007] Non-volatile memory devices are memory devices whose data is not lost even when the power supply is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0008] Various embodiments of this disclosure provide an interface device and a computing system including the interface device, which can adaptively control the link speed based on the entry factors of the configuration operation during a link setup operation.

[0009] According to one aspect of this disclosure, an interface device is provided, comprising: a plurality of ports configured to form a plurality of channels; and a link controller configured to set the speed of a link by determining the speed of the link based on the reason for entering the configuration state of a link comprising the plurality of channels.

[0010] According to another aspect of this disclosure, a method for operating an interface device is provided, the method comprising: allowing the state of a link connected to an external device to enter a configuration state; and setting the speed of the link by determining the speed of the link based on the state of the link immediately preceding the configuration state.

[0011] According to another aspect of this disclosure, a method for operating an interface device is provided, the method comprising: allowing the state of a link connected to an external device to enter a configuration state; when the state of the link is a sub-state of a recovery state, first determining whether the state of the link should enter the configuration state; and in response to the first determination, secondly determining the speed of the link.

[0012] According to another aspect of this disclosure, a method of operating a device is provided, the method comprising: when configuring a link including multiple channels, setting the speed of the link to a first value based on a first state of the link immediately preceding the configuration; and when configuring the link, setting the speed to a second value based on a second state of the link immediately preceding the configuration. Attached Figure Description

[0013] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, these embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0014] In the accompanying drawings, sizes may be exaggerated for clarity. It is understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Similar reference numerals are used throughout the text to refer to similar elements.

[0015] Figure 1 This is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0016] Figure 2 This is a diagram illustrating a peripheral component interconnect fast (PCIe) device according to an embodiment of the present disclosure.

[0017] Figure 3 This is a diagram illustrating a PCIe interface according to an embodiment of the present disclosure.

[0018] Figure 4 This is a diagram illustrating a transmitter, receiver, and channel according to one embodiment of the present disclosure.

[0019] Figure 5This is a diagram illustrating a differential signal according to an embodiment of the present disclosure.

[0020] Figure 6 This is a diagram illustrating the configuration of a data packet according to an embodiment of the present disclosure.

[0021] Figure 7 This is a diagram illustrating a data flow according to an embodiment of the present disclosure.

[0022] Figure 8 This is a diagram illustrating a port according to an embodiment of the present disclosure.

[0023] Figure 9 This is a diagram illustrating the link state of a PCIe device according to an embodiment of the present disclosure.

[0024] Figure 10 The illustration shows an embodiment according to the present disclosure. Figure 9 The diagram shows the detailed sub-states of the recovery state.

[0025] Figure 11 This is a diagram illustrating a PCIe device according to an embodiment of the present disclosure.

[0026] Figure 12A and Figure 12B This is a diagram illustrating the operation of setting up a link according to an embodiment of the present disclosure.

[0027] Figure 13 This is a flowchart illustrating an operation method of a configuration state according to an embodiment of the present disclosure.

[0028] Figure 14 This is a flowchart illustrating an operation method of the L0 state according to an embodiment of the present disclosure.

[0029] Figure 15 This is a flowchart illustrating an operation method for restoring a state according to another embodiment of the present disclosure. Detailed Implementation

[0030] The specific structural or functional descriptions disclosed herein are merely illustrative of embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0031] Figure 1 This is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0032] refer to Figure 1The computing system 100 may include a CPU 110, a root union 120, a memory 130, a switch 140, peripheral component interconnect fast (PCIe) endpoints 150_1 to 150_3, traditional endpoints 160_1 and 160_2, and a PCIe bridge 170.

[0033] The computing system 100 may be an electronic device that supports communication using a PCIe interface. The computing system 100 may be a PC, a laptop computer, or a mobile computing device, and includes expansion cards, expansion boards, adapter cards, insertion cards, or accessory cards. Additionally, the computing system 100 may include a printed circuit board (PCB) that can be inserted into an electrical connector or expansion slot on the motherboard of the computing system 100 to provide additional functionality to the computing system 100 via an expansion bus. Furthermore, the computing system 100 may include memory devices such as solid-state drives (SSDs), and includes graphics cards, network cards, USB cards, etc.

[0034] The CPU 110 can be electrically connected to each component of the computing system 100 and control every operation of the computing system 100. Specifically, the CPU 110 can control software or hardware components connected to the CPU 110 by driving an operating system or application, and perform various data processing and calculations. In addition, the CPU 110 can execute software or applications for controlling the operation of the computing system 100.

[0035] Root union 120 can be a root hub, controller hub, or root controller in a PCIe interconnect architecture. For example, root union 120 may include a chipset, memory controller hub (MCH), northbridge, interconnect controller hub (ICH), southbridge, and root controller / hub. Additionally, root union 120 can connect CPU 110 and memory 130 to an input / output (I / O) hierarchy. Root union 120 can support peer-to-peer (P2P) routing. Root union 120 may include at least one host bridge and at least one root port. Root union 120 can support at least one PCIe port.

[0036] The memory 130 may store data, commands, or program code required for the operation of the computing system 100. In one embodiment, the memory 130 may store program code for executing one or more operating systems (OS) and one or more virtual machines (VMs), as well as program code for executing a virtualization intermediary (VI) for managing the VMs. Alternatively, the memory 130 may be implemented as a volatile memory device such as DRAM or SRAM.

[0037] Switch 140 can route packets or messages uplink or downlink. Specifically, switch 140 can route packets or messages uplink from a PCIe endpoint (e.g., 150_1) to a layer toward root union 120. Furthermore, switch 140 can route packets or messages downlink from root union 120 to a layer toward a PCIe endpoint (e.g., 150_2).

[0038] Switch 140 can be designated as a logical accessory for multiple virtual PCI to PCI bridge devices. Devices that can be connected to switch 140 can include any internal or external devices or components connected to an electronic system, such as network interface controllers (NICs), plug-in cards, audio processors, network processors, hard drives, storage devices, CD / DVD ROMs, monitors, printers, mice, keyboards, routers, mobile storage devices, FireWire devices, Universal Serial Bus (USB) devices, scanners, and other input / output devices. Although not shown in detail, the device may include PCIe to PCI / PCI-X bridges that support legacy or other versions of PCI devices.

[0039] In one embodiment, root union 120 may be connected to an endpoint. This endpoint may represent a type of functional part capable of being a requester or completer of a PCIe transaction. This endpoint may be classified as a traditional endpoint or a PCIe endpoint.

[0040] PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 can act as requesters or completers of PCIe transactions. Transaction Layer Packets (TLPs) transmitted through PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 can provide a configuration space header. Additionally, PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2, as completers, can provide configuration requests. Under certain conditions, Transaction Layer Packets (TLPs) transmitted through PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 must provide a configuration space header. Furthermore, PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2, as completers, must provide a configuration request.

[0041] PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 can be divided based on the size of the memory transaction. For example, when a memory transaction is likely to exceed 4GB, the endpoints can be PCIe endpoints 150_1 to 150_3. When a memory transaction is unlikely to exceed 4GB, the endpoints can be traditional endpoints 160_1 and 160_2. PCIe endpoints 150_1 to 150_3 cannot generate any I / O requests, but traditional endpoints 160_1 and 160_2 can provide or generate I / O requests. Furthermore, PCIe endpoint 150_3 can transmit TLPs with root union 120. Additionally, PCI / PCI-X can transmit TLPs with root union 120 via PCIe bridge 170. PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2 can transmit TLPs with switch 140.

[0042] PCIe endpoints 150_1 to 150_3 can be functional units with a type 00h configuration space header. PCIe endpoints 150_1 to 150_3, as completers, can support configuration requests. PCIe-compatible software drivers and applications can operate such that no locking semantics are used when accessing PCIe endpoints 150_1 to 150_3. PCIe endpoints 150_1 to 150_3, acting as requesters of memory transactions, can generate addresses larger than 4GB. When interrupted resources are requested, PCIe endpoints 150_1 to 150_3 may need to support Message Signaled Interrupt (MSI), MSI-X, or both. When MSI is implemented, PCIe endpoints 150_1 to 150_3 can support a 64-bit message address version of the MSI functional architecture. The minimum memory address range required by the base address register can be 128 bytes. PCIe endpoints 150_1 to 150_3 can exist in one of the hierarchical domains starting from root union 120.

[0043] Traditional endpoints 160_1 and 160_2 can be functional units with a 00h type configuration space header. Traditional endpoints 160_1 and 160_2 can support configuration requests as completers. Traditional endpoints 160_1 and 160_2 can support I / O requests as completers. Traditional endpoints 160_1 and 160_2 can accept I / O requests for one or both locations 80h and 84h, regardless of the corresponding endpoint's I / O decoding configuration. Traditional endpoints 160_1 and 160_2 can generate I / O requests. Traditional endpoints 160_1 and 160_2 can include extended configuration space capabilities. Traditional endpoints 160_1 and 160_2, operating as requesters of memory transactions, may not generate addresses of 4GB or more. When interrupted resources are requested, traditional endpoints 160_1 and 160_2 must support MSI, MSI-X, or both. When MSI is implemented, legacy endpoints 160_1 and 160_2 can support either 32-bit or 64-bit message address versions of the MSI functional architecture. Regarding the base address register for requesting memory resources, legacy endpoints 160_1 and 160_2 can support the 32-bit address specification. Legacy endpoints 160_1 and 160_2 can exist in one of the hierarchical domains initiated by root union 120.

[0044] Figure 2 This is a diagram illustrating a PCIe device according to an embodiment of the present disclosure.

[0045] refer to Figure 2 A PCIe device may include a PCIe interface, and the PCIe device is an electronic device that supports transmitting / receiving using a PCIe interface. For example, a first PCIe device 200-1 or a second PCIe device 200-2 may be in... Figure 1 The diagram shows one of the following: root union 120, switch 140, PCIe endpoints 150_1 to 150_3, legacy endpoints 160_1 and 160_2, and PCIe bridge 170.

[0046] Furthermore, the first PCIe device 200-1 or the second PCIe device 200-2 can perform communication using the first PCIe interface 210-1 or the second PCIe interface 210-2. Specifically, the first PCIe device 200-1 can use the first PCIe interface 210-1 to convert data to be sent from the second PCIe device 200-2 into a protocol suitable for communication. In addition, the first PCIe device 200-1 and the second PCIe device 200-2 can form a link. The first PCIe device 200-1 and the second PCIe device 200-2 can communicate with each other through the formed link. For example, the first PCIe device 200-1 or the second PCIe device 200-2 can send / receive data packets through the link.

[0047] Figure 3 This is a diagram illustrating a PCIe interface according to an embodiment of the present disclosure.

[0048] refer to Figure 3 The diagram illustrates a first PCIe interface 210-1 and a second PCIe interface 210-2. The first PCIe interface 210-1 and the second PCIe interface 210-2 can be formed with the same structure. Therefore, for ease of discussion, the first PCIe interface 210-1 will be described primarily.

[0049] The PCIe layers included in the first PCIe interface 210-1 may include three separate logical layers. For example, the first PCIe interface 210-1 may include a transaction layer 211-1, a data link layer 212-1, and a physical layer 213-1. Similarly, the second PCIe interface 210-2 may include a transaction layer 211-2, a data link layer 212-2, and a physical layer 213-2. Each layer may include two parts. One part may handle outbound (or transmitted) information, while the other part may handle inbound (or received) information. Additionally, the first PCIe interface 210-1 can use data packets to transmit information between other PCIe interfaces.

[0050] The upper layer in the PCIe interface architecture can be a transaction layer. This transaction layer can assemble and decompose Transaction Layer Packets (TLPs). Additionally, the transaction layer can implement split transactions, meaning it can perform transactions that allow another flow to be forwarded over the link while assembling the data required for a target system response. In one embodiment, the four transaction address spaces can include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions can include one or more read and write requests for transferring data to / from a memory-mapped location. In one embodiment, memory space transactions can use two different address formats, such as a short address format like a 32-bit address or a long address format like a 64-bit address. Configuration space transactions can be used to access the configuration space of a PCIe device. Transactions to the configuration space can include read and write requests. Message space transactions (or messages) can be defined to support in-band communication between PCIe devices.

[0051] The transaction layer can store link configuration information, etc. Furthermore, the transaction layer can generate TLPs or convert received TLPs into payload or status information.

[0052] The intermediate layer in the PCIe interface architecture can be the data link layer, which performs the functions of an intermediate stage between the transaction layer and the physical layer. A primary function of the data link layer is link management and data integrity, including error detection and correction. Specifically, the sending side of the data link layer can accept the TLP assembled in the transaction layer, provide data protection codes, or calculate the TLP sequence number. Additionally, the sending side of the data link layer can send the data protection codes and TLP sequence numbers to the physical layer to enable transmission of these codes and sequence numbers over the link. The receiving side of the data link layer can verify the data integrity of the TLP received from the physical layer and send the TLP to the transaction layer for further processing.

[0053] The physical layer can include all the circuitry used for interface operations. This circuitry can include drivers, input buffers, serial-to-parallel converters, parallel-to-serial converters, phase-locked loops (PLLs), and impedance matching circuitry.

[0054] Furthermore, the physical layer can include logical subblocks and electrical subblocks that physically transmit data packets to external PCIe devices. Logical subblocks can perform the functions required for the "digital" functionality of the physical layer. In this regard, a logical subblock can include: a transmitting section for preparing transmission information to be sent by the physical subblock; and a receiving section for identifying and preparing received information before it is forwarded to the data link layer. The physical layer can include transmitters and receivers. Because the transmitter is serialized by the logical subblock, it can receive symbols destined for external devices. Furthermore, the receiver can receive serialized symbols from external devices and convert the received symbols into a bit stream. This bit stream can be deserialized for provisioning to the logical subblock. That is, the physical layer can convert TLPs received from the data link layer into a serialized format and data packets received from external devices into a deserialized format. Additionally, the physical layer can include logical functions associated with interface initialization and maintenance.

[0055] Despite Figure 3 The diagram illustrates the structure of the first PCIe interface 210-1 and the second PCIe interface 210-2, but the structure of the first PCIe interface 210-1 and the second PCIe interface 210-2 can include any form, such as a fast path interconnect structure, a next-generation high-performance computing interconnect structure, or other hierarchical structures.

[0056] Figure 4 This is a diagram illustrating a transmitter, receiver, and channel according to one embodiment of the present disclosure.

[0057] refer to Figure 4The diagram illustrates a first transmitter TX1, a second transmitter TX2, a first receiver RX1, and a second receiver RX2. A channel may include paths comprising differentially driven signal pairs, such as transmit path pairs configured for transmitting and receive path pairs configured for receiving. A PCIe device may include transmit logic for sending data to another PCIe device and receive logic for receiving data from another PCIe device. For example, a channel may include two transmit paths connected to the first transmitter TX1 and two receive paths connected to the first receiver RX1.

[0058] The transmitting path can refer to any path used to transmit data, such as a transmitting line, copper wire, optical line, wireless communication channel, infrared communication link, or another communication path. Furthermore, the receiving path can be implemented identically to the transmitting path but used for receiving data.

[0059] A connection between two PCIe devices, such as a first PCIe device 200-1 and a second PCIe device 200-2, can be designated as a link. This link can support one or more channels. For example, the link may include multiple channels.

[0060] Figure 5 This is a diagram illustrating a differential signal according to an embodiment of the present disclosure.

[0061] refer to Figure 5 The diagram illustrates a differential signal. PCIe devices can use differential signals for both transmitting and receiving purposes. A differential signal can refer to a pair of signals with the same frequency and amplitude but opposite phases. For example, while the first signal is at the rising edge of its transition from 0 to V+, the second signal might be at the falling edge of its transition from 0 to V-. PCIe devices can utilize differential signals to achieve signal integrity, such as more favorable electrical characteristics (e.g., cross-coupling, voltage overshoot / undershoot, and ringing). PCIe devices can adjust their transmission frequency more quickly. Furthermore, a link can include multiple channels to adjust bandwidth. For example, two PCIe devices can form links with 1, 2, 4, 8, 12, 32, 64, or more channels.

[0062] Figure 6 This is a diagram illustrating the configuration of a data packet according to an embodiment of the present disclosure.

[0063] refer to Figure 6Each component of packet 50 can be processed sequentially at each layer of the PCIe interface. Specifically, packet 50 can be configured with different protocols according to the processing at each layer. For example, a transaction layer packet (TLP) can be generated and processed in transaction layer 211-1 or 211-2. A TLP can include a header field, a data field, and an end-to-end cyclic redundancy check (ECRC) field. The header field can be a subfield including the TLP type, information about whether data should be included, information about whether cyclic redundancy check (CRC) should be included, etc. Furthermore, the data field can be a field that includes data to be sent or received, and the ECRC field can be a field that includes the ECRC value representing information at the endpoint. Alternatively, the data field and the ECRC field can be omitted from the TLP.

[0064] Furthermore, data link layer packets (DLLPs) can be generated and processed in data link layer 212-1 or 212-2. In addition to the TLP, the DLLP may also include a sequence number field and a link cyclic redundancy check (LCRC) field. The sequence number field can be a field that includes information about the sequence number of the TLP, and the LCRC field can be a field that includes information about the LCRC.

[0065] Furthermore, physical layer packets (PLPs) can be generated and processed in physical layer 213-1 or 213-2. In addition to DLLPs, PLPs may also include a framing field. This framing field may be a field that includes information about the serialization format.

[0066] Figure 7 This is a diagram illustrating a data flow according to an embodiment of the present disclosure.

[0067] refer to Figure 7 The diagram illustrates a data stream transmitted over an x8 link. This data stream may include the transmission of SKIP ordered sets (SKPOS).

[0068] The data stream can begin by sending a synchronization header (Sync Hdr H1H = 10b) indicating a data block. Therefore, the start of the TLP (STP) framing token can be sent as the zeroth symbol indicating the start of the TLP stream in channels 0 through 3. Furthermore, the TLP header and TLP data can be sent as the first and second symbols. A Link Cyclic Redundancy Check (LCRC) can be sent after the TLP data, and an SDP header indicating that DLLP data will be sent after the LCRC can be sent as the third symbol. Additionally, Cyclic Redundancy Check (CRC) data associated with the DLLP data can also be provided.

[0069] Subsequently, a Logical Idle Token (IDL) indicating that no data has been transmitted over the link can be sent. Additionally, an EDS token can be sent to indicate that the data has been changed to SKP OS data on the channel. For example, another synchronization data, encoded as "01b", can be sent, indicating that the subsequent block will be an SKP OS data block.

[0070] The SKP OS can include parity bits representing the parity status of each channel in the link (e.g., channels 0 through 7). The SKP OS can also include a layout defined for receiver recognition. For example, in the case of 128b / 130b encoding in PCIe, the SKP OS can include 16 basic symbols. Four SKP symbol groups can be added or removed via ports, and the SKP OS can include 8 symbols, 12 symbols, 16 symbols, 20 symbols, 24 symbols, and so on. Furthermore, as... Figure 7 As shown, the SKP_END symbol can be provided to indicate the end position of the SKP OS on the channel and the position of the next block synchronization header sent through the channel.

[0071] Figure 8 This is a diagram illustrating a port according to an embodiment of the present disclosure.

[0072] refer to Figure 8 The diagram illustrates downlink port 215-1 and uplink port 215-2, which are included in the first PCIe device 200-1 and the second PCIe device 200-2, respectively.

[0073] In one embodiment, the first PCIe device 200-1 may be an upper layer than the second PCIe device 200-2, and data movement and transmission to the upper layer can be designated as uplink. Conversely, data movement and transmission to the lower layer can be designated as downlink. For example, refer to... Figure 1 Switch 140 can support both uplink and downlink routing. Specifically, uplink can be routing packets or messages from a PCIe endpoint (e.g., 150_1) to a layer toward the root union 120, and downlink can be routing packets or messages from the root union 120 to a layer toward the PCIe endpoint (e.g., 150_2).

[0074] In one embodiment, a first PCIe device 200-1 including downlink port 215-1 can be designated as an "uplink component". An uplink component can be represented in... Figure 1 The root union 120 or switch 140 is shown in the diagram. Additionally, a second PCIe device 200-2, including uplink port 215-2, can be designated as a "downlink component". A downlink component can be represented in... Figure 1The diagram shows one of the switch 140, PCIe endpoints 150_1 to 150_3, legacy endpoints 160_1 and 160_2, and PCIe bridge 170.

[0075] Each of the downlink port 215-1 and the uplink port 215-2 may include a transmitter Tx, a receiver Rx, and a phase-locked loop (PLL) circuit. The PLL circuit can generate a clock signal to be supplied to the transmitter Tx or receiver Rx using a clock signal provided from a clock signal generator CLK GEN. The PLL circuit can generate a clock signal with a modified frequency by multiplying the signal received from the clock signal generator CLK GEN. For example, the PLL circuit can multiply a reference clock signal with a frequency of 100 MHz to a clock signal with a frequency of 2.5 GHz. The transmitter Tx can convert a parallel data signal into a serial data signal using the output signal of the PLL circuit and send the serial data signal to an external device (e.g., an external PCIe device). The receiver Rx can receive the serial data signal sent from the external device and generate a clock signal for recovering the received serial data signal and a clock signal for converting the recovered serial data signal into a parallel data signal using the output signal of the PLL circuit. The clock signal generator CLK GEN can generate a reference clock signal used for the operation of the PCIe interface. The PCIe interface can be used to communicate with external PCIe devices.

[0076] Figure 9 This is a diagram illustrating the link state of a PCIe device according to an embodiment of the present disclosure.

[0077] refer to Figure 9 The link states of PCIe devices include detection state, polling state, configuration state, hot reset state, disabled state, L0 state, L0s state, L1 state, and L2 state. More specifically, Figure 9 The diagram illustrates the operational configuration of the Link Training and State Machine (LTSSM).

[0078] The detection state is the initialization state after power-on or reset, and the link state transitions from the following states. For example, the detection state can be the state from which the link transitions from configuration, hot reset, disabled, L2, loopback, and recovery states. The detection state can reset all logic, all ports, and all registers, and is the stage for detecting links connected to the PCIe interface. In other words, the detection state can be the stage for searching for channels of physical connections.

[0079] Polling state can refer to the state used to distinguish which channels among the detected channels are capable of data communication. Polling state can be a phase that synchronizes the clock at both ends of the PCIe interface, verifies whether the channel polarity is D+ or D-, and verifies the data transmission rate that the channel can use. In other words, polling state can be a state used to verify polarity reversal. Furthermore, a link in polling state can enter either detection state or configuration state.

[0080] The configuration state can be a state used to verify the connection status of the channel. Specifically, the configuration state can be a state used to define the channel width that allows data communication. Additionally, the configuration state can be a state used to verify channel reversal. The configuration state can be the state where the link transitions from the polling state to the configuration state. Alternatively, the link state can enter the L0 state and then enter the configuration state when the channel width decreases and increases.

[0081] The recovery state can be a state used to reconfigure link bandwidth. The recovery state can change the configured link bandwidth and reset bit locks, symbol locks, and lane-to-lane de-skew. When an error occurs in the L0 state, the link state can enter the recovery state. Subsequently, after the error is recovered during the recovery state, the link state can change from the recovery state back to the L0 state. According to one embodiment of this disclosure, link equalization operations can be performed in the recovery state.

[0082] The L0 state can be a normal operating state capable of sending and receiving data and data packets via a link. Specifically, the L0 state can be the operating state of a physical bus interface through which data and control data packets can be sent and received. The L0 state can also be a fully active state.

[0083] The L0s state can be a state that allows the physical bus interface to quickly enter a power-saving state and recover without going through any recovery state. The L0s state can be a power-saving state. The L0s state can also be an idle or standby state for certain functions in the interface.

[0084] L1 state can be a power-saving state. L1 state can be a state where power saving is increased compared to L0s state. L1 state can be a low-power standby state.

[0085] L2 state can be an active power-saving state. Most transmitters and receivers can be turned off. Main power and clock are not guaranteed, but auxiliary power can be supplied. L2 state can also be a low-power sleep state that does not power most functions. Loopback state can be used for testing and fault isolation. Loopback state operates only on a channel-by-channel basis, and the loopback receiver channel must be selected and configured.

[0086] A disabled state can be a state in which an established link is disabled before further notification. A hot reset state can be triggered solely by the downlink port. The downlink port can use a training sequence (e.g., TS1 or TS2) to propagate a hot reset. A training sequence (TS) can be a set of alignments used to initialize bit alignment, symbol alignment, and physical layer parameter exchange. In this specification, "training sequence" can be specified as an "ordered set of training sequences".

[0087] Figure 10 The illustration shows an embodiment according to the present disclosure. Figure 9 The diagram shows the detailed sub-states of the recovery state. Specifically, Figure 10 The diagram illustrates the operation of the sub-state machine in the recovery state.

[0088] (1) Recovery. Restore Lock (Recovery.RcvrLock)

[0089] When the link operates at data rates of 8.0 GT / s or higher, the receiver will only receive the TS1 or TS2 command set after a block alignment has been acquired in the corresponding channel. When an item in the Recovery.RcvrLock substate begins in Recovery.Speed ​​or L0s, the block alignment will be acquired after the electrical idle condition ends. When an item in this substate begins in L0, the block alignment will be acquired after the last data stream ends.

[0090] (2) Recovery.Equalization

[0091] The transmitter exits the configuration state and then transmits the TS1 ordered set in all channels configured with the link and channel number.

[0092] (3) Recovery Speed

[0093] The transmitter enters an electrically idle state and maintains this state until the receiver channel becomes electrically idle. Subsequently, the transmitter maintains this state for at least 800 ns in the next successful speed negotiation (e.g., success_speed_negotiation = 1b), or for at least 6 μs in the next failed speed negotiation (e.g., success_speed_negotiation = 0b), but not for 1 ms or longer. The operating frequency can only be changed to a new data rate after the receiver channel has entered an electrically idle state.

[0094] (4) Recovery. Recover configuration (Recovery.RcvrCfg)

[0095] The transmitter exits the configuration state and then sends TS2 command sets to all channels configured with the same setting line and the same setting channel number. When the directed_speed_change variable has already been set to 1b, the speed_change bit (bit 7 of the data speed identifier in the TS2 ordered set) will be set to 1b. The N_FTS value of the sent TS2 command sets should reflect the current data speed.

[0096] (5) Recover.Idle

[0097] In the Recovery.Idle substate, the link state progresses to any one of the following states according to the instructions: Recovery.RcvrLock substate, LTSSM detection state, LTSSM hot reset state, LTSSM L0, LTSSM loopback state, and LTSSM configuration state.

[0098] According to this disclosure, the Recovery.RcvrLock substate and the Recovery.RcvrCfg substate belong to the first group, Group1.

[0099] Figure 11 This is a diagram illustrating a PCIe device according to an embodiment of the present disclosure.

[0100] refer to Figure 11 The PCIe device 700 may include multiple ports P0 to Pn and a link controller 710.

[0101] Multiple ports P0 to Pn can form multiple channels. For example, such as Figure 4 As shown, one port can form a channel with a port included in another PCIe device. In one embodiment, each of the plurality of ports P0 to Pn can be a downlink port or an uplink port. For example, when the plurality of ports P0 to Pn are downlink ports, PCIe device 700 can be an uplink component. Alternatively, when the plurality of ports P0 to Pn are uplink ports, PCIe device 700 can be a downlink component. Each of the plurality of ports P0 to Pn can include a receiver and a transmitter.

[0102] Link controller 710 can configure links. A link may include multiple ports P0 to Pn. That is, a link can be formed by multiple ports P0 to Pn. For example, link controller 710 can perform a link configuration operation. The link configuration operation can represent the process of initializing and configuring the link to enable it to operate normally. The link configuration operation constitutes a link initialization and training operation according to the PCIe specification.

[0103] In one embodiment, the link controller 710 may include a link training and status machine (LTSSM). The LTSSM may be a component used to perform link setup operations.

[0104] Link controller 710 can perform link width and channel number negotiation operations. Link width can represent the number of channels forming a link. For example, link controller 710 can determine the link width during link setup. Channel number can represent the number assigned to each channel included in the link. For example, link controller 710 can negotiate the number assigned to each channel during link setup and determine the line number for each channel based on the negotiation. The determined channel number can be sent to another PCIe device, and that other PCIe device can accept the corresponding channel number.

[0105] Link controller 710 can detect faulty channels among multiple channels during link setup. A faulty channel can be a channel that cannot form a link with other channels. Other channels are channels that are not faulty and can include all channels other than the faulty channel. For example, a channel may be faulty if a problem occurs in the transmit or receive path included in the channel. The faulty channel may fail to operate properly when data is transmitted. For example, when the link is in a detection state, link controller 710 can detect the faulty channel through a line setup operation corresponding to the detection state. The link setup operation corresponding to the detection state is an operation performed to set up a line in the detection state and may include operations for finding links at both ends. For example, the two ends can be ports included in different PCIe devices connected to each other via a link. Subsequently, link controller 710 can perform the link setup operation corresponding to the detection state on all channels other than the faulty channel among the multiple channels. Additionally, when the link is in a polling state, link controller 710 can detect the faulty channel through the link setup operation corresponding to this polling state. The link setup operation corresponding to the polling state is an operation performed to set up the link during the polling state, and may include operations such as sending / receiving an ordered set of training sequences. For example, the link setup operation corresponding to the polling state may include operations such as sending / receiving an ordered set of training sequences between ports connected by the link. Subsequently, the link controller 710 may perform the link setup operation corresponding to the polling state on other channels.

[0106] In one embodiment, the link controller 710 can configure a link to have a link width including at least one of the channels other than the faulty channel. For example, when the link is in a configuration state, the link controller 710 can perform link configuration operations corresponding to the configuration state on other channels. The link configuration operations corresponding to the configuration state can be operations performed to configure the link in the configuration state. For example, the link configuration operations corresponding to the configuration state may include operations such as setting the link width, determining the channel number, and offsetting between channels.

[0107] For example, link controller 710 can determine the link number of the link in the configuration state and the channel number of each of the other channels. Link controller 710 can determine the channel number of each of the other channels through a channel number negotiation operation. In one embodiment, link controller 710 can determine the channel number of each of the other channels to cause the channel numbers of the other channels to sequentially increase or decrease.

[0108] In one embodiment, link controller 710 may provide a link number determined by multiple ports P0 to Pn, and a determined channel number for each of the other channels, to other ports that together form multiple channels with the multiple ports P0 to Pn. The other ports may be ports included in another PCIe device different from PCIe device 700. For example, link controller 710 may provide the other ports with a link number determined using an ordered set of training sequences, and a determined channel number for each of the other channels. The other PCIe device may accept this link number and the channel number for each of the other channels.

[0109] Figure 12A and Figure 12B This is a diagram illustrating the operation of setting up a link according to an embodiment of the present disclosure.

[0110] refer to Figure 12AEach of the first PCIe device 700-1 and the second PCIe device 700-2 can represent PCIe device 700. For example, the first PCIe device 700-1 can be a PCIe device including multiple downlink ports P0 to P7. And the second PCIe device 700-2 can be a PCIe device including multiple uplink ports P0' to P7'. However, this is merely an example. In some embodiments, the ports included in the first PCIe device 700-1 can be uplink ports, while the ports included in the second PCIe device 700-2 can be downlink ports. In some embodiments, the first PCIe device 700-1 can include downlink ports, while the second PCIe device 700-2 can include uplink ports. Furthermore, although each of the first PCIe device 700-1 and the second PCIe device 700-2 is illustrated to include eight ports, the number of ports can vary in some embodiments.

[0111] Multiple downlink ports P0 to P7 and multiple uplink ports P0' to P7' can together form multiple channels. For example, the zeroth downlink port P0 and the zeroth uplink port P0' can form the zeroth channel Lane 0; the first downlink port P1 and the first uplink port P1' can form the first channel Lane 1; the second downlink port P2 and the second uplink port P2' can form the second channel Lane 2; the third downlink port P3 and the third uplink port P3' can form the third channel Lane 3; the fourth downlink port P4 and the fourth uplink port P4' can form the fourth channel Lane 4; the fifth downlink port P5 and the fifth uplink port P5' can form the fifth channel Lane 5; the sixth downlink port P6 and the sixth uplink port P6' can form the sixth channel Lane 6; and the seventh downlink port P7 and the seventh uplink port P7' can form the seventh channel Lane 7. The formation of these channels can be performed through a negotiation operation of link width and channel number.

[0112] Figure 12B The illustration shows the case where the channel between the fifth downlink port P5 and the fifth uplink port P5' is a faulty channel when the link is set up between the first PCIe device 700-1 and the second PCIe device 700-2.

[0113] The first PCIe device 700-1 can perform channel number negotiation operations on multiple ports P0 to P7 in ascending order of port numbers. Therefore, according to the PCIe specification, since the channel between the fifth downlink port P5 and the fifth uplink port P5' is a faulty channel, channel number negotiation operations may not be possible for the sixth downlink port P6 and the seventh downlink port P7. The channels between the sixth downlink port P6 and the sixth uplink port P6', and the channels between the seventh downlink port P7 and the seventh uplink port P7', can be in an electrically idle state.

[0114] Furthermore, according to the PCIe specification, the link width can typically be defined as one of 1, 2, 4, 8, 12, 16, or 32 channels. Therefore, the first PCIe device 700-1 can be configured to have a link width comprising four channels, Lanes 0 to 3. This link can be formed using only the four channels, Lanes 0 to 3. Although the channel between the fourth downlink port P4 and the fourth uplink port P4' is not a faulty channel, the channel between the fourth downlink port P4 and the fourth uplink port P4' may be electrically idle.

[0115] When a link error occurs while a PCIe link is in operation, the response is configured to adjust the operating speed or change the link configuration (link width and channel number). Both operations can be performed simultaneously. Furthermore, in the PCIe protocol, there is no method to definitively determine and classify the direct causes of link errors in detail. Therefore, when a link error occurs, the link speed is first adjusted downwards, and then the link configuration is changed.

[0116] Based on the above process, the link speed must first be reduced to change the link configuration. Therefore, when a link error is caused by the link configuration rather than the link speed, performance degradation occurs due to the unnecessary reduction in link speed.

[0117] refer to Figure 9 and Figure 10 There are four scenarios in which the link enters the configuration state.

[0118] (1) Polling → Configuration

[0119] This is a list identifying the main activity channels (in...) Figure 9 The link state then enters the configuration state to perform specific channel configuration (link width identification and channel number specification) after being indicated by 'a'. This is a process that must be performed during the link initialization process and does not correspond to the problematic situation in this disclosure.

[0120] (2) Restore → Configuration

[0121] This situation occurs when the link's state transitions from a recovery state to a configuration state (in...). Figure 9 (Used as b in the text). Simultaneously, a detailed study will be conducted on the configuration states when the link's state enters specific sub-states included in the recovery state.

[0122] (2-1) Recovery.RcvrLock → Configuration

[0123] In scenarios where a specific data rate is applied, a 24ms timeout occurs when it is impossible to send / receive normal data packets. Subsequently, the data rate is adjusted to 2.5GT / s. This is the minimum performance value corresponding to which a PCIe link can be operated. The link speed is reduced to the minimum value as a result of the following situation: the cause of the current link error originates from "high performance," and therefore, an attempt is made to reduce performance first. Even when performance is reduced, the link error continues, eventually determining that the link itself is misconfigured, thus ultimately entering a configuration state (in...). Figure 10 (As indicated by b1).

[0124] The inability to send / receive normal data packets may mean that the channel number or link number value on the data packets sent to each channel is not correctly matched.

[0125] (2-2) Recovery.RcvrCfg → Configuration

[0126] Similar to case b1 in (2-1) above, this occurs when it is impossible to send / receive normal data packets (in... Figure 10 (Indicated by b2). In the Recovery.RcvrCfg substate, completion is only possible when a data packet TS2 with a correctly matched link and channel number is sent / received. Otherwise, the Recovery.RcvrCfg substate will only eventually enter the configuration state when the data rate is 2.5GT / s.

[0127] (2-3) Recovery.Idle → Configuration

[0128] This refers to the situation where, when a host arbitrarily changes the configuration of a corresponding link, the link's state changes according to the host's request, thus altering the link's configuration. Figure 10 (As indicated by b3). This is a process unrelated to the occurrence of link errors, and can be executed when changes to link width, etc., are needed, even during periods when normal operation is maintained.

[0129] Therefore, among the four scenarios mentioned above, the problematic case of "performance degradation due to unnecessary adjustment of the minimum data rate" corresponds to the cases indicated by b1 and b2. When link speed is the cause of the link error, the problem is no longer detected after adjusting the link speed downwards. Therefore, this case does not enter the configuration state. Thus, the case where the link state eventually enters the configuration state refers to a link error unrelated to link speed. Therefore, after resolving the link error by changing the link configuration, it is preferable to restore the link speed to its highest value.

[0130] The host has the authority to change the link speed relative to the PCIe Basic Specification and controls the link speed through a speed change variable. This speed change variable can be a `directed_speed_change` variable. The `directed_speed_change` variable has a value of 0b upon reset. In the existing LTSSM specification, for all four cases mentioned above, it should be reset to "directed_speed_change = 0b". Therefore, even under the b1 and b2 indications, the final speed will still remain at the minimum value (2.5GT / s) after the configuration state ends.

[0131] According to one embodiment of this disclosure, by setting "direct_speed_change = 1b" based on the aforementioned conditions indicated by b1 and b2, the maximum link speed can be applied from the beginning when the link state re-enters the recovery state after executing the configuration state. Therefore, when the cause of the link error is not the link speed, the link speed can be restored to the maximum value. Figure 10 As shown, the Recovery.RcvrLock and Recovery.RcvrCfg substates belong to the first group, Group 1. That is, according to one embodiment of this disclosure, when transitioning from a substate belonging to the first group, Group 1, in the recovery state to the configuration state, any values ​​of the speed change variables are not reset. Therefore, as indicated by b1 and b2, the link speed can be restored to its highest value.

[0132] Figure 13 This is a flowchart illustrating an operation method of a configuration state according to an embodiment of the present disclosure.

[0133] refer to Figure 13 The illustration shows Figure 9This is an embodiment of the configuration state among the states included in the LTSSM shown. Specifically, after the link state enters the configuration state (S110), it is determined whether the link state enters the corresponding configuration state by entering the configuration state from the first group of sub-states in the recovery state (S120). As described above, the first group of sub-states includes at least one of the Recovery.RcvrLock sub-state and the Recovery.RcvrCfg sub-state. When the link state enters the configuration state from the first group of sub-states (S120: Yes), this corresponds to the situation indicated by b1, and therefore, the speed change variable is set to a second value (S150). In operation S150, the speed change variable can be the directed_speed_change variable, and the second value can be "1b".

[0134] When the link state does not transition from the sub-state of the first group to the configuration state (S120: No), this means that transitioning to the corresponding configuration state does not belong to any of the aforementioned situations indicated by b1 and b2. In other words, transitioning to the corresponding configuration state will correspond to the situation indicated by a or b3. Therefore, the speed change variable is set to a first value (S140). In operation S140, the speed change variable can be the directed_speed_change variable, and the first value can be "0b".

[0135] Since the directed_speed_change variable is fully set, detailed operations on the configuration state are then performed (S160). Although in Figure 13 It is not shown in detail, but when operation S160 is fully executed, the link state can be removed from the configuration state, and then as follows: Figure 9 The location shown enters the L0 state.

[0136] Figure 14 This is a flowchart illustrating an operation method of the L0 state according to an embodiment of the present disclosure.

[0137] refer to Figure 14 The illustration shows Figure 9 This is an example of the L0 state among the states included in the LTSSM. Specifically, in Figure 14 The diagram illustrates the operation when the link state changes from the configuration state to the L0 state.

[0138] After the link enters the L0 state (S210), it is determined whether the value of the speed change variable is the second value (S220). In operation S210, it is determined whether the value of the directed_speed_change variable is 1b. When the value of the speed change variable is the second value, that is, when the value of the speed change variable is 1b (S220: Yes), the link enters the recovery state, and the link speed is changed (S230). Since the value of the directed_speed_change variable is 1b, the link speed can be changed to the existing maximum speed. Subsequently, the L0 state operation is executed (S240).

[0139] When the value of the speed change variable is the first value instead of the second value, that is, when the value of the speed change variable is 0b (S220: No), the operation of the L0 state is executed (S240). Since the value of the directed_speed_change variable is 0b, the link speed can be maintained at the minimum value (2.5GT / s).

[0140] As described above, according to embodiments of this disclosure, the value of the speed change variable is adaptively set based on the reason for entering the configuration state in the LTSSM. Therefore, it is possible to prevent the link speed from being unnecessarily adjusted down to the minimum value. Consequently, the overall operating speed of the PCIe device can be improved.

[0141] Figure 15 This is a flowchart illustrating an operation method for restoring a state according to another embodiment of the present disclosure. Figure 15 The diagram illustrates an embodiment of the sub-states included in the first group of sub-states within the recovery state. Figure 13 In the embodiment shown, the speed change variable, i.e., the value of the `directed_speed_change` variable, is set from the perspective of configuration state. However, in Figure 15 In the embodiment shown, the speed change variable, i.e., the value of the directed_speed_change variable, is set from the perspective of the recovery state before entering the configuration state.

[0142] refer to Figure 15First, the link state enters the first sub-state of the recovery state (S310). The first sub-state of the recovery state can be either the Recovery.RcvrLock sub-state or the Recovery.RcvrCfg sub-state. After the link state enters the first sub-state, it is determined whether the link state is to enter the configuration state (S320). When it is determined that the link state is to enter the configuration state (S320: Yes), this corresponds to the case indicated by b1 or b2, and therefore, the speed change variable is set to the second value (S330). For example, in operation S330, directed_speed_change is set to 1b.

[0143] When the state of the link is uncertain and it needs to enter the configuration state (S320: No), the link state enters another sub-state within the recovery state or the detection state (S340). For example... Figure 10 As shown, when the link state enters the first group of sub-states in operation S310, which is the Recovery.RcvrLock sub-state, the link state may change from the Recovery.RcvrLock sub-state to the Recovery.RcvrCfg sub-state, from the Recovery.RcvrLock sub-state to the Recovery.Equalization sub-state, from the Recovery.RcvrLock sub-state to the Recovery.Speed ​​sub-state, or, if the link state does not enter the configuration state, from the Recovery.RcvrLock sub-state to the detection state. In other words, when it is uncertain whether the link state has entered the configuration state (S320: No), the link state may enter another sub-state within the recovery state (e.g., the Recovery.RcvrCfg sub-state, the Recovery.Equalization sub-state, or the Recovery.Speed ​​sub-state) or the detection state (S340). The directed_speed_change variable is not set to 1b.

[0144] In another example, such as Figure 10As shown, when the link state enters the first group of sub-states in operation S310, which is the Recovery.RcvrCfg sub-state, the link state changes from the Recovery.RcvrCfg sub-state to the Recovery.Idle sub-state, from the Recovery.RcvrCfg sub-state to the Recovery.Speed ​​sub-state, or from the Recovery.RcvrCfg sub-state to the detection state. When the link state is not determined to enter the configuration state (S320: No), the link state enters another sub-state in the recovery state (e.g., the Recovery.Idle sub-state or the Recovery.Speed ​​sub-state) or the detection state (S340). The directed_speed_change variable is not set to 1b.

[0145] According to this disclosure, an interface device and a computing system including the interface device can be provided, which can adaptively control the link speed according to the entry factors of the configuration operation during a link setup operation.

[0146] While this disclosure has been shown and described with reference to specific embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0147] In the above embodiments, all operations may be selectively performed, or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0148] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is only for describing embodiments of this disclosure. Therefore, this disclosure is not limited to the above-described embodiments, and many variations can be made within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein and the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. An interface device, comprising: Multiple ports are configured to form multiple channels; as well as The link controller is configured to set the link speed by determining the link speed based on the link's state prior to entering a configuration state of the link, which includes the multiple channels. The link controller is further configured to: when the link enters the L0 state from one of the plurality of states of the link, in response to a speed change variable having a first value, set the speed of the link to the first speed of a first speed and a second speed, wherein the second speed is higher than the first speed.

2. The interface device according to claim 1, wherein the link controller includes a link training and status machine (LTSSM) for setting up the link.

3. The interface device according to claim 2, wherein the link controller sets the speed by: when the link enters the configuration state from the polling state among the plurality of states of the link, initializing the speed of the link by setting the speed change variable to the first value.

4. The interface device according to claim 2, wherein the link controller sets the speed by: when the link enters the configuration state from a sub-state in the first group of the recovery states of the plurality of states of the link, maintaining the speed of the link by setting the speed change variable to a second value.

5. The interface device according to claim 4, wherein the link controller sets the speed by: when the link enters the configuration state from a sub-state other than the first group of the recovery states among the plurality of states of the link, initializing the speed of the link by setting the speed change variable to the first value.

6. The interface device of claim 4, wherein the link controller is further configured to: when the link enters the L0 state from the configuration state among the plurality of states of the link, in response to the speed change variable having the second value, set the speed of the link to the second speed of a first speed and a second speed, wherein the second speed is higher than the first speed.

7. The interface device according to claim 2, wherein the link controller is further configured to: set the speed change variable to a second value when the state is a sub-state within a first group of recovery states among the plurality of states of the link, and the link is determined to enter the configuration state.

8. A method for operating an interface device, the method comprising: The configuration state allows the state of a link connected to an external device to enter one of the multiple states of that link; as well as The link speed is set by determining the link speed based on the link's state before entering the configuration state. Setting the speed of the link includes: when the link enters the L0 state from the configuration state among the plurality of states of the link, in response to the speed change variable having a first value, setting the speed of the link to the first speed of a first speed and a second speed, wherein the second speed is higher than the first speed.

9. The method of claim 8, wherein the setting includes: When the state of the link is a polling state among the plurality of states of the link, the speed of the link is initialized by setting the speed change variable to the first value.

10. The method of claim 8, wherein the setting includes: When the state of the link is a sub-state within the first group of the recovery states among the plurality of states of the link, the speed of the link is maintained by setting the speed change variable to a second value.

11. The method of claim 8, wherein the setting includes: When the state of the link is a sub-state other than the first group of recovery states among the plurality of states of the link, the speed of the link is initialized by setting the speed change variable to the first value.

12. A method for operating an interface device, the method comprising: The configuration state allows the state of a link connected to an external device to enter one of the multiple states of that link; When the state of the link is a sub-state of the recovery state, which is included in the plurality of states of the link, it is first determined whether the link should enter the configuration state. as well as In response to the first determination, and then the determination of the link speed, The initial determination includes: when the link's state is a sub-state within the first group of the recovery state, determining whether the link should enter the configuration state, and The second determination includes: when the state of the link is the sub-state within the first group and the link is determined to enter the configuration state, setting the speed of the link to the speed before the recovery state.

13. The method according to claim 12, The first determination mentioned above includes: When the state of the link is a sub-state other than the first group in the recovery state, determine whether the link should enter the configuration state, and The second determination includes: when the state of the link is a sub-state other than the first group, and the link is determined to enter the configuration state, initializing the speed of the link.

14. A method of operating a device, the method comprising: When configuring a link that includes multiple channels, the speed of the link is set to a first value based on the first state of the link immediately preceding the configuration. When configuring the link, the speed is set to a second value based on a second state of the link immediately preceding the configuration; as well as Setting the speed of the link includes: when the link enters the L0 state from a configuration state among the multiple states of the link, in response to the speed change variable having the first value, setting the speed of the link to the first speed of a first speed and a second speed, wherein the second speed is higher than the first speed.

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