Spi module verification platform and method with dma interface

Abstract

The application relates to an SPI module verification platform and method with a DMA interface. The verification platform comprises: a simulation test top layer file, which is used for initializing the verification platform, connecting the verification platform and a module to be tested (DUT), and starting a test case; a basic test component, which is used for creating a platform environment and an SPI configuration component, and providing common tasks for the test case; a test case component, which is used for providing a test case for function test of the module to be tested (DUT), completing randomization of the SPI configuration component, test excitation generation, data packet starting and running in the test case, and calling the common tasks of the basic test component to compare transmission data; and an environment creation component, which is used for component packaging of an AHB verification system, component parameter configuration of an agent component of the AHB verification system, and setting of an SPI agent component. The method can improve the verification efficiency of the SPI module with the DMA interface.

Description

Technical Field

[0001] This application relates to the field of interface verification technology, and in particular to an SPI module verification platform and method with a DMA interface. Background Technology

[0002] With the increasingly widespread application of various electronic products, the types of chips are also increasing, the pace of updates and iterations is accelerating, and the integration and complexity of systems are also increasing significantly. This brings more daunting challenges to chip design and chip verification. In the entire chip design process, chip verification accounts for more than half of the entire design cycle. Verification work is tedious and extensive. Thorough chip verification is the cornerstone of successful tape-out and a guarantee for enterprises to effectively reduce chip R&D costs. However, traditional chip verification technologies can no longer meet the verification needs of increasingly complex chips, especially when module functions are becoming more diverse.

[0003] Serial Peripheral Interface (SPI) is a popular serial bus interface that conforms to the SPI bus protocol. It can be used in various chip systems, is simple and high-speed, and has a wide range of applications. Therefore, SPI module expansions are becoming increasingly common, making SPI more complex. One frequently used expansion is support for Direct Register Access (DMA) interfaces, which makes SPI transmission more efficient. However, verifying the SPI DMA interface requires interaction with the DMA module, so it is usually done at the system level. System-level verification takes significantly longer than module verification, increasing verification costs and difficulty. Summary of the Invention

[0004] Therefore, it is necessary to provide an SPI module verification platform and method with a DMA interface to address the aforementioned technical problems.

[0005] A verification platform for an SPI module with a DMA interface, the platform comprising:

[0006] The simulation test top-level file is used to verify the initialization of the platform, connect the verification platform and the DUT, and start the test cases;

[0007] Basic testing components are used to create the platform environment and SPI configuration components, as well as provide common tasks for test cases.

[0008] The test case component is used to provide test cases for the functional testing of the module under test (DUT). The test cases complete the randomization of the SPI configuration component, the generation of test stimuli, and the startup and execution of data packets. The common task of the basic test component is called to compare transmitted data.

[0009] The environment creation component is used to encapsulate the components of the AHB verification system, configure the component parameters of the proxy components of the AHB verification system, and set up the SPI proxy components.

[0010] The simulation test top-level file, the basic test component, and the environment creation component constitute a multi-level verification platform; the test case component and the environment creation component are connected through the SPI configuration component, and the module under test (DUT) is connected to the environment creation component through an interface.

[0011] In one embodiment, the module under test (DUT) is connected to the environment creation component via an SPI protocol interface, an AHB bus interface, and a DMA interface of the SPI module.

[0012] In one embodiment, the SPI protocol interface is used to connect to the proxy component of the AHB verification system of the environment creation component, and the AHB bus interface and the DMA interface of the SPI module are used to connect to the SPI proxy component of the environment creation component.

[0013] In one embodiment, the SPI proxy component includes a first sequence manager, an SPI bus driver, an SPI bus monitor, and a DMA function driver;

[0014] The sequence management is connected to the SPI bus driver, and the SPI bus driver and the SPI bus monitor are connected to the SPI protocol interface;

[0015] The DMA function driver is connected to the DMA interface of the SPI module.

[0016] In one embodiment, the agent components of the AHB verification system include: a second sequence management, an AHB stimulus driver, and an AHB monitor;

[0017] The second sequence management is connected to the AHB excitation driver;

[0018] The AHB excitation driver and the AHB monitor are connected to the AHB bus interface.

[0019] A method for verifying SPI modules with DMA interfaces is provided, which is applied to an SPI module verification platform with DMA interfaces to realize the verification of SPI modules with DMA interfaces.

[0020] The aforementioned SPI module verification platform and method with DMA interface is a multi-layered UVM verification platform built using SystemVerilog, integrating the AHB verification system and DMA verification components. Functionally, it has good reusability, and for test cases, the SPI configuration component can generate randomized stimuli for verification. Structurally, the DMA interface verification of the SPI module can be implemented at the module level, enabling thorough verification of the SPI module before system-level verification. Moreover, considering the complexity of the verification layers, module-level verification is more time-saving and labor-saving compared to system-level verification. Attached Figure Description

[0021] Figure 1 This is a block diagram of a verification platform for an SPI module with a DMA interface in one embodiment;

[0022] Figure 2 This is a schematic diagram of the signal processing flow of the DMA interface in one embodiment;

[0023] Figure 3 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0025] In one embodiment, an SPI module verification platform with a DMA interface is provided, comprising:

[0026] The simulation test top-level file is used to verify the initialization of the platform, connect the verification platform and the DUT, and start the test cases;

[0027] Basic testing components are used to create the platform environment and SPI configuration components, as well as provide common tasks for test cases.

[0028] The test case component is used to provide test cases for the functional testing of the module under test (DUT). The test cases complete the randomization of the SPI configuration component, the generation of test stimuli, and the initiation and execution of data packets. They also call the common tasks of the basic test components to compare transmitted data.

[0029] The environment creation component is used to encapsulate the components of the AHB verification system, configure the component parameters of the proxy components of the AHB verification system, and set up the SPI proxy components.

[0030] The simulation test top-level file, basic test components, and environment creation components constitute a multi-level verification platform; the test case components and environment creation components are connected through the SPI configuration component, and the module under test (DUT) is connected to the environment creation component through an interface.

[0031] The aforementioned SPI module verification platform with DMA interface is a multi-layered UVM verification platform built using SystemVerilog. It integrates the AHB verification system and DMA verification components. Functionally, it has good reusability, and for test cases, the SPI configuration component can generate randomized stimuli for verification. Structurally, the DMA interface verification of the SPI module can be implemented at the module level, allowing for thorough verification of the SPI module before system-level verification. Moreover, considering the complexity of the verification layers, module-level verification saves more time and manpower costs compared to system-level verification.

[0032] In one embodiment, such as Figure 1 As shown, for ease of description, the above terms are defined as follows: testbench represents the top-level simulation test file, base_test represents the basic test component, spi_cfg represents the SPI configuration component, testcase represents the test case component, and env represents the environment creation component.

[0033] Furthermore, the testbench layer is the top-level file, whose function is to complete the initialization of the verification platform, connect the verification platform and the DUT, and start the test cases through run_test(). The selection of specific test cases is specified by the UVM_TESTNAME macro in the external script Makefile. To facilitate the investigation of faults and bugs that occur during verification, simulation waveform generation code has been added.

[0034] In another embodiment, base_test is the base test case, which is the second layer of the multi-layer structure. Its function is to create the platform environment env, create spi_cfg, set up the simulation exit mechanism, and design several common tasks that can be used by test cases. It also includes a functional coverage collection component, which will automatically collect coverage each time different test cases are run.

[0035] In addition, a testcase is a series of test cases, which consists of multiple different test cases. It is a series of test cases designed for different functions of the DUT. The test cases complete the randomization of spi_cfg, the generation of test stimuli, the randomization of data packets, and the execution. In the testcase, the transmitted data can be compared by calling a specific task in base_test.

[0036] In one embodiment, the module under test (DUT) and the environment creation component are connected via the SPI protocol interface spi_if, the AHB bus interface ahb_if, and the DMA interface of the SPI module spi2dma_if.

[0037] In another embodiment, an environment creation component env is used for the encapsulation and instantiation of components in the overall system. It creates ahb_system_env, ahb_sys_cfg, and spi_agt, completing the connection work between the components.

[0038] Among them, ahb_system_env is used to complete the component encapsulation of the AHB verification system, and ahb_sys_cfg is used to complete the setting of component configuration parameters of the AHB system and pass the parameters to the lower-level drivers and monitors through the config_db mechanism.

[0039] Specifically, the agent component ahb_master_agt of the AHB verification system includes: the second sequence management sequencer, the AHB stimulus driver ahb_drv, and the AHB monitor ahb_mon.

[0040] In terms of specific functions, the ahb_drv excitation driver parses the AHB excitation and drives it to the AHB interface, writing the data to be written into the DUT's register through the interface.

[0041] The ahb_mon monitor monitors the signals on the AHB interface and collects the interface's signal data and timing behavior. It issues a simulation alarm when it detects incorrect or illegal timing behavior.

[0042] spi_agt proxy component: SPI proxy component, which encapsulates the first sequence management sequencer, SPI bus driver spi_drv, SPI bus monitor spi_mon, and DMA function driver spi2dma_drv.

[0043] spi_drv excitation driver: Drives the SPI excitation to the interface according to the SPI bus protocol, and drives the SPI bus according to the function of the DUT.

[0044] The spi_mon monitor monitors the timing and data on the SPI interface, and performs frequency division and duty cycle adjustments based on the DUT's clock configuration to ensure that the clock is as expected.

[0045] The spi2dma_drv driver monitors the DMA interface of the monitoring module, responds to DMA request signals, simulates DMA behavior by calling the sequencer in ahb_system_agt to initiate AHB bus transmission to the DUT, generates the corresponding request clear signal, and monitors the low pull of the request signal.

[0046] sequencer: Completes request scheduling between sequence generator and driver. After the sequence is generated, the sequencer sends the stimulus generated by the sequence generator to the driver and provides simultaneous arbitration of multiple sequences.

[0047] In addition, the spi_cfg configuration component: combines the configuration components of the platform components and the function configuration variables of the SPI module, and applies relevant constraints.

[0048] It is known that the present invention is equipped with two verification systems: an AHB verification system and a DMA verification component. Through a multi-level structure, it has good reusability. Randomized stimuli are used to verify SPI, and the verification extension of the DMA interface effectively saves the total verification time.

[0049] In one embodiment, a method for verifying an SPI module with a DMA interface is provided. This method can be applied to the aforementioned SPI module verification platform with a DMA interface to achieve SPI module verification with a DMA interface.

[0050] To more clearly demonstrate the above testing process, combined with Figure 2 The signal processing flow of the DMA interface shown is illustrated below, and a specific verification method is given as follows:

[0051] 1) Establish interfaces in the testbench layer. Instantiate the SPI protocol interface spi_if, AHB bus interface ahb_if, and DMA interface spi2dma_if required by the verification platform. Connect the SPI module under test to the verification platform through these interfaces, and pass these interfaces to the components below through the config_db mechanism. Set the module clock in the testbench and set the reset logic at the start of the simulation.

[0052] 2) Configure ahb_sys_cfg. Based on the characteristics of the SPI AHB interface, set the address width and data width parameters of the AHB interface.

[0053] 3) Instantiate ahb_system_env and spi_agt in env, and pass the AHB configuration ahb_sys_cfg to ahb_system_env using the config_db mechanism.

[0054] 4) Start the entire verification platform using the run_test() function in testbench. The verification platform will execute the code in each phase sequentially through the UVM phase mechanism.

[0055] 5) After the verification platform starts, spi_cfg will be instantiated and randomized in the test cases and the build_phase of base_test. Depending on the different functions being tested, various constraints will be attached to the randomization of spi_cfg in the test cases, and spi_cfg will be passed to the components of the lower-level spi_agt through config_db.

[0056] 6) Establish communication connections between the various components of the platform in the connect_phase.

[0057] 7) The main operation and processes of each component of the platform are executed in the main_phase. When entering the main_phase, the test case will create a sequence generator in UVM. In the sequence, randomized transaction packets, i.e., verification stimuli, are generated. Then, the stimuli are sent to ahb_drv and spi_drv through the sequencer using the seq.start method of UVM. The DUT registers are configured and SPI bus data is transmitted. The data to be transmitted on the SPI bus is stored in the set data queue.

[0058] 8) During SPI bus data transmission, spi_mon continuously monitors the SPI bus signal, collects transmission data, samples the SPI signal in real time according to the DUT configuration, performs logical judgments, checks the frequency and duty cycle of the bus clock, and generates UVM uvm_error error message if it finds any unexpected situation.

[0059] 9) If the DMA transfer function of the DUT is enabled, spi2dma_drv will collect the request signals of the DMA interface and call the sequencer in ahb_master_agt according to the type of request signal to perform read or write operations. It will also collect the AHB bus data involved in the read and write operations. After all the read and write operations of a request signal are completed, spi2dma_drv will pull up the request clear signal of the DUT and monitor the pull-down of the corresponding request signal.

[0060] 10) After the SPI bus data transmission is completed, the spi_check_data task in base_test can be called to compare the SPI transmitted data according to the DUT register configuration value and output the comparison result.

[0061] 11) In post_main_phase, functional coverage is achieved by collecting DUT register configuration information from spi_cfg.

[0062] 12) Finally, in the report_phase, error information is collected for the entire verification process and the verification results are output to realize an automated self-check process.

[0063] The above verification method allows for the automated execution of test cases, whether multiple or single, via scripts, facilitating comprehensive coverage collection. Furthermore, for complex and multifunctional SPI modules, the verification environment provided by this invention is concise, clear, and highly reusable, with distinct and independent layers. In particular, the setup of spi2dma_drv enables DMA interface verification of the SPI module to be implemented at the module level, allowing for thorough verification of the SPI module before system-level verification. Moreover, considering the complexity of the verification layers, module-level verification saves more time and manpower compared to system-level verification.

[0064] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 3 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for verifying an SPI module with a DMA interface. The display screen can be a liquid crystal display (LCD) or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0065] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0066] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in the above embodiment.

[0067] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0068] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A verification platform for an SPI module with a DMA interface, characterized in that, The platform includes: The simulation test top-level file is used to verify the initialization of the platform, connect the verification platform and the DUT, and start the test cases; Basic testing components are used to create the platform environment and SPI configuration components, as well as provide common tasks for test cases. The test case component is used to provide test cases for the functional testing of the module under test (DUT). The test cases complete the randomization of the SPI configuration component, the generation of test stimuli, and the initiation and execution of data packets. The common task of the basic test component is called to compare transmitted data. The environment creation component is used to encapsulate the components of the AHB verification system, configure the component parameters of the proxy components of the AHB verification system, and set up the SPI proxy components. The simulation test top-level file, the basic test component, and the environment creation component constitute a multi-level verification platform; the test case component and the environment creation component are connected through the SPI configuration component, and the module under test (DUT) is connected to the environment creation component through an interface. The SPI proxy component includes a first sequence manager, an SPI bus driver, an SPI bus monitor, and a DMA function driver; The first sequence manager is connected to the SPI bus driver, and the SPI bus driver and the SPI bus monitor are connected to the SPI protocol interface; The DMA function driver is connected to the DMA interface of the module under test (DUT); The DMA function driver is used to monitor and respond to DMA request signals through the DMA interface of the module under test (DUT), simulate DMA behavior, call the sequence management in the proxy component of the AHB verification system to initiate AHB bus transmission to the DUT, generate a request clear signal corresponding to the DMA request signal, and monitor the low pull of the DMA request signal.

2. The verification platform according to claim 1, characterized in that, The module under test (DUT) is connected to the environment creation component via an SPI protocol interface, an AHB bus interface, and the DMA interface of the SPI module.

3. The verification platform according to claim 2, characterized in that, The SPI protocol interface is used to connect to the proxy component of the AHB verification system of the environment creation component, and the AHB bus interface and the DMA interface of the SPI module are used to connect to the SPI proxy component of the environment creation component.

4. The verification platform according to claim 2, characterized in that, The proxy components of the AHB verification system include: a second sequence management, an AHB stimulus driver, and an AHB monitor; The second sequence management is connected to the AHB excitation driver; The AHB excitation driver and the AHB monitor are connected to the AHB bus interface.

5. A verification method for an SPI module with a DMA interface, characterized in that, Applied to the SPI module verification platform with DMA interface as described in any one of claims 1 to 4, it realizes the verification of SPI module with DMA interface.

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