A data processing method and apparatus

Abstract

The application discloses a data processing method and device, wherein the data processing method comprises: obtaining a first intermediate object to be processed from a first storage area of a current kernel in a preset kernel set; the first intermediate object is generated based on a corresponding intermediate object to be processed of a target data object by a previous kernel corresponding to the current kernel in the preset kernel set and processing of the previous kernel; processing the first intermediate object by the current kernel, generating a second intermediate object to be processed by a next kernel corresponding to the current kernel in the preset kernel set based on a processing result; and writing the second intermediate object into a second storage area of the next kernel by the current kernel for processing by the next kernel. The preset kernel set is a set formed by kernels occupied by the target data object on a processor; each kernel in the preset kernel set corresponds to a corresponding storage area.

Description

Technical Field

[0001] This application belongs to the field of artificial intelligence technology, and in particular relates to a data processing method and apparatus. Background Technology

[0002] In applications of deep neural networks (DNNs) inference, especially in the field of computer vision, convolutional neural networks (CNNs) are the mainstream network architecture. CNNs perform computation layer by layer, and known technologies have limitations in the data computation process, including low efficiency, high latency, and high bandwidth and power consumption requirements. Summary of the Invention

[0003] Therefore, this application discloses the following technical solution:

[0004] A data processing method, the method comprising:

[0005] The first intermediate object to be processed is obtained from the first storage area of ​​the current kernel in the preset kernel set; the first intermediate object is generated by the current kernel processing the corresponding intermediate object to be processed of the target data object in the previous kernel corresponding to the preset kernel set, and based on the processing result.

[0006] The current kernel processes the first intermediate object, and based on the processing result, generates a second intermediate object to be processed by the next kernel corresponding to the current kernel in the preset kernel set.

[0007] The current kernel writes the second intermediate object to the second storage area of ​​the next kernel for processing by the next kernel;

[0008] The preset kernel set is a collection of kernels occupied by the target data object on the processor; each kernel in the preset kernel set corresponds to a corresponding storage area.

[0009] Optionally, generating a second intermediate object based on the processing result, to be processed by the next kernel corresponding to the current kernel in the preset kernel set, includes:

[0010] The processing result of the first intermediate object is used as the second intermediate object;

[0011] Alternatively, the second intermediate object can be generated based on the first intermediate object and the processing result of the first intermediate object.

[0012] Optionally, the storage area corresponding to each kernel in the preset kernel set is: the cache area corresponding to the local cache integrated in each kernel; each kernel in the preset kernel set also has a corresponding shared cache, and the local cache of each kernel and the shared cache are respectively corresponding to the cache address obtained based on the unified addressing.

[0013] The shared cache is used to store at least one of the following: the target data object, the data processing result obtained by the processor after processing the target data object, and the information required by the processor to process the target data object.

[0014] Optionally, the kernels and shared cache in the preset kernel set are interconnected via an on-chip network;

[0015] The step of writing the second intermediate object into the second storage area of ​​the next kernel in the current kernel includes:

[0016] The current kernel writes the second intermediate object into the local cache of the next kernel through the target segment link, based on the cache address of the local cache of the next kernel.

[0017] The target sub-segment link is the portion of the communication link provided by the on-chip network used to connect the current kernel and the next kernel.

[0018] Optionally, the on-chip network interconnects the various cores in the preset kernel group and the shared cache shared by each core through a provided ring communication link or mesh communication link;

[0019] Among them, different target kernel pairs in the preset kernel set are interconnected between two kernels in their respective target kernel pairs by using different non-overlapping sub-segments of the ring communication link or the mesh communication link; the target kernel pair is a kernel pair formed by adjacent kernels in the preset kernel set.

[0020] Optionally, each kernel in the preset kernel set is used to: perform data processing corresponding to the corresponding network layer in the preset network layer set within the neural network model in a one-to-one manner;

[0021] The process of processing the first intermediate object in the current kernel includes:

[0022] Obtain the weight parameters of the network layer corresponding to the current kernel in the preset network layer set, and process the first intermediate object in the current kernel according to the weight parameters.

[0023] Optionally, each kernel in the preset kernel set is used to perform data processing corresponding to at least one network layer in the preset network layer set within the neural network model, and there is at least one kernel used to perform data processing corresponding to multiple network layers in the preset network layer set; different kernels correspond to different network layers;

[0024] The process of processing the first intermediate object in the current kernel includes:

[0025] If the current kernel corresponds to a network layer, obtain the weight parameters of the network layer corresponding to the current kernel, and process the first intermediate object in the current kernel according to the weight parameters.

[0026] If the current kernel corresponds to multiple network layers, obtain the weight parameters of the multiple network layers corresponding to the current kernel, process the first intermediate object according to the weight parameters of the first network layer among the multiple network layers, generate an intermediate object to be processed by the next network layer among the multiple network layers based on the processing result of the first intermediate object, and process it by the next network layer until the last network layer among the multiple network layers completes the data processing, and obtain the processing result of the current kernel on the first intermediate object.

[0027] Optionally, the preset kernel set includes at least two processor clusters, each processor cluster consisting of multiple cores from the preset kernel set, and different processor clusters have different cores; different processor clusters interconnect their respective cores through different on-chip networks; different processor clusters have corresponding shared caches, and different processor clusters and processor clusters are interconnected with each other and with the shared cache through on-chip networks;

[0028] The process of writing the second intermediate object into the second storage area of ​​the next kernel in the current kernel includes:

[0029] If the next kernel and the current kernel belong to the same processor cluster, the current kernel writes the second intermediate object into the local cache of the next kernel through the first target segment link according to the cache address of the local cache of the next kernel.

[0030] If the next kernel and the current kernel belong to different processor clusters, the current kernel writes the second intermediate object into the local cache of the next kernel through the second target segment link according to the cache address of the local cache of the next kernel.

[0031] Wherein, the first target sub-segment link is the portion of the first on-chip network corresponding to the same processor cluster used to connect the current kernel and the next kernel; the second target sub-segment link is the portion of the second on-chip network used for inter-cluster interconnection that connects the processor cluster to which the current kernel belongs and the processor cluster to which the next kernel belongs.

[0032] Optionally, different target data objects can be processed in parallel across different kernels of the preset kernel set.

[0033] A data processing apparatus, the apparatus comprising:

[0034] The acquisition unit is used to acquire a first intermediate object to be processed from the first storage area of ​​the current kernel in the preset kernel set; the first intermediate object is generated by the current kernel processing the corresponding intermediate object to be processed of the target data object in the previous kernel corresponding to the preset kernel set, and based on the processing result.

[0035] The data processing unit is used to process the first intermediate object in the current kernel and generate a second intermediate object to be processed by the next kernel corresponding to the current kernel in the preset kernel set based on the processing result.

[0036] A write processing unit is configured to write the second intermediate object into a second storage area of ​​the next kernel in the current kernel, so that it can be processed by the next kernel;

[0037] The preset kernel set is a collection of kernels occupied by the target data object on the processor; each kernel in the preset kernel set corresponds to a specific storage area.

[0038] As can be seen from the above scheme, this application discloses a data processing method and apparatus. The data processing method includes: obtaining a first intermediate object to be processed from a first storage area of ​​the current kernel in a preset kernel set; the first intermediate object is generated by the current kernel processing a corresponding intermediate object of a target data object in the previous kernel corresponding to the target data object in the preset kernel set, and based on the processing result; while the current kernel processes the first intermediate object, a second intermediate object is generated based on the processing result to be processed by the next kernel corresponding to the current kernel in the preset kernel set; the current kernel writes the second intermediate object into a second storage area of ​​the next kernel for processing by the next kernel. The preset kernel set is a collection of kernels occupied by the target data object on the processor; each kernel in the preset kernel set corresponds to a specific storage area. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the cache architecture of a multi-core NPU;

[0041] Figure 2 This is a flowchart illustrating the data processing method provided in this application;

[0042] Figure 3 This is a schematic diagram of the processing logic of each network layer in a residual neural network;

[0043] Figure 4 This is a schematic diagram illustrating the unified addressing of kernel local cache and shared caches at all levels, as provided in this application.

[0044] Figure 5 This is a schematic diagram illustrating the interconnection of the kernel local cache with shared caches at various levels via an on-chip network, as provided in this application.

[0045] Figure 6 This is a schematic diagram illustrating the data processing based on the line buffer calculation method for convolution calculation in the network layer of the neural network model provided in this application;

[0046] Figure 7 This is a schematic diagram of the computing network architecture based on processor clusters provided in this application;

[0047] Figure 8 This is a structural diagram of the data processing apparatus provided in this application;

[0048] Figure 9 This is a structural diagram of the electronic device provided in this application. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] In applications of deep neural network inference / training, especially in the field of computer vision, CNN is the mainstream network architecture. The computation of a CNN network is performed layer by layer (network layers of the neural network model) within the NPU (Neural Processing Unit). Specifically, the input feature map of each network layer is used as the input to that layer, and convolution, activation function operations, and other processing are performed on it to output the corresponding features. This computation process is repeated from the first layer to the last layer until the final output is obtained.

[0051] Neural network inference / training can be implemented using multi-core (typically several or dozens) NPUs. In such systems, the visible memory resources of each NPU are usually divided into three or more layers of cache, see [link to documentation]. Figure 1 The provided diagram illustrates the cache architecture of a multi-core NPU, including top-down local cache, L2 cache, and lower-level caches such as system cache and Double Data Rate (DMR) synchronous dynamic random access memory (DDR). An NPU typically has its own local cache, also known as the L1 cache. This local cache is private to each core of the NPU, characterized by tight coupling, low latency, and high bandwidth, but with a relatively small capacity. The L2 cache, along with its lower-level caches (such as system cache and DDR), can be shared by more cores. It has a large capacity but, compared to L1, has higher latency and lower bandwidth.

[0052] In known technologies for CNN-based deep neural network inference / training applications, the computation process for multi-core NPUs is mainly implemented in the following ways:

[0053] For each layer of a neural network model, the input feature map is divided into different rectangular tiles. These tiles are assigned as different subtasks to different kernels in the NPU for separate computation. The output feature maps from all kernels must precisely cover the entire output feature map. The entire CNN network is computed layer by layer in this manner until the final layer outputs. In this process, each kernel needs to read the relevant tile data of the input feature map from a shared cache such as DDR for processing the current layer, and then cache it back to DDR for integration and processing of the next layer's data.

[0054] However, in this approach, each kernel needs to frequently interact with the shared cache, resulting in high bandwidth requirements. This can cause the bandwidth of the shared cache to become a bottleneck, leading to problems such as low efficiency, high latency, and high power consumption in the network computing process.

[0055] To address at least some of the technical problems existing in the known technologies, embodiments of this application disclose a data processing method and apparatus. This method can be applied to, but is not limited to, electronic devices in a variety of general-purpose or special-purpose computing device environments or configurations, such as: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor devices, etc.

[0056] See Figure 2 The diagram illustrates a flowchart of the data processing method provided in this application, which includes:

[0057] Step 201: Obtain the first intermediate object to be processed from the first storage area of ​​the current kernel in the preset kernel set; the first intermediate object is generated by the current kernel processing the corresponding intermediate object to be processed for the target data object in the previous kernel in the preset kernel set, and based on the processing result.

[0058] The preset kernel set is a collection of kernels occupied by the target data object on the processor; each kernel in the preset kernel set corresponds to a corresponding storage area.

[0059] The number of kernels occupied by the target data object on the processor can be one or more processors, without restriction, depending on the actual needs.

[0060] The target data object is the data object to be processed in the corresponding data processing scenario. It can be, but is not limited to, various types of data information such as images, voice, and video, depending on the actual needs.

[0061] This application mainly uses data processing in the inference / training application scenario of neural network models (such as deep neural network models) as an example to illustrate the solution.

[0062] For example, in the inference / training application scenario of deep neural network models, the target data object can specifically be various types of information such as images, speech, and video to be processed by the deep neural network model. The intermediate object to be processed from the target data object can be the input feature map of the image, speech, video, and other data information on the corresponding input channels of the model's network layers during processing. The network layers in the neural network model can be convolutional layers or fully connected layers. Taking image processing based on a neural network model as an example, the intermediate object to be processed from the target data object can specifically be, but is not limited to, the input feature maps on the R, G, and B primary color input channels and texture and semantic input channels of each convolutional layer of the model.

[0063] The data processing method provided in this application can be applied to various fields, including but not limited to natural language processing, image processing, video processing, speech recognition, and industrial inspection (such as equipment defect detection).

[0064] The processor used to process the target data object can be determined according to the specific application scenario, and can be, but is not limited to, various types of processors such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), and NPU. For the inference / training application scenario of neural network models, the processor used may optionally be an NPU, and in the embodiments of this application, the processor used is specifically a multi-core NPU, including multiple independent cores.

[0065] For the target data object to be processed, this application embodiment allocates multiple cores from the various cores contained in the processor such as the NPU to perform data processing on the target data object. That is, the target data object occupies multiple cores on the processor, and the various cores occupied by the target data object on the processor form the preset core set described in this application embodiment.

[0066] Each kernel in the pre-defined kernel set has a corresponding storage area. Optionally, the storage area corresponding to each kernel may be, but is not limited to, the cache area corresponding to the local cache integrated in each kernel, such as L1 mentioned above.

[0067] In this context, the intermediate object to be processed in the first kernel of the preset kernel set is the target data object. That is, if the current kernel is the first kernel in the preset kernel set, then the first intermediate object to be processed obtained from the first storage area of ​​the current kernel in this step is specifically the target data object obtained from the local cache of the first kernel in the preset kernel set. If the current kernel is a kernel other than the first kernel in the preset kernel set, the first intermediate object is the result generated by the processing of the corresponding intermediate object to be processed by the previous kernel corresponding to the target data object in the preset kernel set, based on the processing result.

[0068] Step 202: While the current kernel processes the first intermediate object, a second intermediate object is generated based on the processing result and is to be processed by the next kernel corresponding to the current kernel in the preset kernel set.

[0069] After obtaining the first intermediate object to be processed in the current kernel of the preset kernel set, the required processing is performed on the first intermediate object based on the processing requirements of the application scenario.

[0070] For example, in inference / training applications of neural network models (such as deep neural network models), the obtained input feature maps and other first intermediate objects can be processed as needed, such as convolution and activation function calculation.

[0071] The input feature map can be, but is not limited to, intermediate data to be processed corresponding to various types of information such as images and speech. Specifically, one-dimensional convolution, two-dimensional convolution, or three-dimensional convolution can be performed on the input feature map, without restriction, depending on the actual needs. For example, for a 1*3 size one-dimensional convolution kernel, one-dimensional convolution can be performed on the input feature map based on a 1*3 kernel weight matrix; for a 3*3 size two-dimensional convolution kernel, two-dimensional convolution can be performed on the input feature map based on a 3*3 kernel weight matrix.

[0072] After processing the first intermediate object, a second intermediate object is generated based on the processing result of the first intermediate object, which is to be processed by the next kernel corresponding to the current kernel in the preset kernel set.

[0073] Optionally, in one embodiment, the processing result of the first intermediate object can be directly used as the second intermediate object to be processed by the next kernel corresponding to the current kernel in a preset kernel set.

[0074] However, this is not the only option. In other implementations, a second intermediate object can be generated based on the first intermediate object and the processing result of the first intermediate object, to be processed by the next kernel corresponding to the current kernel in a preset kernel set.

[0075] For example, for residual neural networks such as ResNet, see [link to relevant documentation]. Figure 3 The diagram illustrates the processing logic of the model network. Specifically, the output of each network layer is added to its input as the input of the next network layer. In this case, the processing result of the first intermediate object can be added to the first intermediate object, and the sum can be used as the second intermediate object to be processed by the next kernel in the preset kernel set. For non-residual neural networks, the output of each network layer can be directly used as the input of the next network layer, and the processing result of the first intermediate object can be directly used as the second intermediate object to be processed by the next kernel in the preset kernel set.

[0076] Step 203: The current kernel writes the second intermediate object into the second storage area of ​​the next kernel for processing by the next kernel.

[0077] After obtaining the second intermediate object to be processed by the next kernel in the preset kernel set, the current kernel directly writes the second intermediate object into the second storage area corresponding to its (current kernel's) next kernel, so that the next kernel can directly read the second intermediate object from its own corresponding second storage area for data processing.

[0078] For example, the current kernel performs the corresponding convolution and activation function calculations on the first intermediate object, and uses the calculation results as the input feature map of the next kernel, writing it into the local cache of the next kernel, without having to go through any shared cache (such as L2 or DDR).

[0079] This application proposes a technical approach whereby each kernel in a preset kernel set sequentially processes the intermediate objects output by the previous kernel, and writes the processed intermediate objects to be processed by the next kernel into the storage area of ​​the next kernel for the next kernel to retrieve and process. In other words, each kernel interacts directly with the other kernel through its corresponding storage area (such as its own integrated local cache), and data interaction between different kernels does not rely on shared caches (such as L2 cache, DDR, etc.) as intermediaries.

[0080] Each kernel in the preset kernel set performs the same type of operation on its corresponding intermediate object to be processed. For example, each kernel performs the corresponding convolution and activation function calculation on the input feature map of the corresponding network layer and outputs the corresponding features for the kernel corresponding to the next network layer to process. This calculation process is repeated from the first kernel to the last kernel until the final output is obtained.

[0081] It is easy to understand that the intermediate object output by the last kernel in the preset kernel set is the final data processing result of the target data object in the processor.

[0082] In summary, the data processing method provided in this application, by sequentially processing the intermediate objects output by the previous kernel in each kernel of a preset kernel set, and writing the processed intermediate objects to be processed by the next kernel into the storage area of ​​the next kernel for the next kernel to retrieve and process, eliminates the need for data interaction between different kernels to rely on shared caches (such as L2 cache, DDR, etc.), significantly improving the processing efficiency of the target data object on the processor (such as NPU) and reducing processing latency. Furthermore, since each kernel sequentially processes the intermediate objects output by the previous kernel, each kernel does not need to engage in centralized data interaction with any shared cache, avoiding the shared cache becoming a communication bottleneck in the data path, thereby simultaneously reducing bandwidth and power consumption requirements during data processing.

[0083] In one optional embodiment, the storage area corresponding to each kernel in the preset kernel set is: the cache area corresponding to the local cache integrated in each kernel. For example, the cache area corresponding to the local cache integrated in the NPU kernel.

[0084] Each kernel in the pre-defined kernel set also has a corresponding shared cache. The corresponding shared cache can have one or more levels without restriction. For example, the corresponding shared cache includes the L2 cache mentioned above, as well as the system cache, DDR, and other lower-level caches.

[0085] In this embodiment, the local cache and other storage areas of each kernel in the preset kernel set, as well as the shared cache shared by each kernel, are uniformly addressed, so that the local cache and other storage areas of each kernel and the shared cache are respectively addressed to cache addresses obtained based on the unified addressing. Accordingly, logically speaking, the local cache and other storage areas of each kernel and the shared cache shared by each kernel are uniformly addressed to a whole storage space.

[0086] See Figure 4 In this example, the local cache of each kernel in a preset kernel set (such as the preset kernel set of the NPU), as well as the shared caches such as L2 and DDR caches common to all kernels, are uniformly addressed into a single storage space. Through the address information obtained by the unified addressing, any kernel can directly access the shared cache and the local cache of other kernels, so that the local cache is no longer private to the corresponding kernel. This allows each kernel in the preset kernel set to directly and interactively access other kernels as needed through the corresponding unified address, without having to rely on the intermediate shared cache.

[0087] Thus, after the current kernel in the preset kernel set completes the data processing of the first intermediate object and generates the second intermediate object based on the processing result, which will be processed by the next kernel in the preset kernel set, the current kernel can directly write the second intermediate object into the storage area corresponding to the next kernel according to the unified address information of the storage area such as the local cache. The next kernel can then directly read the second intermediate object from its own local cache and other storage areas to perform the required data processing, without having to obtain it from the shared cache through interaction with the shared cache.

[0088] Shared cache may store, but is not limited to, at least one of the following: target data objects to be processed by processors such as NPUs, data processing results obtained by processors such as NPUs after processing the target data objects, and information required by processors such as NPUs to process the target data objects.

[0089] For example, in the inference / training application scenario of deep neural networks, the information that the processor needs to process the target data object may include the weight parameters required by the network layers of the neural network model to process the input feature map (intermediate object), such as the weight matrix of the convolutional layer.

[0090] In practical applications, information such as weight parameters required for processing the target data object can be stored in the secondary cache or lower-level system cache, DDR, or other shared caches in advance. Preferably, during the initialization phase, each kernel in the preset kernel set reads the data processing information, such as the weight parameters of the corresponding network layer, from the shared cache into its own local cache. This allows the corresponding intermediate data object and network layer weight parameters to be read directly from their respective local caches during data processing, thereby maximizing data processing efficiency and reducing latency.

[0091] For the data processing result of the last kernel in the preset kernel set, it can be used as the final processing result of the target data object in the processor and output to the shared cache, such as the unified address of the L2 cache or the system cache, so as to facilitate the subsequent reading of the processing result of the target data object from the corresponding shared cache to carry out the required application, such as reading the classification result of voice, image and other data information for corresponding decision-making applications.

[0092] This embodiment unifies the addressing of the local caches and other storage areas of each kernel in the preset kernel set, as well as the shared cache, into a unified storage space. This makes the local cache no longer private to the corresponding kernel, thus supporting different kernels in the preset kernel set to directly and interactively access each other on demand through the corresponding unified address, without relying on the intermediate shared cache. This overcomes the technical problems of low efficiency and high latency in the data computation process of known CNN networks.

[0093] In one optional embodiment, the kernels and shared caches in the preset kernel set are interconnected through a network on chip (NoC) to connect the local caches of each kernel in the preset kernel set with the shared caches of each kernel into a whole storage space. The interconnection between the local caches and shared caches of each kernel is realized based on the communication link provided by the network on chip and combined with unified addressing.

[0094] During data processing, when the current kernel needs to write the processed second intermediate object into the second storage area of ​​the next kernel corresponding to the current kernel in the preset kernel set, specifically, the current kernel can write the second intermediate object into the local cache of the next kernel through the target segment link according to the cache address of the local cache of the next kernel.

[0095] The target segment link is the part of the communication link provided by the on-chip network used to connect the current kernel and the next kernel.

[0096] See Figure 5 In the provided example, all kernels in the preset kernel set, along with the L2 cache and the underlying DDR, are interconnected via a NOC (Network On-Chip). Thus, the first kernel in the preset kernel set ( Figure 5 Core 0 in the middle can directly write the calculated result data to be processed by the next kernel to the second kernel through its corresponding sub-segment link in the NOC. Figure 5 The data flow between kernels is similar, with kernel 1 being the internal local cache and not requiring a shared cache such as L2.

[0097] The communication links provided by the on-chip network can be, but are not limited to, ring or mesh. Accordingly, the pre-defined kernel centralization and the shared cache of each kernel can be interconnected through the ring or mesh communication links provided by the on-chip network.

[0098] Each kernel pair in the pre-defined kernel set has its own sub-segment link in the communication link provided by the on-chip network. Based on the corresponding sub-segment link and combined with the local cache address information obtained by unified addressing, direct data interaction can be performed between the local caches of the two kernels contained in each kernel pair.

[0099] In this application, each kernel in the preset kernel set processes the intermediate object output by the previous kernel in sequence, and writes the intermediate object to be processed by the next kernel into the storage area of ​​the next kernel for the next kernel to obtain and process. Therefore, under normal circumstances, there is only data interaction between adjacent kernels in the preset set.

[0100] In this application embodiment, the kernel pair formed by adjacent kernels in the preset kernel set is referred to as the target kernel pair.

[0101] Preferably, different target kernel pairs in the preset kernel set are interconnected between two kernels in their respective target kernel pairs using different non-overlapping sub-segments of the ring communication link or the mesh communication link, so as to avoid data transmission conflicts on the same segment (i.e. the same sub-segment) of the on-chip network, and correspondingly avoid transmission waiting and delay caused by data transmission conflicts.

[0102] This embodiment, based on the communication link provided by the on-chip network and combined with unified addressing, realizes the interconnection between local caches and shared caches of each kernel. It supports direct interaction between kernels in a preset kernel set, eliminating the need to use shared caches as intermediaries and preventing shared caches (such as L2 cache or system cache) from becoming communication bottlenecks in the data path. This enables each kernel to process complete intermediate data objects (such as the complete input feature map of the network layer) without having to split the complete input feature map of the network layer into multiple subtasks and distribute them to multiple kernels and then integrate the results. This effectively improves data processing efficiency, reduces latency, and lowers power consumption requirements.

[0103] In one optional embodiment, for inference / training applications of deep neural networks, each kernel in the preset kernel set is used to: perform data processing corresponding to the corresponding network layer in the preset network layer set within the neural network model in a one-to-one manner. The preset network layer set can be a collection of various convolutional layers or fully connected layers of the neural network model.

[0104] In step 102 of this application, processing the first intermediate object in the current kernel can be implemented as follows: obtaining the weight parameters of a network layer corresponding to the current kernel in a preset network layer set, and processing the first intermediate object in the current kernel according to the obtained weight parameters.

[0105] Taking a convolutional layer as an example, the weight parameters of the network layer corresponding to the current kernel can specifically include the weight matrix of the convolutional layer corresponding to the current kernel.

[0106] During data processing, each kernel can read the weight parameters of the network layer it is responsible for from the shared cache (such as L2 cache or lower-level cache DDR), or it can write the weight parameters of the corresponding network layer from the shared cache to its own local cache during the initialization phase. This supports each kernel directly reading the weight parameters of the network layer it is responsible for from its own local cache for data processing. The latter implementation method is preferred to maximize data processing efficiency and reduce latency.

[0107] For each kernel in the preset kernel set, this embodiment adopts a multi-core serial connection method, with each kernel computing one network layer of the neural network model, to realize multi-core pipelined computing of the target data objects (such as sound, image, video, etc.) to be processed by the model.

[0108] In the multi-core pipelined computation of the target data object, each kernel in the preset kernel set sequentially obtains the intermediate object written by the previous kernel into its own kernel storage area (such as local cache), and processes the obtained intermediate object using the weight parameters of the network layer it is responsible for, thereby realizing the data computation of the network layer it is responsible for. Then, the data (intermediate object) to be processed by the next network layer is written into the storage area of ​​the next kernel for the next kernel to obtain and process.

[0109] See also Figure 5 Taking a ring-shaped NOC interconnect structure as an example, after core 0 completes the first-layer calculation based on the weight parameters of the first layer and obtains the data to be processed by the second layer, it directly writes the data to the local cache of core 1 through the link between core 0 and core 1 in the NOC ring topology. After core 1 completes the calculation on the data in its own local cache based on the weight parameters of the second layer and obtains the data to be processed by the third layer, it writes the data to the local cache of core 2 through the link between core 1 and core 2 in the NOC ring topology for processing by core 2, and so on.

[0110] Each layer's processing may include convolution, activation function operations, etc. Optionally, neural network models such as CNNs may use a line buffer-based computation method for convolution calculations in each layer. In this case, the local buffer of each kernel can operate in a FIFO (First-In, First-Out) manner. As long as there is enough pixel data from the input feature map to fill the line buffer, the corresponding calculation can be performed. For example, a typical CNN network uses 3x3 convolutions for computation. Figure 6 As shown in the figure (kh and kw in the figure represent the height and width of the input feature map of the kth network layer, respectively), as long as the three rows of input feature map data are filled, pipelined convolution calculation can be achieved, and the generated data to be calculated by the next kernel is passed to the local cache of the next kernel for the next layer calculation.

[0111] The first layer, second layer, third layer, etc. mentioned above refer to the first network layer, second network layer, and third network layer in the preset network layer set of the neural network model, respectively.

[0112] This embodiment utilizes a multi-core pipeline approach, where each core computes one network layer of the neural network model. This multi-core pipeline approach effectively reduces the latency of the overall data path and prevents shared caches (such as shared L2 cache) from becoming communication bottlenecks. Compared to known technologies, this significantly improves data processing efficiency, reduces latency, and lowers power consumption. Furthermore, it is compatible with known technologies, allowing the same hardware architecture to still be used to implement deep neural network computations.

[0113] In an optional embodiment, for the inference / training application scenario of deep neural networks, each kernel in the preset kernel set is used to perform data processing corresponding to at least one network layer in the preset network layer set within the neural network model. Unlike the previous embodiment, in this embodiment, there is at least one kernel in the preset kernel set used to perform data processing corresponding to multiple network layers in the preset network layer set; different kernels correspond to different network layers.

[0114] In step 102 of this application's method, processing the first intermediate object in the current kernel can be implemented as follows:

[0115] a1) If the current kernel corresponds to a network layer, obtain the weight parameters of the network layer corresponding to the current kernel, and process the first intermediate object in the current kernel according to the weight parameters.

[0116] For example, obtain the weight matrix of a convolutional layer corresponding to the current kernel, and perform convolution processing on the input feature map of the convolutional layer in the current kernel according to the obtained weight matrix of the convolutional layer.

[0117] b1) If the current kernel corresponds to multiple network layers, obtain the weight parameters of the multiple network layers corresponding to the current kernel, process the first intermediate object according to the weight parameters of the first network layer among the multiple network layers; generate an intermediate object to be processed by the next network layer among the multiple network layers based on the processing result of the first intermediate object, so that it can be processed by the next network layer, until the last network layer among the multiple network layers completes the data processing, and obtain the processing result of the current kernel on the first intermediate object.

[0118] For cases where the current kernel corresponds to multiple network layers, pipelined convolution processing is performed on the multiple network layers corresponding to the current kernel. That is, the multiple network layers corresponding to the current kernel sequentially process the intermediate objects output by the previous network layer until the output result of the last network layer among the multiple network layers is obtained, which is then used as the output of the current kernel.

[0119] In practical applications, if the number of network layers in the preset network layer set of a neural network model is greater than the number of available cores provided by the preset kernel set of a processor (such as an NPU), the limitation that each kernel can only execute one layer (network layer) can be broken. The processing tasks of multiple network layers can be allocated to the same kernel for execution, so that there is at least one kernel in the preset kernel set to execute the data processing corresponding to multiple network layers in the preset network layer set. In this way, multiple network layers with a number greater than the number of cores can be adapted to a processor with a fixed number of cores without the need for additional processor resource scheduling.

[0120] In one optional embodiment, the preset kernel set includes at least two processor clusters, each processor cluster consisting of multiple cores from the preset kernel set, and different processor clusters have different cores; different processor clusters interconnect their respective cores through different on-chip networks; different processor clusters have corresponding shared caches, and different processor clusters and processor clusters are interconnected with each other and with the shared cache through on-chip networks.

[0121] The kernels in the same or different processor clusters can be kernels provided by the same processor or kernels provided by different processors, without restriction.

[0122] In step 103 of this application, writing the second intermediate object into the second storage area of ​​the next kernel in the current kernel can be implemented as follows:

[0123] a2) If the next kernel and the current kernel belong to the same processor cluster, the current kernel writes the second intermediate object into the local cache of the next kernel through the first target segment link according to the cache address of the local cache of the next kernel.

[0124] The first target segment link is the portion of the first on-chip network corresponding to the same processor cluster used to connect the current kernel and the next kernel.

[0125] b2) If the next kernel and the current kernel belong to different processor clusters, the current kernel writes the second intermediate object into the local cache of the next kernel through the second target segment link according to the cache address of the local cache of the next kernel.

[0126] The second target segment link is the portion of the second on-chip network used for inter-cluster interconnection that connects the processor cluster to which the current core belongs with the processor cluster to which the next core belongs.

[0127] In practical applications, when the deep neural network model involves too many network layers, and consequently requires too many processor cores to participate in the computation, making it difficult to interconnect the cores and their shared caches using a single on-chip network, the approach described in this embodiment can be adopted. The cores are divided into multiple processor clusters, each containing multiple cores. These clusters are then interconnected both within and between different on-chip networks. Specifically, within each processor cluster, an on-chip network interconnects the cores within that cluster. Externally, each processor cluster is treated as a connection object, and another on-chip network interconnects the clusters and their corresponding shared caches. This hierarchically organizes the cores involved in the computation into a larger computational network architecture.

[0128] See Figure 7 In this example, there are two processor clusters. The cores within each processor cluster are interconnected using an on-chip network. The two processor clusters and their corresponding shared caches are interconnected using another on-chip network. The entire computing network architecture uses a total of three on-chip networks.

[0129] The local caches of the cores within each processor cluster, as well as the shared caches corresponding to different processor clusters, are also addressed to a unified storage space using a unified addressing method. Different cores within a processor cluster and between different processor clusters can perform cross-cluster / non-cross-cluster data access to the local caches or shared caches of the required cores based on the address information obtained from the unified addressing and the corresponding segment links provided by the on-chip network.

[0130] The computational method employed in the processor cluster-based computing network architecture remains the pipelined approach described above. That is, each core within and between processor clusters sequentially processes the intermediate objects output by the previous core, and writes the resulting intermediate objects, awaiting processing by the next core, into the next core's local cache based on their corresponding unified address, for the next core to retrieve and process. Specifically, if the next core and the current core belong to the same processor cluster, the corresponding intermediate objects generated by the current core are written to the next core's local cache via the first target segment link within that same processor cluster, connecting the current core and the next core. If the next core and the current core belong to different processor clusters, the corresponding intermediate objects generated by the current core are written to the next core's local cache via the corresponding second target segment link of the on-chip network connecting the processor cluster to which the current core belongs and the processor cluster to which the next core belongs, so that the next core can retrieve and process them.

[0131] In a processor cluster-based computing network architecture, each core in the processor cluster can perform data processing corresponding to one network layer of a neural network model, or it can perform data processing corresponding to multiple network layers of a neural network model without restriction, depending on the actual needs.

[0132] It should be noted that the embodiments of this application employ a pipelined processing approach for the same target data object. For example, for a specific image to be processed by a neural network model, the computational processing of the corresponding data to be processed by each network layer (such as the input feature maps of the image in each convolutional layer) is performed in a pipelined manner in a one-to-one manner within each kernel. However, for different target data objects, parallel processing can be performed between different kernels in a preset kernel set. For example, for... Figure 5For example, for the same image, data processing in each network layer is performed sequentially by kernels 0-3 in a pipeline manner (serial manner), while kernels 0-3 can simultaneously process the corresponding network layer input feature maps of different images in parallel to ensure the efficiency of data processing.

[0133] In summary, compared with known technologies, the data processing method of this application embodiment has achieved optimizations in multiple aspects such as bandwidth requirements, cache usage, computational workload, and processing efficiency. The bandwidth requirements, cache usage, and computational workload are all significantly reduced compared with known technologies, improving processing efficiency and reducing latency.

[0134] Specifically, in this embodiment, the computation and read / write operations of each network layer in the neural network model are mapped to a specific core of the processor (NPU). This eliminates the need for collaboration between different cores to perform operations on a complete network layer. Consequently, it avoids the need to process the complete input feature map of the network layer by splitting it into multiple subtasks and distributing them across multiple cores, followed by result integration. This saves the bandwidth required for data distribution and result integration using shared caches across different cores, reducing bandwidth requirements and computational workload, improving processing efficiency, and lowering latency. Furthermore, since the computation and read / write operations of different network layers are essentially fixed on different cores, bandwidth is largely uniform, effectively distributing bandwidth demands and preventing any particular core from having a high bandwidth requirement. In pipelined computing, different target core pairs within a predefined core set are interconnected using non-overlapping sub-segments of the on-chip network communication link. This ensures that the bandwidth requirements for data interaction between different cores are relatively evenly distributed across the different sub-segments of the on-chip network, further reducing bandwidth requirements. In summary, the bandwidth requirements of the entire data processing process in this application embodiment are relatively stable and evenly distributed (e.g., distributed across different sub-segments of the on-chip network), and there is no concentrated high demand for bandwidth in any processing stage or component, which significantly reduces bandwidth requirements.

[0135] Regarding cache usage, known techniques process the complete input feature map of a network layer by splitting it into multiple subtasks and distributing them across multiple kernels, then integrating the results. Since processor kernel resources are typically limited and do not support multiple kernels for each network layer, each kernel in these techniques generally needs to process the fragmented tasks of all (or most) network layers. Consequently, each kernel needs to use the weight parameters of all (or most) network layers, resulting in a high demand for kernel-local cache. When the kernel-local cache space is insufficient (not enough to store the weight parameters of all or most network layers simultaneously in a single kernel's cache), the kernel needs to repeatedly interact with the shared cache to obtain the weight parameters required for the current network layer. This further increases bandwidth requirements, processing workload, and processing latency. This application embodiment, based on the communication link provided by the on-chip network and combined with unified addressing, realizes the interconnection between local caches and shared caches of each kernel. It supports direct interaction between kernels in a preset kernel set, eliminating the need to use shared caches as intermediaries and avoiding shared caches (such as L2 cache or system cache) becoming communication bottlenecks in the data path. This enables each kernel to process complete intermediate data objects (such as the complete input feature map of the network layer), that is, to support each kernel to process the complete network layer. This allows a kernel to process only one or a few network layers under limited processor resources, and correspondingly, only one or a few network layer weight parameters are needed in a kernel. This can alleviate the demand on kernel cache and reduce cache usage. At the same time, it can support writing the required network layer weight parameters into the cache of the corresponding kernel during initialization, without having to temporarily load them from the shared cache during data processing, thereby further reducing bandwidth requirements, improving data processing efficiency and reducing latency.

[0136] Corresponding to the data processing method described above, this application also discloses a data processing apparatus, the composition of which is as follows: Figure 8 As shown, it includes:

[0137] The acquisition unit 801 is used to acquire a first intermediate object to be processed from the first storage area of ​​the current kernel in the preset kernel set; the first intermediate object is generated by the current kernel processing the corresponding intermediate object to be processed of the target data object by the previous kernel in the preset kernel set, and based on the processing result.

[0138] Data processing unit 802 is used to process the first intermediate object in the current kernel and generate a second intermediate object to be processed by the next kernel corresponding to the current kernel in the preset kernel set based on the processing result;

[0139] The write processing unit 803 is configured to write the second intermediate object into the second storage area of ​​the next kernel in the current kernel, so that it can be processed by the next kernel;

[0140] The preset kernel set is a collection of kernels occupied by the target data object on the processor; each kernel in the preset kernel set corresponds to a specific storage area.

[0141] In one embodiment, the data processing unit 802, when generating a second intermediate object to be processed by the next kernel corresponding to the current kernel in the preset kernel set based on the processing result, specifically performs the following:

[0142] The processing result of the first intermediate object is used as the second intermediate object;

[0143] Alternatively, the second intermediate object can be generated based on the first intermediate object and the processing result of the first intermediate object.

[0144] In one embodiment, the storage area corresponding to each kernel in the preset kernel set is: the cache area corresponding to the local cache integrated in each kernel; each kernel in the preset kernel set also has a corresponding shared cache, and the local cache of each kernel and the shared cache are respectively corresponding to the cache address obtained based on the unified addressing.

[0145] The shared cache is used to store at least one of the following: the target data object, the data processing result obtained by the processor after processing the target data object, and the information required by the processor to process the target data object.

[0146] In one embodiment, the kernels in the preset kernel set and the shared cache are interconnected via an on-chip network;

[0147] The write processing unit 803 is specifically used to: write the second intermediate object into the local cache of the next kernel according to the cache address of the local cache of the next kernel through the target segment link in the current kernel;

[0148] The target sub-segment link is the portion of the communication link provided by the on-chip network used to connect the current kernel and the next kernel.

[0149] In one embodiment, the on-chip network interconnects the various cores in the preset kernel group and the shared cache shared by the various cores through a provided ring communication link or mesh communication link;

[0150] Among them, different target kernel pairs in the preset kernel set are interconnected between two kernels in their respective target kernel pairs by using different non-overlapping sub-segments of the ring communication link or the mesh communication link; the target kernel pair is a kernel pair formed by adjacent kernels in the preset kernel set.

[0151] In one embodiment, each kernel in the preset kernel set is used to: perform data processing corresponding to the corresponding network layer in the preset network layer set within the neural network model in a one-to-one manner;

[0152] The data processing unit 802, when the current kernel processes the first intermediate object, is specifically used for:

[0153] Obtain the weight parameters of the network layer corresponding to the current kernel in the preset network layer set, and process the first intermediate object in the current kernel according to the weight parameters.

[0154] In one embodiment, each kernel in the preset kernel set is used to perform data processing corresponding to at least one network layer in the preset network layer set within the neural network model, and there is at least one kernel used to perform data processing corresponding to multiple network layers in the preset network layer set; different kernels correspond to different network layers;

[0155] The data processing unit 802, when the current kernel processes the first intermediate object, is specifically used for:

[0156] If the current kernel corresponds to a network layer, obtain the weight parameters of the network layer corresponding to the current kernel, and process the first intermediate object in the current kernel according to the weight parameters.

[0157] If the current kernel corresponds to multiple network layers, obtain the weight parameters of the multiple network layers corresponding to the current kernel, process the first intermediate object according to the weight parameters of the first network layer among the multiple network layers, generate an intermediate object to be processed by the next network layer among the multiple network layers based on the processing result of the first intermediate object, and process it by the next network layer until the last network layer among the multiple network layers completes the data processing, and obtain the processing result of the current kernel on the first intermediate object.

[0158] In one embodiment, the preset kernel set includes at least two processor clusters, each processor cluster consisting of multiple cores from the preset kernel set, and different processor clusters have different cores; different processor clusters interconnect their respective cores through different on-chip networks; different processor clusters have corresponding shared caches, and different processor clusters and processor clusters are interconnected with each other and with the shared cache through on-chip networks;

[0159] Write processing unit 803 is specifically used for:

[0160] If the next kernel and the current kernel belong to the same processor cluster, the current kernel writes the second intermediate object into the local cache of the next kernel through the first target segment link according to the cache address of the local cache of the next kernel.

[0161] If the next kernel and the current kernel belong to different processor clusters, the current kernel writes the second intermediate object into the local cache of the next kernel through the second target segment link according to the cache address of the local cache of the next kernel.

[0162] Wherein, the first target sub-segment link is the portion of the first on-chip network corresponding to the same processor cluster used to connect the current kernel and the next kernel; the second target sub-segment link is the portion of the second on-chip network used for inter-cluster interconnection that connects the processor cluster to which the current kernel belongs and the processor cluster to which the next kernel belongs.

[0163] In one implementation, different target data objects can be processed in parallel across different kernels of the preset kernel set.

[0164] The data processing apparatus disclosed in this application is relatively simple to describe because it corresponds to the data processing method disclosed in the above method embodiments. For any similarities, please refer to the description of the above method embodiments, which will not be detailed here.

[0165] This application also discloses an electronic device, the composition and structure of which are as follows: Figure 9 As shown, it includes at least:

[0166] Memory 10 is used to store the computer instruction set;

[0167] Computer instruction sets can be implemented in the form of computer programs.

[0168] The processor 20 is configured to implement the data processing method disclosed in any of the above method embodiments by executing a computer instruction set.

[0169] The processor 20 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a neural network processor (NPU), a deep learning processor (DPU), or other programmable logic devices.

[0170] Electronic devices have a display device and / or have a display interface and can connect to an external display device.

[0171] Optionally, the electronic device may also include a camera assembly, and / or be connected to an external camera assembly.

[0172] In addition to these components, electronic devices may also include communication interfaces, communication buses, and other parts. Memory, processor, and communication interface communicate with each other through the communication bus.

[0173] Communication interfaces are used for communication between electronic devices and other devices. Communication buses can be Peripheral Component Interconnect (PCI) buses or Extended Industry Standard Architecture (EISA) buses, and can be categorized into address buses, data buses, control buses, etc.

[0174] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0175] For ease of description, the above systems or devices are described separately as various modules or units based on their functions. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware components.

[0176] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0177] Finally, it should be noted that in this document, relational terms such as first, second, third, and fourth are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0178] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A data processing method, the method comprising: Retrieve the first intermediate object to be processed from the first storage region of the current kernel in the preset kernel set; The first intermediate object is generated by the current kernel processing the corresponding intermediate object to be processed for the target data object in the previous kernel corresponding to the preset kernel set, and based on the processing result. The current kernel processes the first intermediate object, and based on the processing result, generates a second intermediate object to be processed by the next kernel corresponding to the current kernel in the preset kernel set. The current kernel writes the second intermediate object into the second storage area of ​​the next kernel through direct data interaction, so that the next kernel can process it; The preset kernel set is a collection of kernels occupied by the target data object on the processor; each kernel in the preset kernel set corresponds to a specific storage area. The storage area corresponding to each kernel in the preset kernel set is: the cache area corresponding to the local cache integrated in each kernel; each kernel in the preset kernel set also has a corresponding shared cache, and the local cache of each kernel and the shared cache are respectively corresponding to the cache address obtained based on the unified addressing.

2. The method according to claim 1, wherein generating a second intermediate object based on the processing result to be processed by the next kernel corresponding to the current kernel in the preset kernel set comprises: The processing result of the first intermediate object is used as the second intermediate object; Alternatively, the second intermediate object can be generated based on the first intermediate object and the processing result of the first intermediate object.

3. The method according to claim 1, The shared cache is used to store at least one of the following: the target data object, the data processing result obtained by the processor after processing the target data object, and the information required by the processor to process the target data object.

4. The method according to claim 3, wherein the kernels in the preset kernel set and the shared cache are interconnected via an on-chip network; The step of writing the second intermediate object into the second storage area of ​​the next kernel in the current kernel includes: The current kernel writes the second intermediate object into the local cache of the next kernel through the target segment link, based on the cache address of the local cache of the next kernel. The target sub-segment link is the portion of the communication link provided by the on-chip network used to connect the current kernel and the next kernel.

5. The method according to claim 4, wherein the on-chip network interconnects the various cores in the preset core group and the shared cache common to each core through a provided ring communication link or mesh communication link; wherein Different target kernel pairs in the preset kernel set are interconnected between two kernels in their respective target kernel pairs using different non-overlapping sub-segments of the ring communication link or the mesh communication link; the target kernel pair is a kernel pair formed by adjacent kernels in the preset kernel set.

6. The method according to claim 1, wherein each kernel in the preset kernel set is used to: perform data processing corresponding to the corresponding network layer in the preset network layer set within the neural network model in a one-to-one manner; The process of processing the first intermediate object in the current kernel includes: Obtain the weight parameters of the network layer corresponding to the current kernel in the preset network layer set, and process the first intermediate object in the current kernel according to the weight parameters.

7. The method according to claim 1, wherein each kernel in the preset kernel set is used to perform data processing corresponding to one network layer in the preset network layer set within the neural network model, and there is at least one kernel used to perform data processing corresponding to multiple network layers in the preset network layer set; Different kernels correspond to different network layers; The process of processing the first intermediate object in the current kernel includes: If the current kernel corresponds to a network layer, obtain the weight parameters of the network layer corresponding to the current kernel, and process the first intermediate object in the current kernel according to the weight parameters. If the current kernel corresponds to multiple network layers, obtain the weight parameters of the multiple network layers corresponding to the current kernel, process the first intermediate object according to the weight parameters of the first network layer among the multiple network layers, generate an intermediate object to be processed by the next network layer among the multiple network layers based on the processing result of the first intermediate object, and process it by the next network layer until the last network layer among the multiple network layers completes the data processing, and obtain the processing result of the current kernel on the first intermediate object.

8. The method according to claim 3, wherein the preset kernel set includes at least two processor clusters, each processor cluster is composed of multiple kernels in the preset kernel set, and different processor clusters include different kernels; different processor clusters interconnect each kernel in their respective clusters through different on-chip networks; different processor clusters have corresponding shared caches, and different processor clusters and processor clusters are interconnected with each other and with the shared cache through on-chip networks; The process of writing the second intermediate object into the second storage area of ​​the next kernel in the current kernel includes: If the next kernel and the current kernel belong to the same processor cluster, the current kernel writes the second intermediate object into the local cache of the next kernel through the first target segment link according to the cache address of the local cache of the next kernel. If the next kernel and the current kernel belong to different processor clusters, the current kernel writes the second intermediate object into the local cache of the next kernel through the second target segment link according to the cache address of the local cache of the next kernel. Wherein, the first target sub-segment link is the portion of the first on-chip network corresponding to the same processor cluster used to connect the current kernel and the next kernel; the second target sub-segment link is the portion of the second on-chip network used for inter-cluster interconnection that connects the processor cluster to which the current kernel belongs and the processor cluster to which the next kernel belongs.

9. The method according to claim 1, wherein, Different target data objects can be processed in parallel across different kernels of the preset kernel set.

10. A data processing apparatus, the apparatus comprising: The acquisition unit is used to acquire the first intermediate object to be processed from the first storage area of ​​the current kernel in the preset kernel set; The first intermediate object is generated by the current kernel processing the corresponding intermediate object to be processed for the target data object in the previous kernel corresponding to the preset kernel set, and based on the processing result. The data processing unit is used to process the first intermediate object in the current kernel and generate a second intermediate object to be processed by the next kernel corresponding to the current kernel in the preset kernel set based on the processing result. A write processing unit is configured to write the second intermediate object into the second storage area of ​​the next kernel via direct data interaction in the current kernel, so that it can be processed by the next kernel; The preset kernel set is a set of kernels occupied by the target data object on the processor. Each kernel in the preset kernel set corresponds to a corresponding storage area; the storage area corresponding to each kernel in the preset kernel set is: the cache area corresponding to the local cache integrated in each kernel; each kernel in the preset kernel set also corresponds to a corresponding shared cache, and the local cache of each kernel and the shared cache are respectively corresponding to the cache address obtained based on the unified addressing.

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