Method for manufacturing a semiconductor element

Abstract

A method for fabricating a semiconductor device includes providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming an unqualified hard mask layer to fill the via opening; forming a second mask layer on the unqualified hard mask layer; removing the second mask layer and the unqualified hard mask layer; forming a bottom fill layer to fill the via opening; forming a top hard mask layer on the bottom fill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and a trench in the trench opening.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Applications Nos. 17 / 709,569 and 17 / 709,821 (i.e., priority date "March 31, 2022"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a method for fabricating a semiconductor device. Background Technology

[0003] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is continuously shrinking to meet the ever-increasing demands for computing power. However, various problems arise during this shrinking process, and these problems are increasing. Therefore, challenges remain in achieving improvements in quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first masking layer as a mask; forming a defective hard masking layer to fill the via opening; forming a second masking layer on the defective hard masking layer; removing the second masking layer and the defective hard masking layer; forming a bottom filler layer to fill the via opening; forming a top hard masking layer on the bottom filler layer; forming a third masking layer on the top hard masking layer; patterning the top hard masking layer using the third masking layer as a mask; forming a trench opening in the dielectric layer using the top hard masking layer as a mask; and forming a via in the via opening and a trench in the trench opening.

[0006] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first masking layer as a mask; forming a defective hard masking layer to fill the via opening; forming a second masking layer on the defective hard masking layer; removing the second masking layer; performing a recoating process to transform the defective hard masking layer into a bottom fill layer; forming a top hard masking layer on the bottom fill layer; forming a third masking layer on the top hard masking layer; patterning the top hard masking layer using the third masking layer as a mask; forming a trench opening in the dielectric layer using the top hard masking layer as a mask; and forming a via in the via opening and a trench in the trench opening.

[0007] Another aspect of this disclosure provides a method for reworking a semiconductor device, wherein a defective hard mask layer is disposed thereon, the method comprising: removing a defective hard mask layer from a via opening in a dielectric layer; forming a bottom fill layer to fill the via opening; forming a top hard mask layer on the bottom fill layer; and forming a mask layer on the top hard mask layer.

[0008] Another aspect of this disclosure provides a method for reworking a semiconductor device. The method includes: performing a recoating process to transform a defective hard mask layer on a via opening in a dielectric layer into a bottom fill layer; forming a top hard mask layer on the bottom fill layer; and forming a mask layer on the top hard mask layer.

[0009] Due to the design of the semiconductor device fabrication method disclosed herein, by employing a bottom filler layer or a subfill layer, the enlargement of via openings and / or damage to the via opening profile can be mitigated or avoided. Therefore, the yield and / or reliability of the semiconductor device can be improved.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0011] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0012] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of this disclosure.

[0013] Figures 2 to 12 This is a cross-sectional view illustrating the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 13 This is a flowchart illustrating a method for fabricating a semiconductor element according to another embodiment of this disclosure.

[0015] Figures 14 to 24 This is a cross-sectional view illustrating the fabrication process of a semiconductor element according to another embodiment of this disclosure.

[0016] The reference numerals in the attached figures are explained as follows:

[0017] 1A: Semiconductor components

[0018] 1B: Semiconductor components

[0019] 10: Preparation method

[0020] 30: Preparation method

[0021] 101: Base

[0022] 103: Etching Stop Layer

[0023] 105: Dielectric layer

[0024] 107: Through hole

[0025] 109: Ditch

[0026] 201: Bottom Fill Layer

[0027] 203: Bottom Fill Layer

[0028] 205: Top hard mask layer

[0029] 205O: Hard mask opening

[0030] 401: First masking layer

[0031] 403: Second masking layer

[0032] 405: Third masking layer

[0033] 501: Substandard hard masking layer

[0034] 501R: Groove

[0035] 503: Conductive material layer

[0036] EVO: Expanded through-hole opening

[0037] S11: Steps

[0038] S13: Steps

[0039] S15: Steps

[0040] S17: Steps

[0041] S19: Steps

[0042] S21: Steps

[0043] S23: Steps

[0044] S31: Steps

[0045] S33: Steps

[0046] S35: Steps

[0047] S37: Steps

[0048] S39: Steps

[0049] S41: Steps

[0050] S43: Steps

[0051] S45: Steps

[0052] T1: Thickness

[0053] T2: Thickness

[0054] T3: Thickness

[0055] T4: Thickness

[0056] T5: Thickness

[0057] T6: Thickness

[0058] TO: Ditch opening

[0059] VO: Through-hole opening

[0060] Z: Direction Detailed Implementation

[0061] The following disclosure provides numerous different embodiments, or examples, for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of elements and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature on a second feature may include embodiments where the first and second features are in direct contact, or embodiments where additional features can be formed between the first and second features, thus allowing the first and second features to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments throughout this disclosure. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0062] Furthermore, spatial relative terms, such as "below," "below," "under," "above," and "above," are used here for ease of description to describe the relationship between one element or feature and another element(s) shown in the figure. Spatially relative terms are intended to include different orientations of the element in use or operation, as well as the orientations described in the figure. The element may have other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptors used here can be interpreted accordingly.

[0063] It should be understood that when an element or layer is said to be "connected to" or "coupled to" another element or layer, it can be directly connected to or coupled to another element or layer, or there may be intermediate elements or layers.

[0064] It should be understood that although various elements are described herein using terms such as first, second, etc., these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part without departing from the teachings of this disclosure.

[0065] Unless the context otherwise requires, when referring to orientation, layout, location, shape, size, quantity, or other measures, the terms “identical,” “equal,” “planar,” or “coplanar” used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measures, but rather that they include substantially the same orientation, layout, location, shape, size, quantity, or other measures within the range of acceptable variations that may occur, such as due to manufacturing processes. The term “substantially” may be used here to reflect this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially planar” can be exactly the same, equal, or planar, or they can be the same, equal, or planar within the range of acceptable variations that may occur, such as due to manufacturing processes.

[0066] In this disclosure, semiconductor components generally refer to components that function by utilizing the properties of semiconductors. Optoelectronic components, light-emitting display components, semiconductor circuits, and electronic components are all included in the scope of semiconductor components.

[0067] It should be noted that, in the description of this disclosure, up (or above) corresponds to the direction of the arrow in direction Z, and down (or below) corresponds to the opposite direction of the arrow in direction Z.

[0068] It should be noted that the terms “forming,” “being formed,” and “by forming” can refer to and include any method of creating, constructing, patterning, implanting, or depositing elements, dopants, or materials. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, lithography, dry etching, and wet etching.

[0069] It should be noted that the functions or steps described herein may occur in a different order than those shown in the figures. For example, two numbers displayed consecutively may actually be executed simultaneously, or sometimes in reverse order, depending on the functions or steps involved.

[0070] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of this disclosure. Figures 2 to 12 This is a cross-sectional view illustrating the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0071] Reference Figures 1 to 3 In step S11, a substrate 101 may be provided, an etch stop layer 103 may be formed on the substrate 101, a dielectric layer 105 may be formed on the etch stop layer 103, and a via opening VO may be formed to expose the etch stop layer 103.

[0072] Reference Figure 2 The substrate 101 may include a bulk semiconductor substrate composed entirely of at least one semiconductor material, multiple element units (not shown for clarity), multiple dielectric layers (not shown for clarity), and multiple conductive features (not shown for clarity). Fabrication techniques for the bulk semiconductor substrate may include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI compound semiconductors; or combinations thereof.

[0073] In some embodiments, substrate 101 may include a semiconductor structure on an insulator, which, from bottom to top, includes a processing substrate, an insulating layer, and an uppermost semiconductor material layer. The fabrication techniques for the processing substrate and the uppermost semiconductor material layer may include the same materials as those used for the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may include a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The thickness of the insulating layer may be between 10 nanometers and 200 nanometers.

[0074] It should be noted that the use of the term "about" to modify the quantity of ingredients, components, or reactants refers to possible changes in numerical values, such as those arising from typical measurements and liquid handling procedures used to manufacture concentrates or solutions. Furthermore, variations can occur due to oversights in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to manufacture the composition or perform the method. In one context, "about" refers to within 10% of the reported value. In another context, "about" refers to within 5% of the reported value. However, in yet another context, "about" refers to within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0075] Reference Figure 2 Multiple element units can be formed on a bulk semiconductor substrate or the topmost semiconductor material layer. Some portions of the multiple element units can be formed within the bulk semiconductor substrate or the topmost semiconductor material layer. The multiple element units can be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect transistors, or combinations thereof.

[0076] Reference Figure 2 Multiple dielectric layers can be formed on a bulk semiconductor substrate or the topmost semiconductor material layer, covering multiple element units. In some embodiments, the fabrication techniques for the multiple dielectric layers may include, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, low-k (dielectric constant) dielectric materials, or combinations thereof. The dielectric constant of the low-k dielectric material may be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k dielectric material may be less than 2.0. The fabrication techniques for the multiple dielectric layers may include deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar processes. A planarization process may be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent process steps.

[0077] Reference Figure 2 Multiple conductive features may include interconnect layers and conductive vias. The interconnect layers may be separated from each other and may be horizontally disposed within multiple dielectric layers along the Z-direction. Conductive vias may connect adjacent interconnect layers, as well as adjacent component cells and interconnect layers, along the Z-direction. In some embodiments, conductive vias may improve heat dissipation and provide structural support. In some embodiments, the fabrication techniques for the multiple conductive features may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. Multiple conductive features may be formed during the process of forming multiple dielectric layers.

[0078] In some embodiments, multiple element units and multiple conductive features may be configured together in the functional unit of substrate 101. In the description of this disclosure, a functional unit generally refers to a function-related circuit that has been divided into a separate unit. In some embodiments, a functional unit may typically be a highly complex circuit, such as a processor core, memory controller, or accelerator unit. In other embodiments, the complexity of the functional unit may be more or less than its function.

[0079] Reference Figure 2 An etch stop layer 103 may be formed on a substrate 101. The fabrication technique of the etch stop layer 103 may include a dielectric material preferably having an etch selectivity different from that of the uppermost layer (e.g., a dielectric layer) of the substrate 101. For example, the fabrication technique of the etch stop layer 103 may include silicon carbide, silicon oxycarbide, or similar materials, and may be deposited by chemical vapor deposition or plasma-enhanced chemical vapor deposition. In this embodiment, the fabrication technique of the etch stop layer 103 includes silicon nitride. In some embodiments, the thickness T1 of the etch stop layer 103 may be between about 30 nanometers and about 40 nanometers, or about 35 nanometers.

[0080] Reference Figure 2 The dielectric layer 105 can be formed on the etch stop layer 103, and the fabrication techniques can include, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borosilicate glass, spin low-k dielectric layer, chemical vapor deposition low-k dielectric layer, or combinations thereof. In some embodiments, the dielectric layer 105 may include a self-planarization material, such as spin glass or a spin low-k dielectric material, such as SiLK. TMUsing a self-planarizing dielectric material can eliminate the need for subsequent planarization steps. In some embodiments, the fabrication technique of dielectric layer 105 may include deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent process steps. In this embodiment, the fabrication technique of dielectric layer 105 comprises silicon dioxide.

[0081] Reference Figure 2 A first masking layer 401 may be formed on the dielectric layer 105. The first masking layer 401 may be, for example, a photoresist layer. The first masking layer 401 may be patterned to define the position of the via opening VO.

[0082] Reference Figure 3 A via etching process can be performed to remove a portion of the dielectric layer 105 and simultaneously form the via opening VO. The etching rate of the dielectric layer 105 in the via etching process can be faster than the etching rate of the etch stop layer 103. For example, in the via etching process, the etching rate ratio of the dielectric layer 105 to the etch stop layer 103 can be between approximately 100:1 and approximately 1.05:1. As another example, in the via etching process, the etching rate ratio of the dielectric layer 105 to the etch stop layer 103 can be between approximately 100:1 and approximately 10:1. A portion of the etch stop layer 103 can be exposed through the dielectric layer 105.

[0083] Reference Figure 1 and Figure 4 In step S13, a defective hard mask layer 501 can be formed to fill the via opening VO, and a second mask layer 403 can be formed on the defective hard mask layer 501.

[0084] Reference Figure 4The defective hard mask layer 501 may be incorporated by fabrication techniques, such as spin coating or other suitable processes, to fill the via opening VO. In some embodiments, the fabrication technique of the defective hard mask layer 501 may include a material with a slightly faster etch rate (relative to the material of the dielectric layer 105). In some embodiments, the defective hard mask layer 501 may be, for example, AR 40 antireflective agent commercially available from Rohm and Haas Electronic Materials (Phoenix, Ariz.). In some embodiments, the thickness T2 of the defective hard mask layer 501, measured from the top surface of the dielectric layer 105, may be between about 30 nanometers and about 50 nanometers. In some embodiments, the fabrication technique of the defective hard mask layer 501 may include, for example, silicon nitride, silicon oxynitride, or silicon nitride oxide.

[0085] It should be noted that a defective hard mask layer 501 is, for example, a defective hard mask layer 501 with incorrect dimensions, a defective hard mask layer 501 that causes pattern deviation, or a defective hard mask layer 501 that includes defects, such as... Figure 4 The recess 501R is located directly above the via opening VO shown in the diagram. A defective hard mask layer 501 can adversely affect the yield and reliability of the resulting semiconductor device 1A. Therefore, defective hard mask layer 501 requires further processing to avoid or mitigate this effect.

[0086] Reference Figure 4 The second masking layer 403 may be formed on the defective hard masking layer 501. In some embodiments, the thickness T3 of the second masking layer 403 may be between about 180 nanometers and about 220 nanometers. The second masking layer 403 may include trench openings TO (e.g., Figure 9 The pattern shown.

[0087] Reference Figure 1 , Figure 5 and Figure 6 In step S15, the second mask layer 403 and the unqualified hard mask layer 501 can be removed.

[0088] Reference Figure 5 The removal techniques for the second masking layer 403 and the defective hard masking layer 501 may include, for example, an ashing process, an etching process, other suitable processes, or combinations thereof. A cleaning process may optionally be performed to remove any residue formed during the removal of the second masking layer 403 and the defective hard masking layer 501.

[0089] Reference Figure 1 , Figure 6 and Figure 7In step S17, a bottom fill layer 201 can be formed to fill the via opening VO, a top hard mask layer 205 can be formed on the bottom fill layer 201, and a third mask layer 405 can be formed on the top hard mask layer 205.

[0090] Reference Figure 6 The fabrication technique of the underfill layer 201 may include, for example, spin coating, chemical vapor deposition, or other suitable deposition processes to fill the via opening VO. In some embodiments, the fabrication technique of the underfill layer 201 may include, for example, silicon carbide, silicon oxycarbide, or similar materials. In some embodiments, the fabrication technique of the underfill layer 201 may include materials with a slightly faster etch rate (relative to the material of the dielectric layer 105). In some embodiments, the underfill layer 201 may contain carbon and hydrogen. In some embodiments, the underfill layer 201 may contain carbon, hydrogen, and oxygen. In some embodiments, the underfill layer 201 may contain carbon, hydrogen, and fluorine. In some embodiments, the underfill layer 201 may be a carbon film. The term "carbon film" is used herein to describe a material whose mass is predominantly carbon, whose structure is primarily defined by carbon atoms, or whose physical and chemical properties are dominated by its carbon content. The term "carbon film" is used to exclude materials that are merely mixtures or compounds of carbon, such as dielectric materials, such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polycrystalline silicon.

[0091] In some embodiments, the thickness T4 of the bottom fill layer 201, measured from the top surface of the dielectric layer 105, may be between about 180 nanometers and about 220 nanometers.

[0092] When low-k materials are used in dielectric layers (e.g., dielectric layer 105), it is difficult to produce features with almost no surface defects or feature deformation. Low-k dielectric materials are typically porous and easily scratched and damaged during processing, leading to defects on their surface. Furthermore, low-k materials are often brittle and may deform during conventional polishing processes. One solution to limit or reduce surface defects and deformation is to deposit a hard mask layer on the exposed low-k material before performing patterning and etching feature definition. The hard mask layer can resist damage and deformation. During subsequent material deposition and planarization or material removal processes, such as chemical mechanical polishing or etching, the hard mask layer also protects the underlying low-k material, thus reducing defect formation and feature deformation. The hard mask layer can then be removed by a subsequent planarization process before further processing.

[0093] Reference Figure 7A top hard mask layer 205 can be formed on the bottom filler layer 201. In some embodiments, the thickness T5 of the top hard mask layer 205 can be between about 10 nanometers and about 100 nanometers, or between about 10 nanometers and about 50 nanometers. In some embodiments, the fabrication technology of the top hard mask layer 205 may include, for example, silicon, silicon germanium, tetraethyl orthosilicate, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon carbide, etc., or combinations thereof. The fabrication technology of the top hard mask layer 205 may include deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, etc. The process temperature for forming the top hard mask layer 205 can be below 400°C. In some embodiments, the fabrication technology of the top hard mask layer 205 may include, for example, metal nitrides, such as titanium nitride and tantalum nitride.

[0094] Alternatively, in some embodiments, the fabrication technique of the top hard mask layer 205 may include, for example, boron nitride, silicon nitride, boron phosphorus nitride, boron silicon carbide, or similar materials. The fabrication technique of the top hard mask layer 205 may include a film deposition process and a processing process. Specifically, in the film deposition process, a first precursor, which may be a boron-based precursor, may be introduced onto the underlying filler layer 201 to form a boron substrate. Subsequently, in the processing process, a second precursor, which may be a nitrogen-based precursor, may be introduced to react with the boron substrate, transforming the boron substrate into the top hard mask layer 205. In some embodiments, the first precursor may be, for example, diborane, cycloborane, or an alkyl-substituted derivative of cycloborane. In some embodiments, the second precursor may be, for example, ammonia or hydrazine.

[0095] During the patterning of the third mask layer 405, the top hard mask layer 205 can act as an anti-reflective coating to improve the quality of image transmission from the photomask (not shown) to the top hard mask layer 205.

[0096] Reference Figure 7 The third mask layer 405 can be formed on the top hard mask layer 205 using a fabrication technique including lithography. The third mask layer 405 may include a pattern of trench openings TO. In some embodiments, the third mask layer 405 may be a photoresist, such as the commercially available photoresist OCG895i or Epic. TM 2210ArF photoresist or other suitable photoresist.

[0097] The process including removing the second masking layer 403 and the defective hard masking layer 501, forming the bottom fill layer 201, forming the top hard masking layer 205, and forming the third masking layer 405 (including patterning the third masking layer 405) can be called the rework process of the defective hard masking layer 501. This process is used to avoid the adverse effects of the defective hard masking layer 501 on the resulting semiconductor device 1A.

[0098] Conventional reprocessing methods may include issues such as sidewall damage and contour damage of via openings VO. Conversely, by employing an underfill layer 201, sidewall damage and contour damage of via openings VO can be reduced or avoided. Therefore, the yield and reliability of the resulting semiconductor device 1A can be improved.

[0099] Reference Figure 1 , Figure 8 and Figure 9 In step S19, a trench opening TO can be formed in the dielectric layer 105.

[0100] Reference Figure 8 A hard mask etching process can be performed to remove a portion of the top hard mask layer 205, and the pattern of the third mask layer 405 can be transferred to the top hard mask layer 205 to form a hard mask opening 205O along the top hard mask layer 205. The etching rate of the top hard mask layer 205 in the hard mask etching process can be faster than the etching rate of the bottom fill layer 201 in the hard mask etching process. For example, during the hard mask etching process, the etching rate ratio of the top hard mask layer 205 to the bottom fill layer 201 can be between about 100:1 and about 1.05:1. As another example, during the hard mask etching process, the etching rate ratio of the top hard mask layer 205 to the bottom fill layer 201 can be between about 100:1 and about 10:1. A portion of the bottom fill layer 201 can be exposed through the hard mask opening 205O.

[0101] Reference Figure 9 A trench etching process can be performed using a top hard mask layer 205 and / or a third mask layer 405 as a mask to remove a portion of the dielectric layer 105 and the underfill layer 201. In some embodiments, during the trench etching process, the etch rate ratio of the dielectric layer 105 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. During the trench etching process, the etch rate ratio of the underfill layer 201 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. After the trench etching process, a trench opening TO may be formed in the dielectric layer 105. It should be noted that at this stage, the etch stop layer 103 may still be covered by the remaining underfill layer 201 in the via opening VO.

[0102] In some embodiments, the third masking layer 405 may be removed before the trench opening TO is formed. In some embodiments, the third masking layer 405 may be removed after the trench etching process used to form the trench opening TO. The removal of the third masking layer 405 may be achieved by, for example, an ashing process or other suitable process.

[0103] Reference Figure 1 and Figure 10 In step S21, a punching etching process can be performed to form an extended through-hole opening EVO to expose the substrate 101.

[0104] Reference Figure 10 The punch-etch process can remove the remaining underfill layer 201 in the via opening VO and a portion of the etch stop layer 103 exposed through the via opening VO. In some embodiments, during the punch-etch process, the etch rate ratio of the underfill layer 201 to the dielectric layer 105 can be between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. In some embodiments, during the punch-etch process, the etch rate ratio of the etch stop layer 103 to the substrate 101 can be between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. After the punch-etch process, the via opening VO can be extended to form an extended via opening EVO along the dielectric layer 105 and the etch stop layer 103. A portion of the substrate 101 can be exposed through the extended via opening EVO.

[0105] After trench etching and / or punching etching processes, some etching residues may remain (not shown for clarity). Etching residues may be remaining material on the inner surface of the trench opening TO after the trench etching process, remaining material on the inner surface of the extended via opening EVO, or remaining material after the ashing process of the third masking layer 405. Etching residues can have different compositions depending on the material being etched or ashed.

[0106] In some embodiments, a pre-cleaning process and a cleaning process may be used sequentially to remove the etching residues.

[0107] During the pre-cleaning process, Figure 10 The intermediate semiconductor element shown can be rotated at a speed between approximately 10 rpm and approximately 2000 rpm, or between approximately 100 rpm and 1000 rpm. A pre-cleaning solution can be sprayed onto the intermediate semiconductor element to cover its entire front side. While spraying the pre-cleaning solution onto the front side of the intermediate semiconductor element, water or other suitable solution can be sprayed onto its back side to clean it.

[0108] In some embodiments, the pre-cleaning solution may include a chelating agent, a corrosion inhibitor, a fluorinated amine, a surfactant, or a solvent. In some embodiments, the fluorinated amine and the surfactant may be selective.

[0109] Chelating agents are also commonly referred to as chelating agents or clamping agents. Chelating agents can have negatively charged ions, called ligands, that combine with free metal ions to form a complex that maintains solubility. Chelating agents can be used to remove metal ions from intermediate semiconductor devices. Without being bound by any particular theory, chelating agents can also reduce or prevent corrosion of the bottom conductive layer (of substrate 101) exposed through the extended via opening EVO.

[0110] In some embodiments, the chelating agent of the pre-wash solution may include ethylenediaminetetraacetic acid, polyacrylate, carbonate, phosphonate, gluconate, N,N′-bis(2-hydroxyphenyl)ethylenediaminediacetic acid, trinitrosohexaacetic acid, deferoxamine B, N,N′,N″-tris[2-(N-hydroxycarbonyl)ethyl]-1,3,5-benzamide, and / or ethylenediaminedioxophenylacetic acid. In some embodiments, the concentration of the chelating agent may be between about 0.001 mg / L and about 300 mg / L, or between about 0.01 mg / L and about 3 mg / L. In some embodiments, the concentration of the chelating agent may also be between 1 ppm and about 400 ppm of the pre-wash solution, or preferably between about 40 ppm of the pre-wash solution.

[0111] Corrosion inhibitors in pre-cleaning solutions can be used to reduce or prevent metal corrosion during subsequent cleaning processes. In some embodiments, the corrosion inhibitor may comprise an aliphatic alcohol compound having at least one thiol group in its molecule. The alcohol compound has at least two carbon atoms, and one carbon atom bonded to the thiol group and another carbon atom bonded to the hydroxyl group are sequentially bonded to each other. For example, the corrosion inhibitor may be 2-mercaptoethanol and / or thioglycerol. In some embodiments, the concentration of the corrosion inhibitor in the pre-cleaning solution may be between about 0.0001% and about 10% (by weight), or between about 0.001% and about 1% (by weight). When the concentration is too low, the corrosion inhibition effect may be limited to an unsatisfactory level. Excessively high concentrations may not necessarily further improve the corrosion inhibition effect, and may make the compound difficult to handle due to the characteristic odor of thiol-containing compounds.

[0112] In some embodiments, the corrosion inhibitor of the pre-cleaning solution may include aromatic hydrocarbon compounds, such as benzotriazole and / or 5-methylbenzimidazole. In other embodiments, the corrosion inhibitor of the pre-cleaning solution may include uric acid, adenine, caffeine, and / or purine. In other embodiments, the corrosion inhibitor of the pre-cleaning solution may include glyoxylic acid. Due to the presence of glyoxylic acid, which is a reducing agent, even if the metal material is exposed during the pre-cleaning process, the electron transfer between the pre-cleaning solution and the exposed metal material is controlled by adjusting the concentration of glyoxylic acid to control the redox potential of the pre-cleaning solution, thus preventing corrosion of the metal material. In other embodiments, the corrosion inhibitor of the pre-cleaning solution may include 2-mercaptoethanol, thioglycerol, benzotriazole, 5-methylbenzimidazole, uric acid, adenine, caffeine, purine, and / or glyoxylic acid.

[0113] In some embodiments, the fluorinated amine in the pre-cleaning solution may include methylamine hydrogen fluoride, ethylamine hydrogen fluoride, propylamine hydrogen fluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, ethanolamine hydrogen fluoride, methylethanolamine hydrogen fluoride, dimethylethanolamine hydrogen fluoride, and / or triethylenediamine hydrogen fluoride. Fluorinated amines can be used to remove etching residues.

[0114] In some embodiments, the concentration of amine fluoride in the pre-cleaning solution can be determined based on the composition of the etching residue. For example, the concentration of amine fluoride can be between about 0.1% by mass and about 5% by mass of the total pre-cleaning solution composition, or between about 0.2% by mass and about 3% by mass of the total pre-cleaning solution composition. By setting the concentration of amine fluoride within such a range, it can be ensured that the amine fluoride in the pre-cleaning solution can remove etching residues while preventing the amine fluoride from corroding the underlying metal material exposed through the extended via opening (EVO) and inhibiting the etching of the underlying dielectric layer exposed through the extended via opening (EVO). That is, if the concentration of amine fluoride in the pre-cleaning solution is too low, the ability to remove residues will be low; if the concentration is too high, the metal material may be corroded, and the exposed dielectric layer may be etched or undergo structural changes.

[0115] The purpose of surfactants can be to prevent particles from detaching from and reattaching to intermediate semiconductor devices. Preventing reattachment is crucial because allowing it increases overall process time. Surfactants can also impart affinity to water-repellent layers. Generally, surfactants are long hydrocarbon chains, typically containing a hydrophilic (polar, water-soluble group) and a hydrophobic (non-polar, water-insoluble group). The surfactant adheres to the front side of both the particles and the intermediate semiconductor device via its non-polar group. Conversely, the polar group of the surfactant is directed away from the wafer and the particles, towards the pre-cleaning solution covering the front side of the intermediate semiconductor device. As a result, particles bound to the surfactant in the solution are electrostatically repelled from the front side of the intermediate semiconductor device because both the particles and the front side of the intermediate semiconductor device have polar surfactant groups.

[0116] In some embodiments, the surfactant in the pre-cleaning solution may include nonionic, anionic, or a mixture of nonionic and anionic compounds. Nonionic means the surfactant has a static charge rather than an ionic charge at its polar end, while anionic means the surfactant has a negative ionic charge at its polar end. Nonionic surfactants may be, for example, polyoxyethylene butylphenyl ether, while anionic surfactants may be, for example, polyoxyethylene alkylphenyl sulfate. In some embodiments, the concentration of the surfactant in the pre-cleaning solution may be between about 1 ppm and about 100 ppm. In some embodiments, the concentration of the nonionic surfactant in the pre-cleaning solution may be about 30 ppm, and the concentration of the anionic surfactant in the pre-cleaning solution may be about 30 ppm. In some embodiments, the concentration of the surfactant in the pre-cleaning solution may be between 0.0001% by mass and 10% by mass of the total composition of the pre-cleaning solution, or between about 0.001% by mass and about 5% by mass of the total composition of the pre-cleaning solution. By setting the concentration within such a range, it is ensured that the wettability of the front side of the intermediate semiconductor device is commensurate with the concentration of the surfactant.

[0117] In some embodiments, the solvent for the pre-cleaning solution may be deionized water.

[0118] In some embodiments, Figure 10 The front side of the intermediate semiconductor element shown can be covered (or immersed) with a pre-cleaning solution for approximately 2 minutes. Next, the intermediate semiconductor element can be rinsed with deionized water to remove the pre-cleaning solution.

[0119] In some embodiments, a drying process may be performed after the pre-cleaning treatment. The drying process may involve rotating at approximately 100 rpm to approximately 6000 rpm, or approximately 3000 rpm, for approximately 20 seconds, using an airflow to dry the intermediate semiconductor device. In some embodiments, nitrogen or isopropanol may be used to facilitate the drying process. In some embodiments, the drying process may be selective. That is, the cleaning process may be performed directly after rinsing with the pre-cleaning solution.

[0120] In some embodiments, the cleaning process may include three stages, with inter-stage rinsing performed between each stage. Specifically, during the first stage of the cleaning process, after a pre-cleaning treatment (or drying process), a first cleaning solution may be applied to the intermediate semiconductor device. The first cleaning solution may be rinsed by a first-stage inter-rinse. During the second stage of the cleaning process, a second cleaning solution may be applied to the intermediate semiconductor device, and subsequently rinsed by a second-stage inter-rinse. During the third stage of the cleaning process, a third cleaning solution may be applied to the intermediate semiconductor device, and then rinsed by a post-stage rinsing.

[0121] In some embodiments, during the first stage of the cleaning process, the pre-cleaned intermediate semiconductor device can be rotated at a speed between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. A first cleaning solution can be sprayed onto the intermediate semiconductor device to cover its entire front side. While the first cleaning solution is applied to the front side of the intermediate semiconductor device, water or other suitable solution can be applied to the back side of the intermediate semiconductor device to clean it.

[0122] In some embodiments, the first cleaning solution may include diluted hydrofluoric acid. The concentration of the first cleaning solution may be between about 5 parts deionized water to 1 part hydrofluoric acid and about 1000 parts deionized water to 1 part hydrofluoric acid, about 300 parts deionized water to 1 part hydrofluoric acid, or about 50 parts deionized water to 1 part hydrofluoric acid. Typically, the front side of the intermediate semiconductor device may be exposed to the first cleaning solution for a time sufficient to etch sacrificial oxide (typically about 50 to 200 angstroms) or native oxide (typically about 10 angstroms). In some embodiments, the process time of the first stage of the cleaning process may be between about 1 minute and about 5 minutes.

[0123] In some embodiments, the first cleaning solution may further include fluorinated compounds, organic acid salts, and / or glyoxylic acid.

[0124] Fluorine compounds may be included in the first cleaning solution as a component for removing etching residues. Examples of fluorine compounds may include hydrofluoric acid with ammonium or fluorinated amines, such as ammonium fluoride, ammonium hydrogen fluoride, methylamine hydrogen fluoride, ethylamine hydrogen fluoride, propylamine hydrogen fluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, ethanolamine hydrogen fluoride, methylethanolamine ammonium fluoride, dimethylethanolamine hydrogen fluoride, and triethylenediamine hydrogen fluoride. In some embodiments, the concentration of the fluorine compound in the first cleaning solution may be determined based on the composition of the etching residues. For example, the concentration of the fluorine compound may be between about 0.1% by mass and about 5% by mass of the total components of the first cleaning solution, or between about 0.2% by mass and about 3% by mass of the total components of the first cleaning solution.

[0125] Organic acid salts may include, for example, ammonium oxalate, ammonium tartrate, ammonium citrate, and ammonium acetate. Organic acid salts may serve as pH adjusters or buffers in the first cleaning solution. The concentration of the organic acid salt may be between about 0.1% by mass and about 10% by mass of the total components of the first cleaning solution, or between about 0.3% by mass and about 5% by mass of the total components of the first cleaning solution.

[0126] The glyoxylic acid contained in the first cleaning solution can act as a corrosion inhibitor.

[0127] In some embodiments, the first cleaning solution may further include an anti-corrosion remover. Examples of anti-corrosion removers include tetramethylammonium hydroxide and / or monomethylamine.

[0128] An inter-stage rinsing can be performed after the first stage of the cleaning process. During the inter-stage rinsing, the intermediate semiconductor device following the first stage of the cleaning process can be rotated between about 10 rpm and about 1000 rpm while being rinsed with deionized water. In some embodiments, the rinsing temperature can be between about 19°C and about 23°C. In some embodiments, the process time for the inter-stage rinsing can be between about 20 seconds and about 50 seconds, or about 30 seconds.

[0129] In some embodiments, the deionized water used for the first-stage inter-rinse can be oxidized or ozonated by dissolved oxygen or ozone gas before rinsing the intermediate semiconductor components. Dissolved oxygen or ozone can be added to the deionized water at a concentration greater than 1 ppm as an oxidant. For example, the concentration of dissolved oxygen or ozone can be between about 1 ppm and about 200 ppm, or between about 2 ppm and about 20 ppm. Alternatively, the deionized water can be saturated with dissolved oxygen or ozone. Additionally, hydrogen peroxide at a concentration greater than 100 ppm can be added to the deionized water as an oxidant. Regardless of the oxidant used, its oxidation potential should be sufficient to oxidize the most corrosion-resistant metal in the solution. Copper (Cu) 2+The standard reduction potential of metal ions is 0.3V, which is typically the most corrosion-resistant metal currently available. Therefore, a standard reduction potential greater than 0.5V is required. Oxygen or ozone will dissolve the metal ions and prevent precipitation by oxidizing them in the solution. This will make the first-stage rinsing more effective, reducing process time.

[0130] In some embodiments, the deionized water used for the first-stage inter-rinse may contain dissolved carbon dioxide to dissolve static electricity accumulated in the deionized water. This static electricity may originate from the rotation of intermediate semiconductor elements. The dissolved carbon dioxide may also make the deionized water more acidic, thus reducing any metallic contamination. In some embodiments, carbon dioxide may be dissolved in the deionized water in an amount sufficient to dissipate static electricity. For example, the amount of carbon dioxide dissolved in the deionized water may be sufficient to reduce the resistivity of the deionized water to below 5 megohm·cm.

[0131] In some embodiments, isopropanol, or any other liquid with a lower surface tension than deionized water, may be added to the deionized water used for the first-stage inter-rinse. Isopropanol helps the deionized water spread across the front side of the intermediate semiconductor element, thus allowing chemicals to be removed more quickly. Isopropanol also helps the rinsing solution rotate off the intermediate semiconductor element during the swirl process. Additionally, isopropanol vapor can be blown onto the front side of the intermediate semiconductor element during rinsing to assist in the first-stage inter-rinse.

[0132] In some embodiments, the deionized water used to remove the pre-cleaning solution may have a similar treatment to the deionized water used during the rinsing between the first stages.

[0133] In some embodiments, during the second stage of the cleaning process, the intermediate semiconductor device, rinsed between the first stages, can be rotated at a speed between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. A second cleaning solution can be sprayed onto the intermediate semiconductor device to cover its entire front side. While the second cleaning solution is applied to the front side of the intermediate semiconductor device, water or other suitable solution can be applied to the back side of the intermediate semiconductor device to clean it.

[0134] In some embodiments, the second cleaning solution may be an alkaline solution, including, for example, an aqueous solution of inorganic compounds such as sodium hydroxide, potassium hydroxide, and ammonium hydroxide, and an aqueous solution of organic compounds such as tetramethylammonium hydroxide and choline. The second cleaning solution may also include hydrogen peroxide. The purpose of ammonium hydroxide and hydrogen peroxide in the second cleaning solution is to remove particles and residual organic contaminants from the front side of the intermediate semiconductor device.

[0135] For example, in this embodiment, the second cleaning solution may include ammonium hydroxide, hydrogen peroxide, and water. The concentrations of ammonium hydroxide, hydrogen peroxide, and water may be present in dilution ratios defined as 5 / 1 / 1 and 1000 / 1 / 1, respectively. In some embodiments, the ratio of ammonium hydroxide to hydrogen peroxide may vary between 0.05 / 1 and 5 / 1. In some embodiments, hydrogen peroxide is not used at all. The ammonium hydroxide in the second cleaning solution will be derived from an aqueous ammonia solution of 28-29% w / w (mass percentage concentration). The hydrogen peroxide in the second cleaning solution will be a solution of 31-32% w / w hydrogen peroxide in water. Due to the action of ammonium hydroxide and hydrogen peroxide, the pH of the second cleaning solution may be between 9 and 12, or between 10 and 11.

[0136] In some embodiments, the second cleaning solution may further include a chelating agent. The chelating agent in the second cleaning solution may have a similar compound and concentration to the chelating agent in the pre-cleaning solution, and its description will not be repeated here.

[0137] In some embodiments, the second cleaning solution may further include a surfactant. The surfactant in the second cleaning solution may have a similar compound and concentration to the surfactant in the pre-cleaning solution, and its description will not be repeated here.

[0138] In some embodiments, the second cleaning fluid may further include dissolved hydrogen. The dissolved hydrogen in the second cleaning fluid provides cavitation (bubble generation). Providing cavitation to the second cleaning fluid enhances the cleaning process. In some embodiments, the concentration of dissolved hydrogen may be between about 0.01 mg / L and about 5 mg / L, or between about 0.1 mg / L and about 5 mg / L. In some embodiments, other suitable cavitation gases, such as nitrogen, helium, argon, or oxygen, may also be used. For example, dissolved oxygen at a concentration between 1 mg / L and 20 mg / L may be used in the second cleaning fluid.

[0139] In some embodiments, the processing time of the second stage of the cleaning process may be between about 30 seconds and about 100 seconds, between about 30 seconds and 90 seconds, or between about 30 seconds and about 60 seconds. In some embodiments, the temperature of the second cleaning solution may be between about 40°C and about 85°C.

[0140] The second-stage rinsing can be performed after the second stage of the cleaning process. The second-stage rinsing can be performed using a procedure similar to the first-stage rinsing, which will not be described again here.

[0141] In some embodiments, during the third stage of the cleaning process, the intermediate semiconductor device, rinsed between the second and third stages, can be rotated at a speed between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. A third cleaning solution can be sprayed onto the intermediate semiconductor device to cover its entire front side. While the third cleaning solution is applied to the front side of the intermediate semiconductor device, water or other suitable solution can be applied to the back side of the intermediate semiconductor device to clean it.

[0142] In some embodiments, the third cleaning solution may be an acidic solution comprising, for example, aqueous solutions of inorganic acids such as hydrochloric acid, hydrofluoric acid, sulfuric acid, and nitric acid, and aqueous solutions of organic acids such as oxalic acid, citric acid, malonic acid, malic acid, fumaric acid, and maleic acid. In some embodiments, the third cleaning solution may also include hydrogen peroxide. The concentration of the acidic solution may be between about 0.001% and about 10% (by weight), or between about 0.01% and about 5% (by weight). When the concentration is too low, sufficient cleaning effect may not be achieved. When the concentration is too high, metal corrosion of the cleaning equipment or other related equipment may occur.

[0143] After the third stage of the cleaning process, a post-stage rinsing can be performed. The post-stage rinsing can be performed using a procedure similar to the inter-stage rinsing, and its description will not be repeated here.

[0144] In some embodiments, the second and third stages of the cleaning process can be selective. In other words, only the first stage of the cleaning process may be performed. In some embodiments, the third stage of the cleaning process can be selective. In other words, only the first and second stages of the cleaning process may be performed.

[0145] Reference Figure 1 , Figure 11 and Figure 12 In step S23, a through hole 107 can be formed in the extended through hole opening EVO, and a trench 109 can be formed in the trench opening TO.

[0146] Reference Figure 11 A conductive material layer 503 can be formed to completely fill the extended via opening EVO and the trench opening TO. The conductive material can be, for example, copper. The fabrication techniques for the conductive material layer 503 can include, for example, chemical vapor deposition, physical vapor deposition, sputtering, or other suitable deposition processes.

[0147] Reference Figure 8A planarization process, such as chemical mechanical polishing, can be performed until the top surface of the dielectric layer 105 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. After the planarization process, the conductive material layer 503 can become an extended via opening (EVO) in the via 107 and a trench (TO) in the trench. The substrate 101, the first etch stop layer 103, the dielectric layer 105, the via 107, and the trench 109 together configure the semiconductor device 1A.

[0148] Figure 13 This is a flowchart illustrating a method 30 for fabricating a semiconductor element 1B according to another embodiment of this disclosure.

[0149] Figures 14 to 24 This is a cross-sectional view illustrating the fabrication process of semiconductor element 1B according to another embodiment of this disclosure.

[0150] Reference Figures 13 to 15 In step S31, a substrate 101 may be provided, an etch stop layer 103 may be formed on the substrate 101, a dielectric layer 105 may be formed on the etch stop layer 103, and a via opening VO may be formed to expose the etch stop layer 103.

[0151] Reference Figure 14 It can be used in a similar way Figure 2 The process shown forms a substrate 101, an etch stop layer 103, a dielectric layer 105, and a first masking layer 401, the description of which will not be repeated here.

[0152] Reference Figure 15 It can be used in a similar way Figure 3 The procedure shown forms via openings VO along dielectric layer 105 and exposes etch stop layer 103, and its description will not be repeated here.

[0153] Reference Figure 13 Figure 16 In step S33, a defective hard mask layer 501 can be formed to fill the via opening VO, and a second mask layer 403 can be formed on the defective hard mask layer 501.

[0154] Reference Figure 16 It can be used in a similar way Figure 4 The procedure shown forms a defective hard mask layer 501 and a second mask layer 403, the description of which will not be repeated here.

[0155] Reference Figure 13 and Figure 17 In step S35, the second mask layer 403 can be removed.

[0156] Reference Figure 17The second masking layer 403 can be selectively removed. The removal technique for the second masking layer 403 may include, for example, an ashing process or a suitable etching process. In some embodiments, during the removal of the second masking layer 403, the etching rate ratio of the second masking layer 403 to the defective hard masking layer 501 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1.

[0157] Reference Figure 13 and Figure 18 In step S37, the defective hard mask layer 501 can be transformed into a bottom fill layer 203 through a recoating process.

[0158] Reference Figure 18 In some embodiments, the recoating process can be, for example, spin coating, chemical vapor deposition, physical vapor deposition, sputtering, or other suitable deposition processes. The recoating process can repair defects (e.g., grooves 501R) in the defective hard mask layer 501. After the recoating process, the defective hard mask layer 501 can become an underfill layer 203. In some embodiments, the thickness T6 of the underfill layer 203 can be between about 180 nanometers and about 220 nanometers. The fabrication technique of the underfill layer 203 can include the same materials as the defective hard mask layer 501, and its description will not be repeated here. In some embodiments, a planarization process, such as chemical mechanical polishing or other suitable processes, can be performed to provide a substantially flat surface for subsequent process steps. In some embodiments, the planarization process can be omitted.

[0159] Conventionally, removing a defective hard mask layer 501 may enlarge the via opening VO and / or damage the contour of the via opening VO. In this embodiment, recoating to repair the defective hard mask layer 501 instead of removing it can mitigate or avoid the enlargement of the via opening VO or the damage to the contour of the via opening VO.

[0160] Reference Figure 13 and Figure 19 In step S39, a top hard mask layer 205 may be formed on the bottom fill layer 203, and a third mask layer 405 may be formed on the top hard mask layer 205.

[0161] Reference Figure 19 It can be used in a similar way Figure 7 The procedure shown is used to form the top hard mask layer 205 and the third mask layer 405, and its description will not be repeated here.

[0162] The process includes removing the third masking layer 405, fabricating the bottom filler layer 203 using a recoating process, forming the top hard masking layer 205, and forming the third masking layer 405 (including patterning the third masking layer 405), which can be referred to as a defective hard masking layer 501. This process is used to avoid the adverse effects of the defective hard masking layer 501 on the resulting semiconductor device 1B.

[0163] Reference Figure 13 , Figure 20 and Figure 21 In step S41, a trench opening TO can be formed in the dielectric layer 105.

[0164] Reference Figure 20 It can be used in a similar way Figure 8 The procedure shown is used to form the hard mask opening 205O, and its description will not be repeated here. A portion of the bottom fill layer 203 is exposed by the hard mask opening 205O.

[0165] Reference Figure 21 A top hard mask layer 205 and / or a third mask layer 405 can be used as masks to perform a trench etching process to remove portions of the dielectric layer 105 and the underfill layer 203. In some embodiments, during the trench etching process, the etching rate ratio of the dielectric layer 105 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. During the trench etching process, the etching rate ratio of the underfill layer 203 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. After the trench etching process, a trench opening TO can be formed in the dielectric layer 105. It should be noted that at this stage, the etch stop layer 103 can still be covered in the trench opening VO by the remaining underfill layer 203.

[0166] Reference Figure 13 and Figure 22 In step S43, a punching etching process can be performed to form an extended through-hole opening EVO to expose the substrate 101.

[0167] Reference Figure 22The punch-etch process can remove the remaining bottom filler layer 203 in the via opening VO and a portion of the etch stop layer 103 exposed through the via opening VO. In some embodiments, during the punch-etch process, the etch rate ratio of the bottom filler layer 203 to the dielectric layer 105 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. In some embodiments, during the punch-etch process, the etch rate ratio of the etch stop layer 103 to the substrate 101 may be between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. After the punch-etch process, the via opening VO may extend along the dielectric layer 105 and the etch stop layer 103 to the extended via opening EVO. A portion of the substrate 101 may be exposed through the extended via opening EVO.

[0168] In some embodiments, a similar approach can be used. Figure 10 The procedure shown is to... Figure 22 The intermediate semiconductor element shown undergoes pre-cleaning and cleaning processes, the description of which will not be repeated here.

[0169] Reference Figure 13 , Figure 23 and Figure 24 In step S45, a through hole 107 can be formed in the extended through hole opening EVO, and a trench 109 can be formed in the trench opening TO.

[0170] Reference Figure 23 and Figure 24 It can be used in a similar way Figure 11 and Figure 12 The procedure shown is used to form the via 107 and the trench 109, and its description will not be repeated here. The substrate 101, the first etch stop layer 103, the dielectric layer 105, the via 107 and the trench 109 together configure the semiconductor device 1B.

[0171] One aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first masking layer as a mask; forming a defective hard masking layer to fill the via opening; forming a second masking layer on the defective hard masking layer; removing the second masking layer and the defective hard masking layer; forming a bottom filler layer to fill the via opening; forming a top hard masking layer on the bottom filler layer; forming a third masking layer on the top hard masking layer; patterning the top hard masking layer using the third masking layer as a mask; forming a trench opening in the dielectric layer using the top hard masking layer as a mask; and forming a via in the via opening and a trench in the trench opening.

[0172] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first masking layer as a mask; forming a defective hard masking layer to fill the via opening; forming a second masking layer on the defective hard masking layer; removing the second masking layer; performing a recoating process to transform the defective hard masking layer into a bottom fill layer; forming a top hard masking layer on the bottom fill layer; forming a third masking layer on the top hard masking layer; patterning the top hard masking layer using the third masking layer as a mask; forming a trench opening in the dielectric layer using the top hard masking layer as a mask; and forming a via in the via opening and a trench in the trench opening.

[0173] Another aspect of this disclosure provides a defective hard masking layer disposed on a via opening in a dielectric layer, wherein a rework method includes removing the defective hard masking layer; forming a bottom fill layer to fill the via opening; forming a top hard masking layer on the bottom fill layer; and forming a masking layer on the top hard masking layer.

[0174] Another aspect of this disclosure provides a defective hard mask layer disposed on a via opening in a dielectric layer, wherein a rework method comprises performing a recoating process to transform the defective hard mask layer into a bottom fill layer; forming a top hard mask layer on the bottom fill layer; and forming a mask layer on the top hard mask layer.

[0175] Due to the design of the semiconductor device fabrication method disclosed herein, by employing a bottom filler layer or a subfill layer, the enlargement of via openings and / or damage to the via opening profile can be mitigated or avoided. Therefore, the yield and / or reliability of the semiconductor device can be improved.

[0176] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined by the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0177] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor device, comprising: Provide a base; A dielectric layer is formed on the substrate; A first masking layer is used as a mask, and a via opening is formed in the dielectric layer. A defective hard mask layer is formed to fill the through-hole opening, wherein the defective hard mask layer refers to a hard mask layer that is out of specification, has a pattern deviation, or includes grooves. A second masking layer is formed on the substandard hard masking layer; Remove the second masking layer and the defective hard masking layer; A bottom filler layer is formed to fill the through-hole opening; A top hard masking layer is formed on the bottom filler layer; A third masking layer is formed on top of the hard masking layer; The top hard mask layer is patterned using the third mask layer as a mask. Using the top hard masking layer as a mask, a trench opening is formed in the dielectric layer; as well as A through hole is formed in the through hole opening, and a ditch is formed in the ditch opening.

2. The preparation method according to claim 1, wherein the bottom filler layer and the defective hard mask layer comprise different materials.

3. The preparation method as described in claim 2, wherein the thickness of the defective hard mask layer is different from the thickness of the underlying filler layer.

4. The preparation method according to claim 3, wherein the thickness of the defective hard mask layer is between 30 nanometers and 50 nanometers.

5. The preparation method according to claim 4, wherein the thickness of the bottom filling layer is between 180 nanometers and 220 nanometers.

6. The preparation method according to claim 5, wherein the dielectric layer comprises a low-k material.

7. The preparation method according to claim 6, wherein the top hard mask layer comprises boron nitride, boron silicon nitride, boron phosphorus nitride, or boron silicon carbide.

8. The preparation method according to claim 7, wherein the bottom filling layer comprises a carbon film.

9. The preparation method of claim 8, wherein the through hole and the channel comprise copper.

10. The preparation method of claim 9 further includes forming an etch stop layer between the substrate and the dielectric layer.

11. A method for fabricating a semiconductor device, comprising: Provide a base; A dielectric layer is formed on the substrate; A first masking layer is used as a mask, and a via opening is formed in the dielectric layer. A defective hard mask layer is formed to fill the through-hole opening, wherein the defective hard mask layer refers to a hard mask layer that is out of specification, has a pattern deviation, or includes grooves. A second masking layer is formed on the substandard hard masking layer; Remove the second mask layer; Perform a recoating process to turn the defective masking layer into a bottom filler layer; A top hard masking layer is formed on the bottom filler layer; A third masking layer is formed on top of the hard masking layer; The top hard mask layer is patterned using the third mask layer as a mask. Using the top hard masking layer as a mask, a trench opening is formed in the dielectric layer; as well as A through hole is formed in the through hole opening, and a ditch is formed in the ditch opening.

12. The preparation method of claim 11, wherein the bottom filler layer and the defective hard mask layer comprise the same material.

13. The preparation method of claim 12, wherein the thickness of the defective hard mask layer is different from the thickness of the bottom filler layer.

14. The preparation method of claim 13, wherein the thickness of the defective hard mask layer is between 30 nanometers and 50 nanometers.

15. The preparation method of claim 14, wherein the thickness of the bottom filling layer is between 180 nanometers and 220 nanometers.

16. The preparation method of claim 15, wherein the dielectric layer comprises a low-k material.

17. The preparation method of claim 16, wherein the top hard mask layer comprises boron nitride, boron silicon nitride, boron phosphorus nitride, or boron silicon carbide.

18. The preparation method of claim 17 further includes forming an etch stop layer between the substrate and the dielectric layer.

19. The preparation method of claim 18, wherein the etch stop layer comprises silicon carbide or silicon oxycarbide.

20. The preparation method of claim 19, wherein the through hole and the channel comprise copper.

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