Semiconductor assembly and method of manufacturing the same

Abstract

The application discloses a semiconductor assembly and a manufacturing method thereof, comprising a substrate, a well region, a first trench, a second trench, a first gate, a source electrode and a drain electrode. The substrate has a first conductive type, the well region has a second conductive type and is arranged on the substrate, the first trench and the second trench are arranged in the well region, the first trench is provided with a first field plate and a first dielectric layer surrounding the first field plate, the second trench is provided with a second field plate and a second dielectric layer surrounding the second field plate, the first gate is arranged above the first field plate, the source electrode is arranged on a first side of the first trench, the drain electrode is arranged on a second side of the second trench, and the source electrode, the first trench, the second trench and the drain electrode are sequentially arranged along a first direction.

Description

Technical Field

[0001] This invention relates to integrated circuit technology, and in particular to an integrated circuit structure comprising a laterally diffused trench type metal-oxide-semiconductor component and a method for manufacturing the same. Background Technology

[0002] Metal-oxide-semiconductor (MOSFET) field-effect transistors are the most commonly used components in integrated circuits. They include horizontal structures, such as laterally-diffused metal-oxide-semiconductor (LDMOS) MOSFETs, and vertical structures, such as planar-gate MOSFETs and trench-gate MOSFETs. To achieve high voltage withstand capabilities, the length of the field plate and drift region can be increased in laterally-diffused MOSFETs, or the depth of the trench can be increased in trench-gate MOSFETs. However, these methods lead to increased component size, incompatibility with other components' processes, and increased manufacturing complexity. Therefore, the industry urgently needs MOSFET components that can meet various requirements in integrated circuits. Summary of the Invention

[0003] In view of this, the present invention proposes an integrated circuit structure including a laterally diffused trench metal-oxide-semiconductor (LDMOS) device and its manufacturing method. It can use power integrated circuit process technology (Bipolar-CMOS-DMOS, BCD) to simultaneously form laterally diffused trench LDMOS devices, laterally diffused LDMOS devices, and complementary metal-oxide-semiconductor (CMOS) devices on the same semiconductor substrate. Furthermore, it enables the laterally diffused trench LDMOS device to achieve effects such as reducing trench depth, improving process difficulty, increasing breakdown voltage, and reducing on-resistance.

[0004] According to an embodiment of the present invention, a semiconductor component is provided, including a substrate, a well region, a first trench, a second trench, a first gate, a source electrode, and a drain electrode. The substrate has a first conductivity type, the well region has a second conductivity type, and is disposed on the substrate. The first trench and the second trench are disposed in the well region. A first field plate and a first dielectric layer are disposed in the first trench and surround the first field plate. A second field plate and a second dielectric layer are disposed in the second trench and surround the second field plate. The first gate is disposed above the first field plate. The source electrode is disposed on a first side of the first trench, and the drain electrode is disposed on a second side of the second trench. The source electrode, the first trench, the second trench, and the drain electrode are arranged sequentially along a first direction.

[0005] According to an embodiment of the present invention, a method for manufacturing a semiconductor component is provided, comprising the following steps: providing a substrate having a first conductivity type; forming a well region having a second conductivity type on the substrate; forming a first trench and a second trench in the well region; depositing a dielectric layer in the first trench and the second trench in a directional manner, and filling a conductive layer on the dielectric layer; etching the conductive layer in the first trench and the second trench to form a first recess located on a first field plate and a second recess located on a second field plate, respectively; filling the first recess and the second recess with dielectric material to form a first dielectric isolation portion and a second dielectric isolation portion, respectively; etching the dielectric layer and the first dielectric isolation portion in the first trench to form a first groove; forming a first gate in the first groove; and forming a source region and a drain region in the well region, wherein the source region is located on a first side of the first trench and the drain region is located on a second side of the second trench. Attached Figure Description

[0006] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed textual descriptions while reading this invention. Specific embodiments described herein, along with corresponding drawings, are used to explain the detailed implementation of these embodiments and to elucidate their operational principles. Furthermore, for clarity, features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0007] Figure 1 This is a schematic cross-sectional view of a semiconductor component according to an embodiment of the present invention.

[0008] Figure 2 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention.

[0009] Figure 3 These are perspective schematic diagrams and cross-sectional schematic diagrams of a semiconductor component according to another embodiment of the present invention.

[0010] Figure 4This is a three-dimensional schematic diagram of a semiconductor component according to another embodiment of the present invention.

[0011] Figure 5 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention.

[0012] Figure 6 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention.

[0013] Figure 7 This is a cross-sectional schematic diagram of a semiconductor component in the on-state according to an embodiment of the present invention.

[0014] Figure 8 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention.

[0015] Figure 9 This is a cross-sectional schematic diagram of a semiconductor component in the on-state according to another embodiment of the present invention.

[0016] Figure 10 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention.

[0017] Figure 11 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention.

[0018] Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a cross-sectional schematic diagram of each stage of a method for manufacturing an integrated circuit structure according to an embodiment of the present invention, which includes three discontinuous semiconductor component regions.

[0019] Figure 17 This is a cross-sectional schematic diagram of one stage of a method for manufacturing an integrated circuit structure according to another embodiment of the present invention, wherein two rows of doped regions are included below the trench.

[0020] Figure 18 This is a cross-sectional schematic diagram of one stage of a method for manufacturing an integrated circuit structure according to another embodiment of the present invention, wherein four or more rows of doped regions are included below the trench.

[0021] Figure 19 This is a cross-sectional schematic diagram of one stage of a method for manufacturing an integrated circuit structure according to another embodiment of the present invention, wherein doped regions that are laterally adjacent to each other are included below the trench.

[0022] Figure 20This is a schematic diagram of the voltage equipotential line distribution of a semiconductor component in the off-state and on-state, according to an embodiment of the present invention.

[0023] The reference numerals in the attached figures are explained as follows:

[0024] 100, 100-1, 100-2, 100-3, 100-4, 200, 300… Semiconductor Components

[0025] 101…base

[0026] 102… Buried layer

[0027] 103… well area

[0028] 104…Epiaxial layer

[0029] 105-1…First trench

[0030] 105-2…Second trench

[0031] 105-3… Third trench

[0032] 105-4… Fourth trench

[0033] 105-5… Fifth trench

[0034] 106…dielectric layer

[0035] 106-1…First dielectric layer

[0036] 106-2…Second dielectric layer

[0037] 106-3…Third dielectric layer

[0038] 106-4… Fourth dielectric layer

[0039] 107…conductive layer

[0040] 107-1…First game

[0041] 107-2… Second game

[0042] 107-3… Third game

[0043] 107-4… Fourth game

[0044] 108-1…First Dielectric Isolation Section

[0045] 108-2…Second Dielectric Isolation Section

[0046] 108-3…Third Dielectric Isolation Section

[0047] 109-1…First gate

[0048] 109-2…Second gate

[0049] 109C…Gate Connection

[0050] 110…Current Path

[0051] 111…Source Electrode

[0052] 111S…Source Region

[0053] 113…Drain electrode

[0054] 113D…Drain region

[0055] 115… Field plate contact

[0056] 116… interconnection structure

[0057] 117-1…First matrix region

[0058] 117-2…Second matrix region

[0059] 118…heavily doped region

[0060] 119…Gate contact

[0061] 120… interlayer dielectric layer

[0062] 121…Epiaxial layer

[0063] 123, 151, 153… Trap Zone

[0064] 125, 145… Patterned hard masks

[0065] 127-1…First Depression

[0066] 127-2…Second Depression

[0067] 127-3…Third Depression

[0068] 129, 131... trenches

[0069] 135, 137… Shallow trench isolation structure

[0070] 141, 143... doped regions

[0071] 147-1…First Groove

[0072] 147-2…Second Groove

[0073] 155… Gate Dielectric Layer

[0074] 157, 159… gate

[0075] 161S, 163S, 165S… source pole regions

[0076] 161D, 163D, 165D... Drain region

[0077] 171, 181, 191… Source Electrode

[0078] 173, 183, 193… Drain electrodes

[0079] 179, 189, 199… Gate contacts

[0080] 202a…first line

[0081] 204a… second line

[0082] 202b… third line

[0083] 204b… Fourth line

[0084] 202a-1, 202a-2, 202a-3, 202a-4, 202a-5… First doped region

[0085] 202b-1, 202b-2, 202b-3, 202b-4, 202b-5… First doped region

[0086] 204a-1, 204a-2, 204a-3, 204a-4, 204a-5… Second doped region

[0087] 204b-1, 204b-2, 204b-3, 204b-4, 204b-5… Second doped region

[0088] 210…Inverted layer

[0089] 230, 230-1, 230-2… current

[0090] 240-1…First Starting Region

[0091] 240-2…Second Starting Region

[0092] 400-1, 400-2, 400-3, 400-4, 400-5… cross-sectional structures

[0093] 1000…First District

[0094] 2000…Second District

[0095] 3000…Third District

[0096] 10…First side

[0097] 20…Second side

[0098] H1, H2... Depth

[0099] Steps S101, S103, S105, S107, S109, S111, S113, S115, S117…

[0100] 100-off, 100-on… Voltage equipotential line distribution

[0101] aa… Tangent to the cross section Detailed Implementation

[0102] This invention provides several different embodiments that can be used to implement different features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following description of "a first feature forming on or above a second feature" may mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," so that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any relationship between different embodiments and / or configurations.

[0103] Furthermore, for the spatially related descriptive terms mentioned in this invention, such as "below," "low," "under," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one component or feature and another (or more) components or features in the diagrams. In addition to the orientation shown in the diagrams, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0104] Although the present invention uses terms such as first, second, third, etc., to describe various components, parts, regions, layers, and / or sections, it should be understood that such components, parts, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one component, part, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the component, nor do they represent the arrangement order of one component with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first component, part, region, layer, or section discussed below may also be referred to as a second component, part, region, layer, or section.

[0105] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate, meaning that the meaning of "about" or "substantially" may be implied even without specific specification.

[0106] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means or connections.

[0107] Although the invention is described below with reference to specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the knowledge scope of those skilled in the art.

[0108] This invention relates to an integrated circuit structure including a laterally diffused trench metal-oxide-semiconductor (LDMOS) component and its manufacturing method. It can use power integrated circuit process technology (Bipolar-CMOS-DMOS, BCD) to simultaneously form laterally diffused trench LDMOS components, laterally diffused LDMOS components, and complementary metal-oxide-semiconductor (CMOS) components on the same semiconductor substrate. Furthermore, it enables the laterally diffused trench LDMOS components to achieve effects such as reducing trench depth, improving process difficulty, increasing breakdown voltage, and reducing on-resistance.

[0109] Figure 1 This is a schematic cross-sectional view of a semiconductor component according to an embodiment of the present invention. Figure 1As shown, in one embodiment, the semiconductor component 100 includes a substrate 101 having a first conductivity type, such as a p-type silicon substrate, and a well region 103 disposed on the substrate 101. The well region 103 has a second conductivity type opposite to the first conductivity type, such as a deep n-type well (DNW) or an n-type silicon epitaxial layer (N-epi). The semiconductor component 100 also includes a first trench 105-1 and a second trench 105-2 disposed in the well region 103. A first field plate 107-1 and a first dielectric layer 106-1 are disposed in the first trench 105-1 surrounding the first field plate 107-1. A second field plate 107-2 and a second dielectric layer 106-2 are disposed in the second trench 105-2 surrounding the second field plate 107-2. In this embodiment, the first gate 109-1 is also disposed in the first trench 105-1 and located above the first field plate 107-1. The first gate 109-1 and the first field plate 107-1 are separated by a first dielectric isolation portion 108-1, which covers the first field plate 107-1. The first gate 109-1 can be disposed in the first dielectric isolation portion 108-1. When viewed along a direction perpendicular to the surface of the substrate 101 (e.g., the Z-axis direction), the first gate 109-1 and the first field plate 107-1 may not be aligned with each other, resulting in misalignment. For example, the first gate 109-1 may be offset to the right (e.g., along the X-axis direction) relative to the first field plate 107-1. In some embodiments, the first gate 109-1, the first field plate 107-1, and the second field plate 107-2 may be formed of the same conductive material, such as polysilicon, doped polysilicon, metal silicide, metal, or other conductive material. The first dielectric layer 106-1, the second dielectric layer 106-2, and the first dielectric isolation portion 108-1 may also be formed of the same dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a dielectric material with a high dielectric constant.

[0110] Furthermore, the semiconductor component 100 also includes a first substrate region 117-1 disposed on the first side 10 of the first trench 105-1, and a second substrate region 117-2 disposed between the first trench 105-1 and the second trench 105-2. The first substrate region 117-1 and the second substrate region 117-2 have a first conductivity type, for example, both are p-type substrate regions (p-body), and the dopant concentration of the first conductivity type dopant in the first substrate region 117-1 and the second substrate region 117-2 is greater than the dopant concentration of the second conductivity type dopant in the well region 103. The first substrate region 117-1 and the second substrate region 117-2 are formed in the well region 103, close to the top surface of the well region 103, and the bottom surfaces of both the first substrate region 117-1 and the second substrate region 117-2 are higher than the top surface of the first field plate 107-1. The semiconductor component 100 further includes a source region 111S disposed in the first substrate region 117-1 and near the top surface of the first substrate region 117-1, and a drain region 113D disposed in the well region 103 of the second side 20 of the second trench 105-2 and near the top surface of the well region 103. Additionally, the semiconductor component 100 includes an interlayer dielectric layer 120 covering the well region 103. A source electrode 111 extends through the interlayer dielectric layer 120 downward into the first substrate region 117-1 and is adjacent to and electrically coupled to the source region 111S. A drain electrode 113 extends through the interlayer dielectric layer 120 downward into the well region 103 and is adjacent to and electrically coupled to the drain region 113D. The fieldplate contact 115 penetrates the interlayer dielectric layer 120 and extends downward into the second substrate region 117-2, and is electrically coupled to the second substrate region 117-2. In this embodiment, the source electrode 111 is disposed on the first side 10 of the first trench 105-1, and the drain electrode 113 is disposed on the second side 20 of the second trench 105-2. Along a first direction (e.g., from right to left along the X-axis), the source electrode 111, the first trench 105-1, the second trench 105-2, and the drain electrode 113 are arranged sequentially. Furthermore, in some embodiments, the potential of the first fieldplate 107-1 may be the same as the potential of the first gate 109-1 (e.g., both are positive potentials), or the potential of the first fieldplate 107-1 may be the same as the potential of the source electrode 111 (e.g., both are ground potentials).

[0111] See also Figure 1 and Figure 20According to one embodiment of the present invention, a gate dielectric layer 155 is present between the first gate 109-1 and the first substrate region 117-1. Therefore, when a specific bias voltage (e.g., a positive potential) is applied to the first gate 109-1, the conductivity of the first substrate region 117-1 adjacent to this gate dielectric layer can be increased, thereby forming a conductive channel. According to one embodiment of the present invention, when a conduction bias voltage (e.g., a positive potential) is applied to the first gate 109-1, a conductive channel is formed in the first substrate region 117-1. Furthermore, when a positive potential is applied to the first field plate 107-1 and the second field plate 107-2, the electric field distribution or potential distribution in the well region 103 surrounding the first trench 105-1 and the second trench 105-2 can be adjusted, thereby avoiding the generation of a high-intensity electric field in a local area. Therefore, during the operation of the semiconductor component 100, current is allowed to flow from the drain electrode 113 down along the second side 20 of the second trench 105-2 to below the second trench 105-2, then down to below the first trench 105-1, and then up along the first side 10 of the first trench 105-1 through the conductive channel in the first substrate region 117-1, and finally to the source electrode 111, so that the semiconductor component 100 of the present invention has a U-shaped current path 110. Furthermore, regarding the second substrate region 117-2 disposed between the first trench 105-1 and the second trench 105-2, since the conductivity of the second substrate region 117-2 is different from that of the well region 103, during the operation of the semiconductor component 100, current will not flow from the well region 103 into the second substrate region 117-2. Moreover, by applying a potential to the second substrate region 117-2 via the field plate contact 115, the electric field distribution or potential distribution in the well region 103 below the second substrate region 117-2 can be controlled. In embodiments of the present invention, the PN junction between the substrate 101 and the well region 103 is utilized to disperse voltage on both the first side 10 of the first trench 105-1 and the second side 20 of the second trench 105-2, thereby achieving a more even voltage drop distribution along the current path. Furthermore, even with the reduced depth of the first trench 105-1 and the second trench 105-2, the semiconductor device 100 can still achieve the same withstand voltage capability as that achievable with a single extremely deep trench. According to embodiments of the present invention, since the first trench 105-1 and the second trench 105-2 have reduced depths, in addition to reducing the manufacturing difficulty of the semiconductor device 100, the stress generated by the deep trenches on the wafer during the fabrication of the semiconductor device can also be reduced, thus facilitating integrated circuit process integration (BCD) and improving process yield.

[0112] Figure 2 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention. Figure 2As shown, in one embodiment, the semiconductor component 100 may further include a buried layer 102 disposed below the well region 103, for example, disposed between the well region 103 and the substrate 101. The buried layer 102 has a second conductivity type, for example, an n-type buried layer (NBL). In this embodiment, the semiconductor component 100 further includes a third trench 105-3 and a fourth trench 105-4, and the first trench 105-1, the second trench 105-2, the third trench 105-3, and the fourth trench 105-4 are all disposed in the well region 103 and extend downward into the buried layer 102, but do not penetrate the bottom surface of the buried layer 102. Within the second trench 105-2, the second dielectric isolation portion 108-2 covers the second field plate 107-2. Within the third trench 105-3, the third field plate 107-3 and the third dielectric layer 106-3 are disposed and surround the third field plate 107-3. The second gate 109-2 is disposed within the third trench 105-3 and is separated from the third field plate 107-3 by the third dielectric isolation portion 108-3. The third dielectric isolation portion 108-3 covers the third field plate 107-3. The second gate 109-2 is disposed within the third dielectric isolation portion 108-3. When viewed along a direction perpendicular to the surface of the substrate 101 (e.g., the Z-axis direction), the second gate 109-2 and the third field plate 107-3 may not be aligned with each other. For example, the second gate 109-2 may be offset to the left relative to the third field plate 107-3. Furthermore, a gate dielectric layer 155 exists between the second gate 109-2 and the first substrate region 117-1. A fourth field plate 107-4 and a fourth dielectric layer 106-4 are disposed within the fourth trench 105-4, surrounding the fourth field plate 107-4. A source electrode 111 is disposed between the first trench 105-1 and the third trench 105-3, and a drain electrode 113 is disposed between the fourth trench 105-4 and the second trench 105-2. Along a first direction (e.g., from right to left along the X-axis), the third trench 105-3, the source electrode 111, the first trench 105-1, the second trench 105-2, the drain electrode 113, and the fourth trench 105-4 are arranged sequentially. In this embodiment, the top surface of the fourth field plate 107-4 is higher than the top surfaces of the first field plate 107-1, the second field plate 107-2, and the third field plate 107-3. In other embodiments, the top surface of the fourth field plate 107-4 may be at the same horizontal level as the top surfaces of the first field plate 107-1, the second field plate 107-2, and the third field plate 107-3. Additionally, the gate contact 119 penetrates the interlayer dielectric layer 120 and is adjacent to and electrically coupled to the first gate 109-1. Figure 2 Other components of the semiconductor component 100 can be found in [reference needed]. Figure 1 Descriptions of components with the same designation are not repeated here.

[0113] Figure 3These are perspective schematic diagrams and cross-sectional schematic diagrams of a semiconductor component according to another embodiment of the present invention. Figure 3 As shown, in one embodiment, the semiconductor component 100 includes a third trench 105-3, a first trench 105-1, a second trench 105-2, and a fourth trench 105-4 arranged sequentially along a first direction (e.g., from right to left along the X-axis). These trenches are all disposed in the well region 103, and each of the third trench 105-3, the first trench 105-1, the second trench 105-2, and the fourth trench 105-4 includes a third field plate 107-3, a first field plate 107-1, a second field plate 107-2, and a fourth field plate 107-4. Each of these field plates is surrounded by a third dielectric layer 106-3, a first dielectric layer 106-1, a second dielectric layer 106-2, and a fourth dielectric layer 106-4 within the trench. Furthermore, in some embodiments, the top surface of the fourth field plate 107-4 may be higher than the top surfaces of the first field plate 107-1, the second field plate 107-2, and the third field plate 107-3. The first dielectric isolation portion 108-1 covers the first field plate 107-1, and the third dielectric isolation portion 108-3 covers the third field plate 107-3. The top surfaces of the first dielectric isolation portion 108-1 and the third dielectric isolation portion 108-3 may be flush with the top surface of the fourth field plate 107-4.

[0114] also, Figure 3 The semiconductor component 100 further includes a first gate 109-1 disposed on the top surface of the first dielectric isolation portion 108-1, and a second gate 109-2 disposed on the top surface of the third dielectric isolation portion 108-3. The long axes of the first gate 109-1 and the second gate 109-2 extend substantially along a second direction (e.g., the Y-axis direction). In this embodiment, both the first gate 109-1 and the second gate 109-2 are located on the well region 103. Figure 3 The semiconductor component 100 further includes a gate connection portion 109C, which extends from one sidewall of the first gate 109-1 along a first direction (e.g., the X-axis direction) and protrudes beyond the aforementioned sidewall of the first gate 109-1. The gate connection portion 109C extends to one sidewall of the second gate 109-2, and is also disposed on the well region 103. Figure 3 As shown, the first gate 109-1, the second gate 109-2, and the gate connection portion 109C can form an H-shaped structure in the XY plane. The gate connection portion 109C is disposed between the first gate 109-1 and the second gate 109-2, and spacers can be provided on the two opposite outer walls of the first gate 109-1, the second gate 109-2, and the gate connection portion 109C.

[0115] in addition, Figure 3A cross-sectional schematic diagram of a local region of the semiconductor component 100 along the tangent line aa is also shown, as follows. Figure 3 As shown, the semiconductor component 100 further includes a substrate region, such as a first substrate region 117-1, disposed below the gate connection portion 109C. The first substrate region 117-1 extends and protrudes from below one side of the gate connection portion 109C along a second direction (e.g., the Y-axis direction), and is located between the upper regions of the first trench 105-1 and the third trench 105-3. The semiconductor component 100 also includes a second substrate region 117-2, located between the first trench 105-1 and the second trench 105-2. Both the first substrate region 117-1 and the second substrate region 117-2 have a first conductivity type, such as a p-type substrate region, and are both disposed in a well region 103 having a second conductivity type. Furthermore, the semiconductor component 100 also includes a source region 111S located between the first trench 105-1, the third trench 105-3, and the gate connection portion 109C, with the three sides of the source region 111S adjacent to the first trench 105-1, the third trench 105-3, and the gate connection portion 109C, respectively. Additionally, a heavily doped region 118 of a first conductivity type, such as a p-type heavily doped region (P+ region), may be provided in the first substrate region 117-1, with a dopant concentration greater than that of the first substrate region 117-1. The heavily doped region 118 is adjacent to the source region 111S, and the first substrate region 117-1 extends below the source region 111S and the heavily doped region 118. During operation of the semiconductor component 100, the heavily doped region 118 and the source region 111S may be electrically coupled to the same potential (e.g., ground potential), but are not limited thereto.

[0116] like Figure 3 As shown, the semiconductor component 100 further includes a drain region 113D, located between the second trench 105-2 and the fourth trench 105-4, and disposed in the well region 103. Both the drain region 113D and the source region 111S are doped regions of a second conductivity type, such as n-type doped regions. In this embodiment, the first gate 109-1, the second gate 109-2, and the gate connection portion 109C are planar gate structures, which can be formed simultaneously from polysilicon, doped polysilicon, metal, or other conductive materials using deposition, photolithography, and etching processes. Furthermore, the long axis extension direction (second direction, e.g., the Y-axis direction) of the first gate 109-1 and the second gate 109-2 and the long axis extension direction (first direction, e.g., the X-axis direction) of the gate connection portion 109C may have a non-zero angle, such as an angle of approximately 90 degrees, but is not limited thereto. Figure 3In this embodiment, the channel region of the semiconductor component 100 is located below the planar gate structure formed by the gate connection portion 109C, and in the first substrate region 117-1 below the gate connection portion 109C. Either the first gate 109-1 or the second gate 109-2 can serve as a wire structure for transmitting electrical signals to the gate connection portion 109C. According to this embodiment, since the first gate 109-1 and the second gate 109-2 are respectively disposed directly above the first trench 105-1 and the third trench 105-3, and can extend in the same direction (e.g., the Y-axis direction) as the corresponding trenches, the first gate 109-1 and the second gate 109-2 can be prevented from occupying additional wafer area. Furthermore, Figure 3 Other components of the semiconductor component 100 can be found in [reference needed]. Figure 1 Descriptions of components with the same designation are not repeated here.

[0117] Figure 4 This is a three-dimensional schematic diagram of a semiconductor component according to another embodiment of the present invention. Figure 4 As shown, in this embodiment, the first gate 109-1 and the first field plate 107-1 of the semiconductor component 100 are interconnected without being separated by a dielectric isolation portion (not shown). The first gate 109-1 and the first field plate 107-1 are respectively composed of different regions of the same conductive layer in the first trench 105-1. This conductive layer is, for example, polysilicon, doped polysilicon, metal silicide, metal or other conductive material. The potential of the first field plate 107-1 can be the same as the potential of the first gate 109-1 (for example, both are positive potentials). In this embodiment, a first substrate region 117-1 and a second substrate region 117-2 are disposed in the well region 103 along two opposite sides of the first trench 105-1. The first substrate region 117-1 is adjacent to one side of the first trench 105-1, and the second substrate region 117-2 is adjacent to the other side of the first trench 105-1. The second substrate region 117-2 is located between the first trench 105-1 and the second trench 105-2. Both the first substrate region 117-1 and the second substrate region 117-2 have a first conductivity type, such as a p-type substrate region. In some embodiments, both the first substrate region 117-1 and the second substrate region 117-2 extend downward from the top surface height of the first trench 105-1 by a depth H1, for example, approximately 0.3 micrometers (μm) to 2 μm, and the depth H2 of the first trench 105-1 is, for example, approximately 0.5 micrometers (μm) to 10 μm. In some embodiments, the depth H1 of the first substrate region 117-1 and the second substrate region 117-2 may be approximately 3% to 60% of the depth H2 of the first trench 105-1, but is not limited thereto. Figure 4In one embodiment, the channel region (not shown) of the semiconductor component 100 is located on the side of the first gate 109-1 within the first trench 105-1, and within the first substrate region 117-1. Furthermore, Figure 4 Other components of the semiconductor component 100 can be found in [reference needed]. Figure 1 Descriptions of components with the same designation are not repeated here.

[0118] Figure 5 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention. Figure 5 As shown, in one embodiment, the semiconductor component 100 may include an epitaxial layer 104 of a first conductivity type, such as a p-type epitaxial layer, disposed on a substrate 101 of the first conductivity type, and a well region 103 of a second conductivity type, such as an n-type well region, disposed in the epitaxial layer 104. In this embodiment, the semiconductor component 100, with the drain electrode 113 as the center of mirror symmetry, arranges a second trench 105-2, a second substrate region 117-2, a first trench 105-1, a first substrate region 117-1, and a third trench 105-3 sequentially along a first direction (e.g., the X-axis direction) towards the right and left. A source region 111S is disposed in the first substrate region 117-1, and a drain region 113D is disposed between two adjacent second trenches 105-2. A first gate 109-1, a first field plate 107-1, and a first dielectric layer 106-1 are disposed within the first trench 105-1. The second gate 109-2, the third field plate 107-3, and the third dielectric layer 106-3 are disposed within the third trench 105-3. A gate dielectric layer 155 exists between the first gate 109-1 and the first substrate region 117-1 and the source region 111S, and another gate dielectric layer 155 also exists between the second gate 109-2 and the first substrate region 117-1 and the source region 111S. The second field plate 107-2 and the second dielectric layer 106-2 are disposed within the second trench 105-2. Furthermore, the second field plate 107-2 and the second substrate region 117-2 can be electrically coupled to the interconnect structure 116, thereby electrically coupling the second field plate 107-2 and the second substrate region 117-2 to each other. The source electrode 111, drain electrode 113, gate contact 119, and interconnect structure 116 are all disposed in the interlayer dielectric layer 120. The source electrode 111 is electrically coupled to the source region 111S, the drain electrode 113 is electrically coupled to the drain region 113D, and the two gate contacts 119 are respectively electrically coupled to the first gate 109-1 and the second gate 109-2. Figure 5 Other components of the semiconductor component 100 can be found in [reference needed]. Figure 2 Descriptions of components with the same designation are not repeated here.

[0119] Figure 6This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention. Figure 6 As shown, in one embodiment, the semiconductor component 100-1 includes not only... Figure 2 The first trench 105-1 to the fourth trench 105-4 are shown, and a fifth trench 105-5 is disposed between the first trench 105-1 and the second trench 105-2. The fifth trench 105-5 is disposed in the well region 103, and for the semiconductor component 100-1 having the buried layer 102, the bottom of the fifth trench 105-5 extends further into the buried layer 102.

[0120] Below each trench 105-1 to 105-5, there are paired doped regions with different conductivity types, such as first doped regions 202a-1, 202a-2, 202a-3, 202a-4, and 202a-5 with a second conductivity type, and second doped regions 204a-1, 204a-2, 204a-3, 204a-4, and 204a-5 with a first conductivity type. According to one embodiment, the first doped regions 202a-1, 202a-2, and 202a-5 are located in the buried layer 102, and the first doped regions 202a-1, 202a-2, and 202a-5 are respectively disposed below the first trench 105-1, the second trench 105-2, and the fifth trench 105-5. The first doped regions 202a-1, 202a-2, and 202a-5 can be located at substantially the same depth and arranged in a first row 202a. The second doped regions 204a-1, 204a-2, and 204a-5 will be located in the buried layer 102, and the second doped regions 204a-1, 204a-2, and 204a-5 will be disposed below the first doped regions 202a-1, 202a-2, and 202a-5, respectively. The second doped regions 204a-1, 204a-2, and 204a-5 can be located at substantially the same depth and arranged in a second row 202b. According to an embodiment of the present invention, when viewed along the depth direction (e.g., the Z-axis direction) of trenches 105-1 to 105-5, the projections of the first doped regions 202a-1, 202a-2, and 202a-5 partially overlap with the projections of the first trench 105-1, the second trench 105-2, and the fifth trench 105-5, respectively, and the projections of the second doped regions 204a-1, 204a-2, and 204a-5 partially overlap with the projections of the first trench 105-1, the second trench 105-2, and the fifth trench 105-5, respectively.

[0121] According to one embodiment of the present invention, each of the first doped regions 202a-1 to 202a-5 located in the first row 202a is adjacent to each of the second doped regions 204a-1 to 204a-5 located in the second row 202b, such that the adjacent first doped regions 202a-1 to 202a-5 and the adjacent second doped regions 204a-1 to 204a-5 are in contact with each other, and the ratio between the width (i.e., the scale along the X direction) of each first doped region 202a-1 to 202a-5 and the adjacent second doped regions 204a-1 to 204a-5 is between 0.5 and 2, for example, between 0.9 and 1.1. The average doping concentration of the first doped regions 202a-1 to 202a-5 and / or the average doping concentration of the second doped regions 204a-1 to 204a-5 is higher than the doping concentration of the buried layer 102 and the well region 103. The ratio between the average doping concentration of the first doped regions 202a-1 to 202a-5 and the average doping concentration of the second doped regions 204a-1 to 204a-5 is between 0.1 and 10, for example, between 0.9 and 1.1. By appropriately adjusting the width and doping concentration relationships between the first doped regions 202a-1 to 202a-5 and the second doped regions 204a-1 to 204a-5, the first doped regions 202a-1 to 202a-5 in the first row 202a and the second doped regions 204a-1 to 204a-5 in the second row 202b can form a structure similar to a super junction, which is beneficial for further reducing the on-resistance (R) of the semiconductor device 100-1. ON ) and increase breakdown voltage (V BR ).

[0122] Figure 7 This is a cross-sectional schematic diagram of a semiconductor component in the on-state according to an embodiment of the present invention. Figure 7 As shown, taking semiconductor component 100-1 as an example, when the first gate 109-1 is subjected to a conduction bias voltage, causing semiconductor component 100-1 to be in the conduction state, part of the current 230 will flow from the source region (not shown) sequentially through the well region 103, the buried layer 102, the first doped region 202a-1, the buried layer 102, the first doped region 202a-5, the buried layer 102, the first doped region 202a-2, the buried layer 102, the well region 103, and finally reach the drain region 113D (not shown). Since the conductivity types of the first doped regions 202a-1, 202a-2, and 202a-5 are the same as those of the buried layer 102, and the average doping concentration of the first doped regions 202a-1, 202a-2, and 202a-5 is higher than that of the buried layer 102, semiconductor component 100-1 can have a lower on-resistance (R0) compared to other semiconductor components that do not have the first doped regions 202a-1, 202a-2, and 202a-5. ONAccording to one embodiment, when the semiconductor component 100-1 is in the on-state, a bias voltage (e.g., a positive bias voltage) can also be applied to each field plate in each trench 105-1 to 105-5 simultaneously, so that an inversion layer 210 is generated below each trench 105-1 to 105-5. Since this inversion layer 210 has a lower resistance than the well region 103, when a portion of the current from the source region flows through this inversion layer 210, only a small voltage drop is generated, resulting in a lower on-resistance (RON).

[0123] On the other hand, when the semiconductor device 100-1 is in the off state, depletion regions are generated in the first doped regions 202a-1, 202a-2, 202a-5 and the adjacent second doped regions 204a-1, 204a-2, 204a-5. Since the resistance of the depletion region is higher than that of the buried layer 102 and the well region 103, it is beneficial to improve the breakdown voltage (VBR) of the semiconductor device 100-1.

[0124] Figure 8 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention. Figure 8 As shown, semiconductor component 100-2 is similar to Figure 6 The main difference between semiconductor component 100-1 and semiconductor component 100-2 is that semiconductor component 100-2 not only includes a first row 202a composed of first doped regions 202a-1 to 202a-5, but also a third row 202b composed of first doped regions 202b-1 to 202b-5, or a 2n-1 row composed of other first doped regions, where n is an integer greater than 2, such as the fifth row (not shown), the seventh row (not shown)...the 2n-1 row, etc. Furthermore, semiconductor component 100-2 not only includes a second row 204a composed of second doped regions 204a-1 to 204a-5, but also a fourth row 204b composed of second doped regions 204b-1 to 204b-5, or a 2n row composed of other second doped regions, where n is an integer greater than 2, such as the sixth row (not shown), the eighth row (not shown)...the 2n row, etc.

[0125] In one embodiment, rows of the first doped region and rows of the second doped region are alternately arranged along the depth direction (e.g., the Z direction) of the trenches 105-1 to 105-5, and the first doped regions arranged in the same row have substantially similar depths, and the second doped regions arranged in the same row have substantially similar depths.

[0126] Similarly, by appropriately controlling the width and doping concentration relationships between the first doped regions 202a-1~202a-5, 202b-1~202b-5 and the second doped regions 204a-1~204a-5, 204b-1~204b-5, the alternating arrangement of the first doped regions 202a-1~202a-5, 202b-1~202b-5 and the second doped regions 204a-1~204a-5, 204b-1~204b-5 along the trench depth direction (e.g., the Z direction) will form a superjunction structure, which is beneficial for further reducing the on-resistance (R) of the semiconductor device 100-2. ON ) and increase breakdown voltage (V BR ).

[0127] Figure 9 This is a cross-sectional schematic diagram of a semiconductor component in the on-state according to an embodiment of the present invention. Figure 9 As shown, taking semiconductor component 100-2 as an example, when the first gate 109-1 is subjected to a conduction bias voltage, causing semiconductor component 100-2 to be in the conduction state, part of the current 230-1 will flow from the source region (not shown) sequentially through the well region 103, the buried layer 102, the first doped region 202a-1, the buried layer 102, the first doped region 202a-5, the buried layer 102, the first doped region 202a-2, the buried layer 102, the well region 103, and finally reach the drain region 113D (not shown). Meanwhile, another portion of the current 230-2 flows from the source region (not shown) sequentially through the well region 103, the buried layer 102, the first doped region 202b-1, the buried layer 102, the first doped region 202b-5, the buried layer 102, the first doped region 202b-2, the buried layer 102, the well region 103, and finally reaches the drain region 113D (not shown). Since the conductivity types of the first doped regions 202a-1, 202a-2, 202a-5, 202b-1, 202b-2, and 202b-5 are the same as those of the buried layer 102, and the average doping concentration of the first doped regions 202a-1, 202a-2, 202a-5, 202b-1, 202b-2, and 202b-5 is higher than that of the buried layer 102, semiconductor component 100-2 can have a lower on-resistance (R0) compared to other semiconductor components that do not have the first doped regions 202a-1, 202a-2, 202a-5, 202b-1, 202b-2, and 202b-5. ONAccording to one embodiment, when the semiconductor component 100-2 is in the on-state, a bias voltage (e.g., a positive bias voltage) can also be applied to each field plate in trenches 105-1 to 105-5 simultaneously, causing an inversion layer to be generated below each trench 105-1 to 105-5. Since this inversion layer has a lower resistance than the well region 103, when a portion of the current from the source region flows through this inversion layer, only a small voltage drop is generated, resulting in a lower on-resistance (R). ON ).

[0128] On the other hand, when semiconductor device 100-2 is in the off state, depletion regions are generated in adjacent rows 202a, 202b, 204a, and 204b. Since the resistance of the depletion regions is higher than that of the buried layer 102 and the well region 103, this contributes to the breakdown voltage (V) of semiconductor device 100-2. BR The improvement of ).

[0129] Figure 10 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention. Figure 10 As shown, semiconductor component 100-3 is similar to Figure 8 The main difference between the semiconductor component 100-2 shown is that the first doped region of the first conductivity type (e.g., p-type) and the second doped region of the second conductivity type (e.g., n-type) are not provided below the first trench 105-1 and the second trench 105-2 of the semiconductor component 100-3. Instead, they are replaced by the first starting region 240-1 and the second starting region 240-2. The first starting region 240-1 is located below the first trench 105-1, and the second starting region 240-2 is located below the second trench 105-2. The first starting region 240-1 and the second starting region 240-2 can be part of the buried layer 102, so that the overall conductivity type of the first starting region 240-1 and the second starting region 240-2 is the second conductivity type (e.g., n-type). Since no second doped region of the first conductivity type that cannot be blocked by current is provided below the first trench 105-1 and the second trench 105-2, the current from the source electrode 111 or the drain electrode 113 can more easily flow into the wider deep region below the first trench 105-1 and the second trench 105-2, and then turn to flow through the first doped regions 202a-5 and 202b-5, which is beneficial to reducing the on-resistance (R). ON The decrease of ).

[0130] Figure 11 This is a cross-sectional schematic diagram of a semiconductor component according to another embodiment of the present invention. Figure 11 As shown, semiconductor component 100-4 is similar to Figure 8The main difference between the semiconductor component 100-2 and the semiconductor component 100-4 is that the average width (or first average width) of the second doped regions 204a-1, 204a-2, 204b-1, and 204b-2 below the first trench 105-1 and the second trench 105-2 is smaller than the average width (or second average width) of the second doped regions 204a-5 and 204b-5 below the fifth trench 105-5. Because the width of the second doped regions below the first trench 105-1 and the second trench 105-2 is narrower, the current from the source electrode 111 or the drain electrode 113 flows more easily into the wider, deeper region below the first trench 105-1 and the second trench 105-2, and then flows through the first doped regions 202a-5 and 202b-5, which is beneficial for reducing the on-resistance (R0). ON The decrease of ).

[0131] Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a cross-sectional schematic diagram illustrating various stages of a method for manufacturing an integrated circuit structure according to an embodiment of the present invention, including three discontinuous semiconductor component regions. Please refer to... Figure 12 An integrated circuit structure according to one embodiment of the present invention includes at least three discontinuous semiconductor component regions, namely a region of semiconductor component 100 (hereinafter referred to as the first region), a region of semiconductor component 200 (hereinafter referred to as the second region), and a region of semiconductor component 300 (hereinafter referred to as the third region), wherein semiconductor component 100 can be the aforementioned Figures 1 to 5 Any of the embodiments herein, hereinafter referred to as Figure 2 For example, semiconductor component 100 is a laterally diffused metal-oxide-semiconductor (LDMOS) component, semiconductor component 200 is a complementary metal-oxide-semiconductor (CMOS) component, and semiconductor component 300 is a complementary metal-oxide-semiconductor (CMOS) component.

[0132] See Figure 12First, as shown in cross-sectional structure 400-1, a substrate 101 of a first conductivity type, such as a p-type substrate, is provided. A buried layer 102 of a second conductivity type, such as an n-type buried layer, is formed in the substrate 101 of the first region 1000 and the third region 3000. Then, an epitaxial layer 121 of the first conductivity type, such as a p-type epitaxial layer, is formed on the substrate 101, and the epitaxial layer 121 covers the buried layer 102. Next, a patterned mask that masks the third region is formed using a photolithography process. Then, using the same ion implantation process, a well region 103 of the second conductivity type is formed simultaneously in the epitaxial layer 121 of the first region 1000 and the second region 2000. Then, the patterned mask that masks the third region is removed. Next, a patterned mask that masks the first region 1000 and the third region 3000 is formed, and using another ion implantation process, a well region 123 of the first conductivity type is formed in the epitaxial layer 121 of the second region 2000. Subsequently, a patterned hard mask is formed and used as an etching mask for the etching process. Within the well region 103 of the first region 1000, a third trench 105-3, a first trench 105-1, a second trench 105-2, and a fourth trench 105-4 are formed in a sequence from right to left. (Continue reading...) Figure 12 As shown in the cross-sectional structure 400-2, in step S101, a dielectric layer 106 is conventionally formed in each trench of the first region 1000, on the well regions 103 and 123 of the second region 2000, and on the epitaxial layer 121 of the third region 3000 using a deposition process. Then, a conductive layer 107 is filled in each trench of the first region 1000 using a deposition process and a chemical mechanical planarization (CMP) process, such that the top surface of the conductive layer 107 is flush with the top surface of the dielectric layer 106. The conductive layer 107 is, for example, polysilicon, but is not limited to this.

[0133] Next, refer to Figure 13In step S103, a patterned hard mask 125 is formed in the first region, the second region and the third region. The opening of the patterned hard mask 125 in the first region corresponds to the third trench 105-3, the first trench 105-1 and the second trench 105-2. The openings of the patterned hard mask 125 in the second region and the third region correspond to the predetermined areas where trenches will be formed subsequently. Using a patterned hard mask 125 as an etching mask, the same etching process is performed, simultaneously removing a portion of the conductive layer 107 and a portion of the dielectric layer 106 near the top surface in the third trench 105-3, the first trench 105-1, and the second trench 105-2. A third recess 127-3 is formed in the third trench 105-3 on the third field plate 107-3; a first recess 127-1 is formed in the first trench 105-1 on the first field plate 107-1; and a second recess 127-2 is formed in the second trench 105-2 on the second field plate 107-2. Simultaneously, multiple trenches 129 are etched in the second region, and multiple trenches 131 are etched in the third region. (Continue reading...) Figure 13 In step S105, using the same deposition process and chemical mechanical planarization (CMP) process, dielectric material is filled into the third recess 127-3, the first recess 127-1, and the second recess 127-2 in the first region to form the third dielectric isolation portion 108-3, the first dielectric isolation portion 108-1, and the second dielectric isolation portion 108-2, respectively. At the same time, dielectric material is filled into the multiple trenches 129 in the second region and the multiple trenches 131 in the third region to form multiple shallow trench isolation (STI) structures 135 in the second region and multiple shallow trench isolation structures 137 in the third region.

[0134] Then, refer to Figure 14 In step S107, a patterned mask is formed to cover a predetermined area, and an ion implantation process of the first conductivity type is performed in the second region to form a doped region 141, such as a p-type doped region, in the well region 103 of the second conductivity type. Then, the patterned mask covering the predetermined area is removed. Next, a patterned mask is formed to cover another predetermined area, and an ion implantation process of the second conductivity type is performed in the second region to form a doped region 143, such as an n-type doped region, in the well region 103 of the second conductivity type. (Continue reading...) Figure 14In step S109, a patterned hard mask 145 is formed on the first region, the second region, and the third region. The opening of the patterned hard mask 145 in the first region corresponds to the third trench 105-3 and the first trench 105-1. The first dielectric isolation portion 108-1 and a portion of the dielectric layer 106 in the first trench 105-1 of the first region are removed by an etching process to form the first groove 147-1. At the same time, the third dielectric isolation portion 108-3 and a portion of the dielectric layer 106 in the third trench 105-3 are removed to form the second groove 147-2.

[0135] Next, refer to Figure 15 In step S111, a thermal oxidation process is used, and the openings of the patterned hard mask 145 in the second region (such as...) are utilized. Figure 14 As shown, a gate dielectric layer 155 is formed in the second region, and simultaneously, a gate dielectric layer 155 is formed on the well region 103 between the third trench 105-3 and the first trench 105-1 in the first region. Then, all the patterned hard mask 145 is removed, and using an ion implantation process of the first conductivity type, a first substrate region 117-1 and a second substrate region 117-2 (e.g., both p-type substrate regions) are formed in the first region, and simultaneously, a well region 151 of the first conductivity type (e.g., a p-type well region) is formed in the third region. Then, using an ion implantation process of the second conductivity type, a well region 153 of the second conductivity type (e.g., an n-type well region) is formed in the third region. See also... Figure 15 In step S113, a first gate 109-1 is formed in a first groove 147-1 in the first region using a deposition process and a chemical mechanical planarization (CMP) process, and a second gate 109-2 is formed in a second groove 147-2 in the first region. At the same time, a gate 157 is formed in the second region using the same deposition process and another etching process, and a plurality of gates 159 are formed in the third region. The first gate 109-1, the second gate 109-2, the gate 157 and the plurality of gates 159 are all formed by the same conductive material layer, such as a polysilicon layer formed by the same deposition process to form the first gate 109-1, the second gate 109-2, the gate 157 and the plurality of gates 159.

[0136] Then, refer to Figure 16In step S115, using the same second conductivity type ion implantation process, a source region 111S and a drain region 113D are formed in the first region, and a source region 165S and a drain region 165D are formed in the third region. These source regions 111S, 113D, 165S, and 165D are, for example, heavily n-type doped regions. Furthermore, a desired second conductivity type doped region (e.g., a heavily n-type doped region) can also be formed simultaneously in the second region. Using the same first conductivity type ion implantation process, a source region 161S and a drain region 161D are formed in the second region, and a source region 163S and a drain region 163D are formed in the third region. These source regions 161S, 161D, 163S, and 163D are, for example, heavily p-type doped regions. Furthermore, a desired first conductivity type doped region (e.g., a heavily p-type doped region) can also be formed simultaneously in the first region.

[0137] Continue reading Figure 16 In step S117, an interlayer dielectric layer 120 is simultaneously formed on the first, second, and third regions. Using photolithography and etching processes, contact openings are simultaneously formed within the interlayer dielectric layer 120 in the first, second, and third regions. Then, using deposition and chemical mechanical planarization (CMP) processes, a source electrode 111, a gate contact 119, a field plate contact 115, and a drain electrode 113 are simultaneously formed in the first region; a source electrode 171, a gate contact 179, and a drain electrode 173 are formed in the second region; and source electrodes 181 and 191, gate contacts 189 and 199, and drain electrodes 183 and 193 are formed in the third region. Furthermore, other necessary contacts can be simultaneously formed within the interlayer dielectric layer 120 in the first, second, and third regions to simultaneously complete the fabrication of semiconductor components 100, 200, and 300. According to embodiments of the present invention, it is advantageous to use power integrated circuit process integration technology (Bipolar-CMOS-DMOS, BCD) to simultaneously fabricate an integrated circuit structure comprising semiconductor component 100, semiconductor component 200 and semiconductor component 300.

[0138] According to one embodiment of the present invention, in the implementation Figure 12 Prior to the illustrated step S101, a self-aligned doping process may be additionally performed to form a doped region with a second conductivity type below each trench 105-1 to 105-3, thereby forming a structure similar to... Figure 17 , Figure 18 and Figure 19 The structure shown.

[0139] like Figure 17 As shown, Figure 17 The cross-sectional structure 400-3 roughly corresponds to Figure 12The first region 1000 of the cross-sectional structure 400-1, the main difference between the two is that the cross-sectional structure 400-3 further includes a fifth groove 105-5, which is disposed between the first groove 105-1 and the second groove 105-2. In addition, below the first trench 105-1, the second trench 105-2, and the fifth trench 105-5, a first doped region 202a-1, 202a-2, 202a-5 and a second doped region 204a-1, 204a-2, 204a-5 will be formed. The first doped region 202a-1, 202a-2, 202a-5 has a second conductivity type (e.g., n-type), and the second doped region 204a-1, 204a-2, 204a-5 has a first conductivity type (e.g., p-type). The projections of the first doped region 204a-1, 204a-2, 204a-5 in a first direction (e.g., the X-direction) overlap each other, and the projections of the second doped region 204a-1, 204a-2, 204a-5 in the first direction (e.g., the X-direction) overlap each other. According to one embodiment, a first doped region 202a-3, 202a-4 and a second doped region 204a-3, 204a-4 are formed below the third trench 105-3 and the fourth trench 105-4.

[0140] against Figure 17 The cross-sectional structure 400-3 shown is manufactured at a time point such as... Figure 12 The step of filling the conductive layer 107 on the dielectric layer 106 is shown before the process, and the process is illustrated below. First, refer to Figure 17 A fifth trench 105-5 is formed in the well region 102, located between the first trench 105-1 and the second trench 105-2. Subsequently, a self-aligned doping process is performed to form first doped regions 202a-1, 202a-2, 202a-5 and second doped regions 204a-1, 204a-2, 204a-5 below the first trench 105-1, the second trench 105-2, and the fifth trench 105-5. According to one embodiment, the second doped regions 204a-1, 204a-2, 204a-5 can be formed first, followed by the first doped regions 202a-1, 202a-2, 202a-5, but this is not a limitation. Since the doped regions below each trench are formed by performing a self-aligned doping process, the photolithography process can be omitted, effectively reducing process costs.

[0141] like Figure 18 As shown, Figure 18 The cross-sectional structure is similar to 400-4. Figure 17The main difference between the cross-sectional structure 400-3 and the previous one is that the cross-sectional structure 400-4 not only includes the first row 202a formed by the first doped regions 202a-1 to 202a-5, but also includes the third row 202b formed by the first doped regions 202b-1 to 202b-5, or the (2n-1)th row formed by other first doped regions, where n is an integer greater than 2, such as the fifth row (not shown), the seventh row (not shown)... the (2n-1)th row, etc. Furthermore, the cross-sectional structure 400-4 not only includes the second row 204a formed by the second doped regions 204a-1 to 204a-5, but also includes the fourth row 204b formed by the second doped regions 204b-1 to 204b-5, or the 2nth row formed by other second doped regions, where n is an integer greater than 2, such as the sixth row (not shown), the eighth row (not shown)... the 2nth row, etc. According to one embodiment, along the depth direction (Z direction) of each trench, rows 202a and 202b of the first doped regions 202a-1 to 202a-5 and 202b-1 to 202b-5, and rows 204a and 204b of the second doped regions 204a-1 to 204a-5 and 204b-1 to 204b-5 are alternately arranged.

[0142] against Figure 18 The cross-sectional structure 400-4 shown is manufactured at a time when... Figure 12 The step of filling the conductive layer 107 on the dielectric layer 106 is shown before the process includes performing a multi-pass self-aligned doping process to sequentially form the 2nth row, the 2n-1th row... the fourth row 204b, the third row 202b, the second row 204a, and the first row 202a, but the formation order is not limited to this.

[0143] like Figure 19 As shown, Figure 19 The cross-sectional structure is similar to 400-5. Figure 18 The main difference between the two cross-sectional structures is that the third trench 105-3 and the fourth trench 105-4 of the cross-sectional structure 400-5 lack a second doped region below them, and adjacent doped regions in the same rows 202a, 202b, 204a, and 204b are in contact with each other. Regarding... Figure 19 The cross-sectional structure 400-5 shown is manufactured at a time when... Figure 12Before the step of filling the conductive layer 107 on the dielectric layer 106, the process includes, in addition to performing a multi-pass self-aligned doping process to sequentially form rows, at least one thermal treatment process, such that adjacent first doped regions 202a-1, 202a-2, 202a-5, 202b-1, 202b-2, and 202b-5 in the same row are in contact with each other, and adjacent second doped regions 204a-1, 202b-2, and 202b-5 in the same row are in contact with each other, and such that adjacent second doped regions 204a-1, 202b-2, and 202b-5 in the same row are in contact with each other. 4a-2, 204a-5, 204b-1, 204b-2, and 204b-5 are in contact with each other, wherein after the heat treatment process, the first doped regions 202a-1, 202a-2, 202a-5, 202b-1, 202b-2, and 202b-5 and the second doped regions 204a-1, 204a-2, 204a-5, 204b-1, 204b-2, and 204b-5 have the same average doping concentration.

[0144] Figure 20 This is a schematic diagram illustrating the voltage equipotential line distribution of a semiconductor component in the off-state and on-state according to an embodiment of the present invention. Figure 1 The semiconductor component 100 in the embodiment is illustrated by example, such as Figure 20 As shown, when the semiconductor component is in the off state, its voltage equipotential distribution 100-off shows that the voltage can be dispersed on both sides of each trench using the first field plate 107-1 and the second field plate 107-2, resulting in a more uniform voltage drop and avoiding the generation of high-intensity electric fields in local areas. Furthermore, by further increasing the number of trenches and field plates, the breakdown voltage can be further improved. Still as... Figure 20As shown, when the semiconductor component is in the on state, the first gate 109-1 is applied with an on potential (e.g., a positive potential), and the first field plate 107-1 and the second field plate 107-2 are also applied with field plate potentials (e.g., positive potentials). The voltage equipotential distribution 100-on shows a higher voltage (e.g., close to HV) near the drain electrode 113 and a lower voltage (e.g., close to 0V) near the source electrode 111. The current path 110 flows down from the drain electrode 113 along the second side 20 of the second trench 105-2 to below the second trench 105-2, then flows down to below the first trench 105-1, and then flows up along the first side 10 of the first trench 105-1 to the channel region (not shown) and the source electrode 111, thus presenting a U-shaped current path. This allows for a reduction in current path and trench depth (approximately 30% to 50% less than traditional trench depths) without compromising voltage withstand capability, thereby reducing manufacturing complexity and lowering the on-resistance of the semiconductor device. Furthermore, according to embodiments of the present invention, the arrangement of multiple trench field plates reduces the output power capacitance (Coss) of the semiconductor device and increases its breakdown voltage (approximately 100V to 150V). The arrangement of multiple gates reduces the gate-drain charge (Qgd) and gate-drain capacitance (Cgd) of the semiconductor device, thereby improving the switching speed of the semiconductor device and meeting various electrical requirements.

[0145] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A semiconductor component, characterized in that, include: A substrate having a first type of conductivity; A well region having a second conductivity type is disposed on the substrate; A first trench is disposed in the well region, and a first field plate and a first dielectric layer are disposed in the first trench surrounding the first field plate; A second trench is disposed in the well region, and a second field plate and a second dielectric layer are disposed in the second trench surrounding the second field plate; A first gate is disposed above the first field plate; A source electrode is disposed on a first side of the first trench; as well as A drain electrode is disposed on a second side of the second trench, and the source electrode, the first trench, the second trench, and the drain electrode are arranged sequentially along a first direction. When a bias voltage is applied to the first gate, a current is allowed to flow from the drain electrode down along the second side of the second trench to below the second trench, then down to below the first trench, and then up along the first side of the first trench to the source electrode.

2. The semiconductor component as described in claim 1, characterized in that, The first gate is disposed in the first trench and is separated from the first field plate by a first dielectric isolation portion, which is disposed on the first field plate.

3. The semiconductor component as described in claim 1, characterized in that, Also includes: A third trench is disposed in the well region, and a third field plate and a third dielectric layer are disposed in the third trench surrounding the third field plate; as well as A second gate is disposed in the third trench and separated from the third field plate by a third dielectric isolation portion, the third dielectric isolation portion being disposed on the third field plate, and the source electrode being disposed between the first trench and the third trench.

4. The semiconductor component as described in claim 3, characterized in that, The third trench, the source electrode, the first trench, the second trench, and the drain electrode are arranged sequentially along the first direction.

5. The semiconductor component as claimed in claim 1, characterized in that, It also includes a first substrate region having the first conductivity type, disposed on the first side of the first trench, wherein the bottom surface of the first substrate region is higher than the top surface of the first field plate.

6. The semiconductor component as claimed in claim 1, characterized in that, It also includes a second substrate region having the first conductivity type, disposed between the first trench and the second trench, wherein the bottom surface of the second substrate region is higher than the top surface of the first field plate.

7. The semiconductor component as claimed in claim 1, characterized in that, It also includes a fourth trench disposed in the well region, wherein a fourth field plate and a fourth dielectric layer are disposed in the fourth trench and surround the fourth field plate, and the drain electrode is disposed between the fourth trench and the second trench. The source electrode, the first trench, the second trench, the drain electrode and the fourth trench are arranged sequentially along the first direction.

8. The semiconductor component as claimed in claim 7, characterized in that, The top surface of the fourth field plate is higher than the top surface of the first field plate, or at the same horizontal level as the top surface of the first field plate.

9. The semiconductor component as claimed in claim 1, characterized in that, The potential of the first field plate is the same as the potential of the first gate or the source electrode.

10. The semiconductor component as claimed in claim 1, characterized in that, The first gate and the first field plate are interconnected and are each composed of different regions of the same conductive layer within the first trench.

11. The semiconductor component as claimed in claim 10, characterized in that, It also includes a first substrate region and a second substrate region having the first conductivity type, disposed in the well region along two opposite sides of the first trench, and extending downward from the top surface height of the first trench to 3% to 60% of the depth of the first trench.

12. The semiconductor component as claimed in claim 1, characterized in that, Also includes: A gate connection portion extends from a sidewall of the first gate along the first direction, protruding beyond the sidewall of the first gate, and is disposed on the well region; and A substrate region having the first conductivity type is disposed below the gate connection portion.

13. The semiconductor component as claimed in claim 12, characterized in that, Also includes: A third trench is disposed in the well region. A third field plate, a third dielectric layer surrounding the third field plate, and a third dielectric isolation portion covering the third field plate are disposed in the third trench. A second gate is disposed on the top surface of the third dielectric isolation portion and located on the well region; and A source region is located between the first trench, the third trench, and the gate connection portion, with the first trench and the gate connection portion respectively adjacent to each other on both sides of the source region. The gate connection portion is disposed between the first gate and the second gate, and the substrate region extends below the source region.

14. The semiconductor component as claimed in claim 13, characterized in that, The first gate and the second gate extend along a second direction, the first direction having a non-zero angle with the second direction.

15. The semiconductor component as claimed in claim 12, characterized in that, It also includes a first dielectric isolation portion disposed in the first trench and covering the first field plate, wherein the first gate is disposed on the top surface of the first dielectric isolation portion and located on the well region.

16. The semiconductor component as claimed in claim 1, characterized in that, It also includes an epitaxial layer having the first conductivity type disposed on the substrate, wherein the well region is disposed in the epitaxial layer.

17. The semiconductor component as claimed in claim 1, characterized in that, It also includes a buried layer having the second conductivity type disposed below the well region, and the first trench and the second trench extend into the buried layer.

18. The semiconductor component as claimed in claim 1, characterized in that, Also includes: A fifth trench is disposed in the well region and between the first trench and the second trench; Multiple first doped regions are respectively disposed below the first trench, the second trench and the fifth trench, and the first doped regions have the second conductivity type; as well as Multiple second doped regions are respectively disposed below the first doped region, and the second doped regions have the first conductivity type. Wherein, along the depth direction of each trench, the projection of the first doped region partially overlaps with the projections of the first trench, the second trench, and the fifth trench, respectively. Wherein, along the depth direction of each trench, the projection of the second doped region partially overlaps with the projections of the first trench, the second trench, and the fifth trench, respectively. When the first gate is subjected to the on-bias voltage, the current flows through the first doped region.

19. The semiconductor component as claimed in claim 18, characterized in that, The first doped regions are arranged in a first row and a third row, and the second doped regions are arranged in a second row and a fourth row. Along the depth direction of each trench, the rows of the first doped regions and the rows of the second doped regions are alternately arranged. The first doped regions arranged in the same row have substantially similar depths, and the second doped regions arranged in the same row have substantially similar depths.

20. The semiconductor component as claimed in claim 19, characterized in that, The ratio between the average doping concentration of the first doped region and the average doping concentration of the second doped region is between 0.1 and 10. Along the depth direction of each trench, adjacent first doped regions and second doped regions are in contact with each other.

21. The semiconductor component as claimed in claim 18, characterized in that, The second doped region disposed below the first trench and the second trench has a first average width, and the second doped region disposed below the fifth trench has a second average width, wherein the first average width is smaller than the second average width.

22. The semiconductor component as claimed in claim 1, characterized in that, Also includes: A fifth trench is disposed in the well region and between the first trench and the second trench; A first doped region is disposed below the fifth trench, and the first doped region has the second conductivity type; as well as A second doped region is disposed below the first doped region, and the second doped region has the first conductivity type. Wherein, along the depth direction of the fifth trench, the projections of the fifth trench, the first doped region, and the second doped region partially overlap each other. When the first gate is subjected to the on-bias voltage, the current flows through the first doped region.

23. The semiconductor component as claimed in claim 22, characterized in that, Also includes: A first starting region is located below the first trench; as well as A second starting area is located below the second trench. Wherein, the overall conductivity type of the first starting region and the second starting region is the second conductivity type.

24. The semiconductor component as claimed in claim 22, characterized in that, Also includes: Another first doped region is disposed below the second doped region, the other first doped region having the second conductivity type; as well as A second doped region is disposed below the first doped region, and the second doped region has the first conductivity type. Wherein, along the depth direction of the fifth trench, the projections of the fifth trench, the first doped region, the second doped region, the other first doped region, and the other second doped region partially overlap with each other. When the first gate is subjected to the on-bias voltage, the current flows through the first doped region and the other first doped region.

25. A method for manufacturing a semiconductor component as described in any one of claims 1 to 24, characterized in that, include: A substrate is provided having a first conductivity type; A well region is formed on the substrate, the well region having a second conductivity type; A first trench and a second trench are formed in the well region; A dielectric layer is deposited in the first trench and the second trench in a directional manner, and a conductive layer is filled on the dielectric layer; The conductive layers in the first trench and the second trench are etched to form a first recess on a first field plate and a second recess on a second field plate, respectively. A dielectric material is filled into the first recess and the second recess to form a first dielectric isolation portion and a second dielectric isolation portion, respectively. Etch the dielectric layer and the first dielectric isolation portion within the first trench to form a first groove; A first gate is formed within the first groove; as well as A source region and a drain region are formed in the well region, wherein the source region is located on a first side of the first trench and the drain region is located on a second side of the second trench.

26. The method for manufacturing a semiconductor component as described in claim 25, characterized in that, Also includes: A third trench and a fourth trench are formed in the well region, wherein the third trench, the first trench, the second trench and the fourth trench are arranged sequentially along a first direction.

27. The method for manufacturing a semiconductor component as described in claim 26, characterized in that, Also includes: The dielectric layer is deposited in the third trench and the fourth trench and the conductive layer is filled on the dielectric layer, wherein the conductive layer in the fourth trench constitutes a fourth field plate; The conductive layer within the third trench is etched to form a third recess located on a third field plate; The dielectric material is filled into the third recess to form a third dielectric isolation portion; Etching the third dielectric isolation portion and the dielectric layer to form a second groove; and A second gate is formed within the second groove.

28. The method for manufacturing a semiconductor component as described in claim 25, characterized in that, It also includes forming a first substrate region and a second substrate region on opposite sides of the first trench in the well region.

29. The method for manufacturing a semiconductor component as described in claim 25, characterized in that, A power integrated circuit process is used to integrate a laterally diffused metal-oxide-semiconductor (MOS) component and a complementary metal-oxide-semiconductor (CMOS) component on the substrate.

30. The method for manufacturing a semiconductor component as described in claim 26, characterized in that, Before filling the conductive layer onto the dielectric layer, the method further includes: A fifth trench is formed in the well region, located between the first trench and the second trench; A self-aligned doping process is performed to form a plurality of first doped regions and a plurality of second doped regions beneath the first trench, the second trench, and the fifth trench. The first doped regions have the second conductivity type, and the second doped regions have the first conductivity type. Wherein, the first doped regions overlap each other in the first direction, and the second doped regions overlap each other in the first direction.

31. The method for manufacturing a semiconductor component as described in claim 30, characterized in that, The first doped regions are arranged in a first row and a second row, and the second doped regions are arranged in a second row and a fourth row. Along the depth direction of each trench, the rows of the first doped regions and the rows of the second doped regions are alternately arranged.

32. The method for manufacturing a semiconductor component as described in claim 31, characterized in that, Adjacent first doped regions and second doped regions are in contact with each other along the depth direction of each trench.

33. The method for manufacturing a semiconductor component as described in claim 31, characterized in that, Also includes: At least one heat treatment process is performed such that adjacent first doped regions in each row are in contact with each other, and adjacent second doped regions in each row are in contact with each other. After implementing the at least one heat treatment process, the first doped region and the second doped region have the same average doping concentration.

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