Railway vehicle hydraulic oil pump direct current motor drive control circuit and control method

Abstract

The application discloses a kind of track vehicle hydraulic oil pump DC motor drive control circuit and control method, the circuit includes field effect tube Q1, triode Q2, resistance R1, resistance R2, resistance R3, and not gate UA, comparator A, comparator B, diode D1, diode D2, EBCU, photoelectric isolation one, photoelectric isolation two, sawtooth wave generating circuit, start control configuration circuit, reference voltage source, overheat detection circuit, overvoltage and undervoltage detection circuit, current detection circuit, MOS drive chip, amplification circuit and motor M.The application adopts two different mechanism protection mechanism, can more reliably realize overcurrent protection, and through a variety of fault indication, can accurately and effectively diagnose the fault of motor, and the circuit is applied to urban rail transit vehicle hydraulic braking system, can obviously improve the reliability and safety of hydraulic oil pump motor control.

Description

Technical Field

[0001] This invention relates to the field of hydraulic braking control for rail vehicles, and more specifically, to a DC motor drive control circuit and control method for a hydraulic oil pump in rail vehicles. Background Technology

[0002] Hydraulic systems in rail vehicles typically use hydraulic pumps for power, which require a driving method. One common driving method is DC motor drive. The working principle of a DC motor-driven hydraulic pump is as follows: The DC motor receives electrical energy from a power source, generating a magnetic field inside the rotor, causing the motor to rotate. The motor shaft is connected to the hydraulic pump shaft; when the motor rotates, the hydraulic pump rotor also rotates. The rotor movement of the hydraulic pump causes the hydraulic oil to flow, thereby supplying power to the rail vehicle's hydraulic system.

[0003] Currently, the hydraulic pump motor control for hydraulic braking in rail vehicles mostly uses direct drive via power switches. This can easily cause voltage fluctuations in the vehicle's battery during startup, affecting the operation of other equipment. Large starting currents can also damage motor insulation and reduce motor lifespan. Short circuits caused by short circuits in the DC motor wiring of the hydraulic pump or by damage to the internal insulation are common overcurrent faults, requiring accurate and timely monitoring of overcurrent. Therefore, designing a circuit that is easy to configure with soft-start functionality and also has overcurrent and overheat protection functions is extremely important.

[0004] There are currently no effective solutions to the problems in the relevant technologies. Summary of the Invention

[0005] To address the problems in related technologies, this invention proposes a DC motor drive control circuit and control method for a hydraulic oil pump in a rail vehicle, thereby overcoming the aforementioned technical problems in existing related technologies.

[0006] Therefore, the specific technical solution adopted by the present invention is as follows: According to one aspect of the present invention, a DC motor drive control circuit for a hydraulic oil pump of a rail vehicle is provided. The circuit includes a field-effect transistor Q1, a transistor Q2, resistors R1, R2, and R3, a NAND gate UA, a comparator A, a comparator B, a diode D1, a diode D2, an EBCU, an opto-isolation device I, an opto-isolation device II, a sawtooth wave generation circuit, a start-up control configuration circuit, a reference voltage source, an overheat detection circuit, an over / undervoltage detection circuit, a current detection circuit, a MOS driver chip, an amplifier circuit, and a motor M. The output of EBCU is connected to the input of the startup control configuration circuit through opto-isolation 1. The output of the startup control configuration circuit is connected to the inverting input of comparator B and the positive terminal of diode D1. The negative terminal of diode D1 is connected to the output of comparator A. The non-inverting input of comparator A is connected to the reference voltage source. The inverting input of comparator A is connected to the output of the amplifier circuit. The input of the amplifier circuit is connected to one end of resistor R1 and the source of field-effect transistor Q1. The gate of field-effect transistor Q1 is connected to one end of resistor R2. The other end of resistor R2 is connected to the OUT terminal of the MOS driver chip. The CS terminal of the MOS driver chip is connected to the current detection circuit. The ERR terminal of the MOS driver chip is connected to opto-isolation 2 and the first pin of NAND gate UA. The input of the MOS driver chip is connected to the output of comparator B and the collector of transistor Q2. The non-inverting input of comparator B is connected to the sawtooth wave generation circuit. The drain of the field-effect transistor Q1 is connected to the input terminal of the current detection circuit, the positive terminal of the diode D2, and one end of the motor M. The other end of the motor M is connected to the negative terminal of the diode D2 and the input terminal of the over / under voltage detection circuit and connected to 24V. The output terminal of the over / under voltage detection circuit is connected to the second pin of the NAND gate UA and the opto-isolated diode. The third pin of the NAND gate UA is connected to the overheat detection circuit. The overheat detection circuit is connected to the input terminal of the EBCU through the opto-isolated diode. The output terminal of the NAND gate UA is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the base of the transistor Q2. The emitter of the transistor Q2 is grounded.

[0007] Furthermore, the sawtooth wave generating circuit generates a waveform with a frequency of 15kHz, a peak value of 4.3V, and a trough value of 0.7V.

[0008] Furthermore, the startup control configuration circuit includes a square wave generator UE, a dual D flip-flop UD, a NAND gate UB, a transistor Q3, a transistor Q4, an inverter UC, resistors R5, R6, R7, R8, R9, and R10, a diode D3, a capacitor C1, and a capacitor C2. The output terminal of opto-isolation 1 is connected to the DO terminal of the dual D flip-flop and the base of transistor Q4. The emitter of transistor Q4 is connected to one end of capacitor C1 and connected to power supply Vcc. The other end of capacitor C1 is connected to one end of resistor R7 and the input terminal of inverter UC. The other end of resistor R7 is connected to the collector of transistor Q4 and one end of resistor R8. The other end of R8 is grounded. The output of inverter UC is connected to one end of resistor R9. The other end of resistor R9 is connected to the positive terminal of diode D3, resistor R10, resistor R6 and one end of capacitor C2 respectively. The negative terminal of diode D3 is connected to power supply Vcc1. The other end of capacitor C2 is connected to the other end of resistor R10 and grounded. The other end of resistor R6 is connected to the collector of transistor Q3. The emitter of transistor Q3 is connected to power supply Vcc. The base of transistor Q3 is connected to one end of resistor R5. The other end of resistor R5 is connected to the output of NAND gate UB. The input of NAND gate UB is connected to the Q0, Q1, and D1 terminals of the dual D flip-flop. The CP terminal of the dual D flip-flop is connected to the square wave generator UE. The terminal of the dual D flip-flop is connected to one end of resistor R4. The other end of resistor R4 is connected to power supply Vcc.

[0009] Furthermore, the square wave generated by the square wave generator UE is a 15.625kHz square wave.

[0010] Furthermore, the power supply Vcc is 12V, and the power supply Vcc1 is 5V.

[0011] Furthermore, D0 represents the first input terminal of the dual D flip-flop; D1 represents the second input terminal of the dual D flip-flop; Q0 represents the first positive output terminal of the dual D flip-flop; CP represents the clock pulse input terminal of the dual D flip-flop; represents the reset terminal; and represents the second inverted output terminal of the dual D flip-flop.

[0012] According to another aspect of the present invention, a DC motor drive control method for a hydraulic oil pump of a rail vehicle is also provided, the method comprising the following steps: S1. The start signal A is output through EBCU, enters the start control configuration circuit after passing through opto-isolation, and generates voltage Vb; S2. Compare the voltage Vb with the sawtooth wave voltage generated by the sawtooth wave generation circuit through comparator A to generate a PWM drive signal; S3 and PWM drive signals pass through the MOS driver chip and control the on / off state of the field-effect transistor Q1 to achieve drive control of motor M.

[0013] Furthermore, the start signal output by the EBCU, after passing through an opto-isolation circuit, enters the start control configuration circuit and generates voltage Vb, including the following steps: S11. If the start signal A is a switch control signal, the switch control signal establishes the Vb voltage through channel I. S12. If the start signal A is a frequency signal, then the frequency signal establishes the Vb voltage through channel II.

[0014] Furthermore, the voltage Vb is compared with the sawtooth wave voltage generated by the sawtooth wave generation circuit through comparator A to generate a PWM drive signal, including the following steps: S21. If the voltage Vb is greater than the sawtooth wave voltage, it indicates that the output of the PWM drive signal is high. S22. If the voltage Vb is less than the sawtooth wave voltage, it indicates that the output of the PWM drive signal is low.

[0015] Furthermore, the frequency signal is 100Hz-2kHz.

[0016] The beneficial effects of this invention are as follows: 1. This invention provides a DC motor drive control circuit for a hydraulic oil pump in a rail vehicle, which solves the problems of voltage fluctuations in the vehicle battery and reduced lifespan caused by frequent starts when the hydraulic brake oil pump motor starts. The soft start circuit is simple, reliable and low in cost.

[0017] 2. This invention achieves soft-start speed control of DC motors and different duty cycles and equivalent voltages of drive motors after startup by controlling signals of different specifications, in order to adapt to pump DC motor loads with different power and starting characteristics. Furthermore, through two overcurrent protection mechanisms with different mechanisms, it achieves accurate monitoring and timely protection of overcurrent conditions, identifies various fault conditions and shuts off the output of the power switch in a timely manner, and sends the relevant fault status to the electronic brake control unit, which facilitates the electronic brake control unit to carry out fault diagnosis.

[0018] 3. This invention uses different types of control signals to flexibly control the soft-start speed and the drive waveform after startup, making it suitable for different DC motor loads. It features simple circuit design and flexible use. By employing two different protection mechanisms, it can more reliably achieve overcurrent protection. Furthermore, through multiple fault indications, it can accurately and effectively diagnose motor faults. Applying this circuit to the hydraulic braking system of urban rail transit vehicles can significantly improve the reliability and safety of hydraulic oil pump motor control. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a circuit diagram of a DC motor drive control circuit for a hydraulic oil pump in a rail vehicle according to an embodiment of the present invention. Figure 2 This is a circuit diagram of the start-up control configuration circuit in a DC motor drive control circuit for a hydraulic oil pump of a rail vehicle according to an embodiment of the present invention. Figure 3 This is a flowchart of a DC motor drive control method for a hydraulic oil pump in a rail vehicle according to an embodiment of the present invention. Detailed Implementation

[0021] To further illustrate the various embodiments, the present invention provides accompanying drawings, which are part of the disclosure of the present invention. These drawings are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementation methods and the advantages of the present invention.

[0022] According to an embodiment of the present invention, a DC motor drive control circuit and control method for a hydraulic oil pump of a rail vehicle are provided.

[0023] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figure 1 As shown, the DC motor drive control circuit for the hydraulic oil pump of a rail vehicle according to an embodiment of the present invention includes a field-effect transistor Q1, a transistor Q2, resistors R1, R2, and R3, a NAND gate UA, a comparator A, a comparator B, a diode D1, a diode D2, an EBCU, an opto-isolation circuit I, an opto-isolation circuit II, a sawtooth wave generation circuit, a start-up control configuration circuit, a reference voltage source, an overheat detection circuit, an over / under voltage detection circuit, a current detection circuit, a MOS driver chip, an amplifier circuit, and a motor M.

[0024] The output of EBCU is connected to the input of the startup control configuration circuit via opto-isolation 1. The output of the startup control configuration circuit is connected to the inverting input of comparator B and the positive terminal of diode D1. The negative terminal of diode D1 is connected to the output of comparator A. The non-inverting input of comparator A is connected to the reference voltage source. The inverting input of comparator A is connected to the output of the amplifier circuit. The input of the amplifier circuit is connected to one end of resistor R1 and the source of field-effect transistor Q1. The gate of field-effect transistor Q1 is connected to one end of resistor R2. The other end of resistor R2 is connected to the OUT terminal of the MOS driver chip. The CS terminal of the MOS driver chip is connected to the current detection circuit. The ERR terminal of the MOS driver chip is connected to opto-isolation 2 and the first pin of NAND gate UA. The input of the MOS driver chip is connected to the output of comparator B and the collector of transistor Q2. The non-inverting input of comparator B is connected to the sawtooth wave generation circuit.

[0025] The drain of the field-effect transistor Q1 is connected to the input terminal of the current detection circuit, the positive terminal of the diode D2, and one end of the motor M. The other end of the motor M is connected to the negative terminal of the diode D2 and the input terminal of the over / under voltage detection circuit and connected to 24V. The output terminal of the over / under voltage detection circuit is connected to the second pin of the NAND gate UA and the opto-isolated diode. The third pin of the NAND gate UA is connected to the overheat detection circuit. The overheat detection circuit is connected to the input terminal of the EBCU through the opto-isolated diode. The output terminal of the NAND gate UA is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the base of the transistor Q2. The emitter of the transistor Q2 is grounded.

[0026] Specifically, the EBCU (Electronic Brake Control Unit) is an important component in modern automobiles used to control the braking system. It adjusts the distribution of braking force based on information such as vehicle speed and brake pressure to improve braking performance and stability.

[0027] Specifically, resistor R1 is a sampling resistor. The sampled voltage is amplified and compared with the reference voltage source Vc. If it is higher than Vc, a low level is output, pulling the Vb voltage down to VD1 (VD1≤0.7V). VD1 is always at a low level after being compared with the sawtooth wave generation circuit, thereby turning off the drive signal and realizing overcurrent monitoring and protection.

[0028] Specifically, the CS terminal of the MOS driver chip can monitor the on-state voltage of the field-effect transistor Q1 (N-channel enhancement-mode field-effect transistor) through the start-up control configuration circuit. When an overcurrent occurs, the VDS of the field-effect transistor Q1 increases, and after voltage division, it exceeds the detection threshold of the CS terminal of the MOS driver chip, thus identifying an overcurrent. The MOS driver chip will then shut down the output, achieving the overcurrent protection function. Simultaneously, the ERR terminal of the MOS driver chip quickly goes high, turning on the transistor Q2 and cutting off the control signal. Here, the OUT terminal of the MOS driver chip is the output terminal, the CS terminal is the current detection terminal, and the ERR terminal is the overcurrent fault output terminal.

[0029] Specifically, the overheat detection circuit can achieve overheat protection. When the overheat detection circuit detects that the temperature is too high, it outputs a high level, turns on the transistor Q2, and cuts off the control signal.

[0030] Specifically, the over / under voltage detection circuit implements over / under voltage protection. When the supply voltage exceeds the normal voltage range, the current detection circuit outputs a high level, the transistor Q2 is turned on, and the control signal is cut off.

[0031] Specifically, the overheat detection circuit, over / under voltage detection circuit, and current detection circuit not only cut off the control signal but also output relevant fault signals, which are transmitted to the EBCU after passing through an opto-isolation device, facilitating fault diagnosis and maintenance by the EBCU.

[0032] The sawtooth wave generating circuit generates a waveform with a frequency of 15kHz, a peak value of 4.3V, and a trough value of 0.7V.

[0033] like Figure 2 As shown, the startup control configuration circuit includes a square wave generator UE, a dual D flip-flop UD, a NAND gate UB, a transistor Q3, a transistor Q4, an inverter UC, resistors R5, R6, R7, R8, R9, and R10, a diode D3, a capacitor C1, and a capacitor C2.

[0034] Specifically, transistor Q3 is a PNP transistor; resistor R5 is the base resistor; resistors R6 and R8 are both collector resistors; transistor Q4 is a PNP transistor; resistor R7 is the discharge resistor; and resistors R9 and R10 are both voltage divider resistors.

[0035] The output terminal of the opto-isolation unit is connected to the DO terminal of the dual D flip-flop and the base of transistor Q4. The emitter of transistor Q4 is connected to one end of capacitor C1 and connected to power supply Vcc. The other end of capacitor C1 is connected to one end of resistor R7 and the input terminal of inverter UC. The other end of resistor R7 is connected to the collector of transistor Q4 and one end of resistor R8. The other end of R8 is grounded.

[0036] The output of inverter UC is connected to one end of resistor R9. The other end of resistor R9 is connected to the positive terminal of diode D3, resistor R10, resistor R6 and one end of capacitor C2 respectively. The negative terminal of diode D3 is connected to power supply Vcc1. The other end of capacitor C2 is connected to the other end of resistor R10 and grounded.

[0037] The other end of resistor R6 is connected to the collector of transistor Q3. The emitter of transistor Q3 is connected to power supply Vcc. The base of transistor Q3 is connected to one end of resistor R5. The other end of resistor R5 is connected to the output of NAND gate UB. The input of NAND gate UB is connected to the Q0, Q1, and D1 terminals of the dual D flip-flop. The CP terminal of the dual D flip-flop is connected to the square wave generator UE. The terminal of the dual D flip-flop is connected to one end of resistor R4. The other end of resistor R4 is connected to power supply Vcc.

[0038] The square wave generated by the square wave generator UE is a 15.625kHz square wave.

[0039] Among them, the power supply Vcc is 12V and the power supply Vcc1 is 5V.

[0040] Wherein, D0 represents the first input terminal of the dual D flip-flop; D1 represents the second input terminal of the dual D flip-flop; Q0 represents the first positive output terminal of the dual D flip-flop; CP represents the clock pulse input terminal of the dual D flip-flop; terminal 1 represents the reset terminal; terminal 2 represents the second inverted output terminal of the dual D flip-flop; and terminal 3 represents the first inverted output terminal of the dual D flip-flop.

[0041] like Figure 3 As shown, according to another embodiment of the present invention, a DC motor drive control method for a hydraulic oil pump of a rail vehicle is also provided, the method comprising the following steps: S1. The start signal A is output through EBCU, enters the start control configuration circuit after being isolated by opto-isolation, and generates voltage Vb.

[0042] The process of outputting a start signal via the EBCU, passing through an opto-isolated circuit, and then entering the start control configuration circuit to generate voltage Vb includes the following steps: S11. If the start signal A is a switch control signal, then the switch control signal establishes the Vb voltage through channel I.

[0043] Specifically, such as Figure 2 As shown, when the start signal A is a switching control signal, the signal is mainly established by channel I to establish the Vb voltage. When the switching quantity is high (greater than or equal to Vcc), transistor Q4 is cut off, Vcc charges capacitor C1, and after capacitor C1 is fully charged, the voltage at Va is 0, inverter Uc outputs a high level, and charges capacitor C2 through resistor R9. After capacitor C2 is fully charged, a stable voltage Vb is generated. When the start signal A is a switching quantity, after the operation of the dual D flip-flop UD, only during the first f0 cycle (64us) when the switching quantity changes from low to high, the NAND gate UB outputs a low level, transistor Q3 is turned on, and Vcc charges capacitor C2 through resistor R6; in other cases, the NAND gate UB outputs a high level, transistor Q3 is cut off, and capacitor C2 is not charged. Because the charging time is extremely short, channel II has almost no effect on the Vb voltage waveform. Where Vcc=12V, Vcc1=5V, then Vb is a voltage waveform that slowly rises to 5.7V.

[0044] S12. If the start signal A is a frequency signal, then the frequency signal establishes the Vb voltage through channel II.

[0045] The frequency signal is 100Hz-2kHz.

[0046] Specifically, when the start signal A is a frequency signal (100Hz-2kHz), the signal is mainly established by channel II to establish the Vb voltage. For channel I, when the input is low, transistor Q4 is turned on, and capacitor C1 discharges through resistor R7; when the input becomes high, transistor Q4 is turned off, and Vcc charges capacitor C1 through resistors R7 and R8. Since resistor R8 is designed to be 100 ohms greater than resistor R7 (more than 1000 times), capacitor C1 charges slowly but discharges very quickly. The voltage across capacitor C1 hardly changes, meaning Va is approximately equal to Vcc. Therefore, for the frequency input signal UC, the output remains low, and channel I has no effect on the Vb voltage.

[0047] Specifically, for channel II, the control signal f A Taking a frequency of 1kHz as an example, after timing operations by the dual D flip-flop UD, the NAND gate UB outputs a 1kHz frequency signal, where the low-level duration is 1 / f0 and the high-level duration is 1 / f. A-1 / f0. When the NAND gate UB outputs a low level, transistor Q3 is turned on, and Vcc charges capacitor C2 through resistor R6. When the NAND gate UB outputs a high level, transistor Q3 is turned off, and capacitor C2 discharges through resistors R9 and R10. By properly designing the parameters of capacitor C2, resistors R6, R9, and R10, the Vb voltage can rise slowly and eventually reach dynamic equilibrium. Different frequency control signals have different charging and discharging times within their single cycle, thus enabling different waveforms of the VB point voltage and different voltages after dynamic equilibrium.

[0048] S2. The voltage Vb is compared with the sawtooth wave voltage generated by the sawtooth wave generation circuit through comparator A to generate a PWM drive signal.

[0049] The process of comparing the voltage Vb with the sawtooth wave voltage generated by the sawtooth wave generation circuit through comparator A to generate a PWM drive signal includes the following steps: S21. If the voltage Vb is greater than the sawtooth wave voltage, it indicates that the output of the PWM drive signal is high. S22. If the voltage Vb is less than the sawtooth wave voltage, it indicates that the output of the PWM drive signal is low.

[0050] S3 and PWM drive signals pass through the MOS driver chip and control the on / off state of the field-effect transistor Q1 to achieve drive control of motor M.

[0051] Furthermore, this invention provides a DC motor drive control circuit for a hydraulic oil pump in a rail vehicle. This circuit can achieve a fixed soft-start control function or an adjustable soft-start function under the action of different types of input signals. When receiving a continuous high-level switching signal from the electronic brake control unit (EBCU), the power switch is intermittently turned on during the soft-start process, and the on-time gradually increases. After the start-up is completed, the power switch is continuously turned on, and the DC24V directly drives the motor. When receiving a PWM signal of a certain frequency, the power switch is intermittently turned on, and the on-time gradually increases. Different control frequencies can control the speed of soft start-up. Different control frequencies can also result in different duty cycles and equivalent voltages of the drive motor after the start-up is completed, in order to adapt to pump DC motor loads with different power and start-up characteristics.

[0052] Two different overcurrent protection circuits were designed. One circuit uses a current detection circuit configured with a MOS driver chip. When an overcurrent occurs, the voltage drop of the N-channel enhancement-mode MOSFET Q1 in the power switch increases, and the MOS driver chip's current detection circuit identifies this and shuts off the output. The other circuit uses a sampling circuit. When the current exceeds a certain threshold, it directly intervenes in the motor start signal, shutting off the output and achieving overcurrent protection for the oil pump motor. These two different overcurrent protection mechanisms are employed to achieve accurate monitoring and timely protection against overcurrent conditions.

[0053] At the same time, it identifies fault conditions such as overcurrent, overvoltage, undervoltage, and overheating, promptly shuts off the output of the power switch, and sends the relevant fault status to the electronic brake control unit via hard-wired signals, so that the electronic brake control unit can carry out fault diagnosis and other tasks.

[0054] In summary, by means of the above-mentioned technical solution of the present invention, the present invention provides a DC motor drive control circuit for a hydraulic oil pump of a rail vehicle, which solves the problems of voltage fluctuation of vehicle battery and reduced lifespan caused by frequent starts when the hydraulic brake oil pump motor starts. The soft start circuit is simple, reliable and low cost.

[0055] This invention controls the soft-start speed of a DC motor and the duty cycle and equivalent voltage of the drive motor after startup by controlling signals of different specifications. This adapts to pump DC motor loads with different power and startup characteristics. Furthermore, through two overcurrent protection mechanisms with different mechanisms, it achieves accurate monitoring and timely protection against overcurrent conditions. It identifies various fault conditions and shuts off the output of the power switch in a timely manner, and sends the relevant fault status to the electronic brake control unit to facilitate fault diagnosis by the electronic brake control unit.

[0056] This invention flexibly controls the soft-start speed and the drive waveform after startup by using different types of control signals to adapt to different DC motor loads. It features simple circuit design and flexible use. By employing two protection mechanisms with different mechanisms, it can more reliably achieve overcurrent protection. Furthermore, through multiple fault indications, it can accurately and effectively diagnose motor faults. Applying this circuit to the hydraulic braking system of urban rail transit vehicles can significantly improve the reliability and safety of hydraulic oil pump motor control.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A DC motor drive control circuit for a hydraulic oil pump in a rail vehicle, characterized in that, The circuit includes a field-effect transistor Q1, a transistor Q2, resistors R1, R2, and R3, a NAND gate UA, comparator A, comparator B, diodes D1 and D2, an EBCU, opto-isolation circuit 1, opto-isolation circuit 2, a sawtooth wave generation circuit, a start-up control configuration circuit, a reference voltage source, an overheat detection circuit, an over / under voltage detection circuit, a current detection circuit, a MOS driver chip, an amplifier circuit, and a motor M. The output terminal of the EBCU is connected to the input terminal of the startup control configuration circuit through the opto-isolation device. The output terminal of the startup control configuration circuit is connected to the inverting input terminal of the comparator B and the positive terminal of the diode D1. The negative terminal of the diode D1 is connected to the output terminal of the comparator A. The non-inverting input terminal of the comparator A is connected to the reference voltage source. The inverting input terminal of the comparator A is connected to the output terminal of the amplifier circuit. The input terminal of the amplifier circuit is connected to one end of the resistor R1 and the source of the field-effect transistor Q1. The gate of the field-effect transistor Q1 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the OUT terminal of the MOS driver chip. The CS terminal of the MOS driver chip is connected to the current detection circuit. The ERR terminal of the MOS driver chip is connected to the opto-isolation device and the first pin of the NAND gate UA. The input terminal of the MOS driver chip is connected to the output terminal of the comparator B and the collector of the transistor Q2. The non-inverting input terminal of the comparator B is connected to the sawtooth wave generation circuit. The drain of the field-effect transistor Q1 is connected to the input terminal of the current detection circuit, the positive terminal of the diode D2, and one end of the motor M. The other end of the motor M is connected to the negative terminal of the diode D2 and the input terminal of the over / under voltage detection circuit and is connected to 24V. The output terminal of the over / under voltage detection circuit is connected to the second pin of the NAND gate UA and the opto-isolated gate UA. The third pin of the NAND gate UA is connected to the overheat detection circuit. The overheat detection circuit is connected to the input terminal of the EBCU through the opto-isolated gate UA. The output terminal of the NAND gate UA is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the base of the transistor Q2. The emitter of the transistor Q2 is grounded. The startup control configuration circuit includes a square wave generator UE, a dual D flip-flop UD, a NAND gate UB, a transistor Q3, a transistor Q4, an inverter UC, resistors R5, R6, R7, R8, R9, and R10, a diode D3, a capacitor C1, and a capacitor C2. The output terminal of the opto-isolation device is connected to the D0 terminal of the dual D flip-flop and the base of the transistor Q4. The emitter of the transistor Q4 is connected to one end of the capacitor C1 and connected to the power supply Vcc. The other end of the capacitor C1 is connected to one end of the resistor R7 and the input terminal of the inverter UC. The other end of the resistor R7 is connected to the collector of the transistor Q4 and one end of the resistor R8. The other end of the resistor R8 is grounded. The output terminal of the inverter UC is connected to one end of the resistor R9. The other end of the resistor R9 is connected to the positive terminal of the diode D3, the resistor R10, the resistor R6 and one end of the capacitor C2. The negative terminal of the diode D3 is connected to the power supply Vcc1. The other end of the capacitor C2 is connected to the other end of the resistor R10 and grounded. The other end of resistor R6 is connected to the collector of transistor Q3. The emitter of transistor Q3 is connected to power supply Vcc. The base of transistor Q3 is connected to one end of resistor R5. The other end of resistor R5 is connected to the output of NAND gate UB. The input of NAND gate UB is connected to the Q0 terminal of the dual D flip-flop. The CP terminal of the dual D flip-flop is connected to the D1 terminal, and the CP terminal of the dual D flip-flop is connected to the square wave generator UE. One end is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the power supply Vcc.

2. The DC motor drive control circuit for a hydraulic oil pump in a rail vehicle according to claim 1, characterized in that, The sawtooth wave generating circuit generates a waveform with a frequency of 15kHz, a peak value of 4.3V, and a trough value of 0.7V.

3. The DC motor drive control circuit for a hydraulic oil pump in a rail vehicle according to claim 1, characterized in that, The square wave generated by the square wave generator UE is a 15.625kHz square wave.

4. The DC motor drive control circuit for a hydraulic oil pump in a rail vehicle according to claim 3, characterized in that, The power supply Vcc is 12V, and the power supply Vcc1 is 5V.

5. The DC motor drive control circuit for a hydraulic oil pump in a rail vehicle according to claim 4, characterized in that, The D0 terminal represents the first input terminal of the dual D flip-flop; the D1 terminal represents the second input terminal of the dual D flip-flop; the Q0 terminal represents the first positive output terminal of the dual D flip-flop; the CP terminal represents the clock pulse input terminal of the dual D flip-flop; The terminal represents the reset terminal; the The terminal represents the second inverting output of the dual D flip-flop.

6. A DC motor drive control method for a hydraulic oil pump in a rail vehicle, used to implement the DC motor drive control circuit for a hydraulic oil pump in a rail vehicle as described in any one of claims 1-5, characterized in that, The method includes the following steps: S1. The start signal A is output through EBCU, enters the start control configuration circuit after passing through opto-isolation, and generates voltage Vb; S2. Compare the voltage Vb with the sawtooth wave voltage generated by the sawtooth wave generation circuit through comparator A to generate a PWM drive signal; S3 and PWM drive signals pass through the MOS driver chip and control the on / off state of the field-effect transistor Q1 to achieve drive control of motor M.

7. The DC motor drive control method for a hydraulic oil pump in a rail vehicle according to claim 6, characterized in that, The process of outputting a start signal through the EBCU, passing through an opto-isolation unit, and then entering the start control configuration circuit to generate voltage Vb includes the following steps: S11. If the start signal A is a switch control signal, the switch control signal establishes the Vb voltage through channel I. S12. If the start signal A is a frequency signal, then the frequency signal establishes the Vb voltage through channel II.

8. The DC motor drive control method for a hydraulic oil pump in a rail vehicle according to claim 7, characterized in that, The step of comparing the voltage Vb with the sawtooth wave voltage generated by the sawtooth wave generation circuit through comparator A to generate a PWM drive signal includes the following steps: S21. If the voltage Vb is greater than the sawtooth wave voltage, it indicates that the output of the PWM drive signal is high. S22. If the voltage Vb is less than the sawtooth wave voltage, it indicates that the output of the PWM drive signal is low.

9. A DC motor drive control method for a hydraulic oil pump in a rail vehicle according to claim 8, characterized in that, The frequency signal is 100Hz-2kHz.

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