Variable gain low noise amplifier and method of controlling gain thereof

Abstract

The present application provides a variable gain low noise amplifier and a method for controlling the gain of the variable gain low noise amplifier. In one embodiment, the present application provides a variable gain low noise amplifier (LNA) comprising: a first transistor, wherein a gate terminal of the first transistor is configured to receive an input signal; a first negative feedback inductor coupled to a source terminal of the first transistor, wherein the first transistor and the first negative feedback inductor belong to a first branch of the variable gain LNA; a second transistor, wherein a gate terminal of the second transistor is configured to receive the input signal; and a second negative feedback inductor coupled to a source terminal of the second transistor, wherein the second transistor and the second negative feedback inductor belong to a second branch of the variable gain LNA; wherein the gain of the variable gain LNA is determined by controlling the second branch to be turned on or turned off.

Description

Technical Field

[0001] This invention relates to low-noise amplifiers (LNAs), and more specifically, to variable-gain LNAs and methods for controlling the gain of variable-gain LNAs. Background Technology

[0002] For low-noise amplifiers (LNAs), specific architectures have been proposed in related technologies to optimize performance related to noise figure and gain step (e.g., gain tuning) stability. However, with such architectures, input matching and input linearity requirements become challenging. For example, the parameters of the LNA's internal components are typically optimized when the LNA operates in high-gain mode, but if these parameters remain unchanged, the LNA's input matching and input linearity will deteriorate when operating in low-gain mode. Specifically, even if the LNA is optimized under high-gain mode conditions, when the LNA switches to low-gain mode, the input impedance may change, causing the input matching conditions to no longer be optimized. Furthermore, the input linearity is also affected by changes in the input matching conditions.

[0003] One related technique also implements an auxiliary amplifier optimized for low-gain modes. However, the additional path provided by the auxiliary amplifier can impose additional load on the overall architecture, thus affecting the noise figure. Furthermore, tracking between the two amplifiers may be required to achieve gain step stability, where the two amplifiers are independent, making tracking challenging.

[0004] Therefore, a novel architecture and related approach are needed that enables low-noise amplifiers to operate under optimized conditions in all gain modes, or makes it unlikely that the performance of low-noise amplifiers will degrade when operating under low-gain mode conditions. Summary of the Invention

[0005] This invention provides a variable gain low noise amplifier and a method for controlling the gain of the variable gain low noise amplifier.

[0006] In one embodiment, the present invention provides a variable gain low noise amplifier (LNA) comprising: a first transistor, wherein the gate of the first transistor is configured to receive an input signal; a first negative feedback inductor coupled to the source terminal of the first transistor, wherein the first transistor and the first negative feedback inductor belong to a first branch of the variable gain LNA; a second transistor, wherein the gate of the second transistor is configured to receive the input signal; and a second negative feedback inductor coupled to the source terminal of the second transistor, wherein the second transistor and the second negative feedback inductor belong to a second branch of the variable gain LNA; wherein the gain of the variable gain LNA is determined by controlling the second branch to be turned on or off.

[0007] In another embodiment, the method for controlling the gain of a variable gain amplifier provided by the present invention includes: receiving an input signal using the gate terminal of a first transistor, wherein a first negative feedback inductor is coupled to the source terminal of the first transistor, and the first transistor and the first negative feedback inductor belong to a first branch of the variable gain LNA; receiving the input signal using the gate terminal of a second transistor, wherein a second negative feedback inductor is coupled to the source terminal of the second transistor, and the second transistor and the second negative feedback inductor belong to a second branch of the variable gain LNA; and controlling whether to turn off the second branch to determine the gain of the variable gain LNA. Attached Figure Description

[0008] Figure 1 A diagram showing a variable gain low noise amplifier (LNA) 10 according to an embodiment of the present invention is provided.

[0009] Figure 2 This is a schematic diagram of a variable gain LNA 20 according to an embodiment of the present invention.

[0010] Figure 3 This is a schematic diagram of a variable gain LNA 30 according to an embodiment of the present invention.

[0011] Figure 4 This is a schematic diagram of a variable gain LNA 40 according to an embodiment of the present invention.

[0012] Figure 5 This is a schematic diagram of a variable gain LNA 50 according to an embodiment of the present invention.

[0013] Figure 6 This is a schematic diagram of the layout of negative feedback inductors L0, L1, L2, L3, etc., mentioned in the foregoing embodiments of an embodiment of the present invention.

[0014] Figure 7 This is a layout diagram of the negative feedback inductors L0, L1, L2, L3, etc. mentioned in the above embodiments according to another embodiment of the present invention.

[0015] Figure 8 This is a flowchart illustrating a method for controlling the gain of a variable gain LNA according to an embodiment of the present invention. Detailed Implementation

[0016] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." "Substantially" or "approximately" means that, within an acceptable margin of error, those skilled in the art can solve the technical problem and substantially achieve the technical effect. Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. The following description is a preferred mode for carrying out the invention and is intended to illustrate the spirit of the invention rather than to limit the scope of protection of the invention. The scope of protection of the invention shall be determined by the appended claims.

[0017] The following description represents the preferred embodiments of the present invention. These descriptions are intended to illustrate the general principles of the invention and not to limit it. The scope of protection of the invention should be determined based on the claims.

[0018] Figure 1 A diagram illustrating a variable gain low-noise amplifier (LNA) 10 according to an embodiment of the present invention is shown. Figure 1 As shown, the variable gain LNA 10 may include a first transistor (such as transistor Mon) and a first negative feedback inductor (also called a source inductor) (such as negative feedback inductor L). s,on ), second transistor (such as transistor M) off ), and a second negative feedback inductor (such as negative feedback inductor L) s,off ), where the negative feedback inductor L s,on Coupled to transistor M on The source extreme, negative feedback inductor L s,off Coupled to transistor M off The source end. In this embodiment, the variable gain low-noise amplifier 10 may further include a transistor M. c,onand M c,off They are respectively coupled to transistor M on and M off The invention may be designed to achieve the purpose of cascading stages, but it is not limited thereto.

[0019] In this embodiment, transistor M on and M off The gate terminal is configured to receive the input signal Vin. For example, the input signal Vin can be received through resistor R. g and inductor L g Transmitted to transistor M on and M off The gate terminal. The variable gain LNA 10 can adjust the output load Z according to the input signal Vin. o The output signal Vout is generated. More specifically, the variable gain LNA 10 can be used to amplify the input signal to generate the output signal Vout. For example... Figure 1 As shown, transistor M c,on M on and negative feedback inductor L s,on Belonging to the first branch 110 of the variable gain LNA 10, transistor M c,off M off and negative feedback inductor L s,off The second branch 120 belongs to the variable gain LNA 10, where the gain of the variable gain LNA 10 is determined by controlling whether the second branch 120 is turned off. For example, transistor M c,on It can be configured to control the turn-on or turn-off of the first branch 110. Transistor M coff It can be configured to control the on or off of the second branch 120. Transistor M c,on The gate terminal can be fixed at a voltage level VH (e.g., the voltage level of the power supply voltage VDD) to keep the first branch 110 on, transistor M c,off The gate terminal of transistor M can be controlled to a voltage level VH or a voltage level VL (e.g., the voltage level of ground voltage GND). c,off When the gate terminal of transistor M is set to voltage level VH, the second branch 120 is turned on. c,off When the gate terminal is set to voltage level VL, the second branch 120 is turned off.

[0020] In this embodiment, the variable gain low-noise amplifier 10 may further include a resistor R. s,off and switch SW R resistor R s,off Coupled to negative feedback inductor Ls,off Switch SW R Coupled to resistor R s,off Both ends. For example... Figure 1 As shown, resistor R s,off and switch SW R Belonging to the second branch 120, the switch SW can be controlled by whether the second branch 120 is turned off. R For example, the switch SW can be controlled by a control signal. R The control signal can indicate whether the second branch 120 is turned off. For example, when the second branch 120 is turned on (e.g., by turning on transistor M...). c,off The voltage level at the gate terminal is set to voltage level VH), and the control signal can be pulled to a level that can be used to turn on the switch SW. R The voltage level VH of the first logic value (e.g., logic value "1"), and the resistance R. s,off Therefore, it is bypassed and ineffective, causing transistor M to... off The effective source load consists only of inductor L. s,off When the second branch 120 is turned off (e.g., by turning off transistor M), c,off The voltage level at the gate terminal is set to voltage level VL), and the control signal can be pulled up to indicate the switch SW is turned off. R The voltage level VL of the second logic value (e.g., logic value "0"), resistor R s,off Therefore, it works, making transistor M off Effective source loads include inductor L s,off and resistor R s,off A series network.

[0021] Typically, the variable gain LNA 10 may include a plurality of branches, and as shown in one of the first branch 110 and the second branch 120, any of the plurality of branches (e.g., each branch) may include cascaded transistors (e.g., M... c,on and M c,off ), input transistor (e.g., M) on and M off ) and source negative feedback inductors (e.g., L s,on and L s,off More specifically, as shown in the second branch 120, each branch that can be selectively turned off may further include a resistor (e.g., R0). s,off ) and switches (e.g., SW) RTo better understand the performance of the variable gain LNA 10 in different gain modes, assume that the first branch 110 represents all branches on, and the second branch 120 represents all branches off, where the percentage of off branches out of the complex number of branches is α. Transistor M off The introduced transconductance is “α×g” m "Transistor M" on The introduced transconductance is "(1-α)×g m "Transistor M" off The introduced gate-to-source capacitance is α × C gs "Transistor M" on The introduced gate-source capacitance is (1-α)×C gs "Source negative feedback inductor L" s,off For "L" s / α”, source negative feedback inductor L s,on For "L" s / (1–α)", where "g" m "This indicates that the variable gain LNA 10 is based on the overall transconductance in high-gain mode (e.g., when all branches are conducting)," C gs "Indicates the variable gain LNA 10 based on the overall gate-source capacitance (e.g., parallel transistor M) in high-gain mode." on and M off (total capacitance introduced), "L s "Indicates the total negative feedback inductance of the variable gain LNA 10 based on high gain mode (e.g., by a negative feedback inductor L connected in parallel)" s,on and L s,off (Introduced total inductance). Therefore, the gain of the variable gain LNA10 can be obtained as follows:

[0022]

[0023] In the above formula, "ω" represents the frequency parameter, and "j" represents the imaginary unit. By making the resistor R... s,off The resistance value is "(1 / α)×(g) m ×L s / C gs The input impedance Z of the variable gain LNA10 is... in It can be obtained as follows:

[0024]

[0025] As shown in the above equation, the input impedance Z in It does not include the parameter α, that is, the input impedance Z. inThe linearity of the variable gain LNA 10 remains essentially constant across different gain modes. The input linearity is affected by the maximum output voltage Vout of the output signal Vout. o,MAX When limited, the maximum input voltage V representing the input linearity. in,MAX,Vo-limited It can be obtained in the following ways:

[0026]

[0027] When the input linearity of the variable gain LNA 10 is affected by transistor M on Maximum gate-source voltage V gs,MAX When limited, the maximum input voltage V that represents the input linearity. in,MAX,Vgs-limited It can be obtained in the following ways:

[0028] V in,MAX,Vgs-limited =2×g m ×jωL s ×V gs,MAX

[0029] Therefore, the overall linearity of the variable gain LNA10 can be determined by the maximum input voltage V. in,MAX,Vo-limited and V in,MAX,Vgs-limited The minimum value in the expression is represented by .

[0030] Based on the above analysis, when the component parameters are designed to optimize the performance of the variable gain LNA10 operating in high-gain mode (e.g., noise figure correlation performance, gain step stability, input matching, input linearity), the input matching can be kept substantially optimized in all gain modes (e.g., with an S11 parameter equal to or substantially equal to "-∞"). As an example, when the variable gain LNA10 operates in low-gain mode (e.g., when the second branch 120 is off), the input matching can also be kept substantially optimized. Accordingly, the maximum input voltage V... in,MAX,Vo-limited It can increase by 1 dB in response to a 1 dB decrease in gain of the variable gain LNA 10, which basically satisfies the maximum input voltage V. in,MAX,Vo-limited The ideal relationship between the gain of the variable gain LNA10 and the gain of the variable gain LNA10.

[0031] It should be noted that, Figure 1 The use of a dual-branch architecture is for illustrative purposes only and is not intended to limit the invention. Those skilled in the art should understand how it can be extended. Figure 1 The concepts illustrated in the embodiments are extended to architectures with more branches, and related details are omitted here for the sake of brevity.

[0032] Figure 2 This is a schematic diagram of a variable gain LNA 20 according to an embodiment of the present invention, wherein the variable gain LNA 20 can be... Figure 1 This is an example of a variable gain LNA 10. (Example shown) Figure 2 As shown, the variable gain LNA 20 may include transistors Mc0, Mc1, Mc2, Mc3, M0, M1, M2, and M3; resistors Rs1, Rs2, and Rs3; switches SW1, SW2, and SW3; and negative feedback inductors L0, L1, L2, and L3. For simplicity, resistor R... g Inductor L g and output load Z o Not in Figure 2 As shown in the diagram. In this embodiment, the branch including transistors Mc0 and M0 and the negative feedback inductor L0 can be... Figure 1 The example shown is the first branch 110. Furthermore, any one (e.g., each) of the following branches can be: a branch including transistors Mc1 and M1, resistor Rs1, switch SW1, and negative feedback inductor L1; a branch including transistors Mc2 and M2, resistor Rs2, switch SW2, and negative feedback inductor L2; and a branch including transistors Mc3 and M3, resistor Rs3, switch SW3, and negative feedback inductor L3. Figure 1 The example shown is the second branch 120. More specifically, any one of switches SW1, SW2, and SW3 can be... Figure 1 The switch SW shown R Example. Switches SW1, SW2, and SW3 are connected in parallel with resistors Rs1, Rs2, and Rs3, respectively, and the gates of transistors Mc0, Mc1, Mc2, and Mc3 are controlled by control signals Vc0, Vc1, Vc2, and Vc3, respectively. For example... Figure 2 As shown, switch SW1 is coupled between the source terminal of transistor M1 and the negative feedback inductor L1. Switch SW1 is controlled by whether the branch consisting of transistor M1 and inductor L1 is turned off (e.g., whether the control voltage Vc1 is pulled down to voltage level VL). Switch SW2 is coupled between the source terminal of transistor M2 and the negative feedback inductor L2. Switch SW2 is controlled by whether the branch consisting of transistor M2 and inductor L2 is turned off (e.g., whether the control voltage Vc2 is pulled down to voltage level VL). Switch SW3 is coupled between the source terminal of transistor M3 and the negative feedback inductor L3. Switch SW3 is controlled by whether the branch including transistor M3 and inductor L3 is turned off (e.g., whether the control voltage Vc3 is pulled down to voltage level VL).

[0033] Figure 3 This is a schematic diagram of a variable gain LNA 30 according to an embodiment of the present invention, wherein the variable gain LNA 30 may be... Figure 1 Another example of the variable gain LNA 10 shown, more specifically, can be relative to Figure 2The diagram shows an alternative design for the variable gain LNA 20. Figure 3 In the illustrated embodiment, switch SW1 and resistor Rs1 are coupled between the negative feedback inductor L1 and a reference terminal (e.g., AC ground). Switch SW1 is controlled based on whether the branch including transistor M1 and inductor L1 is turned off (e.g., based on whether the control voltage Vc1 is pulled down to voltage level VL). Switch SW2 and resistor Rs2 are coupled between the negative feedback inductor L2 and AC ground. Switch SW2 is controlled based on whether the branch including transistor M2 and inductor L2 is turned off (e.g., based on whether the control voltage Vc2 is pulled down to voltage level VL). Switch SW3 and resistor Rs3 are coupled between the negative feedback inductor L3 and AC ground. Switch SW3 is controlled based on whether the branch including transistor M3 and inductor L3 is turned off (e.g., based on whether voltage Vc3 is pulled down to voltage level VL).

[0034] Figure 4 This is a schematic diagram of a variable gain LNA 40 according to an embodiment of the present invention, wherein the variable gain LNA 40 may be... Figure 1 Another example of the variable gain LNA 10 shown, more specifically, can be relative to Figure 2 The diagram shows an alternative design for the variable gain LNA 20. Figure 4 In the illustrated embodiment, negative feedback inductors L0 and L1 can be combined into a single negative feedback inductor (e.g., L0'), wherein the negative feedback inductor L0' can be... Figure 1 The negative feedback inductor L shown s,on An example. Transistor M0 can be... Figure 1 The transistor M shown on Examples. Furthermore, the variable gain LNA 40 may include a third transistor, such as transistor M1, wherein the gate of transistor M1 is configured to receive the input signal Vin, and a negative feedback inductor L0' is coupled to the source terminal of transistor M1.

[0035] Figure 5 This is a schematic diagram of a variable gain LNA 50 according to an embodiment of the present invention, wherein the variable gain LNA 50 may be... Figure 1 Another example of the variable gain LNA 10 shown, more specifically, can be relative to Figure 4 The diagram shows an alternative design for the variable gain LNA40. Figure 5In the illustrated embodiment, switch SW2 and resistor Rs2 are coupled between negative feedback inductor L2 and AC ground. Switch SW2 is controlled based on whether the branch including transistor M2 and inductor L2 is turned off (e.g., based on whether voltage Vc2 is pulled down to voltage level VL). Switch SW3 and resistor Rs3 are coupled between negative feedback inductor L3 and AC ground. Switch SW3 is controlled based on whether the branch including transistor M3 and inductor L3 is turned off (e.g., based on whether control voltage Vc3 is pulled down to voltage level VL).

[0036] Figure 6 This is a schematic diagram showing the layout of the negative feedback inductors L0, L1, L2, L3, etc., mentioned in the foregoing embodiments of an embodiment of the present invention. Figure 6 As shown, the regions surrounded by negative feedback inductor L0, L1, L2, and L3 do not overlap. In some embodiments, negative feedback inductors L0, L1, L2, and L3 can be implemented in the same metal layer. In some embodiments, negative feedback inductors L0, L1, L2, and L3 can be implemented in different metal layers. In this embodiment, any one of the negative feedback inductors L0, L1, L2, and L3 can be connected to at least one trace different from the metal layer in which it resides, but the invention is not limited thereto.

[0037] Figure 7 This is a layout diagram of the negative feedback inductors L0, L1, L2, L3, etc., mentioned in the above embodiments according to another embodiment of the present invention. Figure 7 As shown, the regions surrounded by negative feedback inductor L0, L1, L2, and L3 overlap. In practical applications, any two of the negative feedback inductors L0, L1, L2, and L3 may have mutual inductance, which needs to be considered when optimizing the above matching conditions. In some embodiments, negative feedback inductors L0, L1, L2, and L3 can be implemented in the same metal layer. In some embodiments, negative feedback inductors L0, L1, L2, and L3 can be implemented in different metal layers. In this embodiment, any one of the negative feedback inductors L0, L1, L2, and L3 can be connected to at least one trace different from the metal layer in which it is located, but the present invention is not limited thereto.

[0038] Figure 8 This illustrates an embodiment of the invention for controlling a variable gain LNA (e.g., Figure 1 The flowchart illustrates the gain method for the variable gain LNA10 shown. It should be noted that... Figure 8The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. If the same results can be obtained, Figure 8 The workflow shown can include the addition, deletion, or modification of one or more steps. Furthermore, the steps do not necessarily need to be followed in sequence. Figure 8 The exact order of execution is shown.

[0039] In step S810, the variable gain LNA can utilize the first transistor (e.g., transistor M). on The gate terminal of the first negative feedback inductor (e.g., negative feedback inductor L) receives the input signal, wherein the gate terminal of the first negative feedback inductor (e.g., negative feedback inductor L) receives the input signal. s,on The first transistor and the first negative feedback inductor are coupled to the source terminal of the first transistor, and belong to the first branch of the variable gain LNA.

[0040] In step S820, the variable gain LNA can utilize a second transistor (e.g., transistor M). off The gate terminal of the second negative feedback inductor (e.g., negative feedback inductor L) receives the input signal, wherein the second negative feedback inductor (e.g., negative feedback inductor L) receives the input signal. s,off It is coupled to the source terminal of the second transistor, and the second transistor and the second negative feedback inductor belong to the second branch of the variable gain LNA.

[0041] In step S830, the variable gain LNA can control whether the second branch is turned off to determine the gain of the variable gain LNA. For example, this can be achieved by controlling the cascaded transistors belonging to the second branch (e.g., transistor M). c,off The second branch is turned on by setting the voltage level of the gate terminal of the cascaded transistor to voltage level VH, and the second branch is turned off by controlling the voltage level of the gate terminal of the cascaded transistor belonging to the second branch to voltage level VL.

[0042] In summary, the variable gain low-noise amplifier and method provided by the embodiments of the present invention not only slices the transistors but also slices the negative feedback inductor, ensuring that the input matching remains in an optimal state and optimizing the input linearity across all gain modes. Furthermore, the embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can solve the problems of related technologies without introducing any side effects or in a manner unlikely to introduce side effects.

[0043] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Anyone skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A variable gain low-noise amplifier (LNA), characterized in that, include: A first transistor, wherein the gate terminal of the first transistor is configured to receive an input signal; A first negative feedback inductor is coupled to the source terminal of the first transistor, wherein the first transistor and the first negative feedback inductor belong to the first branch of the variable gain LNA; A second transistor, wherein the gate of the second transistor is configured to receive the input signal; and A second negative feedback inductor is coupled to the source terminal of the second transistor, wherein the second transistor and the second negative feedback inductor belong to the second branch of the variable gain LNA; The gain of the variable gain LNA is determined by controlling the second branch to be turned on or off; when the second branch is turned off, the second negative feedback inductor is coupled between the source terminal of the second transistor and a resistor.

2. The variable gain LNA as described in claim 1, characterized in that, Further includes: A resistor is coupled to the second negative feedback inductor; and A switch is coupled across the two ends of the resistor; The switch is controlled by whether or not the second branch is turned off.

3. The variable gain LNA as described in claim 2, characterized in that, When the second branch is connected, the switch is activated.

4. The variable gain LNA as described in claim 2, characterized in that, When the second branch is closed, the switch is turned off.

5. The variable gain LNA as described in claim 1, characterized in that, Further includes: A switch is coupled between the source terminal of the second transistor and the second negative feedback inductor; The switch is controlled by whether or not the second branch is turned off.

6. The variable gain LNA as described in claim 1, characterized in that, Further includes: A switch is coupled between the second negative feedback inductor and the reference terminal; The switch is controlled by whether or not the second branch is turned off.

7. The variable gain LNA as described in claim 1, characterized in that, Further includes: A third transistor, wherein the gate of the third transistor is configured to receive the input signal, and the first negative feedback inductor is coupled to the source terminal of the third transistor.

8. The variable gain LNA as described in claim 1, characterized in that, The regions enclosed by the first negative feedback inductor and the regions enclosed by the second negative feedback inductor do not overlap.

9. The variable gain LNA as described in claim 1, characterized in that, The region enclosed by the first negative feedback inductor overlaps with the region enclosed by the second negative feedback inductor.

10. A variable gain low-noise amplifier (LNA), characterized in that, include: A first transistor, wherein the gate terminal of the first transistor is configured to receive an input signal; A first negative feedback inductor is coupled to the source terminal of the first transistor, wherein the first transistor and the first negative feedback inductor belong to the first branch of the variable gain LNA; A second transistor, wherein the gate of the second transistor is configured to receive the input signal; A second negative feedback inductor is coupled to the source terminal of the second transistor, wherein the second transistor and the second negative feedback inductor belong to the second branch of the variable gain LNA; A resistor is coupled to the second negative feedback inductor; and A switch is coupled across the two ends of the resistor; The gain of the variable gain LNA is determined by controlling the second branch to be turned on or off, and the switch is controlled according to whether the second branch is turned off.

11. A variable gain low-noise amplifier (LNA), characterized in that, include: A first transistor, wherein the gate terminal of the first transistor is configured to receive an input signal; A first negative feedback inductor is coupled to the source terminal of the first transistor, wherein the first transistor and the first negative feedback inductor belong to the first branch of the variable gain LNA; A second transistor, wherein the gate of the second transistor is configured to receive the input signal; A second negative feedback inductor is coupled to the source terminal of the second transistor, wherein the second transistor and the second negative feedback inductor belong to the second branch of the variable gain LNA; and A switch is coupled between the second negative feedback inductor and the reference terminal; The gain of the variable gain LNA is determined by controlling the second branch to be turned on or off, and the switch is controlled according to whether the second branch is turned off.

12. A method for controlling the gain of a variable gain low-noise amplifier (LNA), characterized in that, include: The input signal is received using the gate terminal of the first transistor, wherein the first negative feedback inductor is coupled to the source terminal of the first transistor, and the first transistor and the first negative feedback inductor belong to the first branch of the variable gain LNA. The input signal is received using the gate terminal of the second transistor, wherein the second negative feedback inductor is coupled to the source terminal of the second transistor, and the second transistor and the second negative feedback inductor belong to the second branch of the variable gain LNA. and The gain of the variable gain LNA is determined by whether the second branch is turned off; wherein, in response to the second branch being turned off, the second negative feedback inductor is coupled between the source terminal of the second transistor and a resistor.

13. The method as described in claim 12, characterized in that, A resistor is coupled to the second negative feedback inductor, and a switch is coupled across the resistor. The method further includes: The switch is controlled by whether the second branch is turned off.

14. The method as described in claim 13, characterized in that, The switch is controlled based on whether the second branch is shut off, including: In response to the second branch being turned on, the switch is turned on.

15. The method as described in claim 13, characterized in that, The switch is controlled based on whether the second branch is shut off, including: In response to the shutdown of the second branch, the switch is turned off.

16. The method as described in claim 12, characterized in that, A switch is coupled between the source terminal of the second transistor and the second negative feedback inductor, and the method further includes: The switch is controlled by whether the second branch is turned off.

17. The method as described in claim 12, characterized in that, A switch is coupled between the second negative feedback inductor and the reference terminal, and the method further includes: The switch is controlled by whether the second branch is turned off.

18. The method as described in claim 12, characterized in that, Further includes: The input signal is received at the gate of the third transistor, wherein the first negative feedback inductor is coupled to the source terminal of the third transistor.

19. The method as described in claim 12, characterized in that, The regions enclosed by the first negative feedback inductor and the regions enclosed by the second negative feedback inductor do not overlap.

20. The method as described in claim 12, characterized in that, The region enclosed by the first negative feedback inductor overlaps with the region enclosed by the second negative feedback inductor.

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