A 10gsps wideband acquisition system and method

Abstract

The embodiment of the present application discloses a 10Gsps wideband acquisition system and method. In a specific embodiment, the method comprises a clock module, which is used for receiving a first reference clock signal, and sending a sampling clock signal and a synchronization clock signal to an acquisition module, and sending a second reference clock signal to a control module; the acquisition module is used for receiving an input signal and performing analog-to-digital conversion to send sampling data to the control module; the control module is used for sending a first clock frequency control signal and a second clock frequency control signal to the clock module, and sending a sampling control signal to the acquisition module, and sending processed sampling data to a bus module and a storage module; the storage module is used for storing the sampling data and the processed sampling data; the bus module is used for powering each module and interacting with external data. The single-channel and 10Gsps rate wideband sampling system has the advantages of simple structure, high sampling rate and avoidance of time delay error introduced by a multi-channel data acquisition structure.

Description

Technical Field

[0001] This invention relates to the field of broadband signal acquisition technology. More specifically, it relates to a 10Gsps broadband acquisition system and method. Background Technology

[0002] Currently, ultra-wideband radar data acquisition widely employs a multi-channel data acquisition structure, utilizing adjustable time delays to achieve multi-channel data acquisition. This inevitably introduces time delay errors, impacting data recovery. Therefore, real-time data acquisition of ultra-wideband radar echo signals is crucial for ultra-wideband signal processing and target identification. Summary of the Invention

[0003] The purpose of this invention is to provide a 10Gsps broadband acquisition system and method to solve at least one of the problems existing in the prior art.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] The first aspect of this invention provides a 10Gsps broadband acquisition system, the system comprising:

[0006] The clock module is used to receive the first reference clock signal, send the sampling clock signal and the synchronization clock signal to the acquisition module, and send the second reference clock signal to the control module;

[0007] The acquisition module is used to receive input signals, convert them from analog to digital, and send them as sampled data to the control module.

[0008] The control module is used to send a first clock frequency control signal and a second clock frequency control signal to the clock module, send a sampling control signal to the acquisition module, and send the processed sampling data to the bus module and the storage module.

[0009] A storage module is used to store the sampled data and the processed sampled data;

[0010] The bus module is used for power supply, providing clock signals, and external data exchange.

[0011] Optionally, the clock module receives a first reference clock signal at its input terminal, the first and second output terminals are connected to the first and second input terminals of the acquisition module, and the third output terminal is connected to the first input terminal of the control module.

[0012] The third input terminal of the acquisition module receives the input signal, and the first output terminal is connected to the second input terminal of the control module;

[0013] The first output terminal and the second output terminal of the control module are respectively connected to the first input terminal and the second input terminal of the bus module, and the multiple interaction terminals of the control module are respectively connected to the interaction terminals of the clock module, the acquisition module and the storage module.

[0014] Optionally, the first interaction terminal, the second interaction terminal, and the third interaction terminal of the control module are respectively connected to the first interaction terminal and the second interaction terminal of the clock module and the interaction terminal of the acquisition module through a serial peripheral device interface;

[0015] The fourth and fifth interaction terminals of the control module are respectively connected to the first and second interaction terminals of the storage module via a 64-bit data bus.

[0016] Optionally, the first output terminal of the acquisition module is connected to the second input terminal of the control module via multiple sets of high-speed serial interfaces as data converters.

[0017] Optionally, the second reference clock includes a core clock, a system reference clock, and an interface reference clock.

[0018] Optionally, the system further includes an external circuit module, which includes a first dual-channel switch and a second dual-channel switch; wherein

[0019] The first input terminal of the first dual-channel switch is connected to the bus module via an RF connector, the second input terminal is connected to the bus module, and the output terminal is connected to the second input terminal of the clock module;

[0020] The first input terminal of the second dual-channel switch is connected to the crystal oscillator, the second terminal is connected to the output terminal of the first dual-channel switch, and the output terminal is connected to the first input terminal of the clock module.

[0021] Optionally, the clock module includes a clock synthesizer and a clock generator; wherein

[0022] The input terminal of the clock generator is connected to the output terminal of the first dual-channel switch, the first output terminal is connected to the second input terminal of the acquisition module, and the second plurality of second sub-output terminals are respectively connected to the second plurality of first sub-input terminals of the control module.

[0023] The input terminal of the clock synthesizer is connected to the output terminal of the second dual-channel switch, and the output terminal is connected to the first input terminal of the acquisition module.

[0024] Optionally, the bus module includes a first connector, a second connector, and a radio frequency unit; wherein

[0025] The first connector is used to power each module and provide clock signals;

[0026] The second connector is used for external data interaction;

[0027] The radio frequency unit is used to receive external input signals.

[0028] Optionally, the acquisition module includes an analog-to-digital converter; wherein

[0029] The first and second input terminals of the analog-to-digital converter are connected to the first and second output terminals of the clock module, and the third input terminal is connected to the output terminal of the radio frequency unit.

[0030] The interactive terminal of the analog-to-digital converter is connected to the third interactive terminal of the control module;

[0031] The first output terminal of the analog-to-digital converter is connected to the second input terminal of the control module via multiple sets of high-speed serial interfaces as a data converter.

[0032] A second aspect of the present invention provides a 10Gsps broadband data acquisition method, the method comprising:

[0033] Using the clock module, a first reference clock signal is received, and a sampling clock signal and a synchronization clock signal are sent to the acquisition module, as well as a second reference clock signal is sent to the control module;

[0034] The acquisition module receives input signals, converts them into sampled data using analog-to-digital conversion, and sends the data to the control module.

[0035] Using the control module, a first clock frequency control signal and a second clock frequency control signal are sent to the clock module, a sampling control signal is sent to the acquisition module, and the processed sampling data is sent to the bus module and the storage module.

[0036] The sampling data and the processed sampling data are stored using a storage module.

[0037] The bus module is used to power each module and facilitate external data exchange.

[0038] The beneficial effects of this invention are as follows:

[0039] This invention provides a 10Gsps broadband acquisition system, which realizes a single-channel broadband sampling system with a rate of 10Gsps. It has the advantages of simple structure, high sampling rate, and avoidance of delay errors introduced by multi-channel data acquisition structures. Attached Figure Description

[0040] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0041] Figure 1A schematic diagram of the structure of the 10Gsps broadband acquisition system provided in an embodiment of the present invention is shown.

[0042] Figure 2 This diagram illustrates the functional block diagram of the clock module of the 10Gsps broadband acquisition system provided in an embodiment of the present invention.

[0043] Figure 3 This diagram illustrates the functional block diagram of the acquisition module of the 10Gsps broadband acquisition system provided in an embodiment of the present invention.

[0044] Figure 4 The time-domain simulation diagram of the sampling performance of the 10Gsps broadband acquisition system provided in the embodiment of the present invention is shown.

[0045] Figure 5 The sampling performance frequency domain simulation diagram of the 10Gsps broadband acquisition system provided in the embodiment of the present invention is shown. Detailed Implementation

[0046] To more clearly illustrate the present invention, the following description, in conjunction with embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.

[0047] The high-resolution performance and target identification capabilities of ultra-wideband (UWB) radar provide rich and high-quality information for high-tech warfare, making ultra-high-speed data acquisition technology a crucial aspect of UWB radar research. Currently, UWB radar data acquisition systems widely employ multi-channel data acquisition structures, using adjustable time delays to achieve multi-channel data acquisition. This inevitably introduces time delay errors, impacting data recovery. Therefore, real-time data acquisition of UWB radar echo signals is of great significance for UWB signal processing and target identification.

[0048] In view of this, one embodiment of the present invention provides a 10Gsps broadband acquisition system, which includes a clock module for receiving a first reference clock signal and sending a sampling clock signal and a synchronization clock signal to the acquisition module, and sending a second reference clock signal to the control module; the acquisition module for receiving input signals and performing analog-to-digital conversion to sampled data and sending it to the control module; the control module for sending a first clock frequency control signal and a second clock frequency control signal to the clock module, sending a sampling control signal to the acquisition module, and sending the processed sampled data to a bus module and a storage module; the storage module for storing the sampled data and the processed sampled data; and the bus module for supplying power to each module, providing clock signals, and performing external data interaction.

[0049] Specifically, such as Figure 1 As shown, this embodiment provides a 10Gsps broadband acquisition system, including a broadband ADC acquisition module (acquisition module), an FPGA module (control module), a storage module, a clock module, and a VPX module (bus module). The FPGA module is connected to the broadband ADC acquisition module and controls the data acquisition and transmission of the broadband ADC acquisition module via a Serial Peripheral Interface (SPI). The clock module provides the sampling clock, SYSREF clock (synchronization clock), and reference clock (second reference clock) for the broadband ADC acquisition module and the FPGA module. The storage module stores high-speed ADC sampling data. The VPX module provides power to other modules and external data connections.

[0050] This embodiment can achieve single-channel, 10Gsps broadband sampling, which can be used for real-time data acquisition of ultra-wideband radar echo signals.

[0051] In one possible implementation, such as Figure 2 As shown, the clock module receives a first reference clock signal (reference clock 1) at its input terminal, and its first and second output terminals are connected to the first and second input terminals of the acquisition module, respectively. Its third output terminal is connected to the first input terminal of the control module. The acquisition module receives an input signal at its third input terminal, and its first output terminal is connected to the second input terminal of the control module. The control module's first and second output terminals are respectively connected to the first and second input terminals of the bus module. Multiple interaction terminals of the control module are respectively connected to the interaction terminals of the clock module, the acquisition module, and the storage module.

[0052] In one possible implementation, such as Figure 2 As shown, the first, second, and third interaction terminals of the control module are connected to the first and second interaction terminals of the clock module and the interaction terminal of the acquisition module through serial peripheral device interfaces, respectively; the fourth and fifth interaction terminals of the control module are connected to the first and second interaction terminals of the storage module through a 64-bit data bus, respectively.

[0053] Specifically, such as Figure 1 As shown, the 10Gsps broadband acquisition system in this embodiment mainly consists of a broadband ADC acquisition module, an FPGA module, a storage module, a clock module, and a VPX module.

[0054] Furthermore, the FPGA module controls the clock frequency of the clock module and the sampling of the broadband ADC acquisition module through the SPI interface; the clock module is used to provide the ADC sampling clock, the SYSREF clock, and the FPGA reference clock.

[0055] In a specific example, the storage module consists of two sets of 64-bit DDR3 memory modules used to store ADC sampling data.

[0056] In one possible implementation, the system further includes an external circuit module, which includes a first dual-channel switch and a second dual-channel switch; wherein the first input terminal of the first dual-channel switch is connected to the bus module via an RF connector, the second input terminal is connected to the bus module, and the output terminal is connected to the second input terminal of the clock module; the first input terminal of the second dual-channel switch is connected to a crystal oscillator, the second terminal is connected to the output terminal of the first dual-channel switch, and the output terminal is connected to the first input terminal of the clock module.

[0057] Specifically, the implementation method of the clock module is as follows: Figure 2 As shown, the reference clock input of the clock module supports two methods during normal operation: one is that the VPX RF unit first receives the reference clock from other systems, and then connects it to the SSMP RF head (RF connector) via RF cable to input the clock module; the other is that the VPXP0 connector receives the reference clock from other systems and inputs it to the OSCIN pin of the clock module through the internal circuit of the system.

[0058] Furthermore, during debugging, it also supports a mode where the on-board crystal oscillator provides a reference clock input.

[0059] In a specific example, the clock module receives control from the FPGA module via the SPI interface and generates the operating clock for both the broadband ADC acquisition module and the FPGA module.

[0060] In one possible implementation, the clock module includes a clock synthesizer and a clock generator; wherein the input terminal of the clock generator is connected to the output terminal of the first dual-channel switch, the first output terminal is connected to the second input terminal of the acquisition module, and the second plurality of second sub-output terminals are respectively connected to the second plurality of first sub-input terminals of the control module; the input terminal of the clock synthesizer is connected to the output terminal of the second dual-channel switch, and the output terminal is connected to the first input terminal of the acquisition module.

[0061] Specifically, the clock synthesizer can be an LMX2582 chip, and the clock generator can be an HMC7044 chip.

[0062] In one possible implementation, the second reference clock includes a core clock, a system reference clock, and an interface reference clock.

[0063] Specifically, the LMX2582 generates the sampling clock (AD-CLK) for the wideband ADC acquisition module, the HMC7044 generates the SYSREF clock (AD-SYSREF) for the wideband ADC acquisition module, the core clock (CORECLK) for the FPGA module, the GTH reference clock (GTH-REFCLK), which is the GTH interface reference clock, and the JESD204B reference clock (SYSREFCLK), which is the system reference clock.

[0064] In one possible implementation, the first output of the acquisition module is connected to the second input of the control module via multiple sets of high-speed serial interfaces as data converters.

[0065] Specifically, the FPGA module and the broadband ADC acquisition module communicate via the JESD204B protocol.

[0066] Furthermore, the broadband ADC acquisition module receives sampling control from the FPGA module via the SPI interface, and uses the JESD204B high-speed serial interface as a data converter. A total of 16 JESD204B lines, including ADCCOREA and ADCCOREB, ​​are used to transmit the sampled data from the ADC12DJ5200 to the FPGA module.

[0067] In one possible implementation, the bus module includes a first connector, a second connector, and an RF unit; wherein the first connector is used to power the various modules and provide clock signals; the second connector is used for external data interaction; and the RF unit is used to receive external input signals.

[0068] Specifically, the P0 connector (first connector) in the VPX module is used for powering the entire system and has two sets of X4GTH interconnects with the FPGA module. The PI connector (second connector) has two sets of X4GTH interconnects and eight sets of LVDS signal interconnects with the FPGA module for data interaction with other systems. The RF unit conforms to the VITA67 specification and is used to receive input signals from other systems.

[0069] In one possible implementation, the acquisition module includes an analog-to-digital converter (ADC); wherein the first and second input terminals of the ADC are connected to the first and second output terminals of the clock module, and the third input terminal is connected to the output terminal of the radio frequency unit; the interactive terminal of the ADC is connected to the third interactive terminal of the control module; and the first output terminal of the ADC is connected to the second input terminal of the control module via multiple sets of high-speed serial interfaces as a data converter.

[0070] Specifically, the implementation method of the broadband ADC acquisition module is as follows: Figure 3As shown, the broadband ADC acquisition module uses the ADC12DJ5200 chip, which can be configured as a dual-channel, 5.2Gsps ADC or a single-channel, 10.4Gsps ADC. In this embodiment, a single-channel, 10Gsps sampling mode is used.

[0071] Furthermore, the analog input of the broadband ADC acquisition module adopts a differential input method, and the external analog signal is transmitted via an RF cable. An SSMP RF connector is used to introduce the signal into the system. Considering that DC coupling is not required and the signal bandwidth is large, a transformer coupling method is used to convert the single-ended analog signal into a differential analog signal to ensure better ADC performance.

[0072] In a specific example, the clock input of the wideband ADC acquisition module includes a sampling clock input and a SYSREF clock input. When using single-channel sampling mode, the ADC12DJ5200 samples on both the rising and falling edges of the sampling clock. This mode effectively reduces the clock frequency required for ADC operation. The SYSREF clock is the system reference clock of the wideband ADC acquisition module, used to achieve deterministic delay and multi-device synchronization.

[0073] In a specific example, the FPGA module includes an XC7VX690T-2FFG1158 chip and an SPIFLASH chip connected thereto.

[0074] In a specific example, the sampling performance of the 10Gsps broadband acquisition system provided in this embodiment can be further illustrated by the following simulation experiment.

[0075] 1) Simulation experimental environment

[0076] Experimental environment: MATLAB R2015a, Visual Anolog, VIVADO 2016.4, Intel(R) Core(TM) i7-7700 CPU@3.60GHz, Windows 7 Ultimate, KEYSIGHT N5183B.

[0077] 2) Simulation Experiment Content and Result Analysis

[0078] Experimental content: Two KEYSIGHT N5183B signal generators were selected as the clock signal source and analog signal source for ADC performance testing. One signal generator outputs a 100MHz reference clock, while the other outputs a 1GHz analog signal.

[0079] The Xilinx VIVADO software was used to capture 40960 points of ADC data, which were then exported and saved as a CSV file. The sampled data was analyzed using Matlab and Visual Anorlog. Figure 4 and Figure 5 The figures shown are simulation diagrams in the time and frequency domains of the 1GHz signal acquired by the acquisition system.

[0080] Experimental results: From Figure 4 It can be seen that the 1GHz signal acquired by the 10Gsps broadband acquisition system described in this embodiment has consistent amplitude and phase. From Figure 5 As can be seen, the ADC12DJ5200 in the broadband acquisition system described in this embodiment has an effective sampling bit depth of 8.3 bits, which meets the model usage requirements.

[0081] This embodiment implements a single-channel broadband sampling system with a rate of 10Gsps, which has the advantages of simple structure, high sampling rate, and avoidance of delay errors introduced by multi-channel data acquisition structures.

[0082] Another embodiment of the present invention provides a 10Gsps broadband acquisition method, the method comprising: using a clock module to receive a first reference clock signal and send a sampling clock signal and a synchronization clock signal to an acquisition module, and sending a second reference clock signal to a control module; using the acquisition module to receive an input signal and convert it into sampled data by analog-to-digital conversion and send it to the control module; using the control module to send a first clock frequency control signal and a second clock frequency control signal to the clock module, and send a sampling control signal to the acquisition module, and send the processed sampled data to a bus module and a storage module; using the storage module to store the sampled data and the processed sampled data; and using the bus module to power each module and facilitate external data interaction.

[0083] This embodiment implements a single-channel broadband sampling system with a rate of 10Gsps, which has the advantages of simple structure, high sampling rate, and avoidance of delay errors introduced by multi-channel data acquisition structures.

[0084] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0085] It should also be noted that in the description of this invention, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0086] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A 10Gsps broadband data acquisition system, characterized in that, The system includes The clock module is used to receive the first reference clock signal, send the sampling clock signal and the synchronization clock signal to the acquisition module, and send the second reference clock signal to the control module; The acquisition module receives input signals and converts them from analog to digital to sampled data before sending them to the control module. The analog input of the acquisition module uses a differential input method, and the acquisition module uses transformer coupling to convert single-ended analog signals into differential analog signals. The effective number of bits for sampling in the acquisition module reaches 8.3 bits. The control module is used to send a first clock frequency control signal and a second clock frequency control signal to the clock module, send a sampling control signal to the acquisition module, and send the processed sampling data to the bus module and the storage module. A storage module is used to store the sampled data and the processed sampled data; The bus module is used for power supply, providing clock signals, and external data exchange; The system also includes an external circuit module, which comprises a first dual-channel switch and a second dual-channel switch; wherein The first input terminal of the first dual-channel switch is connected to the bus module via an RF connector, the second input terminal is connected to the bus module, and the output terminal is connected to the second input terminal of the clock module; The first input terminal of the second dual-channel switch is connected to the crystal oscillator, the second terminal is connected to the output terminal of the first dual-channel switch, and the output terminal is connected to the first input terminal of the clock module. The clock module includes a clock synthesizer and a clock generator; in The input terminal of the clock generator is connected to the output terminal of the first dual-channel switch, the first output terminal is connected to the second input terminal of the acquisition module, and the second plurality of second sub-output terminals are respectively connected to the second plurality of first sub-input terminals of the control module. The input terminal of the clock synthesizer is connected to the output terminal of the second dual-channel switch, and the output terminal is connected to the first input terminal of the acquisition module.

2. The 10Gsps broadband acquisition system according to claim 1, characterized in that, The clock module receives a first reference clock signal at its input terminal, and its first and second output terminals are connected to the first and second input terminals of the acquisition module, while its third output terminal is connected to the first input terminal of the control module. The third input terminal of the acquisition module receives the input signal, and the first output terminal is connected to the second input terminal of the control module; The first output terminal and the second output terminal of the control module are respectively connected to the first input terminal and the second input terminal of the bus module, and the multiple interaction terminals of the control module are respectively connected to the interaction terminals of the clock module, the acquisition module and the storage module.

3. The 10Gsps broadband acquisition system according to claim 2, characterized in that, The first, second, and third interaction terminals of the control module are respectively connected to the first and second interaction terminals of the clock module and the interaction terminal of the acquisition module through serial peripheral device interfaces. The fourth and fifth interaction terminals of the control module are respectively connected to the first and second interaction terminals of the storage module via a 64-bit data bus.

4. The 10Gsps broadband acquisition system according to claim 3, characterized in that, The first output terminal of the acquisition module is connected to the second input terminal of the control module via multiple sets of high-speed serial interfaces as data converters.

5. The 10Gsps broadband acquisition system according to claim 4, characterized in that, The second reference clock includes the core clock, the system reference clock, and the interface reference clock.

6. The 10Gsps broadband acquisition system according to claim 1, characterized in that, The bus module includes a first connector, a second connector, and a radio frequency unit; wherein... The first connector is used to power each module and provide clock signals; The second connector is used for external data interaction; The radio frequency unit is used to receive external input signals.

7. The 10Gsps broadband acquisition system according to claim 6, characterized in that, The acquisition module includes an analog-to-digital converter; in The first and second input terminals of the analog-to-digital converter are connected to the first and second output terminals of the clock module, and the third input terminal is connected to the output terminal of the radio frequency unit. The interactive terminal of the analog-to-digital converter is connected to the third interactive terminal of the control module; The first output terminal of the analog-to-digital converter is connected to the second input terminal of the control module via multiple sets of high-speed serial interfaces as a data converter.

8. A 10Gsps broadband data acquisition method using the system described in any one of claims 1 to 7, characterized in that, The method includes Using the clock module, a first reference clock signal is received, and a sampling clock signal and a synchronization clock signal are sent to the acquisition module, as well as a second reference clock signal is sent to the control module; The acquisition module receives input signals and converts them from analog to digital to sampled data before sending them to the control module. The analog input of the acquisition module adopts a differential input method, and the acquisition module uses transformer coupling to convert single-ended analog signals into differential analog signals. The effective number of bits for sampling by the acquisition module reaches 8.3 bits. Using the control module, a first clock frequency control signal and a second clock frequency control signal are sent to the clock module, a sampling control signal is sent to the acquisition module, and the processed sampling data is sent to the bus module and the storage module. The sampling data and the processed sampling data are stored using a storage module. The bus module is used to power each module and facilitate external data exchange.

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