Method of manufacturing a semiconductor element with a diode connected to a memory element

Abstract

A method of fabricating a semiconductor device is provided. The method includes providing a substrate. The substrate includes a first well region having a first conductivity type. The method also includes forming a first gate structure on the substrate. The method further includes forming a first doped region in the substrate. The first doped region has a second conductivity type different from the first conductivity type. The first gate structure and the first doped region are included in a first transistor. In addition, the method includes forming a capacitor structure electrically coupled to the first doped region of the substrate. The method also includes forming a second doped region in the substrate. The second doped region has the second conductivity type, the second doped region functions as a diode with the first well region, and the second doped region is electrically coupled to the first doped region.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. Patent Applications Nos. 17 / 706,789 and 17 / 707,445 (i.e., priority date "March 29, 2022"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor element and a circuit. In particular, it relates to a semiconductor element comprising a diode connected to a transistor and a capacitor structure, and a circuit comprising the semiconductor element. Background Technology

[0004] Dynamic Random Access Memory (DRAM) is a type of random access memory that stores each bit of data in a single capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F... 2 DRAM cells are developed where F represents the minimum lithographic feature width or critical dimension (CD). However, recently, with the continuous reduction of word line pitch, DRAM manufacturers face a significant challenge in reducing the area of ​​memory cells. For example, parasitic capacitance can cause multiple charge losses stored in the capacitor, leading to repeated turning on and off of the transistor to refresh the data stored in the DRAM.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first gate structure, a first doped region, and a capacitor structure. The substrate includes a first well region having a first conductivity type. The first gate structure is disposed on the substrate. The first doped region is disposed in the substrate and has a second conductivity type different from the first conductivity type. The first gate structure and the first doped region are included in a first transistor. The capacitor structure includes a first electrode electrically coupled to the first doped region. The second doped region is disposed in the substrate and has the second conductivity type. The second doped region is electrically coupled to the first electrode and the first doped region of the capacitor structure.

[0007] Another embodiment of this disclosure provides a circuit. The circuit includes a first transistor, a capacitor, and a diode. The first transistor includes a gate configured to receive a control signal to turn the first transistor on or off, and a first source. The capacitor includes a first terminal and a second terminal, the first terminal being electrically connected to the first source of the first transistor, and the second terminal being connected to a first voltage. The diode includes a first terminal and a second terminal, the first terminal being electrically connected to the first source of the first transistor, and the second terminal being connected to a second voltage.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate. The substrate includes a first well region having a first conductivity type. The method further includes forming a first gate structure on the substrate. The method further includes forming a first doped region in the substrate. The first doped region has a second conductivity type different from the first conductivity type. The first gate structure and the first doped region are included in a first transistor. Furthermore, the method includes forming a capacitor structure electrically coupled to the first doped region of the substrate. The method also includes forming a second doped region in the substrate. The second doped region has the second conductivity type, and together with the first well region, it functions as a diode, and the second doped region is electrically coupled to the first doped region.

[0009] The embodiments disclosed herein provide a semiconductor device including a memory cell, a diode, and a transistor. Each of the diode and the transistor is electrically connected to a transistor in the memory cell. The diode switches on when the voltage at a node between the capacitor and the diode is below a threshold voltage. The transistor acts as an equalizer, switching on after the diode has already switched on and pulling up the voltage at the node between the capacitor and the diode. Therefore, the data stored in the memory cell can be automatically refreshed.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0011] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description.

[0012] Figure 1 This is a circuit architecture diagram illustrating semiconductor elements of some embodiments of this disclosure.

[0013] Figure 2A This is a layout diagram illustrating semiconductor elements of some embodiments of this disclosure.

[0014] Figure 2B This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 2A The semiconductor device shown is a cross-section along section line A-A'.

[0015] Figure 2C This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 2A The semiconductor device shown is a cross-section along section line B-B'.

[0016] Figure 2D This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 2A The semiconductor device shown is a cross-section along section line C-C'.

[0017] Figure 2E This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 2A The semiconductor element shown is a cross-section along section line D-D'.

[0018] Figure 3 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0019] Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A This is a cross-sectional schematic diagram illustrating different stages in the fabrication of semiconductor devices according to some embodiments of this disclosure.

[0020] Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B This is a sectional view, illustrating the cross-sections along... Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A The section along line A-A'.

[0021] Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C This is a sectional view, illustrating the cross-sections along... Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A The section along line B-B'.

[0022] Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D This is a sectional view, illustrating the cross-sections along... Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A The cross section with section line C-C'.

[0023] Figure 4E , Figure 5E , Figure 6E , Figure 7E , Figure 8E This is a sectional view, illustrating the cross-sections along... Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A The cross section of section line D-D'.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10: Memory cell

[0026] 100: Circuit

[0027] 110: Transistor

[0028] 112: Gate

[0029] 114: Terminal

[0030] 116: Terminal

[0031] 120: Capacitor

[0032] 122: Terminal

[0033] 124: Terminal

[0034] 130: Diode

[0035] 132: Terminal

[0036] 134: Terminal

[0037] 140: Transistor

[0038] 142: Gate

[0039] 144: Terminal

[0040] 146: Terminal

[0041] 200: Semiconductor components

[0042] 202: Base

[0043] 204: Well Area

[0044] 210: Transistor

[0045] 212: Gate structure

[0046] 214: Doped region

[0047] 216: Doped region

[0048] 218: Gap element

[0049] 220: Capacitor

[0050] 222: Electrode

[0051] 224: Electrode

[0052] 226: Isolation layer

[0053] 230: Diode

[0054] 232: Doped region

[0055] 234: Doped region

[0056] 236: Doped region

[0057] 237: Insulation characteristics

[0058] 238: Well Area

[0059] 240: Transistor

[0060] 242: Gate structure

[0061] 244: Doped region

[0062] 246: Doped region

[0063] 248: Gap element

[0064] 252: Conductive layer

[0065] 254: Conductive layer

[0066] 256: Conductive layer

[0067] 261: Conductive via

[0068] 262: Conductive via

[0069] 263: Conductive via

[0070] 264: Conductive via

[0071] 265: Conductive via

[0072] 266: Conductive via

[0073] 267: Conductive via

[0074] 271: Insulation characteristics

[0075] 272: Insulation Characteristics

[0076] 300: Preparation method

[0077] 302: Steps

[0078] 304: Steps

[0079] 306: Steps

[0080] 308: Steps

[0081] 310: Steps

[0082] 312: Steps

[0083] 314: Steps

[0084] 316: Steps

[0085] 318: Steps

[0086] N1: Node

[0087] N2: Node

[0088] N3: Node

[0089] N4: Node

[0090] N5: Node

[0091] V1: Voltage

[0092] V1': Voltage

[0093] V2: Voltage

[0094] V2': Voltage

[0095] V3: Voltage

[0096] V3': Voltage

[0097] V4': Voltage

[0098] X: Axis

[0099] Y: axis

[0100] Z: Axis Detailed Implementation

[0101] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0102] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0103] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include multiple forms unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0104] Figure 1This is a schematic diagram of a circuit architecture, illustrating circuit 100 in some embodiments of this disclosure. In some embodiments, circuit 100 may include a transistor 110, a capacitor 120, a diode 130, and a transistor 140. In some embodiments, circuit 100 may be included in a memory, memory element, memory die, memory chip, or other element. In some embodiments, circuit 100 may be part of a memory, memory element, memory die, or memory chip. For example, circuit 100 may be a memory cell of a memory, memory element, memory die, memory chip, or other element. In some embodiments, the memory may be a dynamic random access memory (DRAM). In some embodiments, the DRAM may be a fourth-generation double data rate (DDR4) DRAM. In some embodiments, the memory includes one or more memory cells (or memory bits, memory regions).

[0105] It should be understood that circuit 100 may also include other components, such as active and / or passive components, coupled to or connected to transistor 110, capacitor 120, diode 130, and / or transistor 140. Active components include a memory element (e.g., a dynamic random access memory (SRAM) element, a static random access memory (SRAM) element, etc.), a power management element (e.g., a power management integrated circuit (PMIC) element), a logic element (e.g., a system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microprocessor, etc.), a radio frequency (RF) element, a sensor element, a microelectromechanical system (MEMS) element, a signal processing element (e.g., a digital signal processing (DSP) element), a front-end element (e.g., an analog front-end (AFE) element), or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse, or other passive components.

[0106] Transistor 110 may include a gate 112, a terminal 114, and a terminal 116. Gate 112 may be configured to receive a signal, such as a voltage V2, to determine whether transistor 110 is turned on or off. In some embodiments, gate 112 may be configured to receive a control signal (e.g., the signal connected to voltage V2) to turn transistor 110 on or off.

[0107] In some embodiments, terminal 114 may be electrically coupled to or connected to capacitor 120. In some embodiments, terminal 114 may be electrically coupled to or connected to diode 130. In some embodiments, terminal 114 may be electrically coupled to or connected to transistor 140.

[0108] Terminal 116 is configured to receive a signal, such as a voltage V1. For example, when transistor 110 is turned on, terminal 116 is used to receive data to be written to circuit 100.

[0109] In some embodiments, transistor 110 may be an N-type metal-oxide-semiconductor (NMOS). Terminal 114 may be a source of transistor 110. Terminal 116 may be a drain of transistor 110. In some embodiments, transistor 110 may be a P-type metal-oxide-semiconductor (PMOS). Terminal 114 may be a drain of transistor 110. Terminal 116 may be a source of transistor 110.

[0110] Capacitor 120 may include a terminal 122 and a terminal 124. In some embodiments, capacitor 120 may be configured to store charge. In some embodiments, capacitor 120 may be configured to store an unstable charge. In some embodiments, capacitor 120 may be configured to store a potential difference between terminals 122 and 124. In some embodiments, capacitor 120 may be electrically connected between a signal, for example, a voltage V3, and terminal 114 of transistor 110. In some embodiments, capacitor 120 may be electrically connected between voltage V3 and diode 130. In some embodiments, capacitor 120 may be electrically connected between voltage V3 and transistor 140 (e.g., the gate 142 and terminal 144 of the transistor).

[0111] In some embodiments, terminal 122 may be electrically coupled to or connected to transistor 110 (e.g., the gate 142 and terminal 144 of the transistor). In some embodiments, terminal 122 may be electrically coupled to or connected to terminal 114 of transistor 110.

[0112] In some embodiments, terminal 124 may be electrically coupled to or connected to voltage V3. In some embodiments, voltage V3 is electrically connected to ground.

[0113] In some embodiments, transistor 110 and capacitor 120 can be used together as a memory cell 10. For example, during a read operation, a word line electrically coupled to or connected to voltage V1 can be asserted, turning on transistor 110. The actuated transistor 110 allows the voltage across capacitor 120 to be read by a sense amplifier via a bit line electrically coupled to or connected to voltage V2. During a write operation, when the word line is asserted, the data to be written is provided on that bit line.

[0114] In some embodiments, diode 130 may be electrically coupled to or connected to transistor 110. In some embodiments, diode 130 may be electrically coupled to or connected to capacitor 120 (e.g., terminal 122 of transistor 120). In some embodiments, diode 130 may be electrically coupled to or connected to transistor 140. Diode 130 may include a terminal 132 and a terminal 134. In some embodiments, diode 130 may be electrically connected between a signal, such as a voltage V4, and capacitor 120. In some embodiments, diode 130 may be electrically connected between voltage V4 and transistor 110. In some embodiments, diode 130 may be configured to charge capacitor 120.

[0115] In some embodiments, terminal 132 may be a cathode of diode 130. In some embodiments, terminal 132 may be connected to terminal 114 of transistor 110. In some embodiments, terminal 132 may be connected to the source of transistor 110. In some embodiments, terminal 132 may be connected to transistor 140 (e.g., a terminal 144 of transistor 140).

[0116] In some embodiments, terminal 134 may be an anode of diode 130. In some embodiments, terminal 134 may be electrically coupled to or connected to voltage V4. In some embodiments, voltage V4 may be a DC current. In some embodiments, voltage V4 has a voltage level higher than voltage V3.

[0117] In some embodiments, transistor 140 may be electrically coupled to or connected to transistor 110. In some embodiments, transistor 140 may be electrically coupled to or connected to terminal 114 of transistor 110. In some embodiments, transistor 140 may be electrically coupled to or connected to capacitor 120. In some embodiments, transistor 140 may be electrically coupled to or connected to terminal 122 of capacitor 120. In some embodiments, transistor 140 may be electrically coupled to or connected to diode 130. In some embodiments, transistor 140 may be electrically coupled to or connected to voltage V4. In some embodiments, transistor 140 may be electrically connected between voltage V4 and terminal 114 of transistor 110. In some embodiments, transistor 140 may be electrically connected between voltage V4 and terminal 122 of capacitor 120. In some embodiments, transistor 140 may be configured to charge capacitor 120.

[0118] In some embodiments, transistor 140 may include a gate 142, a terminal 144, and a terminal 146. In some embodiments, gate 142 may be configured to receive a signal from diode 130, thereby turning on transistor 140. In some embodiments, gate 142 may be electrically coupled to or connected to terminal 132 of diode 130.

[0119] In some embodiments, terminal 144 may be electrically coupled to or connected to transistor 110. In some embodiments, terminal 144 may be electrically coupled to or connected to terminal 114 of transistor 110. In some embodiments, terminal 144 may be electrically coupled to or connected to capacitor 120. In some embodiments, terminal 144 may be electrically coupled to or connected to terminal 122 of capacitor 120. In some embodiments, terminal 144 may be electrically coupled to or connected to terminal 132 of diode 130.

[0120] In some embodiments, terminal 146 may be configured to receive voltage V4. In some embodiments, transistor 140 may be an NMOS. Terminal 144 may be a source of transistor 140. Terminal 146 may be a drain of transistor 140. In some embodiments, transistor 140 may be a PMOS. Terminal 144 may be a drain of transistor 140. Terminal 146 may be a source of transistor 140.

[0121] like Figure 1 As shown, a node N1 can be connected between terminal 114 of transistor 110 and capacitor 120. A node N2 can be connected between terminal 114 of transistor 110 and diode 130. A node N3 can be connected between terminal 114 of transistor 110 and transistor 140. A node N4 can be connected between diode 130 and transistor 140. A node N5 can be connected between voltage V4 and transistor 140. In some embodiments, the voltage levels of nodes N1, N2, and N3 can be the same.

[0122] In some embodiments, transistor 140 may be an equalizer. In some embodiments, the voltage level of node N3 is equal to the voltage level of node N5. In some embodiments, the voltage level of node N2 is equal to the voltage level of node N5. In some embodiments, the voltage level of node N1 is equal to the voltage level of node N5. In some embodiments, transistor 140 may be turned on after diode 130 has been turned on.

[0123] In some embodiments, voltages V1 and V4 may be connected to the same power supply. In some embodiments, each of voltages V1 and V4 may be 102V or 0V.

[0124] In some embodiments, a higher voltage, such as 1.2V (e.g., logic value "1"), can be input at voltage V2 to turn on transistor 110, thereby writing data "1" or "0" into memory cell 10. Charge or unstable charge can be stored in capacitor 120 to store data "1" or "0". In some cases, parasitic capacitance can cause loss of charge stored in capacitor 120, reducing the potential difference between terminals 122 and 124 of capacitor 120. When the data is "1", nodes N1, N2, and N3 may drop after transistor 110 has already turned on due to junction or cell leakage. To refresh the data "1", the reduced potential difference in capacitor 120 needs to be pulled up.

[0125] In some comparative embodiments, transistor 112 is periodically turned on at node N1 to refresh the data "1". However, frequent on / off switching of transistor 112 increases the power consumption of capacitor 100. According to... Figure 1 In the illustrated embodiment, circuit 100 includes a diode 130 and a transistor 140 connected to memory cell 10, which help pull up the voltage at nodes N1, N2, and N3. In operation, diode 130 is turned off when the voltage at nodes N1, N2, and N3 is 1.2V. As charge loss increases, causing the voltage at nodes N1, N2, and N3 to fall below a first threshold voltage, such as 0.5V, 0.6V, or 0.7V, diode 130 is turned on. When diode 130 is turned on, the voltage at node N4 increases, and transistor 140 is turned on, pulling up the voltage at nodes N1, N2, and N3, thereby automatically refreshing the data "1". When the voltage at nodes N1, N2, and N3 exceeds or equals a second threshold voltage, such as 0.9V, 1V, 1.1V, or 1.2V, diode 130 is turned off. Transistor 140 is automatically turned off. By using diode 130 and transistor 140 to automatically refresh the data "1" at node N1, the transistor 110 does not need to be frequently turned on / off, which reduces the power consumption of circuit 100.

[0126] Figure 2A This is a layout diagram illustrating a semiconductor element 200 according to some embodiments of the present disclosure. Figure 2B , Figure 2C , Figure 2D , Figure 2E This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 2A The semiconductor elements shown are illustrated along cross-sections A-A', B-B', C-C', and D-D', respectively. In some embodiments, the semiconductor element 200 may include a substrate 202, a transistor 210, a capacitor 220, a diode 230, and a transistor 240.

[0127] The substrate 202 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 202 may include an elemental semiconductor, including silicon or germanium in a single crystalline, polycrystalline, or amorphous form; a compound semiconductor material, including at least one of: silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge characteristic, wherein the Si to Ge composition changes from a ratio at one location of the gradient SiGe characteristic to another ratio at another location of the gradient SiGe characteristic. In other embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, a SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 202 may have a multilayer structure, or the substrate 202 may include a multilayer compound semiconductor structure.

[0128] like Figure 2A and Figure 2B As shown, semiconductor device 200 may include a well region 204. In some embodiments, well region 204 may include a first conductivity type. In some embodiments, the first conductivity type is p-type. In some embodiments, the p-type dopant includes boron (B), other group III elements, or any combination thereof. In some embodiments, the first conductivity type is n-type. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), other group V elements, or any combination thereof.

[0129] like Figure 2A and Figure 2B As shown, transistor 210 may include a gate structure 212, a doped region 214, and a doped region 216. Transistor 210 may correspond to... Figure 1 The transistor 110 shown. The gate structure 212 can correspond to, as shown in... Figure 1 The gate 112 is shown. The doped region 214 can be used as a terminal of the transistor 210 and corresponds as shown. Figure 1 Terminal 114 is shown. Doped region 216 can be used as a terminal of transistor 210 and corresponds as shown. Figure 1 Terminal 116 is shown. The pair of doped regions 214 and 216 can also be referred to as a source / drain feature.

[0130] A gate structure 212 may be disposed on a substrate 202. In some embodiments, the gate structure 212 may be electrically connected to a voltage V2'. In some embodiments, the voltage V2 may be connected to, for example, a voltage V2'. Figure 1The voltage V2 shown is the same.

[0131] In some embodiments, the gate structure 212 may include a gate dielectric (not shown) and a gate electrode (not shown). The gate dielectric may have a single-layer or multi-layer structure. In some embodiments, the gate dielectric may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. In some embodiments, the gate dielectric is a multi-layer structure including an interface layer and a dielectric layer with a high dielectric constant (dielectric constant greater than 4). The interface layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. The dielectric layer with a high dielectric constant may include a dielectric material with a high dielectric constant, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric material with a high dielectric constant may also be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, and combinations thereof.

[0132] The gate electrode may be disposed on the gate dielectric. The gate electrode may include polycrystalline silicon, silicon-germanium, and / or at least one metallic material comprising elements and compounds, such as Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, or other suitable conductive materials in the art. In some embodiments, the gate electrode includes a work function metal layer that provides a metal gate having an n-type or p-type work function. Materials comprising the p-type work function include, for example, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or other suitable materials. Materials comprising the n-type work function include, for example, hafnium-zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminum compounds, or other suitable materials.

[0133] Doped region 214 may be disposed in substrate 201. Doped region 244 may be embedded in well region 204. In some embodiments, doped region 214 may be configured to be electrically coupled to capacitor structure 220. In some embodiments, doped region 214 may be configured to be electrically coupled to diode 230. In some embodiments, doped region 214 may be configured to be electrically coupled to transistor 240. In some embodiments, doped region 214 may include a second conductivity type, which is different from the first conductivity type. For example, the first conductivity type may be p-type, and the second conductivity type may be n-type.

[0134] Doped region 216 may be disposed in substrate 202. Doped region 216 may be embedded in well region 204. In some embodiments, doped region 216 may include the second conductivity type. Doped regions 214 and 216 may be disposed on two opposite sides of gate structure 212. In some embodiments, doped region 216 may be configured to be electrically coupled to a signal, such as voltage V1'. In some embodiments, voltage V1' may be coupled to a signal such as... Figure 1 The voltage V1 shown is the same. In some embodiments, the doped region 216 may be electrically coupled to or connected to a bit line of transistor 210 (not shown).

[0135] The semiconductor device may include a spacer 218. The spacer 218 may be disposed on a side surface of the gate structure 212. The spacer 218 may include a single-layer structure or a multilayer structure. The spacer 218 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof.

[0136] like Figure 2A and Figure 2B As shown, capacitor structure 220 may be disposed on substrate 202. In some embodiments, capacitor structure 220 may be configured to couple to doped region 214 of transistor 210. In some embodiments, capacitor structure 220 may be disposed on doped region 214 of substrate 202. In some embodiments, capacitor structure 220 may be directly disposed on doped region 214 of substrate 202. In some embodiments, capacitor structure 220 may include an electrode 222, an electrode 224, and an isolation layer 226. Capacitor structure 220 may correspond to... Figure 1 The capacitor 120. Electrode 222 can be used as a first terminal of the capacitor structure 220 and corresponds as follows: Figure 1 Terminal 122. Electrode 224 can be used as a second terminal of capacitor structure 220 and corresponds as follows: Figure 1 Terminal 124 is shown. In some embodiments, transistor 210 is closer to capacitor structure 220 than transistor 214.

[0137] In some embodiments, electrode 222 may be electrically coupled to or connected to the doped region 214 of transistor 210. In some embodiments, electrode 222 may contact the doped region 214 of transistor 210. Electrode 222 may comprise a semiconductor material or a conductive material. The semiconductor material may comprise polycrystalline silicon or other suitable materials. The isoelectric material may comprise tungsten, copper, aluminum, tantalum, or other suitable materials.

[0138] An insulating layer 226 may surround electrode 224. The insulating layer 226 may separate electrode 222 from electrode 224. The insulating layer 226 may include a dielectric material, such as silicon oxide, tungsten oxide, zirconium oxide, copper oxide, aluminum oxide, hafnium oxide, or the like.

[0139] In some embodiments, electrode 224 may be electrically coupled to or connected to a signal, such as voltage V3'. Electrode 224 may be separated from electrode 222 by an isolation layer 226. Electrode 224 may comprise a semiconductor material or a conductive material. The semiconductor material may comprise polysilicon or other suitable materials. The conductive material may comprise tungsten, copper, aluminum, tantalum, or other suitable materials. In some embodiments, voltage V3' may be ground.

[0140] like Figure 2A , Figure 2C , Figure 2D , Figure 2E As shown, diode 230 may be disposed in substrate 202. In some embodiments, doped region 232 may be configured to be electrically coupled or connected to transistor 210. In some embodiments, doped region 232 may be configured to be electrically coupled or connected to doped region 216 of transistor 210. In some embodiments, doped region 232 may be configured to be electrically coupled to capacitor structure 220. In some embodiments, doped region 232 may be configured to be electrically coupled to electrode 222 of capacitor structure 220. In some embodiments, doped region 232 may be configured to be electrically coupled to transistor 240. In some embodiments, doped region 232 may be configured to be electrically coupled to gate (e.g., gate structure 242) of transistor 240. In some embodiments, doped region 214 may include a second conductivity type. In some embodiments, a portion of well region 204 and doped region 232 may together serve as diode 230. In some embodiments, the doping concentration of doped region 232 may exceed the doping concentration of well region 204. In some embodiments, doped region 232 may serve as a terminal and correspond to as shown in the figure. Figure 1 Terminal 132 is shown.

[0141] In some embodiments, semiconductor device 200 may include a doped region 234. Doped region 234 may be disposed in substrate 202. In some embodiments, in a top view, doped region 234 may surround doped region 232. In some embodiments, doped region 234 may have a first conductivity type. In some embodiments, doped region 234 may be configured to be electrically coupled to a terminal (e.g., doped region 246) of transistor 240. In some embodiments, the doping concentration of doped region 234 may exceed the doping concentration of well region 204. In some embodiments, doped region 234 may be electrically connected to a voltage V4'. In some embodiments, voltage V4' may be a DC voltage. In some embodiments, the voltage level of voltage V4' may be greater than the voltage level of voltage V3'.

[0142] In some embodiments, the semiconductor element 200 may include an insulating feature 271. The insulating feature 271 may be disposed in the substrate 202. In some embodiments, the insulating feature 271 may surround a doped region 234. In some embodiments, the insulating feature 271 may be a shallow trench isolation (STI). In other embodiments, the insulating feature 271 may include a structure of localized silicon oxide (LOCOS) or any other suitable insulating structure.

[0143] In some embodiments, semiconductor device 200 may include a doped region 236. Doped region 236 may be disposed in substrate 202. In some embodiments, doped region 236 may be disposed beneath insulating feature 271. In some embodiments, in a top view, doped region 236 may surround doped region 234. In some embodiments, doped region 236 may have a second conductivity type.

[0144] In some embodiments, semiconductor element 200 may include a well region 238. Well region 238 may be included in substrate 202. In some embodiments, well region 238 may be disposed below doped region 236. In some embodiments, well region 238 may be separated from doped region 234 by well region 204. In some embodiments, well region 238 may be separated from doped region 232 by well region 204. In some embodiments, well region 238 may have a second conductivity type. In some embodiments, the doping concentration of well region 238 may be less than the doping concentration of doped region 236. In some embodiments, insulating feature 237, doped region 236, and well region 238 may be configured to provide a conductive path between diode 230 and transistor 210 (or 240) via substrate 202.

[0145] like Figure 2A , Figure 2B , Figure 2C as well as Figure 2E Transistor 240 may include a gate structure 242, a doped region 244, and a doped region 246. Transistor 240 may correspond to, for example... Figure 1 Transistor 142 is shown. Doped region 244 can be used as a terminal of transistor 240 and corresponds as shown. Figure 1 Terminal 144 is shown. Doped region 246 can be used as a terminal of transistor 240 and corresponds as shown. Figure 1 Terminal 146 is shown. The pair of doped regions 244 and 246 can also be considered as a source / drain feature.

[0146] Gate structure 242 may be disposed on substrate 202. In some embodiments, gate structure 242 may include a gate dielectric (not shown) and a gate electrode (not shown). In some embodiments, the material of gate structure 242 may be the same as or similar to the material of gate structure 212.

[0147] Doped region 244 may be disposed in substrate 202. Doped region 244 may be embedded in well region 204. In some embodiments, doped region 244 may be configured to be electrically coupled to doped region 214 of transistor 210. In some embodiments, doped region 244 may be configured to be electrically coupled to electrode 222 of capacitor structure 220. In some embodiments, doped region 244 may include a second conductivity type. In some embodiments, doped region 244 may be separated from doped region 214 by an insulating feature 272.

[0148] Doped region 246 may be disposed in substrate 202. Doped region 246 may be embedded in well region 204. In some embodiments, doped region 246 may include a second conductivity type. Doped regions 244 and 246 may be disposed on opposite sides of gate structure 242.

[0149] The semiconductor device may include a spacer 248. The spacer 248 may be disposed on a side surface of the gate structure 242. The spacer 248 may include a single-layer or multi-layer structure. The spacer 248 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof.

[0150] like Figure 2A As shown, the semiconductor device 200 may include conductive layers 252, 254, and 256. Conductive layers 252, 254, and 256 may be disposed on the substrate 202. Conductive layers 252, 254, and 256 may be located at the same elevation height. Conductive layers 252, 254, and 256 may include conductive materials, such as tungsten, copper, aluminum, tantalum, or other suitable materials.

[0151] like Figure 2A , Figure 2B and Figure 2C As shown, the conductive layer 252 can be configured to electrically connect the doped region 214, the doped region 232, the gate structure 242, and the doped region 244 to each other.

[0152] like Figure 2A and Figure 2E As shown, the conductive layer 254 can be configured to electrically connect the doped regions 234 and 246.

[0153] like Figure 2A and Figure 2B As shown, the conductive layer 256 can be configured to electrically connect the doped region 216 to the voltage V1'.

[0154] like Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2ESemiconductor element 200 may include conductive vias 261, 262, 263, 264, 265, 266, and 267. Conductive vias 261, 262, 263, 264, 265, 266, and 267 may include a pad layer (not shown), a barrier layer (not shown), and a conductive layer (not shown). The pad layer may include oxides or other suitable materials. The barrier layer may include titanium, tantalum, titanium nitride, tantalum nitride, manganese nitride, or combinations thereof. The conductive layer may include metals such as tungsten, copper, aluminum, tantalum, alloys thereof, or combinations thereof.

[0155] like Figure 2B As shown, the conductive via 261 can be configured to electrically connect the doped region 216 and the conductive layer 256.

[0156] like Figure 2B As shown, the conductive via 262 can be configured to electrically connect the doped region 216 and the conductive layer 252.

[0157] like Figure 2B As shown, the conductive via 263 can be configured to electrically connect the doped region 244 and the conductive layer 252.

[0158] like Figure 2B As shown, the conductive via 264 can be configured to electrically connect the doped region 246 and the conductive layer 254.

[0159] like Figure 2C As shown, the conductive via 265 can be configured to electrically connect the doped region 232 and the conductive layer 252.

[0160] like Figure 2C As shown, the conductive via 266 can be configured to electrically connect the gate structure 242 and the conductive layer 252.

[0161] like Figure 2E As shown, the conductive via 267 can be configured to electrically connect the doped region 234 and the conductive layer 254.

[0162] In some embodiments, such as Figure 2A As shown, the doped region 232 can be aligned along the Y-axis with the gate structure 242 of the transistor 240. In some embodiments, such as Figure 2B As shown, capacitor structure 220 can be disposed along the X-axis between gate structure 212 of transistor 210 and gate structure 242 of transistor 240.

[0163] In some embodiments, transistor 210 and capacitor structure 220 can be used as a memory cell. Charge or unstable charge can be stored in capacitor structure 220 to store data "1" or "0". In some cases, parasitic capacitance can cause loss of charge stored in capacitor 220, reducing the potential difference between terminals 222 and 224 of capacitor 220. When the data is "1", the potential difference of capacitor structure 220 may drop after transistor 110 has been turned off. To refresh the data "1", the reduced potential difference of capacitor 220 needs to be pulled up. In this embodiment, semiconductor element 200 also includes diode 230 and transistor 240, which can assist in pulling up the potential difference of capacitor 220. In this embodiment, diode 230 will conduct when the voltage at a node between diode 230 and capacitor 220 is below a threshold voltage. After diode 230 has conducted, transistor 240 will conduct to pull up the potential difference of capacitor structure 220, thereby automatically refreshing the data "1".

[0164] Figure 3 This is a flowchart illustrating a method 300 for fabricating a semiconductor element according to some embodiments of this disclosure.

[0165] Preparation method 300 begins with step 302, which involves providing a substrate. A first well region may be formed within the substrate. The first well region has a first conductivity type.

[0166] The fabrication method 300 continues with step 304, which involves forming a first transistor. The first transistor may include a gate structure and a first doped region. The gate structure may be electrically coupled to or connected to a word line of the semiconductor device. The first doped region may include a second conductivity type, which is different from the first conductivity type.

[0167] The fabrication method 300 continues with step 306, which involves forming a capacitor structure. The capacitor structure may be formed on the substrate. The capacitor structure may include a first electrode and a second electrode. The first electrode of the capacitor structure may be electrically connected to the second terminal of the first transistor. The second electrode of the capacitor structure may be electrically coupled to or connected to a first electrode, which may be grounded. The first transistor and the capacitor structure may be used together as a memory element.

[0168] The fabrication method 300 continues with step 308, which involves forming a second doped region. This second doped region may include the second conductivity type. The second doped region, together with a portion of the first well region, may function as a diode. The second doped region may be electrically coupled to or connected to a node between the first transistor and the capacitor structure.

[0169] The preparation method 300 continues with step 310, which involves forming a third doped region. The third doped region may include the first conductivity type. The third doped region may surround the second doped region. The third doped region may be separated from the second doped region by the first well region.

[0170] The preparation method 300 continues with step 312, which involves forming a fourth doped region. This fourth doped region may include the second conductivity type. The fourth doped region may surround the second doped region. The fourth doped region may be formed under an insulating feature, such as an STI (Surface Insulation Technology).

[0171] The preparation method 300 continues with step 314, which involves forming a second well region. The second well region may include the second conductivity type. The second well region may be disposed below the fourth doped region. The second well region may be separated from the second doped region by the first well region. The second well region may be separated from the third doped region by the first well region.

[0172] The fabrication method 300 continues with step 316, which involves forming a second transistor. This second transistor can be used as an equalizer. Forming the second transistor may include forming a second gate structure, a fifth doped region, and a sixth doped region. The fifth doped region may include the second conductivity type. The fifth doped region may be electrically coupled to or connected to the second doped region. The sixth doped region may include the second conductivity type. The sixth doped region may be electrically connected to the third doped region.

[0173] The fabrication method 300 continues with step 318, which involves forming a first conductive layer and a second conductive layer. The first conductive layer may be formed on the substrate. The first conductive layer may be configured to electrically couple the first doped region, the second gate structure, the fifth doped region, and the second doped region to each other. The second conductive layer may be configured to electrically couple the sixth doped region to the third doped region.

[0174] Preparation method 300 is merely an example and is not intended to limit this disclosure beyond what is expressly recited in the claims. Additional steps may be provided before, during, or after each step of preparation method 300, and for such additional embodiments of the preparation method, some described steps may be replaced, eliminated, or moved. In some embodiments, preparation method 300 may also include steps not explicitly stated in the claims. Figure 3 Some of the steps described. In some embodiments, preparation method 300 may include in Figure 3 The one or more steps described.

[0175] Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8AThis is a cross-sectional schematic diagram illustrating different stages in the fabrication of semiconductor devices according to some embodiments of this disclosure. Figures 4B to 8B , Figures 4C to 8C , Figures 4D to 8D , Figures 4E to 8E This is a sectional view diagram, illustrating the sections along the sections A-A', B-B', C-C', and D-C' respectively.

[0176] like Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E As shown, a substrate 202 is provided. The substrate 202 may include a well region 204. The well region 204 may include a first conductivity type. Insulating features 271 and 272 may be formed in the substrate 202. In some embodiments, an etching process may be performed to form a plurality of trenches recessed from the upper surface of the substrate 202, and then a dielectric material, such as silicon oxide, may be deposited to fill the trenches, thereby forming the insulating features 271 and 272.

[0177] like Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E As shown, gate structures 212 and 242 can be formed on substrate 202. Each of gate structures 212 and 242 may include a gate dielectric and a gate electrode. The fabrication techniques for the gate dielectric and the gate electrode may include chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), flowable CVD (FCVD), or other suitable processes. A spacer 218 may be formed on the sidewall of gate structure 212. A spacer 248 may be formed on the sidewall of gate structure 242. Spacers 218 and 248 may include multiple layers, each of which may be fabricated using techniques including CVD, PECVD, FCVD, or other suitable processes.

[0178] like Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E As shown, doped regions 214, 216, 232, 244, and 246 can be formed to create a transistor 210, a diode 230, and a transistor 240. Doped regions 214, 216, 232, 244, and 246 can have a second conductivity type, which is different from the first conductivity type. Furthermore, a doped region 236 can be formed under insulating feature 271. A well region 238 can be formed under doped region 236. A doped region 234 can be formed in substrate 202. Doped region 234 can have a first conductivity type.

[0179] like Figure 7A , Figure 7B , Figure 7C , Figure 7D and Figure 7E As shown, conductive vias 261, 262, 263, 264, 265, 266, and 267 can be formed. Furthermore, conductive layers 252, 254, and 256 can be formed. The fabrication techniques for conductive layers 252, 254, and 256 may include sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical plating (ECP), electrodeposition (ELD), atomic layer deposition (ALD), or similar processes or combinations thereof.

[0180] like Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E As shown, an electrode 222, an electrode 224, and an isolation layer 226 can be formed to define a capacitor structure 220 on the substrate 200, thereby forming a semiconductor element 200.

[0181] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first gate structure, a first doped region, and a capacitor structure. The substrate includes a first well region having a first conductivity type. The first gate structure is disposed on the substrate. The first doped region is disposed in the substrate and has a second conductivity type different from the first conductivity type. The first gate structure and the first doped region are included in a first transistor. The capacitor structure includes a first electrode electrically coupled to the first doped region. The second doped region is disposed in the substrate and has the second conductivity type. The second doped region is electrically coupled to the first electrode and the first doped region of the capacitor structure.

[0182] Another embodiment of this disclosure provides a circuit. The circuit includes a first transistor, a capacitor, and a diode. The first transistor includes a gate configured to receive a control signal to turn the first transistor on or off, and a first source. The capacitor includes a first terminal and a second terminal, the first terminal being electrically connected to the first source of the first transistor, and the second terminal being connected to a first voltage. The diode includes a first terminal and a second terminal, the first terminal being electrically connected to the first source of the first transistor, and the second terminal being connected to a second voltage.

[0183] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate. The substrate includes a first well region having a first conductivity type. The method further includes forming a first gate structure on the substrate. The method further includes forming a first doped region in the substrate. The first doped region has a second conductivity type different from the first conductivity type. The first gate structure and the first doped region are included in a first transistor. Furthermore, the method includes forming a capacitor structure electrically coupled to the first doped region of the substrate. The method also includes forming a second doped region in the substrate. The second doped region has the second conductivity type, and together with the first well region, it functions as a diode, and the second doped region is electrically coupled to the first doped region.

[0184] The embodiments disclosed herein provide a semiconductor device including a memory cell, a diode, and a transistor. Each of the diode and the transistor is electrically connected to a transistor in the memory cell. The diode switches on when the voltage at a node between the capacitor and the diode is below a threshold voltage. The transistor acts as an equalizer, switching on after the diode has already switched on and pulling up the voltage at the node between the capacitor and the diode. Therefore, the data stored in the memory cell can be automatically refreshed.

[0185] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0186] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor device, comprising: A substrate is provided, wherein the substrate includes a first well region having a first conductivity type; A first gate structure is formed on the substrate; A first doped region is formed in the substrate, wherein the first doped region has a second conductivity type different from the first conductivity type, and the first gate structure and the first doped region are contained in a first transistor; Forming a capacitor structure to be electrically coupled to the first doped region of the substrate; and A second doped region is formed in the substrate, wherein the second doped region has the second conductivity type, the second doped region together with the first well region is used as a diode, and the second doped region is electrically coupled to the first doped region; A third doped region is formed in the substrate, wherein the third doped region has the first conductivity type, and wherein the third doped region surrounds the second doped region.

2. The method for fabricating a semiconductor device as claimed in claim 1 further includes forming a fourth doped region in the substrate, wherein the fourth doped region has the second conductivity type, and wherein the fourth doped region surrounds the third doped region.

3. The method for fabricating a semiconductor device as claimed in claim 2 further includes forming a second well region in the substrate, wherein the second well region is separated from the third doped region by the first well region.

4. The method for preparing a semiconductor device as described in claim 3, further comprising: A second gate structure is formed on the substrate; A fifth doped region is formed in the substrate, wherein the fifth doped region has the second conductivity type; as well as A sixth doped region is formed in the substrate, wherein the sixth doped region has the second conductivity type, and the second gate structure, the fifth doped region, and the sixth doped region are contained in a second transistor; The second gate structure is electrically coupled to the second doped region of the diode and to the first doped region of the first transistor.

5. The method for fabricating a semiconductor device as claimed in claim 4, further comprising forming a first conductive layer on the substrate, wherein the first conductive layer is configured to electrically connect the first doped region, the second gate structure, the fifth doped region, and the second doped region to each other.

6. The method for fabricating a semiconductor device as claimed in claim 5 further includes forming a second conductive layer on the substrate, wherein the second conductive layer is configured to electrically connect the sixth doped region and the third doped region.

7. The method for fabricating a semiconductor element as claimed in claim 4, wherein the second transistor is used as an equalizer.

8. The method for fabricating a semiconductor element as claimed in claim 1, wherein forming the capacitor structure comprises: A first electrode is formed to contact the first doped region of the substrate; as well as A second electrode is formed around the first electrode.

9. The method for fabricating a semiconductor element as claimed in claim 8, wherein the second electrode is electrically connected to a first voltage, the third doped region is electrically connected to a second voltage, and the second voltage has a voltage level higher than the first voltage.

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