Temperature sensor for non-volatile memory

Abstract

Embodiments of the present disclosure provide a temperature sensor that can be integrated with a 1T1C reference voltage generator into a memory device to enable the 1T1C reference voltage generator to provide a temperature-dependent 1T1C reference voltage to a memory core (e.g., an F-RAM memory core) of the memory device. The temperature sensor can detect a temperature of the memory core and output information (e.g., as a trim) for use by the 1T1C reference voltage generator in providing the temperature-dependent 1T1C reference voltage. In this way, both the P-term margin and the U-term margin of the memory core can be maintained even when the temperature of the memory core increases.

Description

[0001] Cross-references to related applications

[0002] This application is an international application of U.S. Nonprovisional Application No. 17 / 219,160, filed March 31, 2021, which claims priority to U.S. Provisional Patent Application No. 63 / 153,412, filed February 25, 2021, all of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to non-volatile (NV) memory devices, and more specifically, to temperature sensors for implementing temperature-dependent single-ended sensing, such as the generation of a single-transistor single-capacitor (hereinafter referred to as "1T1C") reference voltage for ferroelectric random access memory (F-RAM) devices. Background Technology

[0004] Memory that retains its data even when operating power is unavailable is classified as NV memory. Examples of NV memory are non-volatile SRAM (nvSRAM), F-RAM, electrically erasable programmable read-only memory (EE-PROM), and flash memory. This type of memory can be used in applications where critical data must be stored after power is removed or during power interruptions during operation.

[0005] In some implementations, such as in an F-RAM device, 1T1C refers to a memory cell architecture utilizing single-ended sensing, the opposite of the differential sensing used in 2T2C. More specifically, the sensing operation of the sensing amplifier in the 1T1C architecture compares the amplitude of the memory signal output from the first memory cell with a reference signal. The 1T1C F-RAM architecture is advantageous because it results in a smaller cell size compared to a dual-transistor dual-capacitor (2T2C) F-RAM architecture. A non-switching term (U term) is the charge generated on the F-RAM ferroelectric capacitor after a voltage or electric field is applied, without involving polarization switching. A switching term (P term) is the charge generated when polarization switching is present. In a 1T1C configuration, a U term can represent data "0" and a P term can represent data "1," or in some implementations, a U term can represent data "1" and a P term can represent data "0."

[0006] For 1T1C F-RAM, a reference voltage is needed to distinguish between switched (P) and non-switched (U) terms in order to differentiate data "0" from data "1". For example, a temperature-independent 1T1C reference voltage can be generated from a programmable metal-oxide-semiconductor (MOS) capacitor array. The 1T1C reference voltage must be programmed to reference a value higher than the maximum U term and lower than the minimum P term in order to correctly distinguish between data "0" and data "1". Attached Figure Description

[0007] The embodiments are illustrated in the accompanying drawings by way of example rather than limitation.

[0008] Figure 1 This is a diagram illustrating a temperature sensor according to some embodiments of the present disclosure.

[0009] Figure 2 This is a graph showing the comparator outputs representing different temperature zones according to some embodiments of the present disclosure.

[0010] Figure 3 The graph shows the P-term margin and U-term margin in the memory core when using an implementation of the present disclosure with a temperature-independent 1T1C reference voltage and a temperature-dependent 1T1C reference voltage.

[0011] Figure 4 This is a diagram illustrating a temperature sensor according to some embodiments of the present disclosure.

[0012] Figure 5 This illustrates some embodiments according to this disclosure. Figure 4 Block diagram of the temperature sensor.

[0013] Figure 6A This illustrates some embodiments according to this disclosure. Figure 5 A graph showing the performance of the temperature sensor.

[0014] Figure 6B This illustrates some embodiments according to this disclosure. Figure 5 The graph shows the relationship between the sensor's temperature, the counter's digital output, and VCount.

[0015] Figure 7A A memory device in which embodiments of the present disclosure can be implemented is shown.

[0016] Figure 7B A memory device in which embodiments of the present disclosure can be implemented is shown.

[0017] Figure 8 This is a flowchart of a method for providing a temperature-dependent 1T1C reference voltage according to some embodiments of the present disclosure. Detailed Implementation

[0018] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of this embodiment. However, it will be apparent to those skilled in the art that this embodiment can be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail but are illustrated in block diagrams to avoid unnecessarily obscuring the understanding of the description.

[0019] The reference to "one embodiment" or "implementation" in this specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. The phrase "in one embodiment" appearing in various locations throughout this specification does not necessarily refer to the same embodiment.

[0020] The temperature-independent sensing or read reference voltage is fixed and determined based on the P-term and / or U-term at a specific temperature or temperature range, but does not change with temperature. For example, the 1T1C reference voltage can be set to 21mV above the room temperature U-term. However, as the temperature of the F-RAM memory core increases, the P-term memory margin may gradually decrease, causing the P-term margin and U-term margin to become inconsistent during temperature changes (see [link to relevant documentation]). Figure 3 In other NVM devices, the sensing reference voltage can be fixed based on other characteristics of the NVM cell, such as drain current and flash memory threshold voltage.

[0021] Existing 2T2C solutions employing differential sensing do not require a sensing reference voltage, while other alternative solutions involve limiting the use of 1T1C cells until industrial temperatures (e.g., 85 degrees Celsius) are reached and macro-adjusting the 1T1C reference voltage for all 1T1C cells. However, 2T2C solutions are not area efficient and therefore reduce memory density, typically by half. Other previous implementations have been proposed that utilize conventional silicon-based temperature sensor designs based on bandgap circuitry used for temperature sensors. However, these approaches involve high levels of design complexity, slow startup times, high standby current, and require large layout areas.

[0022] Embodiments of this disclosure provide systems and apparatus (temperature sensors) that can adjust the 1T1C reference voltage to take into account the temperature behavior of the F-RAM memory. Although F-RAM memory and 1T1C architecture have been described for illustrative purposes, embodiments of this disclosure are not limited to this approach and can be applied to memory devices having memory cores based on any suitable type of NV memory and any suitable architecture.

[0023] In one embodiment, a temperature sensor is provided, comprising a resistor circuit including an n-well resistor and a silicide-blocked polysilicon resistor. The n-well resistor has a significant positive temperature coefficient. In contrast, the polysilicon resistor has a small temperature coefficient close to zero. The reference voltage of the temperature sensor can increase with increasing memory core temperature, while the input voltage of the temperature sensor will decrease with increasing memory core temperature. The temperature sensor also includes a resistor stack with eight taps, such that when current flows through the stack, the voltage at each tap is lower than the tap above it. Each tap is connected to a corresponding comparator. Given an appropriate ratio between the resistors in the resistor circuit, the comparator output will change at specific temperatures, thereby defining nine different temperature zones. These outputs are used to adjust the ITC reference voltage supplied to the memory core to compensate for increased temperature of the memory core based on the indicated temperature zone.

[0024] Figure 1 This is a diagram illustrating a temperature sensor 100 (hereinafter referred to as "sensor 100") for sensing the temperature of a memory core (e.g., F-RAM memory core 705 as shown in FIG. 7). Sensor 100 may be integrated with a 1T1C reference voltage generator (e.g., F-RAM 1T1C reference voltage generator 715 as shown in FIG. 7) to provide a temperature-dependent 1T1C reference voltage (hereinafter referred to as 1T1C Vref) to the memory core based on the sensed temperature of the memory core. In one embodiment, sensor 100 may be arranged physically adjacent to the memory core such that sensor 100 and the memory core are exposed to substantially the same temperature range. Sensor 100 may include resistors 105 and 110, and resistors 115 and 120 (resistors 105 to 120 may together form a resistor circuit such as a resistor ladder). Resistors 105 and 110 can be N-well resistors or other resistor devices known in the art with a large positive temperature coefficient (i.e., the resistance values ​​of resistors 105 and 110 can vary significantly with the temperature of the memory core). Conversely, resistors 115 and 120 can be silicide-blocked polysilicon resistors or other resistor devices with a small temperature coefficient close to zero relative to the temperature coefficient of resistors 105 and 110. In other words, the resistance values ​​of resistors 115 and 120 may not vary significantly with the temperature of the memory core. Figure 1As shown, resistors 105 to 120 can be coupled together such that the resistance of resistor 105 increases as the temperature of the memory core increases, resulting in an increase in the reference voltage (Vref) of sensor 100. Simultaneously, an increase in the temperature of the memory core can increase the resistance of resistor 110 while the resistance of resistor 120 remains constant, resulting in a decrease in voltage at node 150. This configuration of resistors with different temperature coefficients (e.g., between resistors 105 and 120) allows Vref to increase as the temperature of the memory core increases. It should be noted that Vref refers to the reference voltage of sensor 100 and should be distinguished from the sensing / readout or 1T1C Vref generated by, for example, the F-RAM 1T1C reference voltage generator 715 as shown in Figure 7.

[0025] Sensor 100 may also include a resistor stack 125 located or coupled between resistors 110 and 120. Resistor stack 125 may also be an N-well resistor and may include multiple taps T1 to T8, and the voltage at each tap T1 to T8 (VT1 to VT8) may be lower than the voltage at the tap above it (e.g., VT2 is lower than VT1) as current flows toward ground 160 through resistor stack 125. Although eight taps are shown, resistor stack 125 may include any suitable number of taps, as discussed in further detail herein. Each tap T1 to T8 (also referred to herein as resistor divider points) is connected to a corresponding comparator 130A to 130H, which compares the voltage at the corresponding tap to Vref. As discussed above, as the temperature of the memory core increases, Vref may increase and the voltage at node 150 may decrease based on the ratio of the resistance values ​​among resistors 105 to 115. As a result, as the temperature of the memory core increases, VT at each tap point T1 to T8 can decrease, such that over time, when the VT of each successive comparator 130A to 130H decreases below Vref, the comparator output will change at a specific temperature (e.g., from "0" to "1" or from "low" to "high"), as... Figure 3 As shown. In this way, the outputs of comparators 130A to 130H can be defined in nine different temperature zones, as discussed in further detail herein.

[0026] Figure 2The diagram illustrates the output of each comparator 130 as the temperature of the memory core increases. Because tap T1 is the first tap in resistor ladder 125, the voltage at tap T1 is the highest among all taps T1 to T8. Therefore, the corresponding input voltage to comparator 130A is the highest among all comparators 130A to 130H. As can be seen, when the temperature of the memory core reaches 9 degrees, VT1 can drop below Vref, and comparator 130A can change its output from one binary state to another, for example, from "0" to "1". Similarly, when the temperature of the memory core reaches 25 degrees, VT2 can drop below Vref, and comparator 130B can change its output from "0" to "1". As the temperature of the memory core continues to increase, the number of comparators 130A to 130H with "1" as an output can increase. In this way, the outputs of multiple comparators 130A to 130H can define multiple temperature zones. For example, if the outputs of comparators 130A and 130B are "1" (while the outputs of the remaining comparators 130 are "0"), this corresponds to a temperature range of 25 to 39 degrees Celsius. If the outputs of comparators 130A, 130B, 130C, and 130D are "1", this corresponds to a temperature range of 54 to 77 degrees Celsius. It should be noted that the resolution of the temperature range can be increased by increasing the number of taps T in resistor ladder 125 and the number of comparators 130A to 130H.

[0027] As discussed further in detail herein, sensor 100 can be integrated with a 1T1C reference voltage generator (e.g., F-RAM 1T1C reference voltage generator 715) as part of a memory device (e.g., memory device 700 as shown in FIG. 7), such that the outputs of comparators 130A to 130H can be used as fine-tuning to adjust the 1T1C Vref (i.e., the reference voltage generated by the 1T1C reference voltage generator) based on an indicated temperature zone to compensate for the effects caused by temperature variations in the memory core. As discussed above, the outputs of sensor 100 (i.e., the outputs of the plurality of comparators 130) can define multiple temperature zones. In one embodiment, the 1T1C reference voltage generator can adjust the 1T1C reference voltage based on the output signals received from the plurality of comparators 130A to 130H. For example, when the outputs of comparators 130A and 130B are "1" (while the outputs of the remaining comparators 130 are "0"), this corresponds to a temperature range of 25 to 39 degrees Celsius, and the 1T1C reference voltage generator can adjust the 1T1C reference voltage accordingly. If the outputs of comparators 130A, 130B, 130C, and 130D are "1" (while the outputs of the remaining comparators 130 are "0"), this corresponds to a temperature range of 54 to 77 degrees Celsius. It should be noted that the temperature ranges discussed herein are for illustrative purposes only, and the temperature ranges can be defined with any suitable desired resolution.

[0028] Regarding the adjustment of 1T1C Vref, the 1T1C reference voltage generator can be implemented using any suitable method. In one example, the 1T1C reference voltage generator may include a set of capacitor cells that control 1T1C Vref. The output of sensor 100 can control the removal or addition of capacitor cells from the 1T1C reference voltage generator, causing it to increase or decrease 1T1C Vref as needed. In other embodiments, the output of sensor 100 can be used to adjust or regulate the strength of other single-ended sensing reference signals of other types of memory technologies (e.g., flash memory, R-RAM, M-RAM, floating gate memory, etc.) for temperature compensation.

[0029] Figure 3A graph 300 shows the P-term (shown as curve 315 with squares) and U-term (shown as curve 320 with circles) of the F-RAM memory core (in mV) relative to temperature. Graph 300 also shows a temperature-independent (i.e., constant) 1T1C Vref 305 generated with or without embodiments of this disclosure and a temperature-dependent 1T1C Vref 310 generated according to embodiments of this disclosure. As can be seen, the P-term 315 of the F-RAM cells in the memory core gradually decreases as the temperature of the memory core increases. Therefore, using the temperature-independent 1T1C Vref 305, the sensing margin between the P-term 315 and the 1T1C Vref 305 also gradually decreases as the temperature of the memory core increases. As a result, the ability to distinguish data "1" decreases as the temperature of the memory core increases. However, 1T1C Vref 310 is temperature-dependent and is controlled by the output of sensor 100 (or, as described further herein, sensor 400 in some embodiments) and decreases as the temperature of the memory core increases. In this way, a margin is maintained between P item 315 and 1T1C Vref 310. Figure 3 In the example, when using 1T1C Vref 310, the P-term margin at 125 degrees Celsius can be twice the P-term margin at the same temperature when using 1T1C Vref 305.

[0030] While sensor 100 can be used to achieve varying and temperature-dependent 1T1C Vref, adjusting resistor ladder 125 to achieve outputs with desired temperature intervals can be challenging, especially when each comparator 130 has a different voltage offset and / or a higher resolution is desired (e.g., more comparators 130 are required). Figure 4 A temperature sensor 400 (hereinafter referred to as "sensor 400") for sensing the temperature of a memory core (e.g., the F-RAM memory core 705 shown in Figure 7) is illustrated, which overcomes the limitations of using... Figure 1 The aforementioned problems of sensor 100. According to some embodiments of this disclosure, when integrated with a 1T1C reference voltage generator (e.g., F-RAM 1T1C reference voltage generator 715) as part of a memory device (e.g., memory device 700 as shown in FIG. 7), the output of sensor 400 can be used by the 1T1C reference voltage generator to provide the temperature variable 1T1C Vref.

[0031] Sensor 400 may include resistors 405 and 410, and resistors 415 and 420. Resistors 405 to 420 may form a resistor circuit 407 (e.g., a resistor ladder). Resistors 405 and 410 may be N-well resistors or other resistive devices with a large positive temperature coefficient (i.e., the resistance values ​​of resistors 405 and 410 may change significantly with temperature). In contrast, resistors 415 and 420 may be silicide-blocked polysilicon resistors or other resistive devices with a small temperature coefficient close to zero relative to the temperature coefficient of resistors 405 and 410. In other words, the resistance values ​​of resistors 415 and 420 may not change significantly with the temperature of the memory core. Resistors 405 to 420 may be in a manner similar to... Figure 1 Resistors 105 to 120 are coupled together such that as the temperature of the memory core increases, the resistance of resistor 405 can also increase, resulting in an increase in the voltage (VCount) at node 450. Node 450 can represent the dividing point between resistor 405 and resistor 415. Simultaneously, an increase in the temperature of the memory core can cause an increase in the resistance of resistor 410, while the resistance of resistor 420 remains constant, resulting in a decrease in the reference voltage (Vref) of sensor 400. The voltage at the bottom of resistor 415 can increase with increasing temperature, causing an increase in the resistance of resistor 405. The voltage at the top of resistor 420 can decrease with increasing temperature of the memory core, causing an increase in the resistance of resistor 410. However, as discussed further in detail herein, resistor 405 can be a variable resistor, which can be adjusted or configured to adjust the input voltage to comparator 425 (i.e., as...). Figure 4 The Vref and VCount shown are equal, indicating the state that can determine the current temperature of the memory core. It should be noted that Vref refers to the reference voltage of sensor 400 and should be distinguished from 1T1CVref generated by, for example, the F-RAM 1T1C reference voltage generator 715 shown in Figure 7.

[0032] As discussed above, as the temperature of the memory core increases, Vref can gradually decrease, while VCount gradually increases. Therefore, in order for Vref and VCount to be equal, the resistance of resistor 405 must decrease as the temperature of the memory core increases. Therefore, sensor 400 may also include comparator 425, which can receive the output voltages (Vref and VCount) of resistor circuit 407 as input. Sensor 400 may also include an increment / decrement counter logic block 430 (hereinafter referred to as counter 430), which can be coupled to comparator 425 to form a feedback loop, thereby enabling control of resistor 405, as discussed further in detail herein. Counter 430 can maintain a count value based on the output of comparator 425 and can output the current value of the count. More specifically, as the temperature of the memory core increases, Vref can gradually decrease, while VCount gradually increases, and therefore when VCount is currently higher than Vref, the output of comparator 425 can be "1" ("high"). In response to receiving an input of 1 from comparator 425, counter 430 can increment the count (incrementing the current count value). If VCount is lower than Vref, the output of comparator 425 can be "0" ("low"), and counter 430 can decrement the count (decreasing the current count value) based on receiving an input of 0. Counter 430 can operate based on a clock signal provided by oscillator 440. The count value of counter 430 can be in the range of, for example, 100 to 200, and as the count value increases, this can correspond to an increase in the temperature of the memory core. In some embodiments, the count value can have a minimum value of 0 and a maximum value of 2. X -1 (for the X-bit increment / decrement counter).

[0033] Counter 430 can output the current value of the count (in) Figure 4 and Figure 5 The text is a series of seemingly random characters and symbols, making it difficult to translate accurately. It appears to be a collection of fragments related to counter outputs ("counter digital output [7:0]") and "x" bits. Figure 4In the example, this is an 8-bit numeric input word used to control (fine-tune) the resistance value of resistor 405 to gradually equalize VCount and Vref. As the current value gradually increases, the resistance value of resistor 405 can gradually decrease. For example, for every 10 increments in the current value, counter 430 can change one or more bits of the "x"-bit input word to reflect the current temperature (e.g., a change in the current value from 6 to 16 could correspond to a change in the numeric output word from 00110 to 010000). Therefore, at 50 degrees, the input word could be 00000, and as the temperature of the memory core increases, one or more bits of the input word can change (e.g., from low to high ("0" to "1") or from high to low), which could correspond to an increase in temperature. Continuing the example above, a change in temperature from 50 degrees to 60 degrees could result in an input word of 00001. Therefore, as the temperature of the memory core increases (causing VCount to increase and Vref to decrease), the current value can increase, resulting in a counter digital output that gradually decreases the resistance of resistor 405. Similarly, if the temperature of the memory core decreases, Vcount will drop below Vref, and the output of comparator 425 will be 0. This allows counter 430 to decrement the count value and generate a counter digital output that increases the resistance of resistor 405 until VCount and Vref are equal. This action of comparator 425 and counter 430 continuously adjusts the value of resistor 405 until Vref and VCount are balanced (the input voltage of comparator 425 is balanced), which allows the output of comparator 425 to alternate between "1" and "0". This, in turn, allows counter 430 to switch between two count values ​​(stabilizing). For example, when Vref and VCount are balanced, the current count value can alternate between 99 and 100. When this condition is met, the output of counter 430 (99 or 100 in the example above) can indicate the current temperature of the memory core.

[0034] Counter 430 can be coupled to counter converter logic block 435 (hereinafter referred to as counter converter 435), which can receive the counter digital output from counter 430 as input and convert the counter digital output into an "x" bit fine-tuning (in... Figure 4 and Figure 5The parameters are shown as thermo_sense_trim[11:0]) for the 1T1C reference voltage generator to generate the 1T1C Vref. More specifically, the counter converter 435 can normalize the digital counter output value across process corners and convert the normalized counter output value into a trimmer for the 1T1C reference voltage generator. These trimmers can be provided to the 1T1C reference voltage generator over time (e.g., as the temperature of the memory core increases), and the 1T1C reference voltage generator can use these trimmers to provide a temperature-dependent 1T1C Vref based on the temperature distribution of the memory core.

[0035] Figure 4 The described implementation provides a temperature sensor that is easier to calibrate because it includes a single comparator, making input offset differences negligible. While an oscillator 440 is required to provide a clock signal to the counter 430, the temperature sensor 400 can provide higher resolution (e.g., more output bits) compared to the sensor 100, which is also advantageous. Additionally, the detected temperature can be configured by changing the number of count values ​​between adjacent temperature detections. For example, thermo_sense_trim[0] can be 1 when the count value is 100 (at 25°C), and thermo_sense_trim[1] can be 1 when the count value is 110 (at 35°C). This can be changed so that thermo_sense_trim[0] can be 1 when the count value is 100 (at 25°C), and thermo_sense_trim[1] can be 1 when the count value is 114 (at 40°C).

[0036] Figure 5 A block diagram of a sensor 400 according to some embodiments of the present disclosure is shown. As shown, the sensor 400 can be coupled to a buzzer circuit 445 (hereinafter referred to as "buzzer 445"), which can turn the sensor 400 on and off to manage current consumption. This is possible because the temperature of the memory core does not change instantly, but changes at intervals (e.g., 10 degrees / second). Therefore, the buzzer 445 can generate on / off pulses (in... Figure 5 The on / off pulse (shown as "Tmpsen_on / off") enables sensor 400 to wake up for a period of time and sense the memory core ( Figure 5 The buzzer 445 (not shown) measures the temperature and immediately returns to sleep. In this way, the buzzer 445 can optimize the power consumption of the sensor 400. The buzzer 445 can utilize its own ring oscillator 445A, which can operate at a frequency of, for example, 1MHz to 2MHz.

[0037] Figure 6AThis is graph 600 showing the performance of temperature sensor 400 over time, and specifically, graph 600 showing the inputs of comparator 425 (Vref and VCount), the counter digital output, and the on / off pulses (Tmpsen_on / off) of buzzer 445 relative to time. For the purposes of graph 600, the decimal value of the counter digital output is converted into a voltage so that it can be viewed as a waveform. As can be seen, buzzer 445 can provide an "on" signal to sensor 400 during the initial 10 microseconds (μs), during which time sensor 400 can determine that the temperature of the memory core is -40 degrees Celsius (also shown as 145.0V), represented by the counter digital output (in decimal form) as 100.0. Figure 6A The diagram also illustrates how the inputs (Vref and VCount) of comparator 425 differ at the beginning of the 10 μs measurement cycle, but match near the end, as the actions of comparator 425 and counter 430 continuously adjust the value of resistor 405 until Vref and VCount are equalized, as discussed further in detail herein. At 10 μs, buzzer 445 can send an "off" signal to sensor 400. Later, at 47 μs, buzzer 445 can send an "on" signal to sensor 400 again at 52 μs before sending another "off" signal. During this second measurement cycle, sensor 400 can determine the temperature of the memory core to be 50 degrees Celsius (C) (also shown as 192.0 V), represented as 145.0 by the counter digital output (in decimal form). Again, the Vref and VCount values ​​can differ until later in the measurement cycle, when the actions of comparator 425 and counter 430 equalize Vref and VCount.

[0038] Figure 6B This is a graph showing the counter digital output [7:0] (decimal) from counter 430 and the thermo_sense_trim [11:0] generated by counter converter 435 as the temperature of the memory core increases. Figure 6B The relationship between the counter digital output [7:0] and therm_sense_trim [11:0] is shown as the counter converter 435 normalizes the counter digital output value across process corners and converts the normalized counter digital output value into a fine-tuning value for the 1T1C reference voltage generator.

[0039] Figure 7AA memory device 700 in which embodiments of the present disclosure can be implemented is shown. The memory device 700 includes an F-RAM memory core 705, a sensor 400, a timing control 710, and an IT1C reference voltage generator 715. Although shown with sensor 400, it can also be used herein. Figure 1 The sensor 100 is shown. As can be seen, the output of sensor 400 (or sensor 100) is provided to an IT1C reference voltage generator 715, which adjusts the IT1C reference it provides to the F-RAM memory core based on the output of sensor 400. As discussed herein, the output of sensor 400 may include information for the IT1C reference voltage generator to generate a temperature-dependent IT1C Vref (e.g., ...). Figure 3 With appropriate fine-tuning (best shown in the example of 1T1C Vref310), the temperature-dependent 1T1C Vref is provided to the F-RAM core 705 for single-ended sensing / reading operations. As discussed herein, this 1T1C Vref enables the memory device 700 to distinguish between P-terms and U-terms across a temperature range. Figure 3 As shown, the 1T1C Vref generated using embodiments of this disclosure is temperature-dependent and has a temperature distribution that allows differentiation between the P and U terms over a temperature range. Because the memory device 700 can modulate the 1T1C Vref, it can ensure that the margin of error between the P and U terms remains constant throughout the temperature range. A timing control circuit 710 can provide timing and coordination among the various components of the memory device 700. Although illustrated as an F-RAM memory core 705, the memory core can be a memory device based on any suitable memory technology such as floating gate, flash memory, R-RAM, M-RAM, etc. The 1T1C reference voltage generator 715 can be a device that provides a temperature-dependent sensing reference signal to the memory device, at least partially responding to the output of temperature sensor 400 or temperature sensor 100 to fine-tune or adjust the intensity of the sensing reference signal.

[0040] Figure 7BA block diagram of a semiconductor memory 750 including a memory section 760 is shown. Within the memory section 760, there is a memory array 765 of non-volatile (NV) memory cells 770, arranged with multiple rows each sharing a common word line (WL) and multiple columns each sharing a common bit line. In one embodiment, the NV memory cells 770 may be, for example, 1T1CF-RAM cells. In one embodiment, a 1T1C reference voltage generator 775 and a sensor 400 (or sensor 100 in some embodiments) may also be disposed within the memory section 760. The semiconductor memory 750 also includes a processing element 780, such as a microcontroller, microprocessor, or state machine. In one embodiment, processing element 780 can issue command or control signals (e.g., WL signals, RWL signals) to each of the NV memory cells 770 and the reference generation array 775 to perform read, erase, and program operations as described above, and issue command or control signals (e.g., WL signals, RWL signals) to other peripheral circuitry for reading from or writing to the memory array 765. The peripheral circuitry includes a row decoder 785 for translating memory addresses and applying them to word lines of the NV memory cells 770 in the memory array 765. When a data word is read from the semiconductor memory 750, the NV memory cells 770 coupled to the selected word line (WL) are read to bit lines, and the state of those lines is detected by a sense amplifier / driver 790. A column decoder 795 outputs the data from the bit lines to the sense amplifier / driver 790. In one implementation, the row decoder 785 and / or column decoder 795 may also translate the address and apply it to the read word line (RWL) to control a specific mixed temperature-dependent 1T1C reference signal to the output of the sense amplifier / driver 790 for read operations.

[0041] Figure 8 This is a flowchart of a method 800 for providing a temperature-dependent 1T1C reference voltage according to some embodiments of this disclosure. Method 800 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, programmable logic, processor, processing device, central processing unit (CPU), system-on-a-chip (SoC), etc.), software (e.g., instructions that run / execute on the processing device), firmware (e.g., microcode), or a combination thereof. For example, method 800 can be performed by… Figure 4 and Figure 5 The sensor 400 is used for execution.

[0042] Also refer to Figure 4 and Figure 5At block 805, as the temperature of the memory core increases, Vref can gradually decrease, while VCount gradually increases. Therefore, to make Vref and VCount equal, the resistance of resistor 405 must decrease as the temperature of the memory core increases. Thus, sensor 400 may also include comparator 425, which, at block 810, can receive the output voltages (Vref and VCount) of resistor circuit 407 as input. Sensor 400 may also include an increment / decrement counter logic block 430 (hereinafter referred to as counter 430), which can be coupled to comparator 425 to form a feedback loop, thereby enabling control of resistor 405, as discussed further in detail herein. At block 815, counter 430 can maintain a count value based on the output of comparator 425 (which in turn depends on the temperature of the memory core) and can output the current value of the count. More specifically, as the temperature of the memory core increases, Vref can gradually decrease while VCount gradually increases, and therefore the output of comparator 425 can be "1" ("high") when VCount is currently higher than Vref. In response to receiving an input of 1 from comparator 425, counter 430 can increment the count (incrementing the current count value). If VCount is lower than Vref, the output of comparator 425 can be "0" ("low"), and counter 430 can decrement the count (decreasing the current count value) based on receiving an input of 0. Counter 430 can operate based on a clock signal provided by oscillator 440. The count value of counter 430 can be in the range of, for example, 50 to 150, and this can correspond to an increase in the temperature of the memory core as the count value increases. In some embodiments, the count value can have a minimum value of 0 and a maximum value of 2. X -1 (for the X-bit increment / decrement counter).

[0043] At box 820, counter 430 can output the current value of the count (in... Figure 4 and Figure 5 The text is a series of seemingly random characters and symbols, making it difficult to translate accurately. It appears to be a collection of fragments related to counter outputs ("counter digital output [7:0]") and "x" bits. Figure 4In the example, the digital input word is 8, which is used to control (fine-tune) the resistance value of resistor 405 to gradually equalize VCount and Vref. As the current value gradually increases, the resistance value of resistor 405 can gradually decrease. For example, for every 10 increment of the current value, counter 430 can change one or more bits of the "x" bit input word to reflect the current temperature (e.g., a change in the current value from 6 to 16 could correspond to a change in the digital output word from 00110 to 010000). Therefore, at 50 degrees, the input word could be 00000, and as the temperature of the memory core increases, one or more bits of the input word can change (e.g., from low to high ("0" to "1") or from high to low), which could correspond to an increase in temperature. Continuing the example above, a change in temperature from 50 degrees to 60 degrees could result in an input word of 00001. Therefore, as the temperature of the memory core increases (causing VCount to increase and Vref to decrease), the current value can increase, resulting in a counter digital output that gradually decreases the resistance of resistor 405. Similarly, if the temperature of the memory core decreases, Vcount will drop below Vref, and the output of comparator 425 will be 0. This causes counter 430 to decrement the count value and generate a counter digital output that increases the resistance of resistor 405 until VCount and Vref are equal. This action of comparator 425 and counter 430 continuously adjusts the value of resistor 405 until Vref and VCount are balanced (the input voltage of comparator 425 is balanced), which causes the output of comparator 425 to alternate between "1" and "0". This, in turn, causes counter 430 to switch between two count values ​​(stabilization). For example, when Vref and VCount are balanced, the current value of the count can alternate between 99 and 100. When this condition is met, the output of counter 430 (99 or 100 in the example above) can indicate the current temperature of the memory core.

[0044] Counter 430 can be coupled to counter converter logic block 435 (hereinafter referred to as counter converter 435), which can receive the counter digital output from counter 430 as input and convert the counter digital output into an "x" bit fine-tuning (in Figure 4 and Figure 5The parameters are shown as thermo_sense_trim[11:0], for the 1T1C reference voltage generator to use to generate the 1T1C Vref. More specifically, at block 825, the counter converter 435 can normalize the digital counter output value across process corners and convert the normalized counter output value into a trimmer for the 1T1C reference voltage generator. These trimmers can be provided to the 1T1C reference voltage generator over time (e.g., as the temperature of the memory core increases), and at block 830, the 1T1C reference voltage generator can utilize these trimmers to provide a temperature-dependent 1T1C Vref based on the temperature distribution of the memory core.

[0045] The embodiments described herein can be used in various designs of mutual capacitance sensing systems, self-capacitance sensing systems, or combinations thereof. As will be understood by those skilled in the art who benefit from this disclosure, the embodiments described herein are not dependent on a particular capacitance sensing solution and can also be used with other sensing solutions, including optical sensing solutions.

[0046] Numerous details have been set forth in the foregoing description. However, it will be apparent to those skilled in the art who benefit from this disclosure that embodiments of the disclosure can be practiced without these specific details. In some instances, to avoid obscuring the description, well-known structures and apparatuses are shown in block diagram form rather than in detail.

[0047] Certain parts of the specific implementation are presented according to algorithms and symbolic representations for manipulating data bits within computer memory. These algorithmic descriptions and representations are means by which those skilled in the art of data processing most effectively communicate the substance of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of steps leading to a desired result. These steps are those requiring physical manipulation of physical quantities. Typically, although not mandatory, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for general reasons.

[0048] However, it should be remembered that all these terms, and similar terms, should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. As is apparent from the above discussion, unless otherwise specified, it should be understood that throughout the description, discussions using terms such as “determine,” “detect,” “compare,” “reset,” “add,” and “calculate” refer to the actions and processing of a computing system or similar electronic computing device that manipulates data represented as physical (e.g., electronic) quantities within the registers and memories of the computing system and converts this data into other data similarly represented as physical quantities within the memory or registers of the computing system or other such information storage, transmission, or display devices.

[0049] The terms “example” or “exemplary” are used herein to mean as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or other designs. Rather, the use of the terms “example” or “exemplary” is intended to present the concept in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or clear from the context, “X comprises A or B” is intended to mean any natural inclusive arrangement. That is, if X comprises A, X comprises B, or X comprises both A and B, then “X comprises A or B” is satisfied in any of the foregoing cases. Additionally, unless otherwise stated or clearly addressed to the singular form from the context, the articles “a” and “an” used in this application and the appended claims should generally be construed as meaning “one or more.” Furthermore, unless so described, the use of the terms “implementation” or “an implementation” or “a mode of implementation” or “an mode of implementation” throughout the specification is not intended to refer to the same implementation or mode of implementation.

[0050] The embodiments described herein may also relate to devices for performing the operations described herein. Such devices may be specifically constructed for a desired purpose, or may include a general-purpose computer that can be selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in non-transitory computer-readable storage media, such as, but not limited to, any type of disk including: floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be considered as including a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be considered as including any medium capable of storing, encoding, or carrying a set of instructions that is executed by a machine and causes the machine to perform any one or more of the methods of this embodiment. The term "computer-readable storage medium" should therefore be considered as including, but not limited to, solid-state memory, optical media, magnetic media, and any medium capable of storing a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of this embodiment.

[0051] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The desired architectures of various such systems will become apparent from the descriptions below. Furthermore, this implementation is described without reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of the implementations as described herein.

[0052] The foregoing description sets forth numerous specific details of examples such as specific systems, components, methods, etc., in order to provide a good understanding of several embodiments of this disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of this disclosure can be practiced without these specific details. In other instances, well-known components or methods have not been described in detail, or have been presented in a simple block diagram format, in order to avoid unnecessarily obscuring this embodiment. Therefore, the specific details set forth above are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the scope of this embodiment.

[0053] It should be understood that the above description is intended to be illustrative and not restrictive. Many other embodiments will become apparent to those skilled in the art after reading and understanding the above description. Therefore, the scope of the embodiments should be determined by reference to the appended claims, together with the full scope of their equivalents.

Claims

1. A device for temperature sensing, the device comprising: A resistor circuit includes a set of resistors configured to control a reference voltage based on a memory, each resistor in the set having a first temperature coefficient or a second temperature coefficient, wherein the first resistor in the set modifies its resistance value based on the temperature of the memory until the reference voltage and the output voltage are equal. A comparator configured to output an incrementing count signal and a decrementing count signal; and The counter is configured as follows: The current count value is incremented and decremented based on the increment and decrement signals output by the comparator; and A word corresponding to the current count value is periodically output to the first resistor, the word indicating the temperature of the memory. The set of resistors includes a resistor ladder in which one or more second resistors are connected in series with the first resistor, and wherein the first resistor has a positive first temperature coefficient, and each of the one or more second resistors has a second temperature coefficient that is less than the first temperature coefficient.

2. The device according to claim 1, wherein, To output increment and decrement count signals, the comparator: Compare the reference voltage with the output voltage; as well as If the output voltage is lower than the reference voltage, an increment signal is output to the counter; if the output voltage is higher than the reference voltage, a decrement signal is output to the counter.

3. The device according to claim 2, wherein, The switching of the current count value between two different values ​​indicates that the reference voltage and the output voltage are equal, and wherein the word output after the current count value switching indicates the current temperature of the memory.

4. The device according to claim 3, further comprising: The counter converter is configured to: The word output after the current count value is switched is converted into a fine-tuning value; as well as The fine-tuning value is output to a reference signal generator of a memory device including the memory.

5. The device according to claim 4, wherein, The reference signal generator is a single-transistor, single-capacitor 1T1C reference signal generator.

6. The device according to claim 1, wherein, The memory is a ferroelectric random access memory (F-RAM).

7. The device according to claim 1, wherein, The first resistor is an N-well resistor, and the one or more second resistors include silicide-blocked polysilicon resistors, wherein the second temperature coefficient does not cause the resistance of the one or more second resistors to change based on the temperature of the memory, relative to the first temperature coefficient.

8. A system including a temperature sensor, the system comprising: Memory; A reference signal generator is configured to generate a reference signal based on the current temperature of the memory; as well as The temperature sensor includes: A resistor circuit includes a set of resistors configured to control a reference voltage based on the temperature of the memory, each resistor in the set having a first temperature coefficient or a second temperature coefficient, wherein the first resistor in the set modifies its resistance value based on the temperature of the memory until the reference voltage and the output voltage are equal. A comparator configured to output an incrementing count signal and a decrementing count signal; and The counter is configured as follows: The current count value is incremented and decremented based on the increment and decrement signals output by the comparator; and A word corresponding to the current count value is periodically output to the first resistor, the word indicating the temperature of the memory. Wherein, one or more resistors in the group of resistors having the first temperature coefficient include N-well resistors, and one or more resistors in the group of resistors having the second temperature coefficient include silicide-blocked polysilicon resistors, wherein the second temperature coefficient is smaller than the first temperature coefficient.

9. The system according to claim 8, wherein, To output increment and decrement signals, the comparator is configured to: Compare the reference voltage with the output voltage; and If the output voltage is lower than the reference voltage, an increment signal is output to the counter; if the output voltage is higher than the reference voltage, a decrement signal is output to the counter.

10. The system according to claim 9, wherein, The switching of the current count value between two different values ​​indicates that the reference voltage and the output voltage are equal, and wherein the word output after the current count value switching indicates the current temperature of the memory.

11. The system according to claim 10, wherein, The temperature sensor also includes: The counter converter is configured to: The word output after the current count value is switched is converted into a fine-tuning value; and The fine-tuning value is output to the reference signal generator.

12. The system according to claim 11, wherein, The reference signal is a single-transistor, single-capacitor 1T1C reference signal.

13. The system according to claim 8, further comprising: A buzzer circuit is configured to operate the temperature sensor at periodic intervals and maintain the temperature sensor in a low-power state outside the periodic intervals.

14. A device for temperature sensing, the device comprising: A resistor circuit comprising a set of resistors configured to control a reference voltage based on the temperature of a memory, each of the set of resistors having a first temperature coefficient or a second temperature coefficient. A resistor stack coupled to the resistor circuit, the resistor stack including a plurality of taps, wherein the output voltage at each of the plurality of taps is successively lower than the output voltage at the previous tap; and A plurality of comparators, each of the plurality of comparators being coupled to a corresponding tap of the plurality of taps, wherein each of the plurality of comparators is configured to: Compare the output voltage at the corresponding tap point with the reference voltage; and When the output voltage at the corresponding tap point is greater than the reference voltage, a high signal is output. Wherein, one or more resistors in the group of resistors having the first temperature coefficient include N-well resistors, and one or more resistors in the group of resistors having the second temperature coefficient include silicide-blocked polysilicon resistors, wherein the second temperature coefficient is smaller than the first temperature coefficient.

15. The device according to claim 14, wherein, The reference voltage decreases as the ratio of the resistance values ​​in the set of resistors increases with the temperature, causing each successive comparator in the plurality of comparators to output a corresponding high signal as the temperature of the memory increases.

16. The device according to claim 15, wherein, Each of the plurality of comparators outputs a corresponding high signal to a reference signal generator of the memory device including the memory.

17. The device according to claim 15, wherein, Each consecutive high signal defines a temperature zone, thus defining multiple temperature zones.

18. The device according to claim 14, wherein, The first temperature coefficient is positive; and Wherein, relative to the first temperature coefficient, the second temperature coefficient does not cause the resistance of the one or more second resistors to change based on the temperature of the memory.

19. The device according to claim 14, wherein, The memory is a ferroelectric random access memory (F-RAM).

20. The device according to claim 16, wherein, The reference signal generator is a single-transistor, single-capacitor 1T1C reference signal generator.

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