Communication device and communication system

Abstract

[Problem] To enable audio signals to be transmitted between communication devices and reproduced correctly. [Solution] A communication device includes a measurement unit that measures the number of clocks of a predetermined reference clock included in one cycle of a divided signal of an audio master clock based on the audio master clock, a division ratio of the divided signal, and the predetermined reference clock, wherein the frequency of the audio master clock is a multiple of the frequency of a sampling clock that samples the audio signal; and a data packet generation unit that generates a data packet including information including the number measured by the measurement unit, the bit width of serial data (SD) conforming to the I2S standard, the frequency of the sampling clock, the division ratio of the divided signal with respect to the audio master clock, the frequency ratio of the frequency of the audio master clock with respect to the frequency of the sampling clock, and the SD.

Description

Technical Field

[0001] This disclosure relates to communication devices and communication systems. Background Technology

[0002] In the proposed technology, the master SerDes and the slave SerDes perform high-speed serial communication (see Patent Document 1).

[0003] When transmitting audio signals between two SerDess, signals conforming to the I2S (Inter-IC Voice) protocol can be transmitted.

[0004] [List of Citations]

[0005] [Patent Literature]

[0006] [Patent Document 1]

[0007] JP 2011-239011A Summary of the Invention

[0008] [Technical Issues]

[0009] However, signals conforming to the I2S protocol are asynchronous with the signals transmitted between the two SerDess, and their frequency bands are also different. Furthermore, in some cases, the number of sampling clock frequencies for the audio signal does not necessarily have to be just one, and the sampling clock frequencies vary depending on the sound source. It is essential to ensure that these audio signals can be transmitted between the two SerDess and that the audio signals are reproduced correctly.

[0010] In view of this, the present disclosure provides a communication device and a communication system that enable the transmission of audio signals between communication devices that perform signal transmission asynchronously with audio signals, and the correct reproduction of audio signals.

[0011] [Solution to the problem]

[0012] To address the aforementioned problems, this disclosure provides a communication device comprising: a measurement unit, which measures the number of predetermined reference clocks included in one cycle of the frequency division signal based on an audio master clock, a frequency division ratio of the frequency division signal relative to the audio master clock, and a predetermined reference clock, wherein the frequency of the audio master clock is equal to the product of the frequency of the sampling clock used to sample the audio signal and a multiple thereof; and a data packet generation unit, which generates a data packet including information, wherein the information includes the number measured at the measurement unit, the bit width of the SD (serial data) conforming to the I2S standard, the frequency of the sampling clock, the frequency division ratio of the frequency division signal relative to the audio master clock, the frequency ratio of the audio master clock frequency to the sampling clock frequency, and the SD.

[0013] The data packet generated by the data packet generation unit may include a header portion and a data portion. The header portion may include the quantity measured at the measurement unit, the bit width of the SD, the frequency of the sampling clock, the division ratio, and the frequency ratio, and the data portion may include multiple SDs.

[0014] The header section may include the bit width of the SD, the number of channels of the SD, the frequency of the sampling clock, the division ratio of the frequency division signal relative to the audio master clock, the frequency ratio of the audio master clock frequency relative to the sampling clock frequency, the frequency of the reference clock, and the quantity measured at the measurement unit.

[0015] The data portion may include SDs corresponding to the number of channels and the number of samples.

[0016] The communication device may include: a physical layer clock generation unit that generates a clock that will be used by the physical layers of both the communication device and the communication partner device; and a frequency division unit that divides the clock generated at the physical layer clock generation unit and generates a reference clock.

[0017] The frequency of the clock generated at the physical layer clock generation unit can be 250MHz.

[0018] The frequency of the audio master clock can be 25.6MHz, and the frequency of the sampling clock can be 50kHz.

[0019] The sampling clock and audio master clock can be asynchronous with the reference clock.

[0020] The sampling clock and audio master clock can be synchronized with the reference clock.

[0021] The communication device may include: a PTB clock generation unit that generates a PTB (Precision Time Base) clock, which is used to generate timestamp information shared by the communication device and the communication partner device, wherein the reference clock may be a PTB clock.

[0022] The audio master clock can be synchronized with the PTB clock.

[0023] The PTB clock frequency can be 250MHz.

[0024] This disclosure provides a communication device, comprising: a measurement unit that receives a WS (Word Select) signal conforming to the I2S standard, and measures first timing information and second timing information based on a predetermined reference clock used by the communication device and a communication partner device, wherein the first timing information indicates the timing of a logical change of the WS signal in the first SD (Serial Data) of a plurality of SDs included in a data packet sent to the communication partner device, and the second timing information indicates the timing of a logical change of the WS signal in the last SD; and a data packet generation unit that generates a data packet including the bit width of the SD, the frequency of a sampling clock for sampling an audio signal, the first timing information, the second timing information, the number of SDs included in a data packet, and the SDs.

[0025] The packet generation unit can generate packets that also include information about the number of channels in the SD system.

[0026] This disclosure provides a communication apparatus, comprising: a recovery unit that receives data packets sent from a communication partner device and recovers from the data packets an I2S-compliant SD (serial data), the bit width of the SD, the frequency of a sampling clock used for sampling an audio signal, the frequency ratio of the audio master clock frequency to the sampling clock frequency, the number of predetermined first reference clocks included in one cycle of a division signal of the audio master clock, the frequency of the sampling clock, and the division ratio of the division signal relative to the audio master clock; an audio master clock regeneration unit that regenerates the audio master clock based on the number of first reference clocks, the frequency of the first reference clock, and the division ratio; and an SCK regeneration unit that regenerates the SCK (Serial Clock) based on information about the bit width of the SD, the frequency ratio, and the audio master clock.

[0027] The communication device may include: a clock regeneration circuit that generates a second reference clock synchronized with the signal changes of SD based on data packets; and a frequency ratio calculation unit that calculates the frequency ratio between the frequency of the first reference clock and the frequency of the second reference clock, wherein the audio master clock regeneration unit regenerates the audio master clock based on the number of first reference clocks, frequency information about the first reference clocks, the frequency division ratio, and the frequency ratio calculated by the frequency ratio calculation unit.

[0028] The communication device may include: a PTB clock generation unit that generates a PTB (Precise Time Base) clock, which is used to generate timestamp information shared by the communication device and the communication partner device, wherein the first reference clock may be a PTB clock.

[0029] This disclosure provides a communication apparatus, comprising: a recovery unit that receives data packets sent from a communication partner device and recovers from the data packets an I2S-compliant SD (serial data), bit width information about the SD, frequency information about the SCK (serial clock), first timing information indicating the timing of the first logical change of the WS (word select) signal contained in a data packet, second timing information indicating the timing of the last logical change of the WS signal, and the number of SD segments contained in the data packet; a clock generation unit that generates a reference clock to be used jointly by the communication apparatus and the communication partner device; a WS signal regeneration unit that regenerates the WS signal based on the first timing information, the second timing information, the number of SD segments, and the reference clock; an audio master clock regeneration unit that regenerates an audio master clock, the frequency of which is equal to the product of the frequency of the WS signal regenerated at the WS signal regeneration unit and a multiple thereof; and an SCK regeneration unit that regenerates the SCK based on the WS signal regenerated at the WS signal regeneration unit and the bit width information about the SD.

[0030] The communication device may include: a PTB clock generation unit that generates a PTB (Precise Time Base) clock, which is used to generate timestamp information shared by the communication device and the communication partner device, wherein the first reference clock may be a PTB clock.

[0031] Data packets can be sent within the time period allocated by TDD (Time Division Duplex).

[0032] This disclosure provides a communication system including a first communication device and a second communication device. The first communication device and the second communication device communicate serially. The first communication device includes: a measurement unit that measures the number of predetermined reference clocks included in one cycle of the frequency division signal based on an audio master clock, a frequency division ratio of the frequency division signal relative to the audio master clock, and a predetermined reference clock. The frequency of the audio master clock is equal to the product of the frequency of the sampling clock used to sample the audio signal and a multiple thereof. A data packet generation unit generates a data packet including information, such as the number measured at the measurement unit, the bit width of the SD (serial data) conforming to the I2S standard, the frequency of the sampling clock, the frequency division ratio of the frequency division signal relative to the audio master clock, and the frequency of the audio master clock. The first communication device includes: a recovery unit that receives data packets sent from the first communication device and recovers from the data packets the SD, the bit width of the SD, the frequency of the sampling clock, the frequency ratio of the audio master clock frequency to the sampling clock frequency, a predetermined number of first reference clocks including a division signal of the audio master clock in one cycle, the frequency of the sampling clock, and the division ratio of the division signal to the audio master clock; an audio master clock regeneration unit that regenerates the audio master clock based on the number of first reference clocks, the frequency of the first reference clock, and the division ratio; and an SCK regeneration unit that regenerates the SCK (serial clock) based on the bit width information of the SD, the frequency ratio, and the audio master clock.

[0033] This disclosure provides a communication system including a first communication device and a second communication device, wherein the first communication device and the second communication device perform serial communication. The first communication device includes: a measurement unit that receives a WS (word select) signal conforming to the I2S standard and measures first timing information and second timing information based on a predetermined reference clock shared by the first and second communication devices. The first timing information indicates the timing of a logical change in the WS signal of the first SD (serial data signal) among multiple SDs included in a data packet sent to the second communication device, and the second timing information indicates the timing of a logical change in the WS signal of the last SD. The second communication device includes: a data packet generation unit that generates a data packet including the bit width of the SD, the frequency of a sampling clock for sampling an audio signal, the first timing information, the second timing information, the number of SDs included in a data packet, and the SDs. The second communication device includes: a recovery unit that receives data from the first communication device... The communication device sends data packets and recovers from the data packets the SD (serial data) conforming to the I2S standard, bit width information about the SD, frequency information about the SCK (serial clock), first timing information indicating the timing of the first logical change of the WS (word select) signal contained in a data packet, second timing information indicating the timing of the last logical change of the WS signal, and the number of SDs contained in a data packet; a clock generation unit generates a reference clock to be used by the second communication device and the first communication device; a WS signal regeneration unit regenerates the WS signal based on the first timing information, the second timing information, the number of SDs, and the reference clock; an audio master clock regeneration unit regenerates the audio master clock, the frequency of which is equal to the product of the frequency of the WS signal regenerated at the WS signal regeneration unit and a multiple thereof; and an SCK regeneration unit regenerates the SCK based on the WS signal regenerated at the WS signal regeneration unit and the bit width information about the SD. Attached Figure Description

[0034] Figure 1 This is a block diagram showing the basic configuration of communication system 1.

[0035] Figure 2A This is a diagram used to illustrate frequency division multiplexing.

[0036] Figure 2B This is a diagram used to illustrate time-division multiplexing.

[0037] Figure 3 This is a diagram showing the I2S format.

[0038] Figure 4 This is a block diagram illustrating a schematic configuration of a communication system including a communication device according to the first embodiment.

[0039] Figure 5 It is shown in Figure 4A diagram illustrating the configuration of packets and frames generated in SerDes.

[0040] Figure 6 This is a block diagram showing the internal configuration of the transmitter-side I2S device and the encapsulator and PHY clock generation unit in the SerDes.

[0041] Figure 7 This is a timing diagram of MCK and TxREFCK generated based on the symbol clock of the PHY clock generation unit.

[0042] Figure 8 This is a diagram showing the transmission parameters to be used for regenerating MCK on the receiver side.

[0043] Figure 9 This is a configuration diagram of the application data package generated at SerDes.

[0044] Figure 10A This is a diagram showing the configuration of the header (I2S header) of the application data packet used for I2S signal transmission.

[0045] Figure 10B This is a diagram showing the configuration of the application data packet and CRC for I2S signal transmission.

[0046] Figure 11A It is a timing diagram in the original I2S format.

[0047] Figure 11B It is a timing diagram in a left-aligned format.

[0048] Figure 11C It is a right-aligned sequence diagram.

[0049] Figure 12 This is a block diagram showing the internal configuration of the decapsulator in SerDes.

[0050] Figure 13 This is a block diagram illustrating the internal configuration of the I2S device according to the second embodiment, as well as the package and PHY clock generation unit in the SerDes.

[0051] Figure 14 This is a diagram showing the parameter values ​​used when regenerating MCK using the SerDes in the second embodiment.

[0052] Figure 15 This is a block diagram illustrating the internal configuration of the wrapper in SerDes according to the third embodiment.

[0053] Figure 16 This is a block diagram illustrating the internal configuration of the decapsulator in SerDes according to the third embodiment.

[0054] Figure 17 This is a block diagram illustrating the internal configuration of the I2S device and package in SerDes according to the fourth embodiment.

[0055] Figure 18 This is a block diagram illustrating the internal configuration of the I2S device and package in SerDes according to the fifth embodiment.

[0056] Figure 19 This is a timing diagram of data packets transmitted between two SerDess.

[0057] Figure 20 This is a diagram showing the structure of the application data package generated in SerDes.

[0058] Figure 21 This is a block diagram illustrating the internal configuration of the decapsulator in SerDes according to the fifth embodiment.

[0059] Figure 22A This is a diagram showing the configuration of the header of an application data packet used for I2S signal transmission.

[0060] Figure 22B This is a diagram showing the configuration of the application data packet and CRC for I2S signal transmission.

[0061] Figure 23 This is a diagram illustrating an example of transmitting I2S signals by including them in an application data packet used for transmitting video data. Detailed Implementation

[0062] In the following description, embodiments of the communication apparatus, communication system, and communication method are illustrated with reference to the accompanying drawings. While the main components of the communication apparatus and communication system are primarily described below, there may be components or functions in the communication apparatus and communication system that are not described or explained. The following description does not exclude any components or functions that are not described or explained.

[0063] (Basic configuration of a communication system)

[0064] Figure 1 This is a block diagram showing the basic configuration of communication system 1, in which signals conforming to the I2S protocol are transmitted and received between two SerDes 130 and SerDes 230. Figure 1 The communication system 1 includes a first communication module 100 and a second communication module 200, both of which have a SerDes for performing high-speed serial communication. The first communication module 100 and the second communication module 200 are connected by a cable 300 with a length of several meters to tens of meters.

[0065] For example, the first communication module 100 and the second communication module 200 can transmit audio signals using I2S. I2S is an inter-IC audio signal transmission protocol specified by the FPD-LINK standard, which is one of the high-speed interface technologies for vehicles.

[0066] Currently, the Automotive SerDes Alliance (ASA), the standardization organization for high-speed automotive serial interfaces, is working on standardizing high-speed automotive serial interface technology. The difference between FPD-LINK and ASA lies in the fact that FPD-LINK uses... Figure 2A The frequency division multiplexing shown is used as a method to achieve bidirectional communication, while ASA uses, for example... Figure 2B The diagram illustrates Time Division Duplex (TDD) as a method for implementing bidirectional communication.

[0067] exist Figure 1 The first communication module 100 described herein includes a microphone 110, a first I2S device (I2S audio device) 120, a SerDes device 130, an X'tal 140, a camera 150, and an X'tal 160. The second communication module 200 includes a speaker (SPK) 210, an I2S device (I2S audio device) 220, a SerDes device 230, a video decoder 250, and an ADAS / ADS processor 260.

[0068] The sound signal (audio signal) obtained by the sound collection at the microphone 110 in the first communication module 100 is input to the I2S device 120. The I2S device 120 has an ADC 120-1, an I2S encoder (I2S ENC) 120-2 and a clock generation unit (CLK GEN) 120-3.

[0069] The clock generation unit 120-3 generates the audio sampling clock, audio serial clock, and audio master clock (hereinafter referred to as MCK) synchronously with the reference clock generated at X'tal 140.

[0070] The ADC 120-1 performs AD conversion on the audio signal from the microphone 110 in synchronization with the audio sampling clock and generates audio data. The I2S encoder 120-2 encodes the audio data in synchronization with the audio serial clock and generates SCK (serial clock), WS (word select), and SD (serial data) signals conforming to the I2S protocol. In this specification, SCK, WS, and SD are collectively referred to as I2S signals in some cases.

[0071] The SCK, WS, SD, and MCK signals generated in the I2S device 120 are input to the SerDes 130. In addition, video data acquired by image capture at the camera 150 and the reference clock generated at the X'tal 160 are input to the SerDes 130.

[0072] SerDes 130 generates a data packet containing audio data based on the audio signal obtained by sound collection at microphone 110, and transmits the data packet to SerDes 230 via cable 300. The data packet is transmitted within a time period allocated by TDD. SerDes 230 receives the data packet transmitted from SerDes 130, recovers the original SCK, WS, SD, and MCK signals, and recovers the video data obtained by recording at camera 150.

[0073] The SCK, WS, SD, and MCK signals recovered by the SerDes 230 are input to the I2S device (I2S audio device) 220. The I2S device 220 has an I2S decoder (I2SDEC) 220-1, a DAC 220-2, and a clock divider (CLK divider) 220-3.

[0074] The clock divider 220-3 generates the audio sampling clock and audio serial clock synchronously with the MCK regenerated at SerDes 230. The I2S decoder 220-1 recovers the original audio data synchronously with the audio serial clock. The recovered audio data is provided to the DAC 220-2 and the ADAS / ADS processor 260. The DAC 220-2 performs DA conversion on the audio data to generate an audio signal and inputs the audio signal to the speaker 210. Thus, the audio signal obtained by sound collection at the microphone 110 is reproduced at the speaker 210. The ADAS / ADS processor 260 analyzes the audio data and uses the results for, for example, the recognition of the surrounding environment.

[0075] As mentioned above, in Figure 1In the communication system 1 described herein, the audio signal obtained by sound collection at the microphone 110 in the first communication module 100 undergoes AD conversion at the I2S device 120. Subsequently, the audio signal is converted into a signal conforming to the I2S protocol, and at the SerDes 130, the signal is divided into data packets in the SerDes transmission format and transmitted to the second communication module 200. The SerDes 230 in the second communication module 200 recovers the I2S SCK, WS, SD, and MCK signals from the received data packets. The conversion performed by the I2S device 220 is the reverse of the conversion performed by the I2S device 120, recovering the audio signal and outputting it as sound at the speaker 210. Furthermore, the I2S device 220 provides I2S format audio data to the ADAS / ADS processor 260.

[0076] (I2S format)

[0077] Figure 3 This is a diagram showing the I2S format. Figure 3 The waveforms of MCK, WS, SCK, and SD are shown. The frequency of MCK is equal to the product of the sampling clock frequency fs [Hz] and a multiple K. The multiple K is, for example, 128, 256, or 512. The WS signal has the same frequency as the sampling clock fs. One period of the WS signal is the SD bit width. The SD bit width in one period of the WS signal can be any width. The frequency of SCK varies depending on the SD bit width. SCK is the clock that specifies the timing for performing the serial transmission of each bit in SD.

[0078] Figure 3 An example is shown where left-channel serial data is transmitted during the low-level period of the WS signal and right-channel serial data is transmitted during the high-level period of the WS signal. SD is transmitted bit by bit sequentially from one side of MSB.

[0079] Typically, in digital audio processing, an audio master clock MCK is used. The frequency of the audio master clock MCK is equal to the product of the sampling frequency fs and a multiple K (where K is an integer). Therefore, as... Figure 3 As shown, in some cases, in addition to transmitting WS signals, SCK and SD, MCK is also transmitted. Figure 1 The I2S device 120 generates the WS, SCK, and SD signals synchronously with the MCK. Therefore, when transmitting audio signals, it is important that the transmitter-side MCK is accurately reproduced on the receiver-side, especially with minimal jitter. This is because if the sampling clock used when the digital signal is converted to an audio signal at the receiver-side DAC 220-2 contains jitter, modulation distortion occurs in the temporal direction, leading to undesirable sound quality (S / N) degradation.

[0080] In recent years, audio equipment providing high sound quality has become widely used, and high dynamic range signals are transmitted at high sampling clock frequencies. Therefore, the requirements regarding clock jitter on the playback side have become more stringent. High-quality transmission of audio signals using high-speed serial interface technology requires the transmission frequency to be the same as or an integer multiple of the sampling clock frequency fs (MCK). However, the frequencies of high-speed serial interface technologies used in SerDes130 and SerDes230 are independent of the sampling clock (44.1kHz, 48kHz, 96kHz, 192kHz, etc.) or MCK (22.5792MHz, 24.576MHz, etc.) used in typical audio signal processing. Even if the sampling clock frequency used in audio signal processing and the frequency used at the high-speed serial interface are asynchronous, it is still necessary to ensure that the audio signal transmitted via the high-speed serial interface can be correctly reproduced at the transmission destination. However, existing high-speed serial transmission protocols such as FPD-LINK do not explicitly specify the specific process for the serial transmission of asynchronous audio signals.

[0081] The communication apparatus and communication system 1 described below according to this disclosure are characterized in that they can correctly transmit and reproduce audio signals conforming to the I2S standard using high-speed serial interface technology (e.g., the ASA standard).

[0082] (First Implementation)

[0083] Figure 4 This is a block diagram illustrating a schematic configuration of a communication system 1 including a communication device according to the first embodiment. Figure 4 The components (with) Figure 1 Corresponding parts in the same text use the same reference numerals, and the differences are mainly explained below. Furthermore, in Figure 4 In the diagram, the signal processing flow of the I2S signal is represented by arrow lines.

[0084] Figure 4 The communication system 1 includes a first communication module (first communication device) 10 and a second communication module (second communication device) 20.

[0085] The first communication module 10 includes a microphone 110, an I2S device 120, a SerDes 130, and an X'tal 160. The second communication module 20 includes a speaker 210, an I2S device 220, and a SerDes 230.

[0086] SerDes 130 is the PHY clock master. That is, SerDes 130 generates the PHY clock used on the physical layer of SerDes 130 based on X'tal 160. On the other hand, SerDes 230 is the PHY clock follower, operating synchronously with the PHY clock generated at SerDes 130. More specifically, SerDes 130 generates transmission symbols for the downlink using the PHY clock as the symbol clock and sends these transmission symbols to SerDes 230 via cable 300. SerDes 230 regenerates the PHY clock from the received transmission symbols and decodes the received transmission symbols using the regenerated PHY clock. Here, a transmission symbol corresponds to the smallest unit of the transmission signal variation interval. In the case of PAM (Pulse Amplitude Modulation) 2, the smallest unit is an interval of one bit transmitted per transmission symbol, and in the case of PAM 4, the smallest unit is an interval of two bits transmitted per transmission symbol.

[0087] like Figure 4 As shown, the SerDes 130 includes a PHY section 130-1, a LINK section 130-2, a wrapper (application system wrapper) 130-3, a dewrapper (application system dewrapper) 130-4, and a control register 130-5. The wrapper 130-3 and dewrapper 130-4 are configured for each application (such as I2S signal transmission). In this specification and accompanying drawings, the wrapper 130-3 and dewrapper 130-4 for I2S signal transmission are primarily described.

[0088] The PHY unit 130-1 includes a downlink transmitting unit (DOWN LINK Tx) 130-1-1, a PHY clock generation unit (physical layer clock generation unit, CLK GEN) 130-1-3, and an uplink receiving unit (UP LINK Rx) 130-1-2. The link unit 130-2 includes a frame construction unit 130-2-1, an OAM (Operation Application Maintenance) unit 130-2-3, and a frame deconstruction unit 130-2-2.

[0089] (Packet and frame configuration)

[0090] Figure 5 It is shown in Figure 4 A diagram illustrating the configuration of packets and frames generated in SerDes 130. Figure 4Encapsulator 130-3 in the middle divides signals from applications (such as microphone 110 or camera 150) into data packets for transmission of audio signals from microphone 110, video signals from camera 150, etc., and generates application data packets by adding headers to the data packets. Figure 5 (5-1)). The application data packet generated by the encapsulator 130-3 is sent to the frame construction unit 130-2-1 in the link unit 130-2.

[0091] The OAM section 130-2-3 in the link section 130-2 generates information obtained by monitoring the control or transmission status of the SerDes 130 and includes this information in the application data packet. The frame construction section 130-2-1 generates a container including a container header ( Figure 5 (5-2) in the middle), and further generate multiple container-to-link frames (Link Frame) (where multiple containers are placed together). Figure 5 (5-3)). The container comprises multiple application packets. For each of the multiple application packets, the container header includes the address of the SerDes130 itself, the address of the destination SerDes 230, the address of the receiver of the application packet, and information about the content of the application packet, etc.

[0092] The link frame generated by the frame construction unit 130-2-1 is sent to the downlink transmission unit 130-1-1 in the PHY unit 130-1. The processing of the link unit 130-2 uses a clock with a predetermined frequency, which is synchronized with the symbol clock generated at the PHY clock generation unit 130-1-3 in the PHY unit 130-1.

[0093] The downlink transmitting unit 130-1-1 in the PHY unit 130-1 adds a synchronization signal with a special mode to the link frame and generates a transmission frame. Figure 5 (5-4) in the middle.

[0094] On the other hand, the PHY clock generation unit 130-1-3 in the PHY unit 130-1 generates a symbol clock using the transmission symbol rate (e.g., 2GHz, 4GHz, 8GHz, etc.) of the transmission signal generated synchronously with the reference clock generated at X'tal160. Figure 5 (5-5) in the middle, and provide the symbol clock to the downlink transmitter 130-1-1.

[0095] Downlink transmitter 130-1-1 converts transmission frames into transmission symbols in sync with the symbol clock. Figure 5 (5-6) in the middle), and transmit the transmission symbol to the transmission cable 300 ( Figure 5 (5-7) in the middle.

[0096] Next, the reception processing of the SerDes 230 on the receiver side will be explained. Figure 4 The SerDes 230 in the middle has a PHY section 230-1, a link section 230-2, a wrapper (application stream wrapper) 230-3, a dewrapper (application stream dewrapper) 230-4, and a control register 230-5.

[0097] The PHY unit 230-1 includes an uplink transmitting unit (UP Link Tx) 230-1-1, a downlink receiving unit (Downlink Rx) 230-1-2, a CDR (Clock Data Recovery) 230-1-3, and a clock divider unit 230-1-4.

[0098] When a transmitted symbol is received, the downlink receiver 230-1-2 sends the received transmitted symbol to the CDR 230-1-3. The CDR 230-1-3 extracts the signal level changes of the received transmitted symbol and regenerates a symbol clock synchronized with the transmitted symbol rate. Figure 5 (5-9)). CDR 230-1-3 sends the regenerated symbol clock to downlink receiver 230-1-2 and clock divider 230-1-4.

[0099] Downlink receiver 230-1-2 determines the reception level of the transmitted symbol received at the appropriate time in sync with the symbol clock regenerated at CDR 230-1-3. Therefore, downlink receiver 230-1-2 can correctly receive the transmitted symbol. Downlink receiver 230-1-2 recovers the transmitted frame from the transmitted symbol. Furthermore, downlink receiver 230-1-2 uses a synchronization signal added to the transmitted frame as a clue to determine the position of subsequent link frames.

[0100] Clock divider 230-1-4 generates a suitable symbol clock for uplink transmission processing performed by SerDes 230. For example, the symbol clock generated by clock divider 230-1-4 has a frequency of 2 GHz or 4 GHz. Clock divider 230-1-4 generates the uplink symbol clock synchronously with the downlink symbol clock regenerated at CDR 230-1-3, and provides the uplink symbol clock to the uplink transmitter. In addition, clock divider 230-1-4 provides a clock with an appropriate frequency to link unit 230-2 for link frame processing.

[0101] The link unit 230-2 has a frame deconstruction unit 230-2-2, an OAM segment (OAM) 230-2-3 and a frame construction unit 230-2-1.

[0102] Frame destructuring unit 230-2-2 handles the link frames included in the input from downlink receiving unit 230-1-2. Figure 5 Each container in (5-3) Figure 5 The container header (5-2) is decoded, and if the container is used for OAM section 230-2-3, the container payload is sent to OAM section 230-2-3, and if the container is used for application, the container payload is sent to decapsulator 230-4 corresponding to the application.

[0103] Decapsulator 230-4 processes the application data packets corresponding to the container payload sent from frame deconstruction unit 230-2-2. Figure 5 The header of the data packet (5-1) is decoded, and the content of the subsequent application data packet is determined. Appropriate processing is performed, and the application signal is restored before transmission. Figure 4 (The I2S signal in the case shown). The recovered application signal is sent to the corresponding application. Figure 4 In the case shown, the recovered I2S signal is sent to I2S device 220. I2S device 220 recovers the audio signal from the I2S signal and reproduces the sound from speaker 210.

[0104] The signal processing described so far is as follows: the audio signal obtained by sound collection at microphone 110 is converted according to the I2S protocol at I2S device 120 to generate an application data packet; the generated application data packet is transmitted from SerDes 130 to SerDes 230; the I2S signal is recovered in SerDes 230; the audio signal is recovered from the I2S signal at I2S device 220; and the sound is output from speaker 210.

[0105] On the other hand, an application data packet can also be generated at SerDes 230 based on a signal from an application connected to SerDes 230, and the application data packet can be sent to SerDes 130 via the uplink in the reverse of the above process, and the signal can be regenerated at the application connected to SerDes 130.

[0106] At this time, the symbol clock used in the processing performed by the uplink transmitting unit 230-1-1 in SerDes 230 is the same as the symbol clock regenerated at the downlink receiving unit 230-1-2 and CDR 230-1-3. Figure 5Synchronization (5-9) is achieved. In this way, the symbol clocks of the downlink and uplink between SerDes 130 and SerDes 230 are synchronized with respect to the PHY clock generation unit 130-1-3 in SerDes 130. Furthermore, due to the uplink symbol clock generated at the PHY clock generation unit 130-1-3, the uplink receiving unit 130-1-2 in SerDes 130, which is the uplink receiver side, can easily receive the uplink signal from SerDes 230.

[0107] (Details on the transmitter side)

[0108] Figure 6 This is a block diagram showing the internal configuration of the package 130-3 and the PHY clock generation unit 130-1-3 in the transmitter-side I2S device 120 and SerDes 130.

[0109] Figure 6 The I2S device 120 shown includes an ADC 120-1, an I2S encoder 120-2, and a clock generation unit 120-3, and... Figure 1 Similar to the I2S device 120 in the example. The clock generation unit 120-3 generates the audio sampling clock, audio serial clock, and audio master clock MCK synchronously with the reference clock generated at X'tal 140.

[0110] Figure 6 The encapsulator 130-3 in the encapsulator corresponds to the I2S device 120 and has a FIFO 130-3-1, an MCK divider 130-3-2, a PMC (Period Measurement Counter) 130-3-3, and a data packet construction unit 130-3-4.

[0111] The PHY clock generation unit 130-1-3 includes a PLL circuit 130-1-3-1 and a clock divider unit 130-1-3-2. A reference clock generated at X'tal 160 is input to the PHY clock generation unit 130-1-3. The PLL circuit 130-1-3-1 generates a clock synchronized with the reference clock generated at X'tal 160. The clock divider unit 130-1-3-2 divides the clock generated by the PLL circuit 130-1-3-1 to generate the PHY clock. The PHY clock is used not only for internal processing in the downlink transmitter unit 130-1-1, the uplink receiver unit 130-1-2, and the link unit 130-2, but also as a reference clock for transmitting the MCK. Figure 6 In this context, the PHY clock generated at the PHY clock generation unit 130-1-3 is called the reference clock TxREFCK.

[0112] Typically, although this depends on the individual implementation, the symbol rate of the signals transmitted in the downlink and uplink is normalized, and the normalized symbol rate corresponding to the transmission speed is, for example, 2 GHz, 4 GHz, 6 GHz, or 8 GHz. Frequency division multiples of these symbol rates, such as 1 GHz, 500 MHz, 250 MHz, 125 MHz, and 62.5 MHz, can be readily generated. Therefore, in the example described in this embodiment, any one of 1 GHz, 500 MHz, 250 MHz, 125 MHz, and 62.5 MHz is used as the reference clock TxREFCK.

[0113] Figure 7 This is a timing diagram of MCK and TxREFCK generated by the symbol clock based on the PHY clock generation unit 130-1-3. Figure 8 This is a diagram illustrating an example of transmission parameters to be used for regenerating MCK on the receiver side. Figure 9 This is a configuration diagram of the application data package generated at SerDes 130.

[0114] The first I2S device 120 is connected to X'tal 140. The clock generation unit 120-3 generates sampling clocks 120-3-1, MCK 120-3-3, and SCK 120-3-2 synchronously with the clock generated at X'tal 140.

[0115] The ADC 120-1 converts the sound signal (audio signal) obtained at the microphone 110 into a digital signal using a sampling clock 120-3-1. The I2S encoder 120-2 converts the digital signal into... Figure 3 The I2S format is shown in the figure, and the I2S format signal is input to the wrapper 130-3 for I2S transmission connected thereto.

[0116] Encapsulator 130-3 synchronously stores the WS signal and SD signal from I2S encoder 120-2 on FIFO 130-3-1. The I2S signal in FIFO 130-3-1 is read out according to a readout clock with an appropriate speed, and an application data packet is generated at data packet construction section 130-3-4. Figure 9 (9-3) in the middle.

[0117] like Figure 7 As shown, the MCK divider 130-3-2 counts N, where N is an integer value set in the control register 130-5 of the MCK input from the I2S device 120. A start flag is generated after every N, and this start flag is output to the PMC 130-3-3. Figure 9 (9-1) and (9-2) in the middle.

[0118] PMC 130-3-3 counts the TxREFCKs during the duration of the interval between the start markers output from MCK division unit 130-3-2, and outputs the count value (PMC result value = M) to packet construction unit 130-3-4. Figure 7 (7-3 in the text). MCK frequency divider 130-3-2 and PMC 130-3-3 are measurement units that measure the number of reference signals TxREFCK in one cycle of the frequency divider signal included in MCK.

[0119] The control register 130-5 outputs to the data packet construction unit 130-3-4 the bit length (SD bit width) of the transmitted SD (I2S audio data), the number of transmitted audio channels, the frequency of the sampling clock (fs frq), the sampling clock multiple K (the frequency of the audio master clock MCK, fmck = K × fs frq), the MCK division number N, and the frequency information about TxREFCK (TxREFCK INFO).

[0120] The packet construction section 130-3-4 stores this information and the PMC result value M in the packet header. Figure 9 (9-2)). As described above, the data packet construction unit 130-3-4 generates an application data packet based on information from the control register 130-5, the PMC result value, and the I2S signal (SD). Figure 9 (9-1) in the middle, and output the application data packet to the frame construction part 130-2-1.

[0121] Figure 8 The values ​​of the division factor N of the audio master clock MCK and the expected count value of TxREFCK (PMC result value M) corresponding to the division factor N of the audio master clock MCK are shown when the TxREFCK frequency is 250MHz and the frequency of the audio master clock MCK is equal to the sampling clock frequency fs of 44.1kHz or 48kHz multiplied by 512 (K=512).

[0122] (Configuration of application data packets for I2S transport)

[0123] Figure 10A and Figure 10B This is a diagram illustrating the configuration of application data packets used for I2S signal transmission. Figure 10A Describes the configuration of the application data packet header (I2S header) used for I2S signal transmission. Figure 10B This describes the configuration of the application data packet (I2S data) and CRC used for I2S signal transmission.

[0124] Figure 10AThe bits [7:5] of the first byte in the I2S header shown indicate the I2S frame format. Bits [7:5] of 000 indicate I2S format, bits [7:5] of 001 indicate left-aligned format, bits [7:5] of 010 indicate right-aligned format, and any of bits [7:5] from 011 to 111 indicate reserved bits.

[0125] Figure 11A It is a timing diagram in the original I2S format. Figure 11B It is a left-aligned timing diagram, and Figure 11C It is a right-aligned sequence diagram.

[0126] like Figure 11A As shown, in the original I2S format, during the low-level period of the WS signal, the SD is transmitted bit by bit sequentially from the MSB. For example... Figure 11B As shown, in the left-aligned format, the SD signal is transmitted bit by bit sequentially from the MSB, synchronized with the timing of the WS signal transitioning from low to high. That is, the SD signal is transmitted in a left-aligned manner, synchronized with the timing of the rise of the WS signal. On the other hand, as... Figure 11C As shown, in the right-aligned format, the SD signal is transmitted in a right-aligned manner at the timing of the WS signal transitioning from high to low, such that the LSB of the transmitted SD signal is... Figure 10A The bits [7:5] of the first byte in the format specify whether the SD signal is in a left-aligned or right-aligned format.

[0127] Figure 10A The bits [4:3] of the first byte in the I2S header shown in the figure represent the I2S data bit width. Bits [4:3] of 00 represent 16 bits, bits [4:3] of 01 represent 18 bits, bits [4:3] of 10 represent 20 bits, and bits [4:3] of 11 represent 24 bits.

[0128] Figure 10A The first byte of the I2S header shown in the figure contains bits [2:0], which are 3-bit integers representing the number of stereo data. Bits [2:0] being 1 indicates that one stereo (L×R) data is sent, and bits [2:0] being 4 indicates that four stereo data are sent.

[0129] Figure 10A The bits [7:5] of the second byte in the I2S header shown represent the sampling clock frequency Fs. Bits [7:5] of 000 represent 44.1kHz, bits [7:5] of 001 represent 48kHz, bits [7:5] of 010 represent 96kHz, bits [7:5] of 011 represent 192kHz, and any of bits [7:5] from 100 to 111 represent reserved bits.

[0130] Figure 10AThe bits [4:0] of the second byte in the I2S header shown represent the multiple K used to generate the audio master clock MCK. Bits [4:0] of 0x00 represent 32, bits [4:0] of 0x01 represent 64, bits [4:0] of 0x02 represent 128, bits [4:0] of 0x03 represent 256, bits [4:0] of 0x04 represent 512, bits [4:0] of 0x05 represent 1024, and any of bits [4:0] from 0x06 to 0x1F represent reserved bits.

[0131] Figure 10A Bits [7:5] of the third byte in the I2S header described in the text are reserved bits.

[0132] Figure 10A The bits [4:0] of the third byte in the I2S header shown represent the five most significant bits N[12:8] of the division ratio N of the audio master clock MCK. The division ratio N is a 13-bit integer. Figure 10A The fourth byte of the I2S header shown represents N[7:0], and is the eight least significant bits of the audio master clock MCK.

[0133] The division ratio N of the audio master clock MCK depends on the frequency Fm of the audio master clock MCK (=24.576MHz, 22.5792MHz, etc.). If Fm=24.576MHz, then N=1536, and if Fm=22.5792MHz, then N=7056.

[0134] Figure 10A Bit 7 of the fifth byte in the I2S header shown is a reserved bit. Figure 10A The fifth byte [6:4] of the I2S header shown in the image represents TxREFCK information. Bits [6:4] of 000 represent 1 GHz, bits [6:4] of 001 represent 500 MHz, bits [6:4] of 010 represent 250 MHz, bits [6:4] of 100 represent 125 MHz, bits [6:4] of 101 represent 62.5 MHz, bits [6:4] of 110 represent 31.25 MHz, and bits [6:4] of 111 represent other frequencies.

[0135] Figure 10A Bits [3:2] of the fifth byte in the I2S header shown are reserved bits. Figure 10A The bits [1:0] in the fifth byte of the I2S header shown represent the PMC result value [17:16]. The PMC result value is an 18-bit integer. Figure 10AThe bits [7:0] of the sixth byte in the I2S header shown represent the PMC result value [15:8], and the bits [7:0] of the seventh byte in the I2S header represent the PMC result value [7:0]. The PMC result value is a measurement of Fm / N (seconds) based on a 250MHz reference clock TxREFCK. Ideally, when Fm = 24.576MHz and N = 1536, the PMC result value = 15625. When Fm = 22.5792MHz and N = 7056, the PMC result value = 78125. The receiving device can regenerate Fm by using the PMC result value and N.

[0136] Figure 10B The I2S data shown in the diagram starts from the m-th byte. Bits [7:0] of each byte represent the I2S data field. More specifically, bits [7:0] of the (m+n-1+p)-th byte in the I2S data represent the I2S data [15:8] of the L-channel of sample p in the n-th stereo data, and bits [7:0] of the (m+1+n-1+p)-th byte in the I2S data represent the I2S data [7:0] of the L-channel of sample p in the n-th stereo data. These two bytes represent the 16-bit data width data format of the L-channel in the n-th stereo data.

[0137] Figure 10B The bits [7:0] of the (m+2+n-1+p)th byte in the I2S data shown represent the I2S data [15:8] of the R channel of sample p in the nth stereo data, and the bits [7:0] of the (m+3+n-1+p)th byte in the I2S data represent the I2S data [7:0] of the R channel of sample p in the nth stereo data. These two bytes represent the 16-bit data width data format of the R channel in the nth stereo data.

[0138] Figure 10B The bits [7:0] of the (m+n-1+p)th byte in the I2S data shown represent the I2S data of the L channel of sample p in the nth stereo data [23:16], the bits [7:0] of the (m+1+n-1+p)th byte in the I2S data represent the I2S data of the L channel of sample p in the nth stereo data [15:8], and the bits [7:0] of the (m+2+n-1+p)th byte in the I2S data represent the I2S data of the L channel of sample p in the nth stereo data [7:0]. These three bytes represent the data format of the L channel in the nth stereo data with a data width of 18, 20, and 24 bits. The extra bits of the data with a data width of 18 or 20 bits are filled with 0.

[0139] Figure 10BThe bits [7:0] of the (m+3+n-1+p)th byte in the I2S data shown represent the I2S data of the R channel of sample p in the nth stereo data [23:16], the bits [7:0] of the (m+4+n-1+p)th byte in the I2S data represent the I2S data of the R channel of sample p in the nth stereo data [15:8], and the bits [7:0] of the (m+5+n-1+p)th byte in the I2S data represent the I2S data of the R channel of sample p in the nth stereo data [7:0]. These three bytes represent the data format of the R channel in the nth stereo data with a data width of 18, 20, and 24 bits. The extra bits of the data with a data width of 18 or 20 bits are filled with 0.

[0140] Figure 10B The bits [7:0] of the k-th byte in the CRC shown represent CRC32[31:24], the bits [7:0] of the (k+1)-th byte in the CRC represent CRC32[23:16], the bits [7:0] of the (k+2)-th byte in the CRC represent CRC32[15:8], and the bits [7:0] of the (k+3)-th byte in the CRC represent CRC32[7:0]. CRC32 is checked from the GPIO header of each GPIO payload to the end of the GPIO data. Cyclic Redundancy Check (CRC) uses a polynomial ring 0xF4ACFB13.

[0141] (Details on the receiver side)

[0142] Next, the internal structure and operation of SerDes 230 will be explained. Figure 12 This is a block diagram describing the internal configuration of the decapsulator 230-4 in the SerDes 230. The decapsulator 230-4 includes a packet destructuring unit 230-4-1, a FIFO 230-4-2, an I2S encoder (I2S ENC) 230-4-3, a REFCK ratio calculation unit (REFCK ratio calculation) 230-4-4, a TxREFCK regeneration unit 230-4-5, a TxREFCK frequency division unit 230-4-6, an MCK regeneration unit 230-4-7, and an SCK regeneration unit 230-4-8.

[0143] SerDes 230 regenerates the frequency fmck of the MCK generated by the transmitter-side I2S device 120, and sends the frequency fmck along with the regenerated I2S signals (SCK, WS, and SD) to the I2S device 220.

[0144] As already described, the CDR 230-1-3 in the PHY section 230-1 of the receiver-side SerDes 230 extracts the signal level change points of the received transmitted symbols and regenerates a symbol clock synchronized with the rate of the transmitted symbols transmitted from the SerDes 130. Figure 5 (5-9)). The clock divider (230-1-4) divides the symbol clock provided from CDR 230-1-3 ( Figure 5 The clocks in (5-9) are divided and the clocks required for processing each part are generated. Each of these clock frequencies depends on a separate implementation similar to the transmitter-side SerDes 130, and can be easily generated at frequencies such as 1GHz, 500MHz, 250MHz, 125MHz, and 62.5MHz, which are divided by the symbol rate, while maintaining synchronization with the transmitter-side symbol clock.

[0145] As the reference clock (RxREFCK) used for regenerating the I2S audio master clock MCK on the regenerator side, any one of the aforementioned 1GHz, 500MHz, 250MHz, 125MHz, 62.5MHz, etc., is used. Since the frequency used depends on the implementation, control register 230-5 provides information about the reference clock (RxREFCK_INFO) to de-encapsulator 230-4 used for I2S signal transmission. Simultaneously, clock divider 230-1-4 provides de-encapsulator 230-4 with the reference clock (RxREFCK) having the frequency specified in control register 230-5.

[0146] Next, the operation performed by the decapsulator 230-4 will be explained. The frame deconstruction unit 230-2-2 extracts the application data packets used for transmitting I2S signals. Figure 9 (9-1) in the middle, and provide the application data packet to the data packet destructuring unit 230-4-1.

[0147] Data packet deconstruction section 230-4-1 analyzes application data packets ( Figure 9 The packet header in (9-1) Figure 9 In (9-2), information is obtained for regenerating signals conforming to the I2S protocol, including the bit width of the transmitted SD (I2S audio data), the number of transmitted audio channels, the frequency of the sampling clock (fs frq), the sampling clock multiple K (the frequency of the audio master clock MCK, fmck = K × fs frq), the MCK division number N, the reference clock frequency information (TxREFCK INFO), and the TxREFCK measurement value (PMC result value).

[0148] The REFCK ratio calculation unit 230-4-4 calculates the frequency ratio R (=TxREFCK frequency / RxREFCK frequency) based on the frequency information TxREFCK INFO about the transmitter-side REFCK obtained from the control register 230-5 and the frequency information RxREFCK INFO about the receiver-side REFCK.

[0149] By using the obtained frequency ratio R, when the frequency R of RxREFCK is ≥ 1, the TxREFCK regeneration unit 230-4-5 multiplies the frequency of RxREFCK by R; when R < 1, the TxREFCK regeneration unit 230-4-5 divides RxREFCK by R, thereby regenerating a TxREFCK synchronized with RxREFCK. The frequency of the regenerated TxREFCK is the same as the frequency of the TxREFCK on the transmitter side.

[0150] The TxREFCK frequency divider 230-4-6 uses the PMC result value M obtained at the packet deconstruction unit 230-4-1 to divide the TxREFCK provided from the TxREFCK regeneration unit 230-4-5, and outputs the divided TxREFCK / M to the MCK regeneration unit 230-4-7.

[0151] By multiplying TxREFCK / M by the transmitter-side MCK division number N using N obtained from the packet deconstruction unit 230-4-1, the MCK regeneration unit 230-4-7 regenerates the audio master clock MCK synchronized with the transmitter-side audio master clock MCK. The above operation is the most important MCK regeneration procedure.

[0152] The SCK regeneration unit 230-4-8 regenerates SCK by multiplying the period of MCK by the reciprocal of K, where the reciprocal of K is the ratio of the sampling clock frequency fs frq to twice the SD bit width (SDBW).

[0153] On the other hand, the packet destructuring unit 230-4-1 extracts data from application packets ( Figure 9 Extract the SD (audio serial data) that has been divided into data packets from (9-1) in the middle. Figure 9 (9-3)) and write the SD data into FIFO 230-4-2 according to the write clock with an appropriate frequency.

[0154] The SD card written to FIFO 230-4-2 is read from SCK and provided to I2S encoder 230-4-3.

[0155] The I2S encoder 230-4-3 regenerates the signal by combining the information required by the I2S signal provided by the packet deconstruction unit 230-4-1, the SD bit width, the number of transmitted audio channels, and the sampling clock frequency (fs frq) with the SD bit width. Figure 3 The I2S signals, including SCK, WS, and SD signals, are output to the I2S device 220 connected to the SerDes 230, and the MCK regenerated at the MCK regeneration section 230-4-7 is also output to the I2S device 220.

[0156] I2S device 220 converts the I2S signal synchronized with MCK into an analog audio signal, and the audio signal is finally output as sound at speaker 210.

[0157] Through the above steps, the frequency information of the MCK on the transmitter side is sent to the receiver side, and the MCK can be accurately regenerated on the receiver side by using PHY clock synchronization between transmission and reception.

[0158] Thus, in the first embodiment, SerDes 130 receives the WS signal, SD, SCK, and MCK (whose frequency is equal to the product of the frequency of SCK and a multiple thereof) conforming to the I2S standard, measures the number of reference clocks TxREFCKs in a predetermined period of the frequency division signal included in MCK, and generates a data packet including the measured number, frequency information about the reference clock TxREFCK, the frequency division number N of the MCK, and the frequency ratio K of the MCK to the frequency fs of the sampling clock, and sends the data packet to SerDes 230. SerDes 230 receives the data packet and can recover the MCK based on the information included in the data packet. Therefore, even in this case, i.e., when SerDes 130 and SerDes 230 are asynchronously transmitting and receiving data packets with the I2S signal, SerDes 230 can recover the I2S signal from the received data packet and correctly regenerate the I2S signal.

[0159] (Second Implementation)

[0160] Although in the first embodiment, I2S device 120 and SerDes 130 operate asynchronously, I2S device 120 and SerDes 130 can operate according to clocks synchronized with each other.

[0161] Figure 13 This is a block diagram showing the internal configuration of the package 130-3 and the PHY clock generation unit 130-1-3 in the I2S device 120 and SerDes 130 according to the second embodiment. Figure 13 The I2S device 120 is connected to the clock generation unit 130-6, replacing... Figure 6X'tal 140 in the I2S device 120. The reference clock TxREFCK generated at the PHY unit 130-1 is input to the clock generation unit 130-6. The clock generation unit 130-6 generates, for example, a reference clock of 250MHz in sync with the reference clock TxREFCK. The clock generation unit 120-3 in the I2S device 120 generates, for example, a sampling clock of 50kHz and a 25.6MHz MCK in sync with the 250MHz reference clock generated at the clock generation unit 130-6.

[0162] The SerDes 130 according to the second embodiment operates similarly to the SerDes 130 according to the first embodiment, however, the parameters set by the control registers 130-5 are different from each other. Figure 14 This is a graph depicting the values ​​of the parameters used when regenerating MCK according to the SerDes230 of the second embodiment. In the second embodiment, TxREFCK and MCK are integer multiples of each other. Therefore, N = 64 and the PMC result value M = 625.

[0163] In this way, in the second embodiment, since the I2S device 120 operates synchronously with the reference clock TxREFCK generated by the PHY section 130-1 in the SerDes 130, the frequencies of the audio master clock MCK and TxREFCK can be given an integer multiple relationship. Furthermore, because the I2S device 120 generates the I2S signal synchronously with the PHY clock shared by the physical layers of the transmitter-side SerDes 130 and the receiver-side SerDes 230 in the second embodiment, it is not necessary to use... Figure 6 X'tal 140 in the second embodiment. Furthermore, since the frequency at which the I2S device 120 generates the I2S signal is higher than that in the first embodiment, the jitter characteristics on the regeneration side can be improved.

[0164] (Third Implementation)

[0165] SerDes 130 and SerDes 230 can manage information that synchronizes their timestamps. For example, in the case where SerDes 130 and SerDes 230 perform high-speed serial communication compliant with the ASA standard, PTB (Precise Time Base) is defined in the ASA standard. PTB achieves synchronization of time information with a resolution of 4n seconds (nsec) by exchanging data packets used as the time base between SerDes 130 and SerDes 230. The time information in PTB is synchronized with a 250MHz clock (hereinafter, the PTB clock), and this clock is used as TxREFCK. In this case, because the frequency of TxREFCK is fixed at 250MHz, frequency information about TxREFCK does not need to be sent to the receiver side. Similar to the first embodiment, other information (N, K, etc.) needs to be sent to SerDes 230 by being included in the header of the application data packet. Similarly, frequency information about RxREFCK is not required in SerDes 230.

[0166] Figure 15 This is a block diagram illustrating the internal configuration of the package 130-3 in the SerDes 130 according to a third embodiment. Figure 15 The package 130-3 and Figure 6 Similar to the one shown, it also has a FIFO 130-3-1, an MCK divider unit 130-3-2, a PMC 130-3-3, and a data packet construction unit 130-3-4. Instead of... Figure 6 The reference clock TxREFCK generated at PHY clock generation unit 130-1-3 and the PTB clock generated at PTB clock generation unit 130-7 are input to... Figure 15 The encapsulator 130-3 in the middle.

[0167] Figure 16 This is a block diagram showing the internal configuration of the decapsulator 230-4 in the SerDes 230 according to the third embodiment. Figure 16 The decapsulator 230-4 in the middle and Figure 12 Similar to the one shown, it also includes a packet destructuring unit 230-4-1, a FIFO 230-4-2, an I2S encoder (I2S ENC) 230-4-3, a TxREFCK frequency divider 230-4-6, an MCK regeneration unit 230-4-7, and an SCK regeneration unit 230-4-8. Instead of... Figure 12 The reference clock RxREFCK generated at PHY section 230-1 and the PTB clock generated at PTB clock generation section 230-6 are input to... Figure 16 The decapsulator 230-4 in the middle.

[0168] PTB clock generation unit 130-7 and PTB clock generation unit 230-6 generate PTB clocks synchronized with a Precision Time Base (PTB) conforming to the ASA standard. PTB achieves 4n-second resolution synchronization of time information by exchanging data packets used as the time base between SerDes 130 and SerDes 230. The 250MHz PTB clock used to generate PTB information is used as TxREFCK and RxREFCK. In this case, since the frequencies of TxREFCK and RxREFCK are determined to be 250MHz, and PTB clocks with the same frequency are generated on both the transmitter and receiver sides, TxREFCK INFO does not need to be sent to the receiver side. Other aspects of information and operation are the same as those of SerDes 130 and SerDes 230 according to the first embodiment.

[0169] In this way, SerDes 130 and SerDes 230 use the PTB clock to generate PTB information to manage timestamp information. Since this PTB clock is used as the reference clock TxREFCK and RxREFCK, there is no need to send information about TxREFCK from SerDes 130 to SerDes 230 and regenerate TxREFCK in SerDes 230. Therefore, the amount of information sent and received between SerDes 130 and SerDes 230 can be reduced, and the internal configuration of SerDes 130 and SerDes 230 can be simplified.

[0170] (Fourth Implementation)

[0171] In the fourth embodiment, not only SerDes 130 and SerDes 230 use the PTB clock, but I2S device 120 also uses the PTB clock.

[0172] Figure 17 This is a block diagram showing the internal configuration of the I2S device 120 and the package 130-3 in the SerDes 130 according to the fourth embodiment. Instead of the clock generated at X'tal 140, a 250MHz PTB clock generated at the PTB clock generation unit 130-7 is input to the I2S device 120.

[0173] Therefore, the I2S signals (SCK, SD, WS signals, and MCK) generated at I2S device 120 can be synchronized with the PTB clock. Furthermore, X'tal 140 can be omitted.

[0174] (Fifth Implementation)

[0175] The fifth embodiment is characterized in that, instead of transmitting frequency information about MCK from SerDes 130 to SerDes 230, a WS signal representing the frequency of the sampling clock is transmitted.

[0176] Figure 18 This is a block diagram showing the internal configuration of the I2S device 120 and the package 130-3 in the SerDes 130 according to the fifth embodiment. Figure 19 This is a timing diagram of the data packets transmitted between SerDes 130 and SerDes 230. Figure 20 This is a diagram showing the configuration of the application data package generated at SerDes 130.

[0177] Figure 18 The internal configuration of the I2S device 120 in the middle and Figure 6 and Figure 15 Those are the same as those in the text. Figure 18 The encapsulator 130-3 in SerDes130 includes a FIFO 130-3-1, a packet construction unit 130-3-4, and a PTB timestamp generator 130-3-5. The PTB timestamp generator 130-3-5 is provided as a replacement. Figure 15 The MCK frequency divider 130-3-2 and PMC 130-3-3 are located in the PTB clock. The PTB timestamp generator 130-3-5 operates synchronously with the PTB clock.

[0178] The WS signal, representing the frequency of the sampling clock from I2S device 120, and the PTB time with a resolution of 4n seconds (250MHz) provided from PTB timer 130-8 are provided to PTB timestamp generator 130-3-5. This PTB time is synchronized with the receiver-side PTB time through an ASA-compliant PTB synchronization process.

[0179] The PTB timestamp generator 130-3-5 performs sampling of the rising edge of the input WS based on the PTB time with a resolution of 4n seconds (250MHz) provided from the PTB timer 130-8, that is, almost at the center of a sampling interval of the I2S data, and provides the PTB time to the packet construction unit 130-3-4.

[0180] The packet construction unit 130-3-4 obtains SD and WS, which are I2S audio data rate-adjusted via FIFO 130-3-1. Figure 19 The timing specified in (19-2), (19-4) will include the acquired SD in the application data packet. Note that the SD configuration can be related to... Figure 9This is the same as (9-3) in the previous section. Therefore, the number of SD samples included in each application packet is not constant, but can increase or decrease. Figure 19 In the example shown, the nth data packet includes an SD containing L samples, and the (n+1)th data packet includes an SD containing J samples. Figure 19 (19-2) in the middle.

[0181] The packet construction section 130-3-4 includes the number of SD samples in the header of each application packet. Figure 19 (19-4 in the middle).

[0182] Furthermore, the packet construction section 130-3-4 includes TS1 and TS2 in the packet header, where TS1 and TS2 are generated from the PTB timestamp generator 130-3-5. Figure 19 In section 19-4), the PTB time of the rising edge of the WS of the output SD is the PTB time of the first SD and the last SD included in the application data packet.

[0183] The data packet construction unit 130-3-4 also obtains the bit length (SD bit width), the number of audio channels to be transmitted, and the sampling clock frequency (fs frq) of the transmitted SD (I2S audio data) from the control register 130-5 as reference information, and includes these information, TS1, TS2, and the number of samples in the data packet header.

[0184] In this way, the packet header generated by the packet construction unit 130-3-4 has the following characteristics: Figure 20 The SD bit width, number of channels, sampling clock frequency fs frq, TS1, TS2, and number of samples are shown.

[0185] SD bit width is the bit width of the SD (I2S audio serial data) for each channel. Channel number is the number of audio channels. For example, with channel number = 2, this means normal stereo. fs frq is the frequency of the audio sampling clock, such as 44.1kHz or 48kHz. TS1 is the timing of the rising edge of the WS in the first SD of a packet of multiple SDs. TS2 is the timing of the rising edge of the WS in the last SD of a packet of multiple SDs. Sample number is the number of SD samples included in a packet.

[0186] Additionally, the application data packet following the data packet header includes multiple SDs corresponding to all samples. Each SD is serial data specified by the sample number and channel number. The data packet construction section 130-3-4 creates the application data packet by summing the data packet header and the application data packet including the multiple SDs. Figure 19 (19-4) and output the application data packet to the frame construction section 130-2-1.

[0187] The frame construction unit 130-2-1 adds 'sync' to multiple application data packets for synchronization, configures the transmission frame, and finally outputs the transmission frame to the channel. Because these processes are related to... Figure 5 The ones in ((5-4)) to ((5-7)) are the same, so their descriptions are omitted.

[0188] Next, the receiver-side processing will be described. The processing operation of the frame deconstruction unit in SerDes 230 is similar to the processing operation in the first to fourth embodiments.

[0189] Figure 21 This is a block diagram showing the internal structure of the decapsulator 230-4 in the fifth embodiment of the SerDes 230. Figure 21 The decapsulator 230-4 in the middle has a data packet deconstruction unit 230-4-1, a FIFO 230-4-2, an I2S encoder 230-4-3, an MCK regeneration unit 230-4-7, an SCK regeneration unit 230-4-8, a WS frequency calculation unit, and a PTB clock division unit.

[0190] The processing operation of the data packet decomposition unit 230-4-1 is similar to that in the first to fourth embodiments. The data packet decomposition unit 230-4-1 obtains the rising edge positions of the WS representing the first and last data of all L samples of the SD, as well as the PTB timestamps TS1 and TS2 of the sample number included in the data packet header of the received application data packet, and provides them to the WS frequency calculation unit 230-4-9. The WS frequency calculation unit 230-4-9 calculates (TS2 - TS1) / (sample number). The result of this calculation represents the average period of the audio sampling clock frequency.

[0191] Furthermore, by summing the calculated results of (TS2 - TS1) / (number of samples) obtained from each of the multiple data packets and determining the average value, the period of the sampling clock frequency can be obtained with higher precision. The WS frequency calculation unit 230-4-9 outputs the obtained period to the PTB clock divider unit 230-4-10.

[0192] The PTB clock divider 230-4-10 generates the WS signal by dividing the 250MHz clock provided by the PTB clock generation unit 230-6 by the value obtained by the WS frequency calculation unit 230-4-9. The frequency of the WS signal is the same as the frequency of the sampling clock.

[0193] The MCK regeneration unit 230-4-7 uses K obtained from the control register 230-5 to multiply the WS signal generated at the PTB clock divider 230-4-10 by a factor of K, thereby regenerating the audio master clock MCK necessary for processing at the I2S device 220.

[0194] Furthermore, the SCK regeneration unit 230-4-8 regenerates the SCK by setting the SCK period to the period obtained by multiplying the WS signal period by the SD bit width and then by 2. Synchronously with this SCK, the SD is read from the FIFO 230-4-2 and encoded in the I2S encoder 230-4-3. Since the processing performed in and after the I2S encoder 230-4-3 is the same as the processing performed in the SerDes 230 of the first to fourth embodiments, its description is omitted.

[0195] Figure 22A and Figure 22B This is a diagram showing more specifically the configuration of the application data packet transmitted by the I2S signal generated by the SerDes 130 according to the fifth embodiment. Figure 22A This shows the configuration of the application data packet header (I2S header) used for I2S signal transmission, and Figure 22B This shows the configuration of the application data packet (I2S data) and CRC for I2S signal transmission.

[0196] because Figure 22B and Figure 10B Since they are the same, their descriptions are omitted. Figure 22A The latter half of the I2S header is different from Figure 10A The I2S header in the text. The following text mainly explains the relationship with... Figure 10A Differences in the I2S header.

[0197] Figure 22A The bits [7:5] of the first and second bytes of the I2S header shown in the figure are... Figure 10A Those are the same as those in the text. Figure 22A Bits [4:0] of the second byte in the I2S header described in the document are reserved bits. Figure 22A In the I2S header described in the documentation, bits [7:0] of the third byte represent TS1[23:16], bits [7:0] of the fourth byte represent TS1[15:8], and bits [7:0] of the fifth byte represent TS1[7:0]. Within these third to fifth bytes, TS1 represents a 24-bit integer and indicates the PTB time of the rising edge of the WS signal at the first SD of the multiple SDs in the data packet.

[0198] Figure 22AIn the I2S header shown, bits [7:0] of the sixth byte represent TS2[23:16], bits [7:0] of the seventh byte represent TS2[15:8], and bits [7:0] of the eighth byte represent TS2[7:0]. Within these sixth to eighth bytes, TS2 represents a 24-bit integer and indicates the PTB time of the rising edge of the WS signal at the last SD in the multiple SDs within the data packet.

[0199] Figure 22A The bits [7:0] of the ninth byte in the I2S header shown represent the number of samples [15:8], and the bits [7:0] of the tenth byte in the I2S header represent the number of samples [7:0]. These ninth and tenth bytes represent 16-bit integers and indicate the number of I2S data samples sent in this data packet.

[0200] Note that, as explained so far... Figure 9 , Figure 10A , Figure 20 and Figure 22A In this context, setting information is included as values ​​in the packet header. Information such as the bit width of the transmitted SD (I2S audio data), the number of transmitted audio channels, the sampling clock frequency (fs frq), the sampling clock multiple K (MCK frequency, fmck = K × fs frq), the MCK division number N, or the reference clock frequency information (TxREFCK INFO) once set does not need to be sent in every instance of packet transmission and may not be included in the packet header. However, it can be sent from the transmitter side to the receiver side using the OAM channel or other information transmission means.

[0201] Furthermore, for example, as explained so far Figure 9 and Figure 20 The application data packet described in the document is used for transmitting I2S signals. Figure 9 (9-1) and Figure 20 (20-1) in the example can be transmitted not for a single application, but can be arranged in a way that is not specific to a single application. Figure 23 The video data is transmitted within the application data packets described herein. Figure 23 In the example described, multiple video data are included in the application data packet, and I2S audio data is included between these video data.

[0202] In this way, in the fifth embodiment, since the timing TS1 of the rising edge of the WS signal in the first SD of the multiple SDs in the application data packet, the timing TS2 of the rising edge of the WS signal in the last SD of the multiple SDs, and the number of SD samples are included in the data packet header, the average period of the sampling clock frequency can be calculated, and the WS signal can be generated based on the calculation result. Therefore, unlike the first to fourth embodiments, the fifth embodiment eliminates the need to transmit MCK from the transmitter side SerDes 130 to the receiver side SerDes 230 and to measure the number of reference clocks TxREFCK included in the frequency division signal of MCK in SerDes 230, and thus simplifies the configuration in SerDes 230.

[0203] It should be noted that this technology can be implemented with the following configurations. (1)

[0205] A communication device, comprising:

[0206] The measurement unit measures the number of predetermined reference clocks included in one cycle of the frequency division signal based on the audio master clock, the frequency division ratio of the frequency division signal relative to the audio master clock, and a predetermined reference clock. The frequency of the audio master clock is equal to the product of the frequency of the sampling clock used to sample the audio signal and a multiple thereof.

[0207] The data packet generation unit generates data packets containing information, including the quantity measured at the measurement unit, the bit width of the SD (serial data) conforming to the I2S standard, the frequency of the sampling clock, the division ratio of the frequency divider signal relative to the audio master clock, the frequency ratio of the audio master clock frequency relative to the sampling clock frequency, and the SD. (2)

[0209] According to the communication device described in (1), wherein

[0210] The data packets generated by the data packet generation unit include a header and a data portion.

[0211] The header includes the quantity measured at the measurement unit, the bit width of the SD, the frequency of the sampling clock, the division ratio, and the frequency ratio, and

[0212] The data section includes multiple SDs. (3)

[0214] According to the communication device described in (2), wherein

[0215] The header includes the bit width of the SD, the number of SD channels, the frequency of the sampling clock, the division ratio of the frequency division signal relative to the audio master clock, the frequency ratio of the audio master clock frequency relative to the sampling clock frequency, the frequency of the reference clock, and the quantity measured at the measurement unit. (4)

[0217] According to the communication device described in (3), wherein

[0218] The data section includes SDs corresponding to the number of channels and the number of samples. (5)

[0220] The communication device according to any one of (1) to (4) comprises:

[0221] The physical layer clock generation unit generates a clock that will be used by both the communication device and the communication partner device's physical layer; and

[0222] The frequency divider divides the clock generated at the physical layer clock generation unit and generates a reference clock. (6)

[0224] According to the communication device described in (5), wherein

[0225] The clock frequency generated at the physical layer clock generation unit is 250MHz. (7)

[0227] According to the communication device described in (6), wherein

[0228] The audio master clock frequency is 25.6MHz, and

[0229] The sampling clock frequency is 50kHz. (8)

[0231] The communication device according to any one of (1) to (7), wherein

[0232] The sampling clock and audio master clock are asynchronous with the reference clock. (9)

[0234] The communication device according to any one of (1) to (7), wherein

[0235] The sampling clock and audio master clock are synchronized with the reference clock. (10)

[0237] The communication device according to any one of (1) to (4) comprises:

[0238] The PTB clock generation unit generates a PTB (Precise Time Base) clock. The PTB clock is used to generate timestamp information shared by the communication device and its communication partner device.

[0239] The reference clock is the PTB clock. (11)

[0241] According to the communication device described in (10), wherein

[0242] The audio master clock is synchronized with the PTB clock. (12)

[0244] According to the communication device described in (10) or (11), wherein

[0245] The PTB clock frequency is 250MHz. (13)

[0247] A communication device, comprising:

[0248] The measurement unit receives a WS (word select) signal conforming to the I2S standard and measures first timing information and second timing information based on a predetermined reference clock shared by the communication device and the communication partner device. The first timing information indicates the timing of the logical change of the WS signal in the first SD (serial data) of multiple SDs included in a data packet sent to the communication partner device, and the second timing information indicates the timing of the logical change of the WS signal in the last SD.

[0249] The data packet generation unit generates a data packet that includes the bit width of the SD, the frequency of the sampling clock used to sample the audio signal, first timing information, second timing information, the number of SD entries included in a data packet, and the data packet containing the SD. (14)

[0251] According to the communication device described in (13), wherein

[0252] The packet generation unit generates packets that also include information about the number of SD channels. (15)

[0254] A communication device, comprising:

[0255] The recovery unit receives data packets sent from the communication partner device and recovers from the data packets the SD (serial data) conforming to the I2S standard, the bit width of the SD, the frequency of the sampling clock used to sample the audio signal, the frequency ratio of the audio master clock frequency to the sampling clock frequency, the number of predetermined first reference clocks included in one cycle of the audio master clock division signal, the frequency of the sampling clock, and the division ratio of the division signal to the audio master clock.

[0256] The audio master clock regeneration unit regenerates the audio master clock based on the number of first reference clocks, the frequency of the first reference clocks, and the division ratio; and

[0257] The SCK regeneration unit regenerates the SCK (serial clock) based on information about the bit width of the SD, the frequency ratio, and the audio master clock. (16)

[0259] The communication device according to (15) includes:

[0260] The clock regeneration circuit generates a second reference clock that is synchronized with the signal changes of SD based on data packets; and

[0261] The frequency ratio calculation unit calculates the frequency ratio between the frequency of the first reference clock and the frequency of the second reference clock, wherein...

[0262] The audio master clock regeneration unit regenerates the audio master clock based on the number of first reference clocks, frequency information about the first reference clocks, the division ratio, and the frequency ratio calculated by the frequency ratio calculation unit. (17)

[0264] The communication device according to (15) or (16) includes:

[0265] The PTB clock generation unit generates a PTB (Precise Time Base) clock. The PTB clock is used to generate timestamp information shared by the communication device and its communication partner device.

[0266] The primary reference clock is the PTB clock. (18)

[0268] A communication device, comprising:

[0269] The recovery unit receives data packets sent from the communication partner device and recovers from the data packets the following information: SD (serial data) conforming to the I2S standard, bit width information about the SD, frequency information about the SCK (serial clock), first timing information indicating the timing of the first logical change of the WS (word select) signal contained in a data packet, second timing information indicating the timing of the last logical change of the WS signal, and the number of SDs contained in a data packet.

[0270] The clock generation unit generates a reference clock that will be used by the communication device and the communication partner device.

[0271] The WS signal regeneration unit regenerates the WS signal based on the first timing information, the second timing information, the number of SD lines, and the reference clock.

[0272] The audio master clock regeneration section regenerates the audio master clock, and the frequency of the audio master clock is equal to the product of the frequency of the WS signal regenerated at the WS signal regeneration section and a multiple thereof; and

[0273] The SCK regeneration unit regenerates the SCK based on the WS signal regenerated at the WS signal regeneration unit and the bit width information about SD. (19)

[0275] The communication device according to (14) or (18) includes:

[0276] The PTB clock generation unit generates a PTB (Precise Time Base) clock. The PTB clock is used to generate timestamp information shared by the communication device and its communication partner device.

[0277] The reference clock is the PTB clock. (20)

[0279] The communication device according to any one of (1) to (19), wherein

[0280] Data packets are sent within the time period allocated by TDD (Time Division Duplex). (twenty one)

[0282] First communication device; and

[0283] The second communication device communicates serially with the first communication device, wherein...

[0284] The first communication device includes:

[0285] The measurement unit, based on the audio master clock, the division ratio of the frequency division signal relative to the audio master clock, and a predetermined reference clock, determines the number of predetermined reference clock cycles included in one period of the frequency division signal. The frequency of the audio master clock is equal to the product of the frequency of the sampling clock used to sample the audio signal and a multiple thereof.

[0286] The data packet generation unit generates data packets containing information, including the quantity measured at the measurement unit, the bit width of the SD (serial data) conforming to the I2S standard, the frequency of the sampling clock, the division ratio of the frequency divider signal relative to the audio master clock, the frequency ratio of the audio master clock frequency relative to the sampling clock frequency, and the SD, and

[0287] The second communication device includes:

[0288] The recovery unit receives data packets sent from the first communication device and recovers from the data packets the SD, the bit width of the SD, the frequency of the sampling clock, the frequency ratio of the audio master clock to the sampling clock, the predetermined number of first reference clocks in one cycle of the frequency division signal of the audio master clock, the frequency of the sampling clock, and the frequency division ratio of the frequency division signal to the audio master clock.

[0289] The audio master clock regeneration unit regenerates the audio master clock based on the number of first reference clocks, the frequency of the first reference clocks, and the division ratio; and

[0290] The SCK regeneration unit regenerates the SCK (serial clock) based on information about the bit width of the SD, the frequency ratio, and the audio master clock. (twenty two)

[0292] A communication system, comprising:

[0293] First communication device; and

[0294] The second communication device communicates serially with the first communication device, wherein...

[0295] The first communication device includes:

[0296] The measurement unit receives a WS (word select) signal conforming to the I2S standard and measures first timing information and second timing information based on a predetermined reference clock shared by the first and second communication devices. The first timing information indicates the timing of the logical change of the WS signal in the first SD (serial data) of multiple SDs included in a data packet sent to the second communication device, and the second timing information indicates the timing of the logical change of the WS signal in the last SD.

[0297] The data packet generation unit generates data packets including the bit width of the SD, the frequency of the sampling clock used to sample the audio signal, first timing information, second timing information, the number of SD segments included in a data packet, and the SD data packet itself.

[0298] The second communication device includes:

[0299] The recovery unit receives data packets sent from the first communication device and recovers from the data packets the following information: SD (serial data) conforming to the I2S standard, bit width information of the SD, frequency information of the SCK (serial clock), first timing information indicating the timing of the first logical change of the WS (word select) signal contained in a data packet, second timing information indicating the timing of the last logical change of the WS signal, and the number of SD entries contained in a data packet.

[0300] The clock generation unit generates a reference clock that will be used by both the second and first communication devices.

[0301] The WS signal regeneration unit regenerates the WS signal based on the first timing information, the second timing information, the number of SD lines, and the reference clock.

[0302] The audio master clock regeneration section regenerates the audio master clock. The frequency of the audio master clock is equal to the product of the frequency of the WS signal regenerated at the WS signal regeneration section and a multiple thereof.

[0303] The SCK regeneration unit regenerates the SCK based on the WS signal regenerated at the WS signal regeneration unit and the bit width information about SD.

[0304] This disclosure is not limited to the various embodiments mentioned above and covers various modifications that can be conceived by those skilled in the art, and the advantages of this disclosure are not limited to those mentioned above. That is, various types of additions, changes, and partial deletions can be made without departing from the conceptual idea and spirit of this disclosure derived from the content set forth in the claims and their equivalents.

[0305] [List of Reference Numbers]

[0306] 1: Communication System

[0307] 10: First Communication Module

[0308] 20: Second Communication Module

[0309] 100: First communication module

[0310] 110: Microphone

[0311] 120: The first I2S device

[0312] 120-2: I2S encoder

[0313] 120-3: Clock Generation Department

[0314] 130: SerDes

[0315] 130-1: PHY Department

[0316] 130-1-1: Link Transmission Unit

[0317] 130-1-2: Link Receiving Unit

[0318] 130-1-3: PHY Clock Generation Unit

[0319] 130-1-3-1: PLL Circuit

[0320] 130-1-3-2: Clock divider section

[0321] 130-2: Link Department

[0322] 130-2-1: Frame Construction Department

[0323] 130-2-2: Frame Deconstruction Section

[0324] 130-2-3: OAM Department

[0325] 130-3: Packager

[0326] 130-3-2: MCK frequency divider

[0327] 130-3-4: Data Packet Construction Section

[0328] 130-3-5: PTB Timestamp Generator

[0329] 130-4: Decapsulator

[0330] 130-5: Control Register

[0331] 130-6: Clock Generation Department

[0332] 130-7: PTB Clock Generation Unit

[0333] 130-8: PTB Timer

[0334] 130t: SerDes

[0335] 150: Camera

[0336] 200: Second communication module

[0337] 210: Speaker

[0338] 220: I2S device

[0339] 220-1: I2S Decoder

[0340] 220-3: Clock divider section

[0341] 230: SerDes

[0342] 230-1: PHY Department

[0343] 230-1-1: Link Transmission Unit

[0344] 230-1-2: Link Receiving Unit

[0345] 230-1-4: Clock divider section

[0346] 230-2: Link Section

[0347] 230-2-2: Frame Deconstruction Section

[0348] 230-2-3: OAM Department

[0349] 230-3: Packager

[0350] 230-4-3: I2S Encoder

[0351] 230-4: Decapsulator

[0352] 230-4-1: Data Packet Destruction Section

[0353] 230-4-10: PTB clock divider

[0354] 230-4-3: I2S Encoder

[0355] 230-4-4: REFCK Comparison Calculation Department

[0356] 230-4-5: TxREFCK Regeneration Department

[0357] 230-4-6: TxREFCK crossover section

[0358] 230-4-7: MCK Regeneration Department

[0359] 230-4-7: Regeneration Department

[0360] 230-4-8: SCK Regeneration Department

[0361] 230-4-8: Regeneration Department

[0362] 230-4-9: WS Frequency Calculation Department

[0363] 230-5: Control Register

[0364] 230-6: PTB Clock Generation Unit

[0365] 230-6: Clock

[0366] 250: Video Decoder

[0367] 250MHz: Resolution

[0368] 260: ADAS / ADS processor

[0369] 300: Transmission cable.

Claims

1. A communication device, comprising: The measurement unit determines the number of predetermined reference clocks included in one cycle of the frequency division signal based on the audio master clock, the frequency division ratio of the frequency division signal of the audio master clock, and a predetermined reference clock. The frequency of the audio master clock is equal to the product of the frequency of the sampling clock used to sample the audio signal and a multiple thereof. The data packet generation unit generates a data packet containing information, including the quantity measured at the measurement unit, the bit width of the serial data conforming to the I2S standard, the frequency of the sampling clock, the division ratio of the frequency division signal relative to the audio master clock, the frequency ratio of the audio master clock frequency relative to the sampling clock frequency, and the serial data.

2. The communication device according to claim 1, wherein, The data packet generated by the data packet generation unit includes a header portion and a data portion. The header portion includes the quantity measured at the measuring unit, the bit width of the serial data, the frequency of the sampling clock, the division ratio, and the frequency ratio, and The data portion includes multiple serial data entries.

3. The communication device according to claim 2, wherein, The header includes the bit width of the serial data, the number of channels of the serial data, the frequency of the sampling clock, the division ratio of the frequency division signal relative to the audio master clock, the frequency ratio of the audio master clock frequency relative to the sampling clock frequency, the frequency of the reference clock, and the quantity measured at the measurement unit.

4. The communication device according to claim 3, wherein, The data portion includes the serial data corresponding to the number of channels and the number of samples.

5. The communication device according to claim 1, comprising: The physical layer clock generation unit generates a clock that will be used by the physical layers of both the communication device and the communication partner device. as well as The frequency divider divides the clock generated at the physical layer clock generation unit and generates the reference clock.

6. The communication device according to claim 5, wherein, The clock frequency generated at the physical layer clock generation unit is 250MHz.

7. The communication device according to claim 6, wherein, The frequency of the audio master clock is 25.6MHz, and The sampling clock frequency is 50kHz.

8. The communication device according to claim 1, wherein, The sampling clock and the audio master clock are asynchronous with the reference clock.

9. The communication device according to claim 1, wherein, The sampling clock and the audio master clock are synchronized with the reference clock.

10. The communication device according to claim 1, comprising: A precise time-base clock generation unit generates a precise time-base clock, which is used to generate timestamp information shared by the communication device and the communication partner device. The reference clock is the precise time base clock.

11. The communication device according to claim 10, wherein, The audio master clock is synchronized with the precision time base clock.

12. The communication device according to claim 10, wherein, The frequency of the precision time base clock is 250MHz.

13. A communication device, comprising: The measurement unit receives a word selection signal conforming to the I2S standard and measures first timing information and second timing information based on a predetermined reference clock used by the communication device and the communication partner device. The first timing information indicates the timing of the logical change of the word selection signal in the first of multiple serial data included in a data packet to be sent to the communication partner device, and the second timing information indicates the timing of the logical change of the word selection signal in the last of the serial data. as well as The data packet generation unit generates a data packet that includes the bit width of serial data, the frequency of the sampling clock used to sample the audio signal, the first timing information, the second timing information, the number of serial data segments included in the data packet, and the data packet containing the serial data.

14. The communication device according to claim 13, wherein, The data packet generation unit generates data packets that also include information about the number of channels in the serial data.

15. A communication device, comprising: The recovery unit receives data packets sent from a communication partner device and recovers from the data packets serial data conforming to the I2S standard, the bit width of the serial data, the frequency of the sampling clock used for sampling the audio signal, the frequency ratio of the audio master clock frequency to the sampling clock frequency, the number of predetermined first reference clocks included in one cycle of the frequency division signal of the audio master clock, the frequency of the sampling clock, and the frequency division ratio of the frequency division signal to the audio master clock. The audio master clock regeneration unit regenerates the audio master clock based on the number of the first reference clocks, the frequency of the first reference clocks, and the frequency division ratio. as well as The serial clock regeneration unit regenerates the serial clock based on the bit width information of the serial data, the frequency ratio, and the audio master clock.

16. The communication device according to claim 15, comprising: A clock regeneration circuit generates a second reference clock based on the data packet, which is synchronized with the signal changes of the serial data. as well as The frequency ratio calculation unit calculates the frequency ratio between the frequency of the first reference clock and the frequency of the second reference clock, wherein... The audio master clock regeneration unit regenerates the audio master clock based on the number of the first reference clocks, the frequency information about the first reference clocks, the division ratio, and the frequency ratio calculated by the frequency ratio calculation unit.

17. The communication device according to claim 15, comprising: A precise time-base clock generation unit generates a precise time-base clock, which is used to generate timestamp information shared by the communication device and the communication partner device. The first reference clock is the precise time base clock.

18. A communication device, comprising: The recovery unit receives data packets sent from a communication partner device and recovers from the data packets serial data conforming to the I2S standard, bit width information of the serial data, frequency information of the serial clock, first timing information indicating the timing of the first logical change of the word selection signal in the word selection signal contained in a data packet, second timing information indicating the timing of the last logical change of the word selection signal, and the number of serial data entries contained in the data packet. A clock generation unit generates a reference clock that will be used by the communication device and the communication partner device. The word selection signal regeneration unit regenerates the word selection signal based on the first timing information, the second timing information, the number of serial data entries, and the reference clock. The audio master clock regeneration unit regenerates the audio master clock, the frequency of which is equal to the product of the frequency of the word selection signal regenerated at the word selection signal regeneration unit and a multiple thereof; as well as The serial clock regeneration unit regenerates the serial clock based on the word selection signal regenerated at the word selection signal regeneration unit and the bit width information about the serial data.

19. The communication device according to claim 18, comprising: A precise time-base clock generation unit generates a precise time-base clock, which is used to generate timestamp information shared by the communication device and the communication partner device. The reference clock is the precise time base clock.

20. The communication device according to claim 18, wherein, The data packets are transmitted within the time period allocated by the time-division duplex.

21. A communication system, comprising: First communication device; as well as The second communication device communicates serially with the first communication device, wherein... The first communication device includes: The measurement unit, based on the audio master clock, the division ratio of the frequency division signal relative to the audio master clock, and a predetermined reference clock, determines the number of predetermined reference clocks included in one cycle of the frequency division signal. The frequency of the audio master clock is equal to the product of the frequency of the sampling clock used to sample the audio signal and a multiple thereof. A data packet generation unit generates a data packet containing information, including the quantity measured at the measurement unit, the bit width of the serial data conforming to the I2S standard, the frequency of the sampling clock, the division ratio of the frequency division signal relative to the audio master clock, the frequency ratio of the audio master clock frequency relative to the sampling clock frequency, and the serial data. The second communication device includes: The recovery unit receives data packets sent from the first communication device and recovers from the data packets the serial data, the bit width of the serial data, the frequency of the sampling clock, the frequency ratio of the audio master clock to the sampling clock, the predetermined number of first reference clocks included in one period of the frequency division signal of the audio master clock, the frequency of the sampling clock, and the frequency division ratio of the frequency division signal to the audio master clock. The audio master clock regeneration unit regenerates the audio master clock based on the number of the first reference clocks, the frequency of the first reference clocks, and the frequency division ratio; and The serial clock regeneration unit regenerates the serial clock based on the bit width information of the serial data, the frequency ratio, and the audio master clock.

22. A communication system, comprising: First communication device; as well as The second communication device communicates serially with the first communication device, wherein... The first communication device includes: The measurement unit receives a word select signal conforming to the I2S standard and measures first timing information and second timing information based on a predetermined reference clock shared by the first and second communication devices. The first timing information indicates the timing of a logical change in the word select signal in the first of multiple serial data items included in a data packet to be sent to the second communication device. The second timing information indicates the timing of a logical change in the word select signal in the last of the serial data items. The data packet generation unit generates a data packet including the bit width of the serial data, the frequency of the sampling clock for sampling the audio signal, the first timing information, the second timing information, the number of serial data segments included in the data packet, and the data packet containing the serial data. The second communication device includes: The recovery unit receives the data packet sent from the first communication device and recovers from the data packet serial data conforming to the I2S standard, bit width information of the serial data, frequency information of the serial clock, first timing information indicating the timing of the first logical change of the word select signal in the word select signal included in the data packet, second timing information indicating the timing of the last logical change of the word select signal, and the number of serial data segments included in the data packet. The clock generation unit generates a reference clock that will be used by both the second communication device and the first communication device. The word selection signal regeneration unit regenerates the word selection signal based on the first timing information, the second timing information, the number of serial data entries, and the reference clock. An audio master clock regeneration unit regenerates an audio master clock, the frequency of which is equal to the product of the frequency of the word selection signal regenerated at the word selection signal regeneration unit and a multiple thereof. The serial clock regeneration unit regenerates the serial clock based on the word selection signal regenerated at the word selection signal regeneration unit and the bit width information about the serial data.

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