Mask plate and photolithography method

Abstract

The application belongs to the technical field of semiconductor manufacturing, and particularly relates to a mask plate and a photolithography method. The mask plate comprises a main body region, a first cutting path region and a second cutting path region oppositely located on both sides of the main body region; a first overlay measurement mark and a first opaque region are arranged in the first cutting path region, a second overlay measurement mark and a second opaque region are arranged in the second cutting path region, the position of the first opaque region in the first cutting path region is the same as the position of the second overlay measurement mark in the second cutting path region, and the size of the first opaque region is greater than or equal to the size of the second overlay measurement mark; the position of the second opaque region in the second cutting path region is the same as the position of the first overlay measurement mark in the first cutting path region, and the size of the second opaque region is greater than or equal to the size of the first overlay measurement mark. After photolithography is performed using the mask plate, the overlay measurement marks in the cutting path regions can be reserved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and particularly relates to a photomask and photolithography method. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials, design, and manufacturing tools have resulted in multiple generations of ICs, each with smaller and more complex circuitry than its predecessor. Throughout these advancements, manufacturing methods, tools, and materials have all strived to achieve the desired smaller component sizes. Photolithography is one of the most critical process steps in IC manufacturing.

[0003] In the photolithography process, a layer of photoresist is first coated on the wafer (also known as a silicon wafer). Exposure equipment provides a light source, which shines on the wafer through a photomask (usually called a mask) with a circuit pattern. Utilizing the photosensitive properties of the photoresist material, the pattern on the photomask is transferred to the photoresist layer to form a photoresist pattern.

[0004] Before performing the photolithography process, all the circuit pattern designs are fabricated on a photomask. The circuit pattern design employs multi-layer stacking, and in this multi-layer stacking, the offsets in the X and Y directions between layers must be accurately determined, i.e., overlay accuracy. Therefore, in addition to the circuit pattern, the photomask is also designed with overlay measurement marks for measuring the offsets between layers.

[0005] Currently, due to limitations in the size of a single exposure field in a lithography machine, multiple exposures are required sequentially to form circuit patterns across the entire wafer surface. The boundaries of the photomask mark are the cut points between the chip patterns, i.e., the dicing tracks. To avoid affecting the functionality of the circuit area, overlay measurement marks are placed at the dicing tracks to ensure precise alignment between layers and to measure the offset in the X and Y directions.

[0006] To improve wafer utilization, the area occupied by the dicing traces on the wafer should be minimized. One possible method is to overlap the dicing traces in the subsequent exposure field with those in the previous exposure field. However, when the entire dicing trace area must be defined as the exposure area, repeated exposure will cause the overlay measurement marks to disappear after final development, making overlay measurement impossible. Summary of the Invention

[0007] To address the shortcomings of related technologies, this invention provides a photomask and a photolithography method. By improving the photomask, the overlay measurement marks can still be retained after repeated exposure of the dicing area, effectively reducing the area occupied by the dicing area on the semiconductor substrate without affecting the overlay measurement.

[0008] This application provides a photomask template, including:

[0009] The main area, located in the middle of the photomask, has a circuit pattern formed thereon;

[0010] The first cutting channel area is located on one side of the main area, and the first set of measuring marks is set in the first cutting channel area.

[0011] The second cutting channel area is located on the other side of the main body area, opposite to the first cutting channel area. A second set of measuring marks is provided in the second cutting channel area. The second set of measuring marks and the first set of measuring marks are staggered in the length direction of the second cutting channel area and the first cutting channel area.

[0012] The first opaque area is located in the first cutting channel area. The position of the first opaque area in the first cutting channel area is the same as the position of the second set of measuring marks in the second cutting channel area, and the size of the first opaque area is greater than or equal to the size of the second set of measuring marks.

[0013] The second opaque area is located in the second cutting channel area. The position of the second opaque area in the second cutting channel area is the same as the position of the first set of measuring marks in the first cutting channel area, and the size of the second opaque area is greater than or equal to the size of the first set of measuring marks.

[0014] In some embodiments of this application, the main area is a single-exposure area, and the first cut-out area and the second cut-out area are repeated-exposure areas.

[0015] In some embodiments of the first aspect of this application, the main body region is a rectangular region, and the length direction and width direction of the rectangular region are defined as the X direction and the Y direction, respectively. The first cutting channel region and the second cutting channel region are two sets located in the X direction and the Y direction, respectively, to form an edge region located around the main body region.

[0016] In some embodiments of the first aspect of this application, the first set of measurement marks and the second set of measurement marks are arranged far apart from each other in the X or Y direction.

[0017] In some embodiments of the first aspect of this application, the first set of measuring marks and the second set of measuring marks are the same size.

[0018] In some embodiments of the first aspect of this application, the first opaque region and the second opaque region are the same size.

[0019] In some embodiments of the first aspect of this application, the size of the first set of measurement marks and the second set of measurement marks are both 30×30μm, and the size of the first opaque area and the second opaque area are both 40×40μm.

[0020] A second aspect of this application provides a photolithography method, comprising the following steps:

[0021] Provide a semiconductor substrate;

[0022] A photoresist layer is formed on a semiconductor substrate;

[0023] Based on any of the above photomasks, multiple exposure processes are performed on adjacent areas in sequence. During the multiple exposure process, the main area in each exposure area is only exposed once. The first cutting area in the subsequent exposure area overlaps with the second cutting area in the previous exposure area for a second exposure, until the entire photoresist layer is completely exposed.

[0024] Develop the photoresist layer to pattern it;

[0025] The semiconductor substrate is patterned using the patterned photoresist layer as a mask.

[0026] In some embodiments of the second aspect of this application, a plurality of circuit pattern units corresponding to the main region are formed in the patterned semiconductor substrate, and a first set of measurement marks and a second set of measurement marks exist simultaneously in the cleaving channels between adjacent circuit pattern units.

[0027] In some embodiments of the second aspect of this application, during the patterning of the semiconductor substrate, a dry etching or wet etching process is used to perform an etching process on the semiconductor substrate.

[0028] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0029] (1) The mask provided in at least one embodiment of this application improves the structure of the mask so that it can be used in multiple exposures when the cut track areas overlap. By setting the opaque area, the overlay measurement mark will not disappear even if the cut track areas overlap and are repeatedly exposed.

[0030] (2) The photolithography method provided in at least one embodiment of this application performs multiple exposure processes in adjacent regions in sequence. The first dicing area in the later exposure region overlaps with the second dicing area in the previous exposure region for secondary exposure. This can effectively reduce the area occupied by the dicing area, and the overlay measurement marks are still retained, without affecting the alignment and measurement between layers. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0032] Figure 1 This is a schematic diagram of the exposure fields in different regions of the wafer surface during the photolithography process;

[0033] Figure 2 This is a schematic diagram of a photomask in the prior art;

[0034] Figure 3 To adopt Figure 2 The diagram shown is an illustration of the photomask after multiple exposures.

[0035] Figure 4 A schematic diagram of the mask template provided in an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of the photomask provided in the embodiments of this application after multiple exposures;

[0037] Figure 6 This is a flowchart of the photolithography method provided in the embodiments of this application.

[0038] In the picture:

[0039] 101. Main area; 102. Cutting channel area; 1021. First cutting channel area; 1022. Second cutting channel area; 103. Overlay measurement mark; 1031. First overlay measurement mark; 1032. Second overlay measurement mark; 1041. First opaque area; 1042. Second opaque area. Detailed Implementation

[0040] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0041] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0042] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0043] It is to be understood that although the accompanying drawings may show a specific order of method steps, the order of steps may differ from the depicted order. Furthermore, two or more steps may be performed simultaneously or partially simultaneously. All such variations are within the scope of this disclosure.

[0044] The terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0045] Figure 1 This diagram illustrates the exposure fields in different regions of the wafer surface during photolithography. During exposure, a mask is used to expose the wafer at the current position, then moves to the next adjacent position for further exposure. The area in the middle of each exposure field is where the circuit pattern is placed, while the areas where the exposure fields meet form the dicing zone. Overlay measurement marks for alignment between layers are placed in the dicing zone.

[0046] Figure 2 This is a schematic diagram of a photomask. The central region 101 is the main area where a circuit pattern is formed. Around the main region 101 are cutting slit regions 102, and overlay measurement marks 103 are formed in the cutting slit regions 102. In this photomask, each cutting slit region 102 has an overlay measurement mark 103 formed. The shape of the overlay measurement mark 103 is not limited; for example, it can be a rectangular frame shape as shown in the figure.

[0047] To improve the utilization rate of the wafer surface, it is necessary to minimize the area occupied by the dicing region 102 on the wafer surface. One method is to overlap the dicing region 102 at the edge of the mask with the dicing region 102 of the previous exposure during the next exposure, and repeat the exposure twice on the wafer surface corresponding to the dicing region 102, thereby reducing the area occupied by the dicing region 102.

[0048] like Figure 3 As shown, after the above-mentioned photomask is exposed three times from left to right, the pattern of the overlay measurement mark 103 will eventually disappear on the wafer surface after the dicing area 102 is exposed twice, and overlay measurement cannot be performed.

[0049] To address the aforementioned problems, this application improves the structure of the photomask. The improved photomask includes:

[0050] The main area 101 is located in the middle area of ​​the photomask and has a circuit pattern formed thereon;

[0051] The first cutting channel area 1021 is located on one side of the main body area 101, and a first set of measuring marks 1031 is provided in the first cutting channel area 1021;

[0052] The second cutting channel region 1022 is located on the other side of the main body region 101, opposite to the first cutting channel region 1021. A second set of engraving measurement marks 1032 is provided in the second cutting channel region 1022. The second set of engraving measurement marks 1032 and the first set of engraving measurement marks 1031 are staggered in the length direction of the second cutting channel region 1022 and the first cutting channel region 1021.

[0053] The first opaque area 1041 is located in the first dicing area 1021. The position of the first opaque area 1041 in the first dicing area 1021 is the same as the position of the second set of etch measurement marks 1032 in the second dicing area 1022. The size of the first opaque area 1041 is greater than or equal to the size of the second set of etch measurement marks 1032, so that during the second exposure process, the first opaque area 1041 can block the second set of etch measurement marks 1032 on the photoresist layer that has already been exposed once.

[0054] The second opaque region 1042 is located in the second dicing region 1022. The position of the second opaque region 1042 in the second dicing region 1022 is the same as the position of the first set of measurement marks 1031 in the first dicing region 1021. The size of the second opaque region 1042 is greater than or equal to the size of the first set of measurement marks 1031, so that during the secondary exposure process, the part on the semiconductor substrate opposite to this region is exposed only once to retain the first set of measurement marks 1031.

[0055] Figure 4 This is a schematic diagram of a mask template provided in one embodiment of this application. Figure 5 To adopt Figure 4 A schematic diagram of the pattern formed by the photomask undergoing three exposures from left to right (the circuit pattern in the main area 101 is not shown; it is designed according to actual needs). Figure 4 and Figure 5 As shown, the photomask provided in this application embodiment can be used in multiple exposure processes where the dicing areas overlap. Before exposure, a photoresist layer is first formed on the semiconductor substrate. Since the overlay measurement marks on opposite sides of the photomask are formed at staggered positions, at least two sets of overlay measurement marks will be formed at two different positions after repeated exposure of the same dicing area in the photoresist layer. Furthermore, by setting an opaque area, the overlay measurement marks will not disappear even if the dicing area is repeatedly exposed, thus solving the problem of overlay measurement marks disappearing due to repeated exposure of the dicing area. When the photomask moves to the next position for exposure, a dicing area at the next position can overlap with the dicing area of ​​the previous exposure field without causing the overlay measurement marks to disappear, effectively reducing the area of ​​the dicing area on the semiconductor substrate and improving utilization.

[0056] In the photolithography process using the photomask provided in the above embodiments, the main area 101 is a single-exposure area, and the first dicing area 1021 and the second dicing area 1022 are repeated-exposure areas. That is to say, as Figure 5 As shown, after the photomask is exposed at position (1), it moves to position (2) for a second exposure. At position (2), the first dicing area 1021 of the photomask coincides vertically with the second dicing area 1022 on the photoresist layer surface that was previously exposed, resulting in this area undergoing a second exposure. The main body area 101 at positions (1) and (2) is only exposed once, making it a single-exposure area. After the photomask completes the second exposure at position (2), it moves to position (3) for a third exposure, and the process is the same as above.

[0057] In some embodiments, the main body region 101 is a rectangular region, with its length direction defined as the X direction and its width direction defined as the Y direction. Two sets of first cutting channel regions 1021 and second cutting channel regions 1022 are located in the X and Y directions respectively, forming edge regions surrounding the main body region 101. In the X direction, the first cutting channel region 1021 and the second cutting channel region 1022 are located on either side of the main body, and in the Y direction, the first cutting channel region 1021 and the second cutting channel region 1022 are also located opposite each other. It is understood that the first cutting channel region 1021 and the second cutting channel region 1022 are defined only for the convenience of describing the positional relationship between two adjacent exposure fields, and they may be identical in shape or structure.

[0058] During the photolithography process Figure 5 The diagram illustrates how the photomask is translated in the X direction for sequential exposure. It can be understood that the photomask can also be translated in the Y direction as shown in the diagram until the exposure area covers the entire surface of the semiconductor substrate. During the translation process, the cutting areas are always kept to overlap during the two exposure processes.

[0059] In some embodiments, such as Figure 4 As shown, the first set of measurement marks 1031 and the second set of measurement marks 1032 are arranged far apart from each other in the X or Y direction. That is, the measurement marks on opposite sides are distributed at both ends of the photomask, thus allowing the photomask to be positioned as shown in the image. Figure 5 After multiple exposures, two sets of etch measurement marks located at both ends can be formed in the same cutting area, allowing for precise alignment between layers and measurement of offset in this direction.

[0060] In some embodiments, the first set of overlay measurement marks 1031 and the second set of overlay measurement marks 1032 may have the same shape and size, so that the same overlay measurement marks are formed on the same layer, and are paired with the overlay measurement marks between adjacent layers for alignment. This application does not limit the specific shape and pattern of the overlay measurement marks, as long as alignment measurement can be achieved.

[0061] The first opaque area 1041 and the second opaque area 1042 are used to cover the second set of measurement marks 1032 and the first set of measurement marks 1031, respectively. The dimensions of the first opaque area 1041 and the second opaque area 1042 are not specifically limited, as long as the size of the first opaque area 1041 is greater than or equal to the size of the second set of measurement marks 1032 and the size of the second opaque area 1042 is greater than or equal to the size of the first set of measurement marks 1031. In some embodiments, the first opaque area 1041 and the second opaque area 1042 have the same size.

[0062] In some embodiments, the first set of measurement marks 1031 and the second set of measurement marks 1032 have the same size, both being 30×30μm, and the first opaque region 1041 and the second opaque region 1042 have the same size, both being 40×40μm. Furthermore, it is understood that the first and second opaque regions can also have other sizes, as long as the first opaque region 1041 is slightly larger than the second set of measurement marks 1032, and the second opaque region 1042 is slightly larger than the first set of measurement marks 1031.

[0063] Based on the photomask provided in the above embodiments, this application also provides a photolithography method, such as... Figure 6 As shown, the photolithography method includes the following steps:

[0064] S1: Provide a semiconductor substrate;

[0065] S2: Forming a photoresist layer on a semiconductor substrate;

[0066] S3: Based on the photomask provided in any of the above embodiments, multiple exposure processes are performed on adjacent areas in sequence. During the multiple exposure process, the main area 101 in each exposure area is only exposed once. The first cutting area 1021 in the next exposure area overlaps with the second cutting area 1022 in the previous exposure area for a second exposure, until the entire photoresist layer is completely exposed.

[0067] S4: Development to pattern the photoresist layer;

[0068] S5: Pattern the semiconductor substrate using the patterned photoresist layer as a mask.

[0069] After the above photolithography process, multiple circuit pattern units corresponding to the main area 101 of the mask are formed in the semiconductor substrate. The first set of etching measurement marks 1031 and the second set of etching measurement marks 1032 exist simultaneously in the dicing channel between adjacent circuit pattern units. The etching measurement marks will not disappear due to repeated exposure of the dicing channel area.

[0070] In step S2 above, the photoresist layer can be formed by methods such as transfer coating, dip coating, air knife coating, wire rod coating, lamination, extrusion coating, etc. Those skilled in the art can determine the appropriate method based on the actual situation.

[0071] During the multiple exposures in step S3, different wavelengths of light beams can be used for exposure as needed. For example, a 193nm or 248nm light beam can be selected to irradiate the photoresist layer covering the semiconductor substrate through the mask. The areas of the photoresist layer that have been irradiated by the light beam will be transformed into photoacids, which will be neutralized and removed by the developer during the subsequent development process in step S4, thereby forming a pattern on the surface of the photoresist layer.

[0072] During the exposure process in step S3, due to the presence of the first opaque area 1041 and the second opaque area 1042 on the photomask, the light beam cannot pass through the area and be projected onto the photoresist layer. Even though the dicing area is exposed on both sides, the area where the overlay measurement mark needs to be formed actually only undergoes one exposure, so that the overlay measurement mark is retained.

[0073] After the photoresist layer is developed, in step S5, a dry etching or wet etching process can be used to perform an etching process on the semiconductor substrate to transfer the pattern of the photoresist layer to the semiconductor substrate.

[0074] Finally, it should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A photomask, characterized in that, include: The main body area is located in the middle area of ​​the mask template and has a circuit pattern formed thereon; The first cutting channel area is located on one side of the main body area, and a first set of measurement marks is provided in the first cutting channel area; The second cutting channel area is located on the other side of the main body area, opposite to the first cutting channel area. A second set of engraving and measuring marks is provided in the second cutting channel area. The second set of engraving and measuring marks is staggered from the first set of engraving and measuring marks in the length direction of the second cutting channel area and the first cutting channel area. The first opaque area is located in the first cutting channel area. The position of the first opaque area in the first cutting channel area is the same as the position of the second set of measuring marks in the second cutting channel area. The size of the first opaque area is greater than or equal to the size of the second set of measuring marks. The second opaque area is located in the second cutting channel area. The position of the second opaque area in the second cutting channel area is the same as the position of the first set of measuring marks in the first cutting channel area, and the size of the second opaque area is greater than or equal to the size of the first set of measuring marks. The main area is a single-exposure area, and the first cutting channel area and the second cutting channel area are repeated-exposure areas; The main body area is a rectangular area, and the length direction and width direction of the rectangular area are defined as the X direction and the Y direction, respectively. The first cutting channel area and the second cutting channel area are in two sets and are located in the X direction and the Y direction, respectively, to form an edge area around the main body area. The first set of measurement marks and the second set of measurement marks are arranged far apart from each other in the X direction or the Y direction.

2. The mask template according to claim 1, characterized in that, The first set of measuring marks and the second set of measuring marks are the same size.

3. The mask template according to claim 2, characterized in that, The first opaque area and the second opaque area are the same size.

4. The mask template according to claim 3, characterized in that, The size of the first set of measurement marks and the second set of measurement marks is 30×30μm, and the size of the first opaque area and the second opaque area is 40×40μm.

5. A photolithography method, characterized in that, Includes the following steps: Provide a semiconductor substrate; A photoresist layer is formed on the semiconductor substrate; Based on the photomask according to any one of claims 1-4, multiple exposure processes are performed sequentially for adjacent regions. During the multiple exposure process, the main region in each exposure region is only exposed once, and the first cutting channel region in the subsequent exposure region overlaps with the second cutting channel region in the previous exposure region for a second exposure, until the entire photoresist layer is completely exposed. Develop to pattern the photoresist layer; The semiconductor substrate is patterned using the patterned photoresist layer as a mask.

6. The photolithography method according to claim 5, characterized in that, Multiple circuit pattern units corresponding to the main region are formed in the patterned semiconductor substrate, and the first set of measurement marks and the second set of measurement marks exist simultaneously in the cleavage between adjacent circuit pattern units.

7. The photolithography method according to claim 6, characterized in that, During the patterning of the semiconductor substrate, an etching process is performed on the semiconductor substrate using either dry etching or wet etching.

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