Tlc write performance improvement method, device and computer equipment of solid state disk
By allocating only one hardware descriptor for TLC write commands in the solid-state drive and having the hardware automatically perform subpage write operations, the time consumption problem caused by multiple descriptor configurations in the prior art is solved, thus improving TLC write performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2023-07-18
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, when processing TLC write commands, solid-state drives (SSDs) need to request and configure hardware descriptors for three subpages: low, middle, and upper. This results in a long processing time and frequent access to the NFC hardware register to check the FIFO status, which reduces the efficiency of descriptor distribution and affects TLC write performance.
One approach is to request only one hardware descriptor after obtaining the TLC write command, and complete the write operation command sequence of three subpages one by one at the hardware level, which simplifies the software processing flow and reduces the number of accesses to NFC hardware registers.
By reducing the number of hardware descriptor configurations and software involvement, the TLC write performance of solid-state drives is improved, the processing flow is simplified, and the efficiency of write operations is increased.
Smart Images
Figure CN116909478B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive (SSD) technology, and in particular to a method, apparatus, computer device, and storage medium for improving the TLC write performance of SSDs. Background Technology
[0002] Solid-state drives (SSDs) are widely used in various applications and are gradually replacing traditional hard disk drives (HDDs) in the PC market, providing users with a better experience in terms of reliability and performance. Currently, mainstream SSD manufacturers primarily use TLC NAND flash memory. For TLC write commands, the write operation must be performed simultaneously on the low, middle, and upper subpages of the TLC flash memory, following the flash memory's command sequence requirements, to write the data from all three subpages to the flash memory at the same time. Therefore, in SSD systems, the efficiency of descriptor issuance should be maximized.
[0003] In traditional technology, after receiving a TLC write command, the SSD backend first requests hardware descriptor resources for the low page of the TLC write operation. After properly configuring the hardware descriptor, it sends it to the command FIFO of the corresponding NFC channel, instructing the hardware to execute the corresponding write operation command sequence. Then, the software waits for the low page's write operation to complete before processing the middle and upper pages of the current TLC write command in the same way. As can be seen from the above software processing of TLC write operations, it is necessary to request and properly configure a hardware descriptor for each of the three TLC subpages. In actual testing, configuring each descriptor takes a considerable amount of time. Furthermore, the process of sending each descriptor to the NFC command FIFO requires checking if the FIFO is full, increasing the number of accesses to the NFC hardware registers, thus reducing the descriptor sending efficiency and consequently affecting the TLC write performance of the SSD. Summary of the Invention
[0004] Therefore, it is necessary to provide a method, apparatus, computer device, and storage medium for improving the TLC write performance of solid-state drives in response to the above-mentioned technical problems.
[0005] A method for improving the TLC write performance of a solid-state drive, the method comprising:
[0006] Obtain the issued TLC write command and request a hardware descriptor for the TLC write command;
[0007] Configure the hardware descriptor by setting the page_bit_map information of the low, middle, and upper pages that represent the pages to be written in the hardware descriptor.
[0008] After configuration, the hardware descriptor is sent to the FIFO memory;
[0009] The NFC hardware retrieves the hardware descriptor from the FIFO memory and completes the write operation command sequence of the subpage corresponding to the page_bit_map information one by one.
[0010] After each subpage write operation command is completed, the corresponding bit in the page_bit_map is cleared, and then the next write operation command is executed to update the page information in the hardware descriptor.
[0011] In one embodiment, the step of configuring the hardware descriptor and setting the page_bit_map information of the low, middle, and upper pages in the hardware descriptor that indicate the page to be written further includes:
[0012] Determine and configure whether a Multi-Plane write operation needs to be performed.
[0013] In one embodiment, the method further includes:
[0014] If a multi-plane write operation is required, after performing the multi-plane write operation of a subpage, the page_bit_map information and page information of the hardware descriptor are updated first, and then the multi-plane write operation of the next subpage is performed until all page_bit_map information is 0.
[0015] In one embodiment, the method further includes:
[0016] Once the NFC hardware recognizes different subpages, it issues a sequence of commands that conform to the corresponding write command operation protocol.
[0017] A device for improving the TLC write performance of a solid-state drive, the device comprising:
[0018] The acquisition module is used to acquire the issued TLC write command and apply for a hardware descriptor for the TLC write command;
[0019] The configuration module is used to configure the hardware descriptor by setting the page_bit_map information of the low, middle, and upper pages in the hardware descriptor that indicate the write operation to be performed.
[0020] The first sending module is used to send the hardware descriptor to the FIFO memory after configuration is completed;
[0021] The first execution module is used for the NFC hardware to retrieve the hardware descriptor from the FIFO memory and complete the write operation command sequence of the subpage corresponding to the page_bit_map information one by one.
[0022] The clearing module is used to clear the corresponding bit of the page_bit_map after each subpage write operation command is completed, and then execute the next write operation command and update the page information in the hardware descriptor.
[0023] In one embodiment, the device further includes:
[0024] The judgment module is used to determine and configure whether a Multi-Plane write operation needs to be performed.
[0025] In one embodiment, the device further includes:
[0026] The second execution module is used to, if a Multi-Plane write operation is required, first update the page_bit_map information and page information of the hardware descriptor after performing the Multi-Plane write operation of the subpage, and then perform the Multi-Plane write operation of the next subpage until all page_bit_map information is 0.
[0027] In one embodiment, the device further includes:
[0028] The second sending module is used to send a command sequence that conforms to the corresponding write command operation protocol when the NFC hardware recognizes different subpages.
[0029] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.
[0030] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.
[0031] The aforementioned method, apparatus, computer equipment, and storage medium for improving TLC write performance of solid-state drives (SSDs) can effectively enhance SSD TLC write performance. Specifically, for the write operation of the three subpages in TLC, the previous configuration of three hardware descriptors is reduced to configuring only one, thus saving the time required to configure two hardware descriptors. During the process of issuing the hardware descriptor to the NFC command FIFO, the software needs to access hardware registers to check if there is remaining space in the command FIFO of the corresponding channel. Since only one descriptor needs to be issued, the number of accesses to the NFC hardware registers is reduced. Simultaneously, since the NFC hardware automatically executes the write operation command sequence for different subpages without software intervention, it effectively avoids the time wasted and reduced descriptor issuance efficiency caused by the software needing to check the completion of the previous subpage's write operation before configuring and issuing the hardware descriptor for the next subpage, which was the previous method. This reduces software-level involvement, simplifies the software processing flow, and thus effectively improves the TLC write performance of SSDs. Attached Figure Description
[0032] Figure 1 This is a flowchart illustrating a method for improving TLC write performance of a solid-state drive in one embodiment;
[0033] Figure 2 This is a flowchart illustrating a method for improving TLC write performance of a solid-state drive in another embodiment;
[0034] Figure 3 This is a flowchart illustrating a method for improving TLC write performance of a solid-state drive in another embodiment;
[0035] Figure 4 This is a structural block diagram of a TLC write performance enhancement device for a solid-state drive in one embodiment;
[0036] Figure 5 This is a structural block diagram of a TLC write performance enhancement device for a solid-state drive in another embodiment;
[0037] Figure 6 This is a structural block diagram of a TLC write performance enhancement device for a solid-state drive in another embodiment;
[0038] Figure 7 This is a structural block diagram of a TLC write performance enhancement device for a solid-state drive in yet another embodiment;
[0039] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0041] The current method for issuing TLC write operation command descriptors involves the following steps: After receiving a TLC write command, the existing SSD backend first requests hardware descriptor resources for the low page of the TLC write operation. After properly configuring the hardware descriptor, it is issued to the command FIFO of the corresponding NFC channel, instructing the hardware to execute the corresponding write operation command sequence. Then, the software waits for the low page's write operation to complete before processing the middle and upper pages of the current TLC write command in the same way. As can be seen from the above software processing of TLC write operations, it is necessary to request and properly configure a hardware descriptor for each of the three TLC subpages. In actual testing, configuring each descriptor takes a considerable amount of time. Furthermore, the process of issuing each descriptor to the NFC command FIFO requires checking if the FIFO is full, increasing the number of accesses to the NFC hardware registers, thus reducing descriptor issuance efficiency and impacting TLC write performance.
[0042] Based on this, this solution provides a method to improve the TLC write performance of solid-state drives (SSDs), aiming to effectively enhance the TLC write performance of SSDs.
[0043] In one embodiment, such as Figure 1 As shown, a method for improving the TLC write performance of a solid-state drive is provided, the method including:
[0044] Step 102: Obtain the issued TLC write command and apply for a hardware descriptor for the TLC write command;
[0045] Step 104: Configure the hardware descriptor by setting the page_bit_map information of the low, middle, and upper pages in the hardware descriptor that indicate the page to be written.
[0046] Step 106: After configuration, the hardware descriptor is sent to the FIFO memory;
[0047] Step 108: The NFC hardware retrieves the hardware descriptor from the FIFO memory and completes the write operation command sequence of the subpage corresponding to the page_bit_map information one by one.
[0048] Step 110: After the write operation command for each subpage is completed, clear the corresponding bit in the page_bit_map, and then execute the next write operation command and update the page information in the hardware descriptor.
[0049] This embodiment provides a method for improving TLC write performance of a solid-state drive (SSD). In this solution, after receiving a TLC write command, the SSD backend software requests a hardware descriptor resource for the current TLC write operation command, configures the descriptor, and then sends it to the NFC internal command FIFO. The configured hardware descriptor information includes setting the page_bit_map information corresponding to the low, middle, and upper subpages of the current TLC write operation. The NFC hardware automatically executes the corresponding three subpage write operation command sequence one by one according to the page_bit_map information configured in the descriptor. When the write operation of the corresponding subpage is completed, the corresponding bit of the page_bit_map is cleared until the page_bit_map information becomes zero, completing the current TLC write operation.
[0050] Specifically, upon receiving a TLC write operation command, instead of requesting hardware descriptor resources and configuring the descriptors for each of the three subpages of a TLC before sending them to the NFC internal command FIFO, only one hardware descriptor resource is requested and configured for the current write operation command before being sent to the NFC internal command FIFO, and the hardware completes the write operation command for the three subpages of the TLC.
[0051] The hardware descriptor configuration mainly includes setting the page_bit_map information for the three subpages (low, middle, and upper) to be written to using TLC. This bit is cleared by the hardware after the write operation to the corresponding subpage is completed. Additionally, in write operation exception handling, the page_bit_map information reflects the subpage where the write operation failed.
[0052] The hardware-based scheme for completing the three subpage write operations of a TLC involves the hardware sequentially executing the write operation command sequence for each subpage corresponding to the page_bit_map information. After each subpage's write operation is completed, the corresponding bit in the page_bit_map is cleared, and then the write operation for the next page is performed. Simultaneously, the hardware automatically updates the page information in the descriptor.
[0053] In one embodiment, the method further includes: when the NFC hardware identifies different subpages, issuing a command sequence conforming to the corresponding write command operation protocol. Specifically, this refers to issuing a corresponding command sequence conforming to the write (including multi-plane write) operation protocol after the hardware identifies different subpages.
[0054] In the above embodiments, SSD TLC write performance can be effectively improved. The write operation for the three subpages of TLC is changed from configuring three hardware descriptors to configuring only one, thus saving the time required to configure two hardware descriptors. During the process of sending the hardware descriptor to the NFC command FIFO, the software needs to access hardware registers to check if there is remaining space in the command FIFO of the corresponding channel. Since only one descriptor needs to be sent, the number of accesses to the NFC hardware registers is reduced. Simultaneously, since the NFC hardware automatically executes the write operation command sequence for different subpages without software intervention, it effectively avoids the time wasted and reduced descriptor sending efficiency caused by the software needing to check the completion of the previous subpage's write operation before configuring and sending the hardware descriptor for the next subpage. This reduces software-level involvement, simplifies the software processing flow, and thus effectively improves SSD TLC write performance.
[0055] In one embodiment, such as Figure 2 As shown, a method for improving the TLC write performance of a solid-state drive is provided, which further includes:
[0056] Step 202: Determine and configure whether a Multi-Plane write operation needs to be performed;
[0057] Step 204: If a Multi-Plane write operation is required, after performing the Multi-Plane write operation of the subpage, first update the page_bit_map information and page information of the hardware descriptor, and then perform the Multi-Plane write operation of the next subpage until all page_bit_map information is 0.
[0058] Specifically, refer to Figure 3 The method shown here for improving TLC write performance of solid-state drives includes the following software and hardware processing steps:
[0059] Step 3.1: The SSD backend receives the TLC write command.
[0060] Step 3.2: The SSD backend software requests a hardware descriptor resource for the current TLC write command.
[0061] Step 3.3: Configure the SSD backend software descriptor, set the page_bit_map information of the low, middle, and upper pages that indicate the write operation to be performed, and determine and configure whether it is a multi-plane write operation.
[0062] Step 3.4: The SSD backend software sends the descriptor to the NFC command FIFO.
[0063] Step 3.5: The NFC hardware retrieves the hardware descriptor from the command FIFO.
[0064] Step 3.6: Determine if it is a Multi-Plane write operation. If it is, return to step 3.5; otherwise, proceed to step 3.7.
[0065] Step 3.7: The NFC hardware executes a write operation command for a page in the TLC based on the page information in the descriptor.
[0066] Step 3.8: The NFC hardware waits for the write operation command of the current page of TLC to complete.
[0067] Step 3.9: The NFC hardware clears the bit corresponding to page in the page_bit_map information of the descriptor to zero.
[0068] Step 3.10: Determine if the page_bit_map in the NFC hardware descriptor is zero. If it is zero, proceed to step 3.12; otherwise, proceed to step 3.11.
[0069] Step 3.11: After the NFC hardware updates the page information in the descriptor according to the page corresponding to the non-zero bit in page_bit_map, it executes step 3.7.
[0070] Step 3.12: NFC completes the write operation.
[0071] In this embodiment, the involvement of the software layer is reduced during the SSD TLC write command processing, simplifying the software processing flow and thus effectively improving the SSD's TLC write performance.
[0072] It should be understood that, although Figures 1-3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-3At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0073] In one embodiment, such as Figure 4 As shown, a TLC write performance enhancement device 400 for solid-state drives is provided, the device comprising:
[0074] Acquisition module 401, the acquisition module is used to acquire the issued TLC write command and apply for a hardware descriptor for the TLC write command;
[0075] Configuration module 402, the configuration module is used to configure hardware descriptors, and set the page_bit_map information of the low, middle and upper pages in the hardware descriptors that indicate the write operation to be performed;
[0076] The first sending module 403 is used to send the hardware descriptor to the FIFO memory after configuration is completed;
[0077] The first execution module 404 is used for the NFC hardware to retrieve the hardware descriptor from the FIFO memory and complete the write operation command sequence of the subpage corresponding to the page_bit_map information one by one.
[0078] The clearing module 405 is used to clear the corresponding bit of page_bit_map after the write operation command of each subpage is completed, and then execute the next write operation command and update the page information in the hardware descriptor.
[0079] In one embodiment, such as Figure 5 As shown, a TLC write performance enhancement device 400 for solid-state drives is provided, the device further comprising:
[0080] The judgment module 406 is used to determine and configure whether a Multi-Plane write operation needs to be performed.
[0081] In one embodiment, such as Figure 6 As shown, a TLC write performance enhancement device 400 for solid-state drives is provided, the device further comprising:
[0082] The second execution module 407 is configured to, if a Multi-Plane write operation is required, first update the page_bit_map information and page information of the hardware descriptor after performing the Multi-Plane write operation of the subpage, and then perform the Multi-Plane write operation of the next subpage until all page_bit_map information is 0.
[0083] In one embodiment, such as Figure 7 As shown, a TLC write performance enhancement device 400 for solid-state drives is provided, the device further comprising:
[0084] The second sending module 408 is used to send a command sequence that conforms to the corresponding write command operation protocol when the NFC hardware recognizes different subpages.
[0085] For specific limitations on devices for improving TLC write performance of solid-state drives, please refer to the limitations on methods for improving TLC write performance of solid-state drives mentioned above, which will not be repeated here.
[0086] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 8 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for improving the TLC write performance of a solid-state drive.
[0087] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0088] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.
[0089] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.
[0090] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.
[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0092] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for improving the TLC write performance of a solid-state drive, the method comprising: Obtain the issued TLC write command and request a hardware descriptor for the TLC write command; Configure the hardware descriptor by setting the page_bit_map information of the low, middle, and upper pages that represent the pages to be written in the hardware descriptor. After configuration, the hardware descriptor is sent to the FIFO memory; The NFC hardware retrieves the hardware descriptor from the FIFO memory and completes the write operation command sequence of the subpage corresponding to the page_bit_map information one by one. After each subpage write operation command is completed, the corresponding bit in the page_bit_map is cleared, and then the next write operation command is executed to update the page information in the hardware descriptor.
2. The method for improving TLC write performance of a solid-state drive according to claim 1, characterized in that, The step of configuring the hardware descriptor and setting the page_bit_map information of the low, middle, and upper pages in the hardware descriptor that indicate the page to be written to further includes: Determine and configure whether a Multi-Plane write operation needs to be performed.
3. The TLC write performance improvement method of the solid state disk according to claim 2, characterized in that, The method further includes: If a multi-plane write operation is required, after performing the multi-plane write operation of a subpage, the page_bit_map information and page information of the hardware descriptor are updated first, and then the multi-plane write operation of the next subpage is performed until all page_bit_map information is 0.
4. The method of claim 1-3, wherein, The method further includes: Once the NFC hardware recognizes different subpages, it issues a sequence of commands that conform to the corresponding write command operation protocol.
5. A TLC write performance improvement device of a solid state disk, characterized by, The device includes: The acquisition module is used to acquire the issued TLC write command and apply for a hardware descriptor for the TLC write command; The configuration module is used to configure the hardware descriptor by setting the page_bit_map information of the low, middle, and upper pages in the hardware descriptor that indicate the write operation to be performed. The first sending module is used to send the hardware descriptor to the FIFO memory after configuration is completed; The first execution module is used for the NFC hardware to retrieve the hardware descriptor from the FIFO memory and complete the write operation command sequence of the subpage corresponding to the page_bit_map information one by one. The clearing module is used to clear the corresponding bit of the page_bit_map after each subpage write operation command is completed, and then execute the next write operation command and update the page information in the hardware descriptor. 6.The TLC write performance improvement device of a solid state disk according to claim 5, characterized in that, The device further includes: The judgment module is used to determine and configure whether a Multi-Plane write operation needs to be performed.
7. The TLC write performance improvement device of the solid state disk according to claim 6, characterized in that, The device further includes: The second execution module is used to, if a Multi-Plane write operation is required, first update the page_bit_map information and page information of the hardware descriptor after performing the Multi-Plane write operation of the subpage, and then perform the Multi-Plane write operation of the next subpage until all page_bit_map information is 0.
8. The device for improving TLC write performance of a solid state disk according to any one of claims 5-7, characterized in that, The device further includes: The second sending module is used to send a command sequence that conforms to the corresponding write command operation protocol when the NFC hardware recognizes different subpages.
9. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.