一种快速获取场效应管寄生电阻的方法
By combining TCAD simulation with the conductivity integration method, the parasitic resistance of the field-effect transistor can be obtained quickly and accurately with only one simulation experiment, which solves the problems of high simulation resource consumption and low efficiency, and realizes efficient and accurate parasitic resistance analysis.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOUTHEAST UNIV
- Filing Date
- 2023-08-08
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies consume enormous computational resources in analyzing the parasitic resistance of field-effect transistors and struggle to obtain accurate results quickly and directly, especially at nanoscale process nodes, where traditional methods are inefficient and have strong limitations.
By combining TCAD simulation calculation with the conductivity integration method, the integrable and non-integrable regions are divided. The parasitic resistance of each part of the field-effect transistor is calculated by integrating the conductance of each region and the quantitative relationship. Accurate values can be obtained with only one simulation experiment.
It significantly improves the efficiency of parasitic resistance analysis of field-effect transistors, with calculation results differing from traditional methods by no more than 5%. It is applicable to two-dimensional and three-dimensional field-effect transistors, and has a significant advantage for three-dimensional devices such as FinFETs.
Smart Images
Figure CN116911234B_ABST