A wiring method with automatic obstacle avoidance

Abstract

The application discloses a wiring method for automatic obstacle avoidance, which comprises: initializing wiring resources of a to-be-processed layout, including: obtaining layout data, wiring settings and process constraints corresponding to an L-shaped region in the to-be-processed layout; determining a connection relationship, including: sorting and one-to-one corresponding two groups of Bus ports framed in the L-shaped region based on a specified connection relationship; determining a wiring layer, including: obtaining available wiring layers for avoiding obstacles when implementing L-shaped wiring of a wiring port pair according to the layout data, and selecting two wiring layers for L-shaped wiring from the available wiring layers; creating and adjusting a via, including: creating a via at a connection place of two sub-regions needing cross-layer connection according to the determined wiring layer, limiting the minimum number of vias to 2, and adjusting the position of the via; and outputting geometric figures corresponding to wiring and vias to the to-be-processed layout.

Description

Technical Field

[0001] This patent application belongs to the field of circuit design technology, and in particular relates to a wiring method for automatic obstacle avoidance. Background Technology

[0002] The data size of integrated circuit layouts is becoming increasingly massive with advancements in process nodes and design complexity. If layout design still relies solely on manual methods, the integrated circuit development cycle will be excessively long. To further improve the efficiency of layout design, computer-aided design technology is indispensable.

[0003] In analog integrated circuit layout design, there are many local scenarios involving bus routing. For these scenarios, L-shaped paths are frequently used to connect buses. When connecting bus ports, certain constraints must be met, such as connection relationships and design rule constraints. Specifically, when creating vias, the minimum number of cuts must be two, and obstacles encountered during routing must be bypassed or bypassed by drilling through layers to avoid them.

[0004] Currently, analog integrated circuit layout still relies heavily on manual design. As a result, when routing bus routes in local scenarios of integrated circuit layout, obstacles are not considered, and short circuits (hereinafter referred to as Short) are easily caused by the creation of vias and adjacent routes. The usability and manufacturability of the router are also poor. Summary of the Invention

[0005] This patent application provides an automatic obstacle avoidance wiring method to overcome or mitigate the shortcomings of the prior art.

[0006] An automatic obstacle avoidance wiring method, comprising:

[0007] Step S101: Initialize the routing resources of the layout to be processed, including: obtaining the layout data, routing settings and process constraints corresponding to the L-shaped area in the layout to be processed;

[0008] Step S102: Determine the connection relationship, including: sorting and matching the two groups of Bus ports selected in the L-shaped area according to the specified connection relationship;

[0009] Step S103: Determine the routing layer, including: based on the layout data, obtain the available routing layers that avoid obstacles when implementing L-shaped routing corresponding to the routing port, and select two routing layers from the available routing layers for L-shaped routing;

[0010] Step S104, Creating and Adjusting Vias, includes: creating vias at the connection point of two sub-regions that need to cross layers according to the determined wiring layer, and limiting the minimum number of vias to 2, while adjusting the position of the vias;

[0011] Step S105: Output the geometric shapes such as wiring and vias to the layout to be processed.

[0012] Optionally, the layout data includes obstacle graphics in the layout and two groups of bus ports selected by box; the routing settings include connection relationship settings, which include at least one of sequential connection, reverse connection, and connection according to port name; the process constraints include the processing process constraints used by the layout to be processed, which include available metal layers, available via definitions, and minimum number of vias.

[0013] Optionally, the step of sorting and mapping the two selected groups of Bus ports based on the specified connection relationship includes: sorting the two selected groups of Bus ports and performing a pre-connection check on the cabling between the two selected groups of Bus ports to implement a one-to-one mapping.

[0014] Optionally, sorting the two selected groups of bus ports includes:

[0015] S112. Divide the Bus cabling ports into the first group (Group A) and the second group (Group B);

[0016] S122. Set the routing direction for the first group (GroupA) and the second group (GroupB) respectively, and perform the following steps for either the first group or the second group as the target group:

[0017] S1221. Take the direction with the most identical directions in the target group as the wiring direction of the target group;

[0018] S1222. Determine the coordinates of the port direction perpendicular to the target group;

[0019] S1223. Use the coordinate values ​​as sorting reference values ​​for Bus cabling ports within the target group;

[0020] S1224. Sort the Bus cabling ports within the target group based on the sorting reference value.

[0021] Optionally, step S1221 is executed to determine that the wiring direction of the first group (GroupA) is horizontal and the wiring direction of the second group (GroupB) is vertical. Then, steps S1222-S1224 are executed for the first group and the second group respectively to sort the Bus wiring ports in the first group (GroupA) and the second group (GroupB).

[0022] Optionally, any Bus cabling port can be used as the target cabling port to perform the above-mentioned cabling pre-connection check, including the following steps:

[0023] Take the intersection of the center extensions of the routing direction of the target routing port as the pre-routing inflection point, and check whether the pre-routing segment of the target routing port intersects with the pre-routing segment of other target routing ports.

[0024] If not, the pre-connection relationship of the target cabling port is determined to be sequential connection.

[0025] If the specified connection relationship for the target cabling port is a reverse connection, then the cabling ports in the group to which the target cabling port belongs will be rearranged in reverse order.

[0026] If the specified connection relationship for the target cabling port is a connection via port name, then skip the sorting step and perform a one-to-one correspondence by matching port names.

[0027] Optionally, obtaining a usable cabling layer to avoid obstacles when implementing L-shaped cabling corresponding to the cabling port includes:

[0028] S113. Divide the L-shaped region into several sub-regions.

[0029] S123. Perform spatial indexing of the geometry in each sub-region to obtain continuous available wiring layer intervals;

[0030] S133. Select the two metal layers with the fewest vias within the available layer range as wiring layers.

[0031] Optionally, selecting the two metal layers with the fewest vias within the available layer range as wiring layers includes:

[0032] Calculate the layer selection cost of connecting several sub-regions within an L-shaped region, and select the two metal layers that generate the fewest vias as wiring layers.

[0033] Optionally, the calculation of the layer selection cost for connecting several sub-regions within the L-shaped region includes: calculating the layer number difference between each pair of sub-regions in the horizontal direction and the layer number difference between two adjacent sub-regions in the vertical direction within the L-shaped region, so as to calculate the layer selection cost for connecting several sub-regions within the L-shaped region.

[0034] Optionally, creating vias at the connection point of two sub-regions that need to cross layers, based on the determined wiring layer, includes:

[0035] Based on the determined wiring layer, check whether the sub-region spans multiple layers. If it does, create vias. The creation of vias includes at least one of setting the minimum number of vias, selecting the via direction, and adjusting the via position.

[0036] The solution provided in this invention includes: step S101, initializing the routing resources of the layout to be processed, including: acquiring layout data, routing settings, and process constraints corresponding to the L-shaped area in the layout to be processed; step S102, determining the connection relationship, including: sorting and matching the two groups of Bus ports selected in the L-shaped area according to the specified connection relationship; step S103, determining the routing layer, including: obtaining the available routing layers for avoiding obstacles when implementing L-shaped routing corresponding to the routing ports according to the layout data, and selecting the routing layer from the available routing layers. The L-shaped wiring has two wiring layers; Step S104: Create and adjust vias, including: based on the determined wiring layers, create vias at the connection of two sub-regions that need to cross layers, and limit the minimum number of vias to 2, while adjusting the position of the vias; Step S105: Output the geometry corresponding to the wiring and vias to the layout to be processed. When performing Bus wiring in the local scene of the integrated circuit layout, the obstacle situation is considered, and the problem of short circuit (hereinafter referred to as Short) caused by the creation of vias with adjacent wiring is avoided, which improves the ease of use and manufacturability of wiring. Attached Figure Description

[0037] Figure 1 This is the overall flowchart of the present invention.

[0038] Figure 2 This is a diagram showing the L-shaped wiring area division of the present invention.

[0039] Figure 3 This is a diagram showing the available orientation of the through-hole in this invention.

[0040] Figure 4 This is a diagram showing the adjustment of the dual-hole position according to the present invention.

[0041] Figure 5 This is a porous diagram of the present invention.

[0042] Figure 6 This is an exemplary application diagram of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of this patent application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this patent application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this patent application are within the scope of protection of this patent application.

[0044] The terms "first," "second," etc., used in the specification and claims of this patent application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this patent application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0045] The solution provided in this invention includes: step S101, initializing the routing resources of the layout to be processed, including: acquiring layout data, routing settings, and process constraints corresponding to the L-shaped area in the layout to be processed; step S102, determining the connection relationship, including: sorting and matching the two groups of Bus ports selected in the L-shaped area according to the specified connection relationship; step S103, determining the routing layer, including: obtaining the available routing layers for avoiding obstacles when implementing L-shaped routing corresponding to the routing ports according to the layout data, and selecting the routing layer from the available routing layers. The L-shaped wiring has two wiring layers; Step S104: Create and adjust vias, including: based on the determined wiring layers, create vias at the connection of two sub-regions that need to cross layers, and limit the minimum number of vias to 2, while adjusting the position of the vias; Step S105: Output the geometry corresponding to the wiring and vias to the layout to be processed. When performing Bus wiring in the local scene of the integrated circuit layout, the obstacle situation is considered, and the problem of short circuit (hereinafter referred to as Short) caused by the creation of vias with adjacent wiring is avoided, which improves the ease of use and manufacturability of wiring.

[0046] Figure 1 This is a schematic flowchart illustrating an automatic obstacle avoidance wiring method according to an embodiment of the present invention. Figure 1 As shown, it includes the following steps:

[0047] Step S101: Initialize the routing resources of the layout to be processed, including obtaining the layout data, routing settings and process constraints corresponding to the L-shaped area in the layout to be processed.

[0048] In step S101, the layout data includes, but is not limited to, obstacle graphics in the layout and two selected groups of Bus ports. The routing settings include connection relationship settings, which include at least one of sequential connection, reverse connection, and connection by port name. If the specified connection relationship is sequential connection, the principle of sequential connection is that the routing between each port will not intersect. If the specified connection relationship is reverse connection, the connection order is the reverse of sequential connection. If the specified connection relationship is connection by port name, it precisely matches ports with the same port name in the two groups of Bus ports, regardless of the specific positions of the two ports within their respective groups. The process constraints include the processing process constraints used by the layout to be processed, which include, but are not limited to, available metal layers, available via definitions, and the minimum number of vias (also known as MinNumberCut).

[0049] Step S102: Determine the connection relationship, including sorting and matching the two groups of Bus ports selected in the L-shaped area according to the specified connection relationship.

[0050] In this embodiment, the reason for selecting the bus ports according to two groups is that in the design scenario of integrated circuit layout, the connection is usually between two groups of bus ports. Multiple groups of buses can also be divided into two pairs connected to form a scenario of two groups of bus ports connected together. This reduces the design difficulty of routing and improves routing efficiency. Selecting the ports according to two groups allows us to consider one group as the source and the other group as the target based on electrical signal relationships, and connect from the source to the target.

[0051] In step 102, the two selected groups of bus ports are sorted and matched one-to-one based on the specified connection relationship. This includes sorting the two selected groups of bus ports and performing a pre-connection check on the cabling between the two selected groups of bus ports to ensure a one-to-one correspondence. The specified connection relationship can be manually specified by the designer, for example.

[0052] The two selected bus ports are sorted, including:

[0053] S112. Divide the Bus cabling ports into the first group (Group A) and the second group (Group B);

[0054] S122. Set the routing direction for the first group (GroupA) and the second group (GroupB) respectively, including: for either the first group or the second group as the target group, perform the following steps:

[0055] S1221. Take the direction with the most identical directions in the target group as the wiring direction of the target group;

[0056] The wiring direction is, for example, horizontal or vertical.

[0057] S1222. Determine the coordinates of the port direction perpendicular to the target group;

[0058] S1223. Use the coordinate values ​​as sorting reference values ​​for Bus cabling ports within the target group;

[0059] S1224. Sort the Bus cabling ports within the target group based on the sorting reference value, for example, sort them from smallest to largest.

[0060] For example, in step S1221, the wiring direction of the first group (GroupA) is determined to be horizontal, and the wiring direction of the second group (GroupB) is determined to be vertical. Then, steps S1222-S1224 are executed for the first group and the second group respectively to sort the bus wiring ports in the first group (GroupA) and the second group (GroupB). For example, for the first group (GroupA), the bus wiring ports are sorted from bottom to top, based on the corresponding sorting reference value, in ascending order as 1 / 2 / 3 / 4. For the bus wiring ports in the second group (GroupB), the bus wiring ports are sorted from left to right, based on the corresponding sorting reference value, in ascending order as 1 / 2 / 3 / 4.

[0061] Optionally, after completing the bus cabling port sorting, the above-mentioned cabling pre-connection check is performed. By performing the above-mentioned cabling pre-connection check, it is determined whether the specified connection relationship matches if cabling is performed based on the sorted bus cabling ports.

[0062] Using any Bus cabling port as the target cabling port, perform the above-mentioned cabling pre-connection check, including the following steps:

[0063] Take the intersection of the center extensions of the routing direction of the target routing port as the pre-routing inflection point, and check whether the pre-routing segment of the target routing port intersects with the pre-routing segment of other target routing ports.

[0064] If not, the pre-connection relationship of the target cabling port is determined to be sequential; if it is, the pre-connection relationship of the target cabling port is determined to be reverse.

[0065] If the specified connection relationship is a sequential connection, then when the pre-routing segment of the target routing port does not intersect with the pre-routing segment of other target routing ports, it is determined that if routing is performed based on the sorted Bus routing ports, the specified connection relationship can be matched; or, when the pre-routing segment of the target routing port intersects with the pre-routing segment of other target routing ports, it is determined that if routing is performed based on the sorted Bus routing ports, it would be a reverse connection, and the reverse connection needs to be reversed to become a sequential connection in order to match the specified connection relationship.

[0066] Conversely, if the specified connection relationship is a reverse connection, then when the pre-routing segment of the target routing port does not intersect with the pre-routing segment of other target routing ports, the pre-connection relationship of the target routing ports is a sequential connection. Therefore, if routing is performed based on the sorted Bus routing ports, the specified connection relationship does not match, and the pre-connection relationship that is a sequential connection needs to be reversed to obtain a reverse connection to match the specified reverse connection. Alternatively, when the pre-routing segment of the target routing port intersects with the pre-routing segment of other target routing ports, the pre-connection relationship of the target routing port is a reverse connection. Therefore, if routing is performed based on the sorted Bus routing ports, the specified connection relationship can be matched.

[0067] If, for the target cabling port, the specified connection relationship is a reverse connection while the pre-connection relationship is a sequential connection, then the cabling ports in the group to which the target cabling port belongs are rearranged in reverse order, thereby reversing the pre-connection relationship to match the specified connection relationship.

[0068] If the specified connection relationship for the target cabling port is a connection by port name, then the sorting step is skipped, and a one-to-one correspondence is performed by matching port names, so that when determining the pre-routing segment, ports with the same port name in the two groups of Bus ports are connected together.

[0069] Step S103, determining the routing layer to set the routing path on the routing layer, includes: obtaining the available routing layers for avoiding obstacles when implementing L-shaped routing corresponding to the routing port according to the layout data, and selecting two routing layers for L-shaped routing from the available routing layers.

[0070] Optionally, obtaining a usable cabling layer to avoid obstacles when implementing L-shaped cabling at the cabling port includes:

[0071] S113. Divide the L-shaped region into several sub-regions.

[0072] See Figure 2For the two selected sets of bus ports, the L-shaped area is formed by the connection area between the two sets of bus ports and the cabling port. Therefore, the L-shaped area can be directly divided into a first sub-area (e.g., Figure 2 Middle region A), second sub-region (e.g.) Figure 2 Middle region B), third sub-region (e.g.) Figure 2 Middle region C), fourth sub-region (e.g.) Figure 2 The central area (D) comprises four sub-areas: A and B in the horizontal direction, and C and D in the vertical direction. B and C have overlapping areas. Areas A and D contain two sets of bus ports, while B and C form the connection area between the cabling ports. This division into four areas is merely an example and not a definitive limitation.

[0073] S123. Perform spatial indexing of the geometry in each sub-region to obtain continuous available wiring layer intervals.

[0074] In this embodiment, before step S123, all geometric shapes of the entire layout to be processed are stored in a data index library. Therefore, when executing step S123, the coordinates of each sub-region are passed in, and all geometric shapes within each sub-region are extracted from the data index library. Then, by performing spatial indexing of the geometric shapes within each sub-region, the obstacle shapes within each sub-region are extracted. The layer containing the obstacle shapes is then removed from all valid routing layers, thereby obtaining a continuous list of available routing layers to determine the available routing layer intervals. Because the obstacle shapes are removed, short circuits caused by routing along obstacles are avoided.

[0075] S133. Select the two metal layers with the fewest vias within the available layer range as wiring layers to set wiring paths on them.

[0076] Optionally, within the available layer range, the two metal layers that generate the fewest vias are selected as wiring layers, including:

[0077] Calculate the layer selection cost of connecting several sub-regions within an L-shaped region, and select the two metal layers that generate the fewest vias as routing layers to set routing paths on them.

[0078] The calculation of the layer selection cost for connecting several sub-regions within an L-shaped region includes: calculating the layer number difference between each pair of sub-regions in the horizontal direction and the layer number difference between two adjacent sub-regions in the vertical direction within the L-shaped region, in order to calculate the layer selection cost for connecting several sub-regions within the L-shaped region.

[0079] For example, when selecting a layer, the layer number of the bus port in sub-regions A and D is recorded as Layer. A and Layer DLet the layer number of subregions B and C be Layer. B and Layer C Cost = Min(abs(Layer) A -Layer B )+abs(Layer B -Layer C )+abs(Layer C -Layer D As a cost of layer selection, optimal layer selection is performed. To create fewer vias and avoid layers containing obstacles, the two metal layers that generate the fewest vias are selected, satisfying the following conditions:

[0080] Selecting a layer has the lowest cost;

[0081] Layer A and Layer B Within sub-region A, connections can be made via the same layer or through-holes;

[0082] Layer B and Layer C Within the overlapping area of ​​sub-regions B and C, connections can be made through the same layer or vias;

[0083] Layer C and Layer D Within sub-region D, connections can be made via the same layer or through-holes.

[0084] Step S104: Create and adjust vias on the wiring layer, including: creating vias at the connection of two sub-regions that need to cross layers according to the determined wiring layer, and limiting the minimum number of vias to 2, so as to adjust the position of the vias.

[0085] Based on the determined wiring layer, vias are created at the junction of two sub-regions that need to cross layers, including:

[0086] Based on the determined wiring layer, check whether the overlapping areas of sub-region A and sub-region B, sub-region B and sub-region C, and sub-region C and sub-region D cross layers. If they cross layers, create vias. The creation of vias includes at least one of setting the minimum number of vias, selecting the via direction, and adjusting the via position.

[0087] Specifically, when checking whether sub-regions A and B, B and C, and C and D cross layers, the layer numbers of the two sub-regions are compared to determine if they cross layers. For example, if the layer numbers of sub-regions A and B are not equal, then sub-regions A and B cross layers; otherwise, they do not. Similarly, the layer checks are performed for the overlapping areas of sub-regions B and C, and C and D.

[0088] To meet the layout requirements of analog integrated circuits, the minimum number of vias MinNumberCut specified by the process is read, and the minimum number of vias generated during the wiring process is taken as Max(Min Number Cut,2) to reduce the voltage drop on the wiring connection path.

[0089] The minimum number of through holes is limited to 2, in order to adjust the position of the through holes, including:

[0090] When Max(Min Number Cut,2) = 2, the created vias are translated or rotated to align with the edges of the wiring paths to identify wirings that are not short-circuited to each other.

[0091] In this step, such as Figure 3 As shown, there are four possible arrangement directions for the through holes: horizontal to the left, horizontal to the right, vertical to the top, and vertical to the bottom. All through holes will be selected according to these four directions. First, the overall matching of the through holes (hereinafter referred to as Matching) is considered. All through holes with the same orientation are considered as matched through holes, thus producing the following... Figure 4 All vias shown in the Matching diagram are oriented in the same direction (all horizontal to the right), and there are no short circuits between the wiring and vias. For example... Figure 4 As shown, selecting the horizontal left direction will produce a Short, resulting in an overall mismatch of the via (hereinafter referred to as a non-Matching via). However, selecting the horizontal right (or vertical down in other embodiments) will not produce a Short.

[0092] If the via matching cannot be satisfied after trying all directions, then the direction of a single via is adjusted, including: trying each via in one of the four arrangement directions using a greedy strategy until a direction that does not produce a Short is found, i.e., produces a... Figure 4 For non-Matching through-hole arrangements, three are horizontally facing left and one is vertically facing up.

[0093] Furthermore, when Max(Min Number Cut,2)>2, such as Figure 5As shown, the created vias are aligned to the center of the routing path, and the number of cuts is maximized in the overlapping area of ​​the routing paths, so that the vias completely cover the overlapping area of ​​the routing paths.

[0094] Step S105: Output the wiring path and via geometry to the layout to be processed.

[0095] Specifically, in step S105, the wiring paths set on the wiring layer and the corresponding graphics of the vias are merged into the layout to be processed.

[0096] The solution based on the above embodiments of this application, when applied to a specific scenario, such as... Figure 6 As shown, the general steps are as follows:

[0097] (1) Select two groups of Bus ports, referred to as Group A and Group B respectively, and set the connection relationship as reverse connection. In the process constraint, MinNumberCut is 1.

[0098] (2) Determine the connection relationship, such as Figure 6 As shown, after sorting the two groups of ports and performing a pre-connection check, there are no intersections between the wiring ports. Since step (1) sets the connection relationship to reverse order, one group of Bus ports is rearranged in reverse order. The result after reordering is as follows. Figure 6 The connection relationships are shown below.

[0099] (3) Perform L-shaped region layer selection, because... Figure 6 There is a Metal3 obstacle in the L-shaped wiring area, so the upper right area cannot be connected using Metal3. It is necessary to cross the layer to Metal2 through the via V2 (the via connecting Metal3 to Metal2) to complete the connection. Therefore, the two wiring layers are Metal2 and Metal3.

[0100] (4) Create vias. Since the MinNumberCut in the process is 1, according to the double-via principle, the minimum number of vias is 2. Cross-layer vias are created at the L-shaped area connection and the Bus port. The double vias within the L-shaped connection area are aligned. The final wiring result is as follows: Figure 6 The L-shaped wiring result is shown.

[0101] This patent application also provides an electronic device. The electronic device includes a memory and a processor, the memory storing a computer-executable program, and the processor running the computer-executable program to implement the method described in any embodiment of this patent application.

[0102] The embodiments of this patent application have been described above with reference to the accompanying drawings. However, this patent application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms based on the teachings of this patent application without departing from the spirit and scope of the claims of this patent application, and all of these forms are within the scope of protection of this patent application.

Claims

1. A wiring method for automatic obstacle avoidance, characterized in that, include: Step S101: Initialize the routing resources of the layout to be processed, including: obtaining the layout data, routing settings and process constraints corresponding to the L-shaped area in the layout to be processed; Step S102: Determine the connection relationship, including: sorting and matching the two groups of Bus ports selected in the L-shaped area according to the specified connection relationship; Step S103: Determine the routing layer, including: based on the layout data, obtain the available routing layers that avoid obstacles when implementing L-shaped routing corresponding to the routing port, and select two routing layers from the available routing layers for L-shaped routing; Step S104, Creating and Adjusting Vias, includes: creating vias at the connection point of two sub-regions that need to cross layers according to the determined wiring layer, and limiting the minimum number of vias to 2, while adjusting the position of the vias; Step S105: Output the geometry of the wiring and vias to the layout to be processed; Wherein, obtaining the available cabling layer for avoiding obstacles when implementing L-shaped cabling corresponding to the cabling port includes: S113. Divide the L-shaped region into several sub-regions; S123. Perform spatial indexing of the geometry in each sub-region to obtain continuous available wiring layer intervals; S133. Select the two metal layers with the fewest vias within the available wiring layer range as wiring layers. The sorting of the two selected bus ports includes: S112. Divide the Bus cabling ports into the first group (GroupA) and the second group (GroupB). S122. Set the routing direction for the first group (GroupA) and the second group (GroupB) respectively, and perform the following steps for either the first group or the second group as the target group: S1221. Take the direction with the most identical directions in the target group as the wiring direction of the target group; S1222. Determine the coordinates of the port direction perpendicular to the target group; S1223. Use the coordinate values ​​as sorting reference values ​​for the Bus cabling ports within the target group; S1224. Sort the Bus cabling ports within the target group based on the sorting reference value; Prior to step S123, all geometric shapes of the entire layout to be processed are stored in a data index library. Therefore, when executing step S123, the coordinates of each sub-region are passed in, all geometric shapes in each sub-region are extracted from the data index library, and then the spatial index of the geometric shapes in each sub-region is performed to extract the obstacle shapes in each sub-region. The layer where the obstacle shapes are located is removed from all valid routing layers to obtain a continuous list of available routing layers to determine the available routing layer interval.

2. The method according to claim 1, characterized in that, The layout data includes obstacle graphics in the layout and two groups of bus ports selected by box; the routing settings include connection relationship settings, which include at least one of sequential connection, reverse connection, and connection according to port name; the process constraints include the processing process constraints used by the layout to be processed, which include available metal layers, available via definitions, and minimum number of vias.

3. The method according to claim 2, characterized in that, Execute step S1221 to determine that the wiring direction of the first group (GroupA) is horizontal and the wiring direction of the second group (GroupB) is vertical. Then, execute the above steps S1222-S1224 for the first group and the second group respectively to sort the Bus wiring ports in the first group (GroupA) and the second group (GroupB).

4. The method according to claim 3, characterized in that, Use any Bus cabling port as the target cabling port to perform a cabling pre-connection check, including the following steps: Take the intersection of the center extensions of the routing direction of the target routing port as the pre-routing inflection point, and check whether the pre-routing segment of the target routing port intersects with the pre-routing segment of other target routing ports. If not, the pre-connection relationship of the target cabling port is determined to be a sequential connection; If the specified connection relationship for the target cabling port is a reverse connection, then the cabling ports in the group to which the target cabling port belongs are rearranged in reverse order. If the specified connection relationship for the target cabling port is a connection via port name, then skip the sorting step and perform a one-to-one correspondence by matching port names.

5. The method according to claim 1, characterized in that, Selecting the two metal layers with the fewest vias within the available wiring layer range as wiring layers includes: Calculate the layer selection cost of connecting several sub-regions within an L-shaped region, and select the two metal layers that generate the fewest vias as wiring layers.

6. The method according to claim 5, characterized in that, The calculation of the layer selection cost for connecting several sub-regions within an L-shaped region includes: calculating the layer number difference between two adjacent sub-regions in the horizontal direction and the layer number difference between two adjacent sub-regions in the vertical direction within the L-shaped region, in order to calculate the layer selection cost for connecting several sub-regions within the L-shaped region.

7. The method according to claim 6, characterized in that, The step of creating vias at the connection point of two sub-regions that need to cross layers, based on the determined wiring layer, includes: Based on the determined wiring layer, check whether the sub-region spans multiple layers. If it does, create vias. The creation of vias includes at least one of setting the minimum number of vias, selecting the via direction, and adjusting the via position.

Images