Shift register, gate drive circuit, display panel and display device

Abstract

This disclosure provides a shift register, a gate driving circuit, a display panel, and a display device, relating to the field of display technology. In the shift register: a first display input circuit is configured to write a signal from a first signal terminal to a first pull-up node under the signal control of a first display input terminal; a first display shift circuit is configured to write a signal from a first shift signal terminal to a first shift output terminal under the signal control of the first pull-up node; a black bead insertion input circuit is configured to write a signal from a second voltage terminal to the first pull-up node under the signal control of a first black bead insertion input terminal, a first control terminal, and a second control terminal; a first black bead insertion shift circuit is configured to write a signal from a second shift signal terminal to a second shift output terminal under the signal control of the first pull-up node; and a first output circuit is configured to write a signal from the first signal terminal to a first output terminal under the signal control of the first pull-up node.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display panel, and a display device. Background Technology

[0002] In the display field, especially in organic light-emitting diode (OLED) display devices, the switching process of dynamic display images is prone to causing motion blur, i.e., when switching from one frame to the next, a blur of the previous frame can be perceived. To overcome this motion blur, related technologies have added a black-cutting process during pixel illumination. By adding this black-cutting process, the normal display time of pixels is reduced, thereby effectively improving the motion blur phenomenon. Summary of the Invention

[0003] Embodiments of this disclosure provide a shift register, a gate drive circuit, a display panel, and a display device that improve the motion blur phenomenon in dynamic images.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On the one hand, a shift register is provided, including a first scanning unit, the first scanning unit including a first display input circuit, a first display shift circuit, a black bead input circuit, a first black bead shift circuit and a first output circuit; The first display input circuit is electrically connected to the first display input terminal, the first voltage terminal, and the first pull-up node. The first display input circuit is configured to write the signal of the first voltage terminal to the first pull-up node under the signal control of the first display input terminal. The first display shift circuit is electrically connected to the first pull-up node, the first shift signal terminal, and the first shift output terminal. The first display shift circuit is configured to write the signal of the first shift signal terminal to the first shift output terminal under the signal control of the first pull-up node. The black bar input circuit is electrically connected to the first black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the first pull-up node. The black bar input circuit is configured to write the signal of the second voltage terminal to the first pull-up node under the signal control of the first black bar input terminal, the first control terminal, and the second control terminal. The first black-insertion shift circuit is electrically connected to the first pull-up node, the second shift signal terminal, and the second shift output terminal. The first black-insertion shift circuit is configured to write the signal of the second shift signal terminal to the second shift output terminal under the signal control of the first pull-up node. The first output circuit is electrically connected to the first pull-up node, the first signal terminal, and the first output terminal. The first output circuit is configured to write the signal from the first signal terminal to the first output terminal under the signal control of the first pull-up node.

[0005] In some embodiments, the shift register further includes a second scanning unit, which includes a second display input circuit, a second display shift circuit, and a second output circuit; The second display input circuit is electrically connected to the first shift output terminal, the first voltage terminal, and the second pull-up node. The second display input circuit is configured to write the signal of the first voltage terminal to the second pull-up node under the signal control of the first shift output terminal. The second display shift circuit is electrically connected to the second pull-up node, the third shift signal terminal, and the third shift output terminal. The second display shift circuit is configured to write the signal of the third shift signal terminal to the third shift output terminal under the signal control of the second pull-up node. The second output circuit is electrically connected to the second pull-up node, the second signal terminal, and the second output terminal. The second output circuit is configured to write the signal from the second signal terminal to the second output terminal under the signal control of the second pull-up node. The black bar input circuit is electrically connected to both the first pull-up node and the second pull-up node, and the black bar input circuit is also configured to write a signal to the second pull-up node.

[0006] In some embodiments, the black string insertion input circuit includes a first black string insertion input circuit and a second black string insertion input circuit; the first black string insertion input circuit is electrically connected to the first pull-up node and is configured to write a signal to the first pull-up node; the second black string insertion input circuit is electrically connected to the second pull-up node and is configured to write a signal to the second pull-up node.

[0007] In some implementations, at the same time, the signal written by the first black bar input circuit at the first pull-up node is the same as the signal written by the second black bar input circuit at the second pull-up node.

[0008] In some implementations... The first black bar input circuit is electrically connected to the first black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the first pull-up node. The first black bar input circuit is configured to write the signal of the second voltage terminal to the first pull-up node under the signal control of the first black bar input terminal, the first control terminal, and the second control terminal. The second black bar input circuit is electrically connected to the first black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the second pull-up node. The second black bar input circuit is configured to write the signal of the second voltage terminal to the second pull-up node under the signal control of the first black bar input terminal, the first control terminal, and the second control terminal.

[0009] In some implementations, the first black-insertion input circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit is electrically connected to the first black bar input terminal, the first control terminal, the second voltage terminal, and the first node. The first sub-circuit is configured to write the signal of the second voltage terminal to the first node under the signal control of the first black bar input terminal and the first control terminal. The second sub-circuit is electrically connected to the second control terminal, the first node and the first pull-up node. The second sub-circuit is configured to write the signal of the first node into the first pull-up node under the signal control of the second control terminal. The second black bar input circuit is electrically connected to the first node, the second control terminal, and the second pull-up node. The second black bar input circuit is configured to write the signal of the first node into the second pull-up node under the signal control of the second control terminal.

[0010] In some embodiments, the second black-insertion input circuit includes a first sub-circuit and a second sub-circuit; The first sub-circuit is electrically connected to the first black bar input terminal, the first control terminal, the second voltage terminal, and the second node. The first sub-circuit is configured to write the signal of the second voltage terminal to the second node under the signal control of the first black bar input terminal and the first control terminal. The second sub-circuit is electrically connected to the second control terminal, the second node and the second pull-up node. The second sub-circuit is configured to write the signal of the second node into the second pull-up node under the signal control of the second control terminal. The first black bar input circuit is electrically connected to the second node, the second control terminal, and the first pull-up node. The second black bar input circuit is configured to write the signal of the second node into the first pull-up node under the signal control of the second control terminal.

[0011] In some implementations, the first black bar input circuit is electrically connected to the first black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the first pull-up node. The first black bar input circuit is configured to write the signal of the second voltage terminal to the first pull-up node under the signal control of the first black bar input terminal, the first control terminal, and the second control terminal. The second black bar input circuit is electrically connected to the second black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the second pull-up node. The second black bar input circuit is configured to write the signal of the second voltage terminal to the second pull-up node under the signal control of the second black bar input terminal, the first control terminal, and the second control terminal. The second scanning unit further includes a second black-insertion shift circuit, which is electrically connected to the second pull-up node, the fourth shift signal terminal, and the fourth shift output terminal. The second black-insertion shift circuit is configured to write the signal of the fourth shift signal terminal to the fourth shift output terminal under the signal control of the second pull-up node.

[0012] In some implementations, the second voltage terminal and the second control terminal are electrically connected, or the second voltage terminal and the second control terminal are disconnected.

[0013] In some implementations, the first sub-circuit includes a third sub-circuit and a fourth sub-circuit; The third sub-circuit is electrically connected to the first black bar input terminal, the first control terminal, and the second node. The third sub-circuit is configured to write the signal from the first black bar input terminal to the second node under the signal control of the first control terminal. The fourth sub-circuit is electrically connected to the second node, the second voltage terminal, and the first pull-up node. The fourth sub-circuit is configured to write the signal of the second voltage terminal to the first pull-up node through the second sub-circuit under the signal control of the second node and the second control terminal.

[0014] In some embodiments, the first scanning unit further includes a first black-pin reset circuit, which is electrically connected to the first pull-up node, the second node, the black-pin reset control terminal, and the first reset voltage terminal. The first black-pin reset circuit is configured to write the signal of the first reset voltage terminal to the pull-up node under the signal control of the second node and the black-pin reset control terminal.

[0015] In some implementations, the first scanning unit further includes a first pull-down circuit and a first noise reduction circuit; The first pull-down circuit is electrically connected to the first pull-up node, the first reset voltage terminal, and the first pull-down node. The first pull-down circuit is configured to write the signal of the first reset voltage terminal into the first pull-down node under the signal control of the first pull-up node. The first noise reduction circuit is electrically connected to the first pull-down node, the first reset voltage terminal, and the second shift output terminal. The first noise reduction circuit is configured to write the signal of the first reset voltage terminal to the second shift output terminal under the signal control of the first pull-down node.

[0016] In some embodiments, the shift register further includes a fifth reset circuit, which is electrically connected to the second control terminal, the second node, the first reset voltage terminal, and the first pull-down node. The fifth reset circuit is configured to write the signal from the first reset voltage terminal to the first pull-down node under the signal control of the second node and the second control terminal.

[0017] On the other hand, a gate drive circuit is provided, including a plurality of the aforementioned shift registers, wherein the plurality of the shift registers are cascaded.

[0018] In some embodiments, the plurality of shift registers include a cascaded first shift register and a second shift register. The shift registers include a first display shift circuit, a second display shift circuit, and a first black-insertion shift circuit. The second shift output of the first shift register is electrically connected to the first black-insertion input of the second shift register, and the third shift output of the first shift register is electrically connected to the first display input of the second shift register.

[0019] In some embodiments, the plurality of shift registers include a cascaded first shift register and a second shift register. When the shift register includes a first display shift circuit, a second display shift circuit, a first black-insertion shift circuit, and a second black-insertion shift circuit, the third shift output terminal of the first shift register is electrically connected to the first display input terminal of the second shift register, the second shift output terminal of the first shift register is electrically connected to the first black-insertion input terminal of the second shift register, and the fourth shift output terminal of the first shift register is electrically connected to the second black-insertion input terminal of the second shift register.

[0020] In some embodiments, the gate driving circuit includes multiple gate lines, the first scanning unit includes multiple first output circuits, and the first output terminals of the multiple first output circuits are electrically connected to different gate lines respectively; and / or, the second scanning unit includes multiple second output circuits, and the second output terminals of the multiple second output circuits are electrically connected to different gate lines respectively, and the first output terminal and the second output terminal are electrically connected to different gate lines.

[0021] In some embodiments, the first scanning unit includes four first output circuits, and the second scanning unit includes four second output circuits.

[0022] In another aspect, a display panel is provided, including the aforementioned gate driving circuit.

[0023] In another aspect, a display device is provided, including the aforementioned display panel.

[0024] The shift register, gate driving circuit, display panel, and display device of this disclosure embodiment are further provided with a first black bead insertion input circuit, a first black bead insertion shift circuit, a first display input circuit, a first display shift circuit, and a first output circuit. The first output circuit is electrically connected to the pixel driving circuit P1 to control the pixel driving circuit P1 to write screen data signals and black data signals. The first black bead insertion input circuit, the first output circuit, and the first black bead insertion shift circuit constitute a black bead insertion driving module to realize black bead insertion driving, and the first display input circuit, the first output circuit, and the first display shift circuit constitute a display driving module to realize display driving. The first black bead insertion shift circuit can be used to realize the cascading of different black bead insertion driving modules, and the first display shift circuit can be used to realize the cascading of different display driving modules, that is, a separate first black bead insertion shift circuit can be set to realize the cascading between different black bead insertion driving modules. Compared with the related technology that realizes the cascading of black bead insertion driving modules by multiplexing display shift circuits and / or display output circuits, the first black bead insertion shift circuit in this disclosure embodiment cascades fewer shift registers and has lower wiring difficulty. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 An exemplary front view structure of a display device is shown; Figure 2 An exemplary structural diagram of a display panel is shown; Figure 3 An exemplary circuit diagram of a pixel driving circuit is shown; Figure 4 An exemplary structural diagram of another display panel is shown; Figure 5 An example is shown Figure 3 The diagram shows a signal timing diagram of a pixel driving circuit. Figure 6 An exemplary circuit block diagram of a shift register is shown; Figure 7 An exemplary circuit diagram of a first scanning unit is shown; Figure 8 An exemplary block diagram of another shift register is shown; Figure 9 An exemplary block diagram of another shift register is shown; Figure 10 An exemplary circuit diagram of a shift register is shown; Figure 11 An exemplary circuit diagram of a first black-plug input circuit is shown; Figure 12 An exemplary circuit diagram of a second black-plug input circuit is shown; Figure 13 An exemplary circuit diagram of a shift register is shown; Figure 14 An exemplary circuit diagram of a first black-plug input circuit is shown; Figure 15 A block diagram of a gate drive circuit is shown as an example; Figure 16 A timing diagram of a gate drive circuit is shown as an example; Figure 17 An exemplary circuit diagram of a shift register is shown; Figure 18 A circuit diagram of another shift register is shown as an example. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0029] To enable those skilled in the art to better understand the technical solutions of this disclosure, a scanning unit and its driving method, gate driving circuit and display device provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0030] The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "coupled" or "connected" are not limited to physical or mechanical coupling, but can include electrical coupling, whether direct or indirect.

[0031] The transistors used in the embodiments of this disclosure can be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with the same characteristics. Since the source and drain of the transistors are symmetrical, there is no distinction between them. In the embodiments of this disclosure, to distinguish the source and drain of the transistor, one is called the first electrode, the other the second electrode, and the gate is called the control electrode. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments use N-type transistors for illustration. When using an N-type transistor, the first electrode is the source, the second electrode is the drain, and when the gate input is high, the source and drain are conducting. The opposite is true for P-type transistors. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without inventive effort, and therefore it is also within the scope of protection of the embodiments of this disclosure.

[0032] In this embodiment, "effective level signal" refers to a signal that, when input to the control electrode of a transistor, can control the transistor to conduct, and "ineffective level signal" refers to a signal that, when input to the control electrode of a transistor, can control the transistor to cut off. For N-type transistors, a high-level signal is an effective level signal, and a low-level signal is an ineffective level signal; for P-type transistors, a low-level signal is an effective level signal, and a high-level signal is an ineffective level signal.

[0033] Figure 1 An exemplary front view of a display device is shown. For example... Figure 1 As shown, some embodiments of this disclosure provide a display device that can be any device that displays text or images, whether in motion (e.g., video) or stationary (e.g., still images). More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 The illustration uses a television as an example.

[0034] The display device includes a display panel. Exemplarily, the display device includes a housing and a display panel, with the display panel attached to the housing. In practical applications, the display device may also include a circuit board, a display driver IC (integrated circuit), and other electronic components disposed inside the housing.

[0035] The display panel can be a liquid crystal display (LCD); it can also be an electroluminescent display panel or a photoluminescent display panel. When the display panel is an electroluminescent display panel, it can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. When the display panel is a photoluminescent display panel, the photoluminescent display device can be a quantum dot photoluminescent display panel. Some embodiments of this disclosure are illustrated using an organic light-emitting diode (OLED) display panel as an example.

[0036] Figure 2 An exemplary structural diagram of a display panel is shown. For example... Figure 2 As shown, the display panel includes a substrate and multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL disposed on one side of the substrate.

[0037] The substrate can be either a rigid substrate or a flexible substrate, and the choice can be made according to actual needs.

[0038] For example, the substrate is a rigid substrate. For instance, the rigid substrate can be a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc.

[0039] For example, the substrate can be a flexible substrate. For instance, the flexible substrate can be a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylenenaphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate, etc.

[0040] The display panel may have a display area A and a non-display area B electrically connected to the display area A. The non-display area B may be located on one, two, or three sides of the display area A, or it may surround the display area A. Multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL may be located within the display area A.

[0041] For example, multiple subpixels PX can be arranged in an array. For instance, the array arrangement of multiple subpixels PX forms multiple subpixel rows and multiple subpixel columns. Multiple subpixels PX in a subpixel row are arranged along a first direction X, and multiple subpixels PX in a subpixel column are arranged along a second direction Y.

[0042] In this configuration, the first direction X and the second direction Y intersect each other. The included angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the included angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92°, or 95°, etc.

[0043] The sub-pixel PX may include a pixel driving circuit P1 and a light-emitting device P2 electrically connected to the pixel driving circuit P1. When the display panel is working, the light-emitting device P2 can emit light under the drive of the pixel driving circuit P1.

[0044] For example, a gate line GL can be electrically connected to multiple pixel driving circuits P1 in a sub-pixel row, and a data line DL can be electrically connected to multiple pixel driving circuits P1 in a sub-pixel column.

[0045] The pixel driving circuit P1 has various structures, which can be selected according to actual needs. For example, the pixel driving circuit P1 can include structures such as "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C". Here, "T" represents a transistor, and the number before "T" indicates the number of transistors; "C" represents a storage capacitor, and the number before "C" indicates the number of storage capacitors.

[0046] During the use of the display device, the stability of the transistors in the pixel driving circuit P1 and the light-emitting device OLED may decrease (e.g., the threshold voltage of the driving transistors drifts), affecting the display effect of the display device. Therefore, it is necessary to compensate for the sub-pixel PX.

[0047] There are various ways to compensate sub-pixels PX, and the appropriate method can be selected based on actual needs. For example, a pixel compensation circuit can be incorporated into the sub-pixel PX to perform internal compensation. Alternatively, the driving transistor or light-emitting device can be sensed by the transistors inside the sub-pixel PX, and the sensed data can be transmitted to an external sensing circuit. This external sensing circuit can then calculate the required driving voltage value for compensation and provide feedback, thereby achieving external compensation for the sub-pixel PX.

[0048] This disclosure illustrates the structure and operation of a sub-pixel PX using an external compensation method (sensing the driving transistor) and a pixel driving circuit with a "3T1C" structure as an example.

[0049] Figure 3 An exemplary circuit diagram of a pixel driving circuit is shown. For example, such as... Figure 3 As shown, the pixel driving circuit P1 may include a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst.

[0050] The control terminal of the switching transistor T1 is electrically connected to the first gate signal terminal G1, the first terminal of the switching transistor T1 is electrically connected to the data signal terminal Data, and the second terminal of the switching transistor T1 is electrically connected to the node G. The switching transistor T1 is configured to transmit the data signal from the data signal terminal Data to the node G under the control of the first scan signal of the first gate signal terminal G1.

[0051] Here, the data signals include, for example, detection data signals and display data signals. The detection data signals are used during the blanking period, and the display data signals are used during the display period. The display period and blanking period can be referred to in the descriptions of some of the following embodiments, and will not be repeated here.

[0052] The control electrode of driving transistor T2 is electrically connected to node G, the first electrode of driving transistor T2 is electrically connected to the sixth voltage signal terminal ELVDD, and the second electrode of driving transistor T2 is electrically connected to node S. Driving transistor T2 is configured to conduct under the signal control of node G and to write a driving signal related to node G and the sixth voltage signal terminal ELVDD to node S.

[0053] The first terminal of the storage capacitor Cst is electrically connected to node G, and the second terminal of the storage capacitor Cst is electrically connected to node S. During the charging of node G, the switching transistor T1 simultaneously charges the storage capacitor Cst.

[0054] The anode of the light-emitting device P2 is electrically connected to node S, and the cathode of the light-emitting device P2 is electrically connected to the seventh voltage signal terminal ELVSS. The light-emitting device P2 is configured to emit light under the drive of a driving signal.

[0055] The control terminal of sensing transistor T3 is electrically connected to the second gate signal terminal G2, the first terminal of sensing transistor T3 is electrically connected to node S, and the second terminal of sensing transistor T3 is electrically connected to the sensing signal terminal Sense. Sensing transistor T3 is configured to detect the electrical characteristics of driving transistor T2 under the control of a second scan signal from the second gate signal terminal G2 to achieve external compensation. These electrical characteristics include, for example, the threshold voltage and / or carrier mobility of driving transistor T2.

[0056] Here, the sensing signal terminal Sense can provide a reset signal or acquire a sensing signal. The reset signal is used to reset node S during the display period, and the acquire sensing signal is used to acquire the threshold voltage and / or carrier mobility of the driving transistor T2 during the blanking period.

[0057] When the structure of pixel driving circuit P1 adopts the following... Figure 3 In the structure shown, multiple pixel driving circuits P1 in a sub-pixel row can be electrically connected to two gate lines GL. For example, the multiple gate lines include a first gate line and a second gate line. The first gate line is electrically connected to multiple first gate signal terminals G1 in a sub-pixel row, so that each first gate signal terminal G1 can receive a first scan signal through the first gate line. The second gate line is electrically connected to multiple second gate signal terminals G2 in a sub-pixel row, so that each second gate signal terminal G2 can receive a second scan signal through the second gate line.

[0058] Of course, multiple pixel driving circuits P1 in a sub-pixel row can also be electrically connected to a gate line GL. Figure 4 An exemplary structural diagram of another display panel is shown. For example... Figure 4 As shown, the first gate signal terminal G1 and the second gate signal terminal G2 in a sub-pixel row are both electrically connected to the same gate line GL.

[0059] Continue to refer to Figure 2 A gate driving circuit is also provided on one side of the substrate. The gate driving circuit, the aforementioned multiple sub-pixels PX, gate lines GL, and data lines DL are located on the same side of the substrate. The gate driving circuit includes multiple cascaded shift registers, each with an output terminal that can be electrically connected to the gate line GL. When the gate driving circuit is operating, the multiple cascaded shift registers output first and second scan signals to the pixel driving circuit P1 step by step through their output terminals.

[0060] It should be noted that during the display phase of one frame, the first scan signal transmitted by the first gate signal terminal G1 and the second scan signal transmitted by the second gate signal terminal G2 are both provided by the gate driving circuit. That is, each shift register in the gate driving circuit can be electrically connected to the first gate signal terminal G1 through the first gate line to transmit the first scan signal to the first gate signal terminal G1 through the first gate line, and can be electrically connected to the second gate signal terminal G2 through the second gate line to transmit the second scan signal to the second scan signal terminal G2 through the second gate line.

[0061] Figure 4 An exemplary structural diagram of another display panel is shown. For example... Figure 4As shown, the first gate signal terminal G1 and the second gate signal terminal G2 of multiple pixel driving circuits P1 in a sub-pixel row can also be electrically connected to the same gate line GL. In this case, the first scan signal and the second scan signal are the same. Each shift register in the gate driving circuit can be electrically connected to the first gate signal terminal G1 and the second gate signal terminal G2 through the corresponding gate line GL, and transmits the scan signal to the first gate signal terminal G1 and the second gate signal terminal G2 through the gate line GL.

[0062] In related technologies, sub-pixels (PXs) exhibit motion blur during operation; that is, when the display device switches from one frame to another, the user perceives a blur of the previous frame. To mitigate this issue, a black data writing process and a black data retention process can be incorporated into the PX's emission process. Figure 5 An example is shown Figure 3 The image shows a signal timing diagram of a pixel driving circuit, such as... Figure 5 As shown, a black data writing process and a black data holding process are added sequentially to the original emission process, which is to say, a black insertion process is set up. This reduces the emission time and enhances the Moving Picture Response Time (MPRT). The larger the MPRT, the less ghosting occurs.

[0063] The control circuit P1 for writing data and emitting light is called display driving; the control circuit P1 for writing and holding black data is called black insertion driving. The gate driving circuit can simultaneously perform both display driving and black insertion driving functions; that is, each stage of the shift register within the gate driving circuit can be used for both display driving and black insertion driving. Figure 5 As can be seen, the timing of the display drive and the timing of the black insertion drive are not synchronized. Therefore, the circuit structure in the gate drive circuit used to implement the display drive can have different cascading relationships with the circuit structure used to implement the black insertion drive.

[0064] The operation of the gate drive circuit can include alternating display drive and black bar insertion drive phases. During the display drive phase, several shift registers within the gate drive circuit sequentially output display drive signals (e.g., ...) for display driving. Figure 5 In the black insertion drive stage, the output terminals of several shift registers in the gate drive circuit output black insertion drive signals for black insertion drive (e.g., pulse 1); Figure 5 Pulse 2 in the middle.

[0065] Figure 6 An exemplary circuit block diagram of a shift register is shown. For example... Figure 6As shown, the shift register includes a first scanning unit MD1, which includes a first display input circuit 11, a first display shift circuit 12, a black bead input circuit 13, a first black bead shift circuit 14, and a first output circuit 15.

[0066] The first display input circuit 11 is connected to the first voltage terminal GVDD1 and the first display input terminal CR. <k-1>The first pull-up node Q1 is electrically connected. The first output circuit 15 is electrically connected to the first pull-up node Q1, the first signal terminal CLKE1, and the first output terminal Gout1. The first display shift circuit 12 is connected to the first pull-up node Q1, the first shift signal terminal CLKD3, and the first shift output terminal CR. <k>Electrical connection.

[0067] During the display driving phase, the first display input circuit 11 is configured to operate at the first display input terminal CR. <k-1>Under the signal control of the first voltage terminal GVDD1, the signal of the first voltage terminal GVDD1 is written to the first pull-up node Q1. The first output circuit 15 is configured to write the signal of the first signal terminal Gout1 under the signal control of the first pull-up node Q1. The first display shift circuit 12 is configured to write the signal of the first shift signal terminal CLKD3 to the first shift output terminal CR under the signal control of the first pull-up node Q1. <k>.

[0068] The first voltage terminal GVDD1 can be supplied with a constant level signal. For example, the first voltage terminal GVDD1 can be supplied with a constant high level signal. Exemplarily, the display panel includes a first voltage line, a constant high level signal is supplied through the first voltage line, and the first voltage line is electrically connected to the first voltage terminal GVDD1.

[0069] The first pull-up node Q1 does not represent an actual existing component, but rather the junction point of related electrical connections in the circuit diagram. In other words, the first pull-up node Q1 is an equivalent node derived from the junction point of related electrical connections in the circuit diagram. Similarly, the second pull-up node Q2, the first pull-down node QB1, the second pull-down node QB2, node G, node S, the first node P, and the second node M in this embodiment are all equivalent nodes derived from the junction points of related electrical connections in the circuit diagram.

[0070] First display input terminal CR <k-1>It can be electrically connected to the start signal line STV to receive the start signal in the start signal line STV. For example, when the shift register is the first shift register in the gate drive circuit, the first display input terminal CR in the shift register... <k-1>Electrically connected to the start signal line STV. First display input terminal CR <k-1>It can also be electrically connected to the previous level shift register to receive the first shift signal output by the previous shift register. For example, the shift register is the nth shift register (n>1), and the first display input terminal CR of the nth shift register... <k-1>It is electrically connected to the (n-1)th shift register.

[0071] The first output terminal Gout1 can be electrically connected to the gate line GL to provide a scan signal to the first gate signal terminal G1 and / or the second gate signal terminal G2 through the gate line GL.

[0072] The first signal terminal can be electrically connected to a clock signal line. For example, the gate drive circuit includes multiple display clock signal lines CE, and the first signal terminal is electrically connected to the display clock signal lines CE.

[0073] The first shift signal terminal CLKD3 can be electrically connected to a clock signal line. For example, the gate drive circuit includes multiple black-stamped clock signal lines CD, and the first shift signal terminal CLKD3 is electrically connected to the black-stamped clock signal lines CD.

[0074] For example, the first display input terminal CR <k-1>When receiving a high-level signal from the previous stage shift register or the start signal line STV, the path between the first voltage terminal GVDD1 and the first pull-up node Q1 is connected, and the high-level signal of the first voltage terminal GVDD1 is written into the first pull-up node Q1, making the signal of the first pull-up node Q1 a high-level signal. Under the control of the high-level signal of the first pull-up node Q1, the first output circuit 15 connects the path between the first signal terminal and the first output terminal Gout1, and the high-level signal of the first signal terminal is written into the first output terminal Gout1. That is, the first output terminal Gout1 of the shift register provides a high-level signal to the first gate signal terminal G1 and the second gate signal terminal G2 through the gate line GL, causing the pixel driving circuit P1 to write the image data signal. Under the control of the high-level signal of the first pull-up node Q1, the first shift signal terminal CLKD3 and the first shift output terminal CR <k>The path between them is connected, and the high-level signal of the first shift signal terminal CLKD3 is written to the first shift output terminal CR. <k>.

[0075] That is, the first display input circuit 11, the first output circuit 15, and the first display shift circuit 12 constitute a display driving module to realize display driving. For example, the gate driving circuit may include multiple display driving modules, and the first shift output terminal CR of the previous display driving module <k>With the first display input terminal CR of the next display driver module <k-1>Electrical connections are used to enable the cascading of multiple display driver modules.

[0076] Black bar input circuit 13 and first black bar input terminal CR2 <k-2>The first control terminal BCK1, the second voltage terminal V2, the second control terminal BCK2, and the first pull-up node Q1 are electrically connected. The first black-insertion shift circuit 14 is connected to the first pull-up node Q1, the second shift signal terminal CLKD2, and the second shift output terminal CR2. <k>Electrical connection.

[0077] During the black insertion drive phase, the black insertion input circuit 13 is configured to operate at the first black insertion input terminal CR2. <k-2>Under the signal control of the first control terminal BCK1, the signal of the second voltage terminal V2 is written to the first pull-up node Q1. The first output circuit 15 is also configured to write the signal of the first signal terminal to the first output terminal Gout1 under the signal control of the first pull-up node Q1. The first black-insertion shift circuit 14 is configured to write the signal of the second shift signal terminal to the second shift output terminal CR2 under the signal control of the first pull-up node Q1. <k>.

[0078] The first control terminal BCK1 and the second control terminal BCK2 can be electrically connected to clock signal lines. For example, the gate drive circuit includes multiple control signal lines BC, and the first control terminal BCK1 and the second control terminal BCK2 can be electrically connected to different control signal lines BC.

[0079] The second voltage terminal V2 can be supplied with the same signal as the second control terminal BCK2, for example, the second voltage terminal V2 can be electrically connected to the second control terminal BCK2. The second voltage terminal V2 can also be supplied with a constant level signal, for example, the display panel includes a fourth voltage line GVDD4, the fourth voltage line is supplied with a constant high level signal, and the second voltage terminal V2 is electrically connected to the fourth voltage line GVDD4.

[0080] For example, the first black input terminal CR2 <k-2>Both the first control terminal BCK1 and the second control terminal BCK2 receive high-level signals, making the path between the second voltage terminal V2 and the first pull-up node Q1 conductive. The high-level signal of the second voltage terminal V2 is written into the first pull-up node Q1. Under the control of the high-level signal of the first pull-up node Q1, the first output circuit 15 makes the path between the first signal terminal and the first output terminal Gout1 conductive. The high-level signal of the first signal terminal is written into the first output terminal Gout1. That is, the first output terminal Gout1 of the shift register provides a high-level signal to the first gate signal terminal G1 and the second gate signal terminal G2 through the gate line GL, so that the pixel driving circuit P1 writes the black data signal. Under the control of the high-level signal of the first pull-up node Q1, the first black insertion shift circuit 14 makes the second shift signal terminal CLKD2 and the second shift output terminal CR2 conductive. <k>The path between them is connected, and the high-level signal of the second shift signal terminal CLKD2 is written to the second shift output terminal CR2. <k>.

[0081] That is, the black bar insertion input circuit 13, the first output circuit 15, and the first black bar insertion shift circuit 14 constitute a black bar insertion driving module to realize black bar insertion driving. The gate driving circuit may include multiple black bar insertion driving modules, and the previous black bar insertion driving module and the next black bar insertion driving module can be cascaded through the first black bar insertion shift circuit 14.

[0082] The shift register in this embodiment includes a black bead insertion input circuit 13, a first black bead insertion shift circuit 14, a first display input circuit 11, a first display shift circuit 12, and a first output circuit 15. The first output circuit 15 is electrically connected to the pixel driving circuit P1 to control the pixel driving circuit P1 to write screen data signals and black data signals. The black bead insertion input circuit 13, the first output circuit 15, and the first black bead insertion shift circuit 14 constitute a black bead insertion driving module to implement black bead insertion driving, and the first display input circuit 11, the first output circuit 15, and the first display shift circuit 12 constitute a display driving module to implement display driving. The first black bead insertion shift circuit 14 can be used to cascade different black bead insertion driving modules, and the first display shift circuit 12 can be used to cascade different display driving modules, that is, the first black bead insertion shift circuit 14 can be set separately to achieve cascading between different black bead insertion driving modules. Compared with the cascading of black-insertion drive modules by reusing display shift circuits and / or display output circuits in related technologies, the first black-insertion shift circuit 14 in this embodiment of the present disclosure cascades across fewer shift registers and is less difficult to wire.

[0083] The first scanning unit MD1 may include multiple first output circuits 15, each electrically connected to a different gate line GL. This allows the first scanning unit MD1 to simultaneously drive multiple rows of sub-pixels PX, reducing the number of first scanning units MD1. The more first output circuits 15 included in the first scanning unit MD1, the fewer first scanning units MD1 are required, but the more display clock signal lines are needed to be electrically connected to the first output circuits 15. Therefore, the first scanning unit MD1 may include four first output circuits 15, reducing the number of first scanning units MD1 without excessively increasing the number of display clock signal lines.

[0084] For example, the display clock signal lines include a first display clock signal line CE1, a second display clock signal line CE2, a third display clock signal line CE3, and a fourth display clock signal line CE4. The four display clock signal lines are electrically connected to four first output circuits 15, respectively. The first output circuit 15 electrically connected to the first display clock signal line CE1 is electrically connected to the Nth row sub-pixel PX, the first output circuit 15 electrically connected to the second display clock signal line CE2 is electrically connected to the (N+1)th row sub-pixel PX, the first output circuit 15 electrically connected to the third display clock signal line CE3 is electrically connected to the (N+2)th row sub-pixel PX, and the first output circuit 15 electrically connected to the fourth display clock signal line CE4 is electrically connected to the (N+3)th row sub-pixel PX.

[0085] Of course, the number of the first output circuits 15 in the first scanning unit MD1 is not limited in the embodiments disclosed herein; it can be one, two, three, five, etc.

[0086] The shift register may consist only of the first scan unit MD1. In this case, multiple shift registers in the gate drive circuit are cascaded, i.e., multiple first scan units MD1 are cascaded. For example, the multiple shift registers may include cascaded first shift registers and second shift registers, with the first shift output terminal CR of the first shift register... <k>With the first display input terminal CR of the second shift register <k-1>Electrical connection, the second shift output terminal CR2 of the first shift register <k>The first black-insertion input CR2 of the second shift register <k-2>Electrical connection.

[0087] For example, the gate drive circuit includes a first control signal line BC1, a second control signal line BC2, a third control signal line BC3, and a fourth control signal line BC4; it also includes a second black-insertion clock signal line CD2, a third black-insertion clock signal line CD3, a sixth black-insertion clock signal line CD6, and a seventh black-insertion clock signal line CD7; and a first display clock signal line CE1, a second display clock signal line CE2, a third display clock signal line CE3, a fourth display clock signal line CE4, a fifth display clock signal line CE5, a sixth display clock signal line CE6, a seventh display clock signal line CE7, and an eighth display clock signal line CE8. The first control signal line BC1 is electrically connected to the first control terminal BCK1 of the first shift register; the second control signal line BC2 is electrically connected to the second control terminal BCK2 and the second voltage terminal V2 of the first shift register; the third control signal line BC3 is electrically connected to the first control terminal BCK1 of the second shift register; and the fourth control signal line BC4 is electrically connected to the second control terminal BCK2 and the second voltage terminal V2 of the second shift register. The second black clock signal line CD2 is electrically connected to the second shift signal terminal CLKD2 of the first shift register, and the third black clock signal line CD3 is electrically connected to the first shift signal terminal CLKD3 of the first shift register. The seventh black clock signal line CD7 is electrically connected to the first shift signal terminal CLKD3 of the second shift register, and the sixth black clock signal line CD6 is electrically connected to the second shift signal terminal CLKD2 of the second shift register. The four first output circuits 15 of the first shift register are electrically connected to the first display clock signal line CE1, the second display clock signal line CE2, the third display clock signal line CE3, and the fourth display clock signal line CE4, respectively. The four first output circuits 15 of the second shift register are electrically connected to the fifth display clock signal line CE5, the sixth display clock signal line CE6, the seventh display clock signal line CE7, and the eighth display clock signal line CE8, respectively.

[0088] Figure 7 An exemplary circuit diagram of a first scanning unit is shown. For example... Figure 7 As shown, the first scanning unit MD1 may also include a first pull-down circuit 117, a first pull-down control circuit 116, a first noise reduction circuit 118, a first reset circuit 20, a second reset circuit 26, a third reset circuit 22, a fourth reset circuit 23, and a first blanking circuit 24.

[0089] The first pull-down control circuit 116 is electrically connected to the third voltage terminal and the first pull-down node QB1. The first pull-down control circuit 116 is configured to write the signal of the third voltage terminal into the first pull-down node QB1.

[0090] For example, the first pull-down control circuit 116 includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17. The fourteenth transistor M14 and the fifteenth transistor M15 are connected in series, and the control terminals of both the fourteenth transistor M14 and the fifteenth transistor M15 are electrically connected to the second voltage line GVDD2. The second terminal of the fifteenth transistor M15 is electrically connected to the control terminal of the sixteenth transistor M16, and the first terminal of the sixteenth transistor M16 is electrically connected to the second voltage line GVDD2 and the first pull-down node QB1. The control terminal of the seventeenth transistor M17 is electrically connected to the first pull-up node Q1, and the second terminal of the seventeenth transistor M17 is electrically connected to the second terminal of the fifteenth transistor M15. The first terminal of the seventeenth transistor M17 is electrically connected to the first pull-down node QB1.

[0091] The first pull-down circuit 117 is electrically connected to the first pull-up node Q1, the first reset voltage terminal VGL1, and the first pull-down node QB1. The first pull-down circuit 117 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-down node QB1 under the signal control of the first pull-up node Q1.

[0092] For example, the first pull-down circuit 117 includes an eighteenth transistor M18, the control terminal of the eighteenth transistor M18 is electrically connected to the first pull-up node Q1, the first terminal of the eighteenth transistor M18 is electrically connected to the first reset voltage terminal VGL1, and the second terminal of the eighteenth transistor M18 is electrically connected to the first pull-down node QB1.

[0093] The first noise reduction circuit 118 is connected to the first pull-down node QB1, the first pull-up node Q1, the first reset voltage terminal VGL1, and the first shift output terminal CR. <k>and the second shift output terminal CR2 <k>Electrically connected, the first noise reduction circuit 118 is configured to write the signal of the first reset voltage terminal VGL1 to the first pull-up node Q1 and the first shift output terminal CR under the signal control of the first pull-down node QB1. <k>and the second shift output terminal CR2 <k>.

[0094] For example, the first noise reduction circuit 118 includes a nineteenth transistor M19, a twentieth transistor M20, a twenty-second transistor M22, a twenty-fourth transistor M24, a twenty-sixth transistor M26, a twenty-eighth transistor M28, a thirtieth transistor M30, and a thirty-fifth transistor M35. The nineteenth transistor M19 and the twentieth transistor M20 are connected in series, and their control terminals are electrically connected to the first pull-down node QB1. The first terminal of the twentieth transistor M20 is electrically connected to the first reset voltage terminal VGL1, and the second terminal of the nineteenth transistor M19 is electrically connected to the first pull-up node Q1. The control terminals of the twenty-second transistor M22, the twenty-fourth transistor M24, the twenty-sixth transistor M26, the twenty-eighth transistor M28, the twentieth transistor M30, and the thirty-fifth transistor M35 are electrically connected to the first pull-down node QB1. The first terminals of the twenty-second transistor M22 and the thirty-fifth transistor M35 are electrically connected to the first reset voltage terminal VGL1, and the second terminal of the twenty-second transistor M22 is connected to the second shift output terminal CR2. <k>Electrical connection: The second terminal of the thirty-fifth transistor M35 is connected to the first shift output terminal CR. <k>Electrical connections. The second terminals of transistors M24 (twenty-fourth), M26 (twenty-sixth), M28 (twenty-eighth), and M30 (thirtieth) are electrically connected to the first output terminal Gout1, and their first terminals are electrically connected to the second reset voltage terminal VGL2. A constant low-level signal can be applied to the second reset voltage terminal VGL2.

[0095] The first reset circuit 20 is electrically connected to the reset signal terminal TRST, the first pull-up node Q1, and the first reset voltage terminal VGL1. The first reset circuit 20 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-up node Q1 under the signal control of the reset signal terminal TRST.

[0096] For example, the first reset circuit 20 includes a ninth transistor M9 and a tenth transistor M10. The control terminals of the ninth transistor M9 and the tenth transistor M10 are electrically connected to the reset control terminal. The first terminal of the tenth transistor M10 is electrically connected to the first reset voltage terminal VGL1. The second terminal of the ninth transistor M9 is electrically connected to the first pull-up node Q1.

[0097] The second reset circuit 26 is electrically connected to the reset input terminal, the first pull-up node Q1, and the first reset voltage terminal VGL1. The second reset circuit 26 is configured to write the signal from the first reset voltage terminal VGL1 to the first pull-up node Q1 under the signal control of the reset input terminal. The reset input terminal can be connected to the first shift output terminal CR of the next stage scanning unit.<K+1> Electrical connection.

[0098] For example, the second reset circuit 26 includes a twelfth transistor M12 and a thirteenth transistor M13 connected in series, and the control terminals of the twelfth transistor M12 and the thirteenth transistor M13 are electrically connected to the reset input terminal. The second terminal of the twelfth transistor M12 is electrically connected to the first pull-up node Q1, and the first terminal of the thirteenth transistor M13 is electrically connected to the first reset voltage terminal VGL1.

[0099] The third reset circuit 22 is connected to the first pull-down node QB1, the first reset voltage terminal VGL1, and the first display input terminal CR. <k-1>Electrical connection, the third reset circuit 22 is configured to connect at the first display input terminal CR <k-1>Under the signal control, the signal of the first reset voltage terminal VGL1 is written into the first pull-down node QB1.

[0100] For example, the third reset circuit 22 includes a thirty-third transistor M33, the control electrode of which is connected to the first display input terminal CR. <k-1>Electrically connected, the first terminal of the thirty-third transistor M33 is electrically connected to the first reset voltage terminal VGL1, and the second terminal of the thirty-third transistor M33 is electrically connected to the first pull-down node QB1.

[0101] The first blanking circuit 24 is connected to the fifth control terminal OE and the first display input terminal CR. <k-1>The fourth voltage terminal CLKA and the first pull-up node Q1 are electrically connected, and the first blanking circuit 24 is configured to connect the fifth control terminal and the first display input terminal CR. <k-1>Under the signal control, the signal of the fourth voltage terminal CLKA is written into the first pull-up node Q1.

[0102] For example, when the first display input terminal CR <k-1>The signals at the fifth control terminal OE and the fourth voltage terminal CLKA are both high-level signals. The high-level signal at the fourth voltage terminal CLKA is written to the first pull-up node Q1. Under the control of the high-level signal at the first pull-up node Q1, the first output circuit 15 writes the high-level signal at the first signal terminal to the first output terminal Gout1. The first output terminal Gout1 provides a high-level signal to the second gate signal terminal G1 through the gate line GL, thereby resetting node S or driving the sub-pixel PX to display a black screen. In this way, in conjunction with the electrical signals on the sensing signal lines on the display substrate, the effect of eliminating ghosting in the displayed image is achieved.

[0103] For example, the first blanking circuit 24 includes a first capacitor C1, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The first transistor M1 and the second transistor M2 are connected in series, and the control terminals of the first transistor M1 and the second transistor M2 are electrically connected to the fifth control terminal OE. The second terminal of the first transistor M1 is connected to the first display input terminal CR. <k-1>Electrical connections are established: the first terminal of the second transistor M2 is electrically connected to node H; the second terminal of the third transistor M3 is connected between the first transistor M1 and the second transistor M2; the first terminal of the third transistor M3 is connected to the first voltage line; one plate of the first capacitor C1 is electrically connected to node H, and the other plate is electrically connected to the first reset voltage terminal VGL1; the control terminal of the fourth transistor M4 is electrically connected to node H; the second terminal of the fourth transistor M4 is electrically connected to the fourth voltage terminal CLKA; the first terminal of the fourth transistor M4 is electrically connected to node N; the fifth transistor M5 and the sixth transistor M6 are connected in series, and the control terminals of the fifth transistor M5 and the sixth transistor M6 are electrically connected to the fourth voltage terminal CLKA; the second terminal of the fifth transistor M5 is electrically connected to node N; and the first terminal of the sixth transistor M6 is electrically connected to the first pull-up node Q1.

[0104] The fourth reset circuit 23 is electrically connected to the first pull-down node QB1, the first reset voltage terminal VGL1, the fourth voltage terminal CLKA, and node H. The fourth reset circuit 23 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-down node QB1 under the signal control of node H and the fourth voltage terminal CLKA.

[0105] For example, the fourth reset circuit 23 includes a thirty-first transistor M31 and a thirty-second transistor M32. The control electrode of the thirty-first transistor M31 is electrically connected to the fourth voltage terminal CLKA, the control electrode of the thirty-second transistor M32 is electrically connected to node H, the second electrode of the thirty-first transistor M31 is electrically connected to the first pull-down node QB1, and the first electrode of the thirty-second transistor M32 is electrically connected to the first reset voltage terminal VGL1.

[0106] Figure 8 An exemplary block diagram of another shift register is shown. For example... Figure 8 As shown, the shift register may also include a second scanning unit MD2, which includes a second display input circuit 16, a second display shift circuit 17, and a second output circuit 18.

[0107] The second display input circuit 16 and the first shift output terminal CR <k>The first voltage terminal GVDD1 and the second pull-up node Q2 are electrically connected. The second display shift circuit 17 is connected to the second pull-up node Q2, the third shift signal terminal CLKD7, and the third shift output terminal CR.<K+1> Electrically connected, the second output circuit 18 is electrically connected to the second pull-up node Q2, the second signal terminal and the second output terminal Gout2.

[0108] During the display driving phase, the second display input circuit 16 is configured to operate at the first shift output terminal CR. <k>Under the signal control of the second pull-up node Q2, the signal at the first voltage terminal GVDD1 is written to the second pull-up node Q2. The second display shift circuit 17 is configured to write the signal at the third shift signal terminal CLKD7 to the third shift output terminal CR under the signal control of the second pull-up node Q2.<K+1> The second output circuit 18 is configured to write the signal from the second signal terminal to the second output terminal Gout2 under the signal control of the second pull-up node Q2.

[0109] The third shift signal terminal CLKD7 can be electrically connected to a clock signal line. For example, the gate drive circuit includes multiple black-stamped clock signal lines CD, and the third shift signal terminal CLKD7 is electrically connected to the black-stamped clock signal lines CD.

[0110] The third shift output terminal CR<K+1> With the first display input CR of the next stage shift register <k-1>Electrical connection.

[0111] For example, the second display input receives the first shift output CR. <k>When the output high-level signal is received, the path between the first voltage terminal GVDD1 and the second pull-up node Q2 is connected, and the high-level signal of the first voltage terminal GVDD1 is written to the second pull-up node Q2, making the signal of the second pull-up node Q2 a high-level signal. Under the control of the high-level signal of the second pull-up node Q2, the second output circuit 18 connects the path between the second signal terminal and the second output terminal Gout2, and the high-level signal of the second signal terminal is written to the second output terminal Gout2. That is, the second output terminal Gout2 of the shift register provides a high-level signal to the first gate signal terminal G1 and the second gate signal terminal G2 through the gate line GL, causing the pixel driving circuit P1 to write the image data signal. Under the control of the high-level signal of the second pull-up node Q2, the second shift signal terminal CLKD2 and the second shift output terminal CR2 are connected. <k>The path between them is connected, and the high-level signal of the second shift signal terminal CLKD2 is written to the second shift output terminal CR2. <k>.

[0112] The second scanning unit MD2 may further include a second pull-down circuit, a second pull-down control circuit, a second noise reduction circuit, a first reset circuit, a second reset circuit, a third reset circuit, a fourth reset circuit, a fifth reset circuit, and a second blanking circuit. The circuit structures and connections of the second pull-down circuit, second pull-down control circuit, second noise reduction circuit, first reset circuit, second reset circuit, third reset circuit, fourth reset circuit, fifth reset circuit, and second blanking circuit can be referenced from the first scanning unit MD1 and will not be repeated here. That is, the structures of the first scanning unit MD1 and the second scanning unit MD2 can be the same or similar, except for the black-insertion input circuit 13 and the first black-insertion shift circuit 14. The following example illustrates the situation where the structures of the first scanning unit MD1 and the second scanning unit MD2 are the same except for the black-insertion input circuit 13 and the first black-insertion shift circuit 14.

[0113] The black pixel insertion input circuit 13 is also electrically connected to the second pull-up node Q2, and is configured to write signals to the second pull-up node Q2. Black pixel insertion is achieved by controlling the sub-pixels PX electrically connected to the first scanning unit MD1 and the second scanning unit MD2 through the black pixel insertion input circuit 13.

[0114] Figure 9 An exemplary block diagram of another shift register is shown. For example... Figure 9 As shown, the black pixel insertion input circuit 13 may include a first black pixel insertion input circuit 13a and a second black pixel insertion input circuit 13b. The first black pixel insertion input circuit 13a is electrically connected to a first pull-up node Q1 and is configured to write a signal to the first node. The second black pixel insertion input circuit 13b is electrically connected to a second pull-up node Q2 and is configured to write a signal to the second pull-up node Q2. That is, black pixel insertion is achieved by driving the sub-pixel PX electrically connected to the first scanning unit MD1 through the first black pixel insertion input circuit 13a, and black pixel insertion is achieved by driving the sub-pixel PX electrically connected to the second scanning unit MD2 through the second black pixel insertion input circuit 13b.

[0115] At the same time, the signal written by the first black bar input circuit 13a at the first pull-up node Q1 and the signal written by the second black bar input circuit 13b at the second pull-up node Q2 can be the same. Here, "signals are the same" means that the signal written by the first black bar input circuit 13a at the first pull-up node Q1 can drive the first output circuit 15 to conduct the first signal terminal and the first output terminal Gout1, and the signal written by the second black bar input circuit 13b at the second pull-up node Q2 can drive the second output circuit 18 to conduct the second signal terminal and the second output terminal Gout2, not necessarily that the two signals have strictly identical level values.

[0116] When the signal written by the first black pixel insertion input circuit 13a to the first pull-up node Q1 and the signal written by the second black pixel insertion input circuit 13b to the second pull-up node Q2 are the same, the sub-pixel PX electrically connected to the first black pixel insertion input circuit 13a and the sub-pixel PX electrically connected to the second black pixel insertion input circuit 13b can be driven to simultaneously perform black pixel insertion, thereby reducing the black pixel insertion time.

[0117] Figure 10 An exemplary circuit diagram of a shift register is shown. For example... Figure 9 and 10 As shown: The first black plug input circuit 13a can be connected to the first black plug input terminal CR2. <k-2>The first control terminal BCK1, the second control terminal BCK2, the second voltage terminal V2, and the first pull-up node Q1 are electrically connected. The first black insert input circuit 13a is configured to connect at the first black insert input terminal CR2. <k-2>Under the signal control of the first control terminal BCK1 and the second control terminal BCK2, the signal of the second voltage terminal V2 is written into the first pull-up node Q1.

[0118] The second black plug input circuit 13b can also be connected to the first black plug input terminal CR2. <k-2>The first control terminal BCK1, the second control terminal BCK2, the second voltage terminal V2, and the second pull-up node Q2 are electrically connected. The second black insert input circuit 13b is configured to connect to the first black insert input terminal CR2. <k-2>Under the signal control of the first control terminal BCK1 and the second control terminal BCK2, the signal of the second voltage terminal V2 is written into the second pull-up node Q2.

[0119] Since both the first black bar input circuit 13a and the second black bar input circuit 13b are electrically connected to the first black bar input terminal, the first control terminal BCK1, the second control terminal BCK2, and the second voltage terminal V2, the signal written by the first black bar input circuit 13a at the first pull-up node Q1 is the same as the signal that the second black bar input circuit 13b can write at the second pull-up node Q2, and the number of signal lines electrically connected to the black bar input circuit 13 is reduced.

[0120] Figure 11 An exemplary circuit diagram of a first black-plug input circuit is shown. For example... Figure 11 As shown, the first black input circuit 13a includes a first sub-circuit 1 and a second sub-circuit 2.

[0121] First sub-circuit 1 and first black plug input terminal CR2 <k-2>The first control terminal BCK1, the second voltage terminal V2, and the first node are electrically connected. The first sub-circuit 1 is configured to connect to the first black plug input terminal CR2. <k-2>Under the signal control of the first control terminal BCK1, the signal of the second voltage terminal V2 is written into the first node P.

[0122] The second sub-circuit 2 is electrically connected to the second control terminal BCK2, the first node P, and the first pull-up node Q1. The second sub-circuit 2 is configured to write the signal of the first node P into the first pull-up node Q1 under the signal control of the second control terminal BCK2.

[0123] For example, the first sub-circuit 1 includes a thirty-sixth transistor M36, a thirty-seventh transistor M37, a thirty-eighth transistor M38, an eighth capacitor C8, and a thirty-ninth transistor M39. The thirty-sixth transistor M36 and the thirty-seventh transistor M37 are connected in series, and their gates are electrically connected to the first control terminal BCK1. The second terminal of the thirty-sixth transistor M36 is connected to the first black pin input terminal CR2. <k-2>Electrical connections are established: the first terminal of transistor M37 is electrically connected to the second node M. The second terminal of transistor M38 is connected between transistors M36 and M37, and the first terminal of transistor M38 is electrically connected to the first voltage line GVDD1. One plate of transistor M8 is electrically connected to node M, and the second plate is electrically connected to the first reset voltage terminal VGL1. The second terminal of transistor M39 is electrically connected to the second control terminal BCK2, the control terminal of transistor M39 is electrically connected to node M, and the first terminal of transistor M39 is electrically connected to the first node P.

[0124] For example, the second sub-circuit 2 includes a fortieth transistor M40 and a forty-first transistor M41, which are connected in series. The control terminals of the fortieth transistor M40 and the forty-first transistor M41 are electrically connected to the second control terminal BCK2. The first terminal of the forty-first transistor M41 is electrically connected to the first pull-up node Q1, and the second terminal of the fortieth transistor M40 is electrically connected to the first node P.

[0125] Of course, the second sub-circuit 2 may also include only the 40th transistor M40, the control terminal of the 40th transistor M40 is electrically connected to the second control terminal BCK2, the first terminal of the 40th transistor M40 is electrically connected to the first pull-up node Q1, and the second terminal of the 40th transistor M40 is electrically connected to the first node P.

[0126] Figure 12 An exemplary circuit diagram of a second black-plug input circuit is shown. For example... Figure 12 As shown, the second black bar input circuit 13b is electrically connected to the first node, the second control terminal BCK2, and the second pull-up node Q2. The second black bar input circuit 13b is configured to write the signal of the first node into the second pull-up node Q2 under the signal control of the second control terminal BCK2.

[0127] For example, the second black input circuit 13b includes a 40th transistor M40 and a 41st transistor M41, which are connected in series, and the control terminals of the 40th transistor M40 and the 41st transistor M41 are connected to the second control terminal BCK2.

[0128] Figure 13 An exemplary circuit diagram of a shift register is shown. For example... Figure 12 and 13 As shown, the second black bar input circuit 13b takes the signal of the first node P in the first black bar input circuit 13a as the input signal, which is equivalent to the second scanning unit MD2 sharing the first sub-circuit 1 in the first scanning unit MD1, thus reducing the circuit complexity of the shift register.

[0129] Alternatively, the second black input circuit 13b can include a first sub-circuit 1 and a second sub-circuit 2. In this case, it is equivalent to the first scanning unit MD1 sharing the first sub-circuit 1 in the second scanning unit MD2.

[0130] For example, the first sub-circuit 1 and the first black plug input terminal CR2 <k-2>The first control terminal BCK1, the second voltage terminal V2, and the second node are electrically connected. The first sub-circuit 1 is configured to connect to the first black plug input terminal CR2. <k-2>Under the signal control of the first control terminal BCK1, the signal of the second voltage terminal V2 is written to the second node. The second sub-circuit 2 is electrically connected to the second control terminal BCK2, the second node, and the second pull-up node Q2. The second sub-circuit 2 is configured to write the signal of the second node to the second pull-up node Q2 under the signal control of the second control terminal BCK2. The first black input circuit 13a is electrically connected to the second node, the second control terminal BCK2, and the first pull-up node Q1. The second black input circuit 13b is configured to write the signal of the second node to the first pull-up node Q1 under the signal control of the second control terminal BCK2.

[0131] Furthermore, when the first scanning unit MD1 includes the first blanking circuit 24, the second scanning unit MD2 may also include a second blanking circuit, and the second blanking circuit may share some of the structure of the first blanking circuit 24. For example... Figure 13 As shown, the second blanking circuit is electrically connected to node N, the fourth voltage terminal CLKA, and the second pull-up node Q2. The second blanking circuit is configured to write the signal of node N into the second pull-up node Q2 under the signal control of the fourth voltage terminal CLKA.

[0132] Figure 14 An exemplary circuit diagram of a first black-plug input circuit is shown. For example... Figure 14 As shown, the first sub-circuit 1 may include a third sub-circuit 1a and a fourth sub-circuit 1b.

[0133] The third sub-circuit 1a and the first black plug input terminal CR2 <k-2>The first control terminal BCK1 and the second node M are electrically connected. The third sub-circuit 1a is configured to, under the signal control of the first control terminal BCK1, connect the first black plug input terminal CR2. <k-2>The signal is written to the second node.

[0134] The fourth sub-circuit 1b is electrically connected to the second node, the second voltage terminal V2, the second control terminal BCK2, and the first pull-up node Q1. The fourth sub-circuit 1b is configured to write the signal of the second voltage terminal V2 into the first pull-up node Q1 under the signal control of the second node and the second control terminal BCK2.

[0135] Continue to refer to Figure 7 The first scanning unit MD1 may also include a first black-pin reset circuit 19. The first black-pin reset circuit 19 is electrically connected to the first pull-up node Q1, node M, black-pin reset control terminal BTRST and the first reset voltage terminal VGL1. The first black-pin reset circuit 19 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-up node Q1 under the signal control of node M and black-pin reset control terminal BTRST.

[0136] For example, the first black-insertion reset circuit 19 includes a forty-fourth transistor M44, a forty-fifth transistor M45, and a forty-sixth transistor M46, which are connected in series. The control electrode of the forty-fourth transistor M44 is electrically connected to node M, and the control electrodes of the forty-fifth transistor M45 and the forty-sixth transistor M46 are electrically connected to the black-insertion reset control terminal BTRST.

[0137] The first scanning unit MD1 may also include a fifth reset circuit 21. The fifth reset circuit 21 is electrically connected to the second control terminal BCK2, node M, the first pull-down node QB1 and the first reset voltage terminal VGL1. The fifth reset circuit 21 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-down node QB1 under the signal control of the second control terminal BCK2 and node M.

[0138] For example, the fifth reset circuit 21 includes a forty-second transistor M42 and a forty-third transistor M43 connected in series. The gate of the forty-second transistor M42 is electrically connected to the second control terminal BCK2, and the gate of the forty-third transistor M43 is electrically connected to node M.

[0139] The first scanning unit MD1 may also include a leakage protection circuit 25. The leakage protection circuit is electrically connected to the first voltage terminal GVDD1, the first pull-up node Q1, the first black bar input circuit 13A, the first blanking circuit 24, the first black bar reset circuit 19, the first reset circuit 20, and the first noise reduction circuit 118. The leakage protection circuit is configured to write the signal of the first voltage terminal GVDD1 into the first black bar input circuit 13A, the first blanking circuit 24, the first black bar reset circuit 19, the first reset circuit 20, and the first noise reduction circuit 118 under the signal control of the first pull-up node Q1.

[0140] For example, the leakage protection circuit 25 includes an eleventh transistor M11, the control terminal of the eleventh transistor is electrically connected to the first pull-up node Q1, and the first terminal of the eleventh transistor is connected between the thirty-sixth transistor M36 and the thirty-seventh transistor M37, between the fifth transistor M5 and the sixth transistor M6, between the ninth transistor M9 and the tenth transistor M10, between the forty-fifth transistor M45 and the forty-sixth transistor M46, between the twelfth transistor M12 and the thirteenth transistor M13, and between the nineteenth transistor M19 and the twentieth transistor M20.

[0141] The gate drive circuit may include multiple first shift registers and multiple second shift registers, which are arranged alternately and cascaded. The connection relationship of each shift register is illustrated below using the connection relationship of the cascaded first and second shift registers as an example.

[0142] Figure 15 A block diagram of a gate drive circuit is shown as an example. Figure 15 In this diagram, A represents the first shift register, and B represents the second shift register. A<1-8> refers to the first shift register electrically connected to sub-pixels PX in rows 1 to 8, and B<9-16> refers to the second shift register electrically connected to sub-pixels PX in rows 9 to 16, and so on. The first and second output terminals of both the first shift register A and the second shift register B are represented by G1. CD1-CD8 refer to the black clock signal lines numbered CD1 to CD8, including, for example, the second black clock signal line CD2, the third black clock signal line CD3, the sixth black clock signal line CD6, the seventh black clock signal line CD7, and so on. Further explanation of other labels is omitted here.

[0143] For example, such as Figure 15 As shown, the gate drive circuit includes a first control signal line BC1, a second control signal line BC2, a third control signal line BC3, and a fourth control signal line BC4. It also includes a second black-insertion clock signal line CD2, a third black-insertion clock signal line CD3, a sixth black-insertion clock signal line CD6, a seventh black-insertion clock signal line CD7, a tenth black-insertion clock signal line CD10, an eleventh black-insertion clock signal line CD11, and a fifteenth black-insertion clock signal line CD15. Furthermore, it includes a first display clock signal line CE1, a second display clock signal line CE2, a third display clock signal line CE3, a fourth display clock signal line CE4, a fifth display clock signal line CE5, a sixth display clock signal line CE6, a seventh display clock signal line CE7, an eighth display clock signal line CE8, a ninth display clock signal line CE9, a tenth display clock signal line CE10, an eleventh display clock signal line CE11, a twelfth display clock signal line CE12, a thirteenth display clock signal line CE13, a fourteenth display clock signal line CE14, a fifteenth display clock signal line CE15, and a sixteenth display clock signal line CE16. The first control signal line BC1 is electrically connected to the first control terminal BCK1 of the first shift register. The second control signal line BC2 is electrically connected to the second control terminal BCK2 and the second voltage terminal V2 of the first shift register. The third control signal line BC3 is electrically connected to the first control terminal BCK1 of the second shift register. The fourth control signal line BC4 is electrically connected to the second control terminal BCK2 and the second voltage terminal V2 of the second shift register. The second black-insertion clock signal line CD2 is electrically connected to the second shift signal terminal CLKD2 of the first shift register. The third black-insertion clock signal line CD3 is electrically connected to the first shift signal terminal CLKD3 of the first shift register. The seventh black-insertion clock signal line CD7 is electrically connected to the third shift signal terminal CLKD7 of the first shift register. The tenth black clock signal line CD10 is electrically connected to the second shift signal terminal CLKD2 of the second shift register. The eleventh black clock signal line CD11 is electrically connected to the first shift signal terminal CLKD3 of the second shift register. The fifteenth black clock signal line CD15 is electrically connected to the third shift signal terminal CLKD7 of the second shift register. The four first output circuits 15 of the first shift register are electrically connected to the first display clock signal line CE1, the second display clock signal line CE2, the third display clock signal line CE3, and the fourth display clock signal line CE4, respectively. The four first output circuits 15 of the second shift register are electrically connected to the fifth display clock signal line CE5, the sixth display clock signal line CE6, the seventh display clock signal line CE7, and the eighth display clock signal line CE8, respectively.

[0144] Figure 16 An exemplary timing diagram of a gate drive circuit is shown. For example... Figure 16 As shown, the black insertion driving stage of the gate driving circuit includes the first stage T1, the second stage T2, the third stage T3, and the fourth stage T4.

[0145] In the first stage T1, BSTV (first black input terminal CR2) <k-2>Both the first control terminal BCK1 and the black input circuit 13 are high-level signals, and the black input circuit 13 writes a high-level signal at node M.

[0146] In the second stage T2, the second control terminal BCK2 is a high-level signal. Under the signal control of node M, the black-insertion input circuit 13 writes the high-level signal of the second voltage terminal V2 (second control terminal BCK2) into the first pull-up node Q1 and the second pull-up node Q2.

[0147] In the third stage T3, the first output circuit 15 is turned on under the control of the high-level signal of the first pull-up node Q1, and the second output circuit 18 is turned on under the control of the high-level signal of the second pull-up node Q2. All the first signal terminals (CLKE1, CLKE2, CLKE3, CLKE4, CLKE5, CLKE6, CLKE7, CLKE8) are high-level signals, so that both the first output terminal and the second output terminal output high-level signals, controlling the pixel driving circuit P1 to write black data signals.

[0148] In the fourth stage T4, the first black plug reset control terminal BTRST is a high-level signal. The first black plug reset circuit 19 is turned on under the control of the high-level signal of the first black plug reset control terminal BTRST, so that the signal of the first reset voltage terminal VGL1 is written into the first pull-up node Q1 and the second pull-up node Q2, thus completing the reset of the first pull-up node Q1 and the second pull-up node Q2.

[0149] Figure 17 An exemplary circuit diagram of a shift register is shown. For example... Figure 17 As shown, the first black insert input circuit 13a and the first black insert input terminal CR2 <k-2>The first control terminal BCK1, the second control terminal BCK2, the second voltage terminal V2, and the first pull-up node Q1 are electrically connected. The first black insert input circuit 13a is configured to connect at the first black insert input terminal CR2. <k-2>Under the signal control of the first control terminal BCK1 and the second control terminal BCK2, the signal of the second voltage terminal V2 is written into the first pull-up node Q1.

[0150] The second black bar input circuit 13b is electrically connected to the second black bar input terminal, the first control terminal BCK1, the second control terminal BCK2, the second voltage terminal V2, and the second pull-up node Q2. The second black bar input circuit 13b is configured to write the signal of the second voltage terminal V2 into the second pull-up node Q2 under the signal control of the second black bar input terminal, the first control terminal BCK1, and the second control terminal BCK2.

[0151] The second scanning unit MD2 also includes a second black-insertion shift circuit, which is electrically connected to the second pull-up node Q2, the fourth shift signal terminal, and the fourth shift output terminal. The second black-insertion shift circuit is configured to write the signal of the fourth shift signal terminal to the fourth shift output terminal under the signal control of the second pull-up node Q2.

[0152] The gate drive circuit may include multiple first shift registers and multiple second shift registers, which are arranged alternately and cascaded. The connection relationship of each shift register is illustrated below using the connection relationship of the cascaded first and second shift registers as an example.

[0153] The second shift output terminal CR2 of the first shift register <k>The first black-insertion input CR2 of the second shift register <k-2>Electrically connected, the fourth shift output of the first shift register is electrically connected to the second black insertion input of the second shift register. This reduces the number of scan units cascaded when the black insertion driver modules are connected, simplifying the wiring.

[0154] Figure 18 An exemplary circuit diagram of another shift register is shown. For example... Figure 18 As shown, the first display input circuit 11 may include a seventh transistor M7, an eighth transistor M8, a forty-seventh transistor M47, and a forty-eighth transistor M48. The seventh transistor M7 and the eighth transistor M8 are connected in series, and the control terminals of the seventh transistor M7 and the eighth transistor M8 are connected to the first display input terminal CR. <k-1>Electrically connected, the second terminal of the seventh transistor M7 is electrically connected to the first voltage terminal GVDD1, and the first terminal of the eighth transistor M8 is electrically connected to the first pull-up node Q1. The forty-seventh transistor M47 and the forty-eighth transistor M48 are connected in series, and the control terminals of the forty-seventh transistor M47 and the forty-eighth transistor M48, as well as the second terminal of the forty-seventh transistor, are electrically connected to the voltage line GVDD3. A constant high-level signal is supplied to GVDD3, and the first terminal of the forty-eighth transistor M48 is connected between the seventh transistor M7 and the eighth transistor M8.

[0155] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims. < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. A shift register, characterized in that, The first scanning unit includes a first display input circuit, a first display shift circuit, a black dot input circuit, a first black dot shift circuit, and a first output circuit. The first display input circuit is electrically connected to the first display input terminal, the first voltage terminal, and the first pull-up node. The first display input circuit is configured to write the signal of the first voltage terminal to the first pull-up node under the signal control of the first display input terminal. The first display shift circuit is electrically connected to the first pull-up node, the first shift signal terminal, and the first shift output terminal. The first display shift circuit is configured to write the signal of the first shift signal terminal to the first shift output terminal under the signal control of the first pull-up node. The black bar input circuit is electrically connected to the first black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the first pull-up node. The black bar input circuit is configured to write the signal of the second voltage terminal to the first pull-up node under the signal control of the first black bar input terminal, the first control terminal, and the second control terminal. The first black-insertion shift circuit is electrically connected to the first pull-up node, the second shift signal terminal, and the second shift output terminal. The first black-insertion shift circuit is configured to write the signal of the second shift signal terminal to the second shift output terminal under the signal control of the first pull-up node. The first output circuit is electrically connected to the first pull-up node, the first signal terminal, and the first output terminal. The first output circuit is configured to write the signal from the first signal terminal to the first output terminal under the signal control of the first pull-up node. A constant-level signal is supplied to the first voltage terminal.

2. The shift register according to claim 1, wherein, The shift register further includes a second scanning unit, which includes a second display input circuit, a second display shift circuit, and a second output circuit. The second display input circuit is electrically connected to the first shift output terminal, the first voltage terminal, and the second pull-up node. The second display input circuit is configured to write the signal of the first voltage terminal to the second pull-up node under the signal control of the first shift output terminal. The second display shift circuit is electrically connected to the second pull-up node, the third shift signal terminal, and the third shift output terminal. The second display shift circuit is configured to write the signal of the third shift signal terminal to the third shift output terminal under the signal control of the second pull-up node. The second output circuit is electrically connected to the second pull-up node, the second signal terminal, and the second output terminal. The second output circuit is configured to write the signal from the second signal terminal to the second output terminal under the signal control of the second pull-up node. The black bar input circuit is electrically connected to both the first pull-up node and the second pull-up node, and the black bar input circuit is also configured to write a signal to the second pull-up node.

3. The shift register according to claim 2, wherein, The black bar input circuit includes a first black bar input circuit and a second black bar input circuit; the first black bar input circuit is electrically connected to the first pull-up node and is configured to write a signal to the first pull-up node; the second black bar input circuit is electrically connected to the second pull-up node and is configured to write a signal to the second pull-up node.

4. The shift register according to claim 3, wherein, At the same time, the signal written by the first black bar input circuit at the first pull-up node is the same as the signal written by the second black bar input circuit at the second pull-up node.

5. The shift register according to claim 4, wherein, The first black bar input circuit is electrically connected to the first black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the first pull-up node. The first black bar input circuit is configured to write the signal of the second voltage terminal to the first pull-up node under the signal control of the first black bar input terminal, the first control terminal, and the second control terminal. The second black bar input circuit is electrically connected to the first black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the second pull-up node. The second black bar input circuit is configured to write the signal of the second voltage terminal to the second pull-up node under the signal control of the first black bar input terminal, the first control terminal, and the second control terminal.

6. The shift register according to claim 4, wherein, The first black-insertion input circuit includes a first sub-circuit and a second sub-circuit; The first sub-circuit is electrically connected to the first black bar input terminal, the first control terminal, the second voltage terminal, and the first node. The first sub-circuit is configured to write the signal of the second voltage terminal to the first node under the signal control of the first black bar input terminal and the first control terminal. The second sub-circuit is electrically connected to the second control terminal, the first node and the first pull-up node. The second sub-circuit is configured to write the signal of the first node into the first pull-up node under the signal control of the second control terminal. The second black bar input circuit is electrically connected to the first node, the second control terminal, and the second pull-up node. The second black bar input circuit is configured to write the signal of the first node into the second pull-up node under the signal control of the second control terminal.

7. The shift register according to claim 4, wherein, The second black-insertion input circuit includes a first sub-circuit and a second sub-circuit; The first sub-circuit is electrically connected to the first black bar input terminal, the first control terminal, the second voltage terminal, and the second node. The first sub-circuit is configured to write the signal of the second voltage terminal to the second node under the signal control of the first black bar input terminal and the first control terminal. The second sub-circuit is electrically connected to the second control terminal, the second node and the second pull-up node. The second sub-circuit is configured to write the signal of the second node into the second pull-up node under the signal control of the second control terminal. The first black bar input circuit is electrically connected to the second node, the second control terminal, and the first pull-up node. The second black bar input circuit is configured to write the signal of the second node into the first pull-up node under the signal control of the second control terminal.

8. The shift register according to claim 3, wherein, The first black bar input circuit is electrically connected to the first black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the first pull-up node. The first black bar input circuit is configured to write the signal of the second voltage terminal to the first pull-up node under the signal control of the first black bar input terminal, the first control terminal, and the second control terminal. The second black bar input circuit is electrically connected to the second black bar input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the second pull-up node. The second black bar input circuit is configured to write the signal of the second voltage terminal to the second pull-up node under the signal control of the second black bar input terminal, the first control terminal, and the second control terminal. The second scanning unit further includes a second black-insertion shift circuit, which is electrically connected to the second pull-up node, the fourth shift signal terminal, and the fourth shift output terminal. The second black-insertion shift circuit is configured to write the signal of the fourth shift signal terminal to the fourth shift output terminal under the signal control of the second pull-up node.

9. The shift register according to claim 4, wherein, The second voltage terminal and the second control terminal are electrically connected, or the second voltage terminal and the second control terminal are disconnected.

10. The shift register according to claim 6, wherein, The first sub-circuit includes a third sub-circuit and a fourth sub-circuit; The third sub-circuit is electrically connected to the first black bar input terminal, the first control terminal, and the second node. The third sub-circuit is configured to write the signal of the first black bar input terminal to the second node under the signal control of the first control terminal. The fourth sub-circuit is electrically connected to the second node, the second voltage terminal, and the first node. The fourth sub-circuit is configured to write the signal of the second voltage terminal to the first pull-up node through the second sub-circuit under the signal control of the second node.

11. The shift register according to claim 10, wherein, The first scanning unit further includes a first black-pin reset circuit, which is electrically connected to the first pull-up node, the second node, the black-pin reset control terminal, and the first reset voltage terminal. The first black-pin reset circuit is configured to write the signal of the first reset voltage terminal to the pull-up node under the signal control of the second node and the black-pin reset control terminal.

12. The shift register according to claim 11, wherein, The first scanning unit further includes a first pull-down circuit and a first noise reduction circuit; The first pull-down circuit is electrically connected to the first pull-up node, the first reset voltage terminal, and the first pull-down node. The first pull-down circuit is configured to write the signal of the first reset voltage terminal into the first pull-down node under the signal control of the first pull-up node. The first noise reduction circuit is electrically connected to the first pull-down node, the first reset voltage terminal, and the second shift output terminal. The first noise reduction circuit is configured to write the signal of the first reset voltage terminal to the second shift output terminal under the signal control of the first pull-down node.

13. The shift register according to claim 12, wherein, The shift register further includes a fifth reset circuit, which is electrically connected to the second control terminal, the second node, the first reset voltage terminal, and the first pull-down node. The fifth reset circuit is configured to write the signal of the first reset voltage terminal into the first pull-down node under the signal control of the second node and the second control terminal.

14. A gate driving circuit, characterized in that, It includes a plurality of shift registers as described in any one of claims 1 to 13, wherein the plurality of shift registers are cascaded.

15. The gate drive circuit according to claim 14, wherein, The plurality of shift registers include a cascaded first shift register and a second shift register. Each shift register includes a first display shift circuit, a second display shift circuit, and a first black-insertion shift circuit. The second shift output terminal of the first shift register is electrically connected to the first black-insertion input terminal of the second shift register, and the third shift output terminal of the first shift register is electrically connected to the first display input terminal of the second shift register.

16. The gate drive circuit according to claim 14, wherein, The multiple shift registers include a cascaded first shift register and a second shift register. When the shift registers include a first display shift circuit, a second display shift circuit, a first black bead insertion shift circuit, and a second black bead insertion shift circuit, the third shift output terminal of the first shift register is electrically connected to the first display input terminal of the second shift register, the second shift output terminal of the first shift register is electrically connected to the first black bead insertion input terminal of the second shift register, and the fourth shift output terminal of the first shift register is electrically connected to the second black bead insertion input terminal of the second shift register.

17. The gate drive circuit according to any one of claims 14 to 16, wherein, The gate driving circuit includes multiple gate lines, the first scanning unit includes multiple first output circuits, and the first output terminals of the multiple first output circuits are electrically connected to different gate lines respectively; and / or, the second scanning unit includes multiple second output circuits, and the second output terminals of the multiple second output circuits are electrically connected to different gate lines respectively, and the first output terminal and the second output terminal are electrically connected to different gate lines.

18. The gate drive circuit according to claim 17, wherein, The first scanning unit includes four first output circuits, and the second scanning unit includes four second output circuits.

19. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 14 to 18.

20. A display device, characterized in that, Includes the display panel as described in claim 19.

Images