Light emitting diode epitaxial wafer and preparation method thereof, and light emitting diode

Abstract

The application discloses a light emitting diode epitaxial wafer and a preparation method thereof and a light emitting diode. The light emitting diode epitaxial wafer comprises a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a V-shaped pit layer, a multi-quantum well layer, an insertion layer, an electron blocking layer and a P-type GaN layer which are sequentially stacked on the substrate; and the insertion layer comprises an AlN layer, an Al layer and a WS2 layer which are sequentially stacked. The application can increase the light emitting efficiency and the anti-static capability of the light emitting diode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a light-emitting diode epitaxial wafer and its fabrication method, and a light-emitting diode. Background Technology

[0002] Currently, GaN-based light-emitting diodes (LEDs) have achieved industrial-scale production and are widely used in solid-state lighting and display fields. Due to lattice and thermal mismatches between GaN and the substrate, GaN-based LEDs exhibit a high density of penetrating dislocations, inducing V-shaped pits. The V-shaped pit sidewalls extend throughout the active region in a V-shape. Because of their unique geometry, holes can easily be injected into deeper quantum wells through these sidewalls, thereby reducing operating voltage and improving the non-uniform distribution of electrons and holes, thus increasing luminous efficiency. However, V-shaped pits also present certain problems: First, since they are generated along the line dislocations in the underlying layer, they are themselves natural leakage channels, affecting the LED's anti-static capability. Furthermore, the growth process of V-shaped pits easily introduces many defects, which become non-radiative recombination centers that trap charge carriers, affecting internal quantum efficiency and thus impacting luminous efficiency. Additionally, current V-shaped pit filling is performed in the electron blocking layer structure, meaning that defects in the V-shaped pits can consume holes passing through the electron blocking layer, affecting hole injection. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a light-emitting diode epitaxial wafer that improves the luminous efficiency and antistatic capability of the light-emitting diode epitaxial wafer.

[0004] The technical problem to be solved by the present invention is to provide a method for preparing an epitaxial wafer of a light-emitting diode, which is simple in process and produces an epitaxial wafer with stable performance.

[0005] To achieve the above-mentioned technical effects, the present invention provides a light-emitting diode epitaxial wafer, comprising a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a V-shaped pit layer, a multiple quantum well layer, an insertion layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate;

[0006] The insertion layer comprises an AlN layer, an Al layer, and a WS2 layer stacked sequentially.

[0007] As an improvement to the above technical solution, the thickness of the AlN layer is 5-20 nm; the thickness of the Al layer is 1-10 nm; and the thickness of the WS2 layer is 5-20 nm.

[0008] As an improvement to the above technical solution, the growth temperature of the Al layer is less than the growth temperature of the AlN layer.

[0009] As an improvement to the above technical solution, the V-shaped pit layer includes periodically stacked InGaN and GaN layers with a period number of 3-10, the thickness of the InGaN layer is 1-5nm, and the thickness of the GaN layer is 3-20nm.

[0010] Accordingly, the present invention also discloses a method for preparing a light-emitting diode epitaxial wafer, which includes the following steps:

[0011] A substrate is provided on which a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a V-shaped pit layer, a multiple quantum well layer, an insertion layer, an electron blocking layer and a P-type GaN layer are sequentially grown.

[0012] The insertion layer comprises an AlN layer, an Al layer, and a WS2 layer stacked sequentially.

[0013] As an improvement to the above technical solution, the AlN layer is grown by MOCVD, the growth temperature of the AlN layer is 950-1000℃, the growth pressure is 50-100 Torr, and the carrier gas is a mixture of N2 and H2.

[0014] As an improvement to the above technical solution, the Al layer is grown by MOCVD, the growth temperature of the Al layer is 800-900℃, the growth pressure is 100-300 Torr, and the carrier gas is a mixture of N2 and H2.

[0015] As an improvement to the above technical solution, the WS2 layer is grown by CVD, the growth temperature of the WS2 layer is 700-1000℃, sodium thiosulfate and tungsten disulfide are used as precursors, the molar ratio of sodium thiosulfate and tungsten disulfide is 1:(1-3), and the carrier gas is a mixture of Ar and H2.

[0016] As an improvement to the above technical solution, the V-shaped pit layer includes periodically stacked InGaN and GaN layers. The V-shaped pit layer is grown by MOCVD. The growth temperature of the V-shaped pit layer is 800-900℃, the growth pressure is 100-500 Torr, and the carrier gas is N2.

[0017] Accordingly, the present invention also discloses a light-emitting diode, including the above-mentioned light-emitting diode epitaxial wafer.

[0018] Implementing the embodiments of the present invention has the following beneficial effects:

[0019] This invention incorporates an insertion layer between a multi-quantum well layer and an electron blocking layer. This insertion layer comprises an AlN layer, an Al layer, and a WS2 layer. The AlN layer forms a dense V-shaped pit blocking layer and can create V-shaped nanopores within the multi-quantum well layer. These V-shaped nanopores reduce total internal reflection within the multi-quantum well layer, increasing light extraction efficiency. Simultaneously, the V-shaped nanopores allow for better stress release within the multi-quantum well layer, reducing piezoelectric polarization and thus increasing the overlap of electron and hole wave functions, thereby enhancing luminous efficiency. Furthermore, the high density of the AlN layer causes defects generated during V-shaped pit growth to be distorted and annihilated within this layer, reducing the consumption of holes by defects before they enter the multi-quantum well layer. The wide bandgap of AlN material partially blocks electrons, significantly enhancing the luminous efficiency of the light-emitting diode and increasing its antistatic capability.

[0020] Al layers have very high light reflectivity. Placing them in the region where the active region of the multi-quantum well layer has just been grown can greatly increase diffuse reflection of light, thereby reducing light consumption inside the LED in traditional structures.

[0021] The carrier mobility in the WS2 layer is very high, so the WS2 layer can act as a buffer layer to increase the number of holes entering the multiple quantum wells and increase the hole expansion capability. Each atom in the WS2 layer has covalent bonds on its plane, and adjacent layers are coupled by weak van der Waals forces. Therefore, there is no need to consider lattice mismatch constraints, which can provide sufficient lattice orientation guidance for the subsequent epitaxial layers, increase the lattice matching with the subsequent electron blocking layers, and at the same time reduce the hole consumption of the subsequent electron blocking layers and P-type semiconductor layers. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of the light-emitting diode epitaxial wafer provided in an embodiment of the present invention;

[0023] Figure 2 This is a flowchart of the method for fabricating a light-emitting diode epitaxial wafer provided in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments.

[0025] like Figure 1 As shown, an embodiment of the present invention provides a light-emitting diode epitaxial wafer, including a substrate 1 and a nucleation layer 2, an intrinsic GaN layer 3, an N-type GaN layer 4, a V-shaped pit layer 5, a multiple quantum well layer 6, an insertion layer 7, an electron blocking layer 8, and a P-type GaN layer 9 sequentially stacked on the substrate 1; the insertion layer 7 includes an AlN layer, an Al layer, and a WS2 layer sequentially stacked.

[0026] An AlN layer is grown on the multi-quantum-well layer 6 to form a dense V-shaped pit blocking layer. Traditionally, the V-shaped pits are gradually filled during electron blocking layer growth, leaving no nanopores. However, the high density and smoothness of the two-dimensionally grown AlN layer ensures that the V-shaped pits are not filled but remain within the multi-quantum-well layer, forming V-shaped nanopores. The retention of these nanopores has the following effects: it reduces total internal reflection within the multi-quantum-well layer, increasing light extraction efficiency, especially significantly increasing lateral light emission; it allows for better stress release in the multi-quantum-well layer, reducing piezoelectric polarization and thus increasing the overlap of electron and hole wave functions, thereby increasing luminous efficiency. Furthermore, the high density of the AlN layer causes defects generated during V-shaped pit growth to be distorted and annihilated within this layer, reducing the consumption of holes by defects; the wide bandgap of AlN material acts as a partial electron blocking layer, significantly enhancing the luminous efficiency and antistatic capability of the LED.

[0027] The Al layer is located between the AlN layer and the WS2 layer. As a metal reflective layer, the Al layer has a very high light reflectivity. Placing it in the region where the active region of the multi-quantum well layer has just been grown can greatly increase the diffuse reflection of light and reduce the light consumption inside the LED in the traditional structure.

[0028] WS2 can serve as a buffer layer. Carrier mobility is high within the WS2 layer, thus increasing the number of holes entering the multiple quantum wells and enhancing hole expansion capabilities. As a transition metal chalcogenide, WS2 has a layered structure with covalent bonds on each atomic plane. Adjacent layers are coupled by weak van der Waals forces, eliminating the need to consider lattice mismatch constraints and providing sufficient lattice orientation guidance for subsequent epitaxial layers. Therefore, the WS2 layer improves lattice matching with subsequent electron-blocking layers, reduces defects, and also reduces hole consumption by the electron-blocking layers and p-type GaN layers.

[0029] In one embodiment, the thickness of the AlN layer is 5-20 nm. If the thickness is less than 5 nm, it cannot effectively block the V-shaped pit; if the thickness is greater than 20 nm, it will cause a decrease in crystal quality. For example, the thickness of the AlN layer is 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, or 20 nm, but is not limited to these.

[0030] In one implementation, the thickness of the WS2 layer is 5-20 nm. If the thickness is less than 5 nm, it is difficult to improve the carrier mobility; if the thickness is greater than 20 nm, it will result in a waste of resources. For example, the thickness of the WS2 layer is 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, or 20 nm, but is not limited to these.

[0031] In one implementation, the thickness of the Al layer is 1-10 nm. For example, the thickness of the Al layer is 1 nm, 3 nm, 5 nm, 7 nm, 8 nm or 10 nm, but is not limited thereto.

[0032] In one embodiment, the growth temperature of the Al layer is lower than that of the AlN layer. The Al layer grown at a lower temperature has a higher roughness, which is beneficial for diffuse reflection of light within it.

[0033] In one embodiment, the V-shaped pit layer 5 comprises periodically stacked InGaN and GaN layers with a period number of 3-10. The thickness of the InGaN layer is 1-5 nm, and the thickness of the GaN layer is 3-20 nm. The V-shaped pit layer 5 can shield against dislocation increase, thereby reducing the performance degradation caused by dislocations. Furthermore, the V-shaped sidewalls extend throughout the entire active region, allowing holes to be easily injected into deeper light-emitting quantum wells through the V-shaped sidewalls, thereby reducing the operating voltage, improving the spatial non-uniform distribution of electrons and holes, and increasing luminous efficiency.

[0034] In addition to the composite interface layer described above, the other layered structures of the present invention have the following characteristics:

[0035] In one embodiment, the substrate 1 is one of a sapphire substrate, a silicon carbide substrate, or a silicon substrate. Preferably, the substrate 1 is a sapphire substrate.

[0036] In one embodiment, the nucleation layer 2 is an AlGaN nucleation layer or an AlN nucleation layer. Preferably, the nucleation layer 2 is an AlGaN nucleation layer, and the thickness of the nucleation layer 2 is 20-100 nm.

[0037] In one embodiment, the thickness of the intrinsic GaN layer 3 is 300-800 nm.

[0038] In one embodiment, the thickness of the N-type GaN layer 4 is 1-3 μm, and the N-type doping can be Si doping with a Si doping concentration of 5 × 10⁻⁶. 18 -1×10 19 cm -3 .

[0039] In one embodiment, the multi-quantum-well layer 6 includes periodically stacked InGaN quantum well layers and GaN quantum barrier layers, with a stacking period of 3-15. The thickness of the InGaN quantum well layer is 3-7 nm, and the thickness of the GaN quantum barrier layer is 6-15 nm.

[0040] In one embodiment, the electron blocking layer 8 comprises periodically stacked AlGaN and InGaN layers with a stacking period of 3-15, wherein the thickness of the AlGaN layer is 4-8 nm and the thickness of the InGaN layer is 4-8 nm.

[0041] In one embodiment, the thickness of the p-type GaN layer 9 is 5-60 nm, and the p-type doping can be Mg doping with a Mg doping concentration of 5 × 10⁻⁶ nm. 17 -1×10 20 cm -3 .

[0042] Correspondingly, such as Figure 2 As shown, the present invention also provides a method for fabricating a light-emitting diode epitaxial wafer, comprising the following steps:

[0043] S100 provides a substrate:

[0044] A sapphire substrate is selected and loaded into the MOCVD process. The reaction chamber temperature is controlled at 1000-1200℃ and the pressure at 200-600 Torr. The sapphire substrate is then subjected to high-temperature annealing for 5-8 minutes in an H2 atmosphere to clean the particles and oxides on the surface of the sapphire substrate.

[0045] S101 nucleation layer:

[0046] MOCVD growth was employed, with the reaction chamber temperature controlled at 500-700℃ and the pressure at 200-400 Torr. NH3 was introduced as the N source, N2 and H2 as the carrier gas, TMGa as the Ga source, and TMAl as the Al source.

[0047] S102 grows intrinsic GaN layers:

[0048] MOCVD growth was employed, with the reaction chamber temperature controlled at 1100-1150℃ and the pressure at 100-500 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, and TMGa was introduced as the Ga source.

[0049] S103 grows N-type GaN layers:

[0050] MOCVD growth was employed, with the reaction chamber temperature controlled at 1100-1150℃ and the pressure at 100-500 Torr. NH3 was introduced as the N source, N2 and H2 as the carrier gas, TMGa as the Ga source, and SiH4 as the doping source.

[0051] S104 growth V-shaped pit layer:

[0052] MOCVD growth was employed, with the reaction chamber temperature controlled at 800-900℃ and the pressure at 100-500 Torr. NH3 was introduced as the N source, N2 as the carrier gas, TEGa as the Ga source, and TMIn as the In source to grow InGaN layers. The In source was then turned off, while the Ga source was continued to grow GaN layers. This stacking and periodic growth of InGaN and GaN layers was repeated. Only N2 was used as the carrier gas; H2 was not introduced, as H2 is beneficial for two-dimensional growth and reduces the formation of V-shaped pits.

[0053] S105 multi-quantum-well layer growth:

[0054] MOCVD growth was employed, with the reaction chamber temperature controlled at 700-800℃ and the pressure at 100-500 Torr. NH3 was introduced as the N source, N2 as the carrier gas, TEGa as the Ga source, and TMIn as the In source to grow an InGaN quantum well layer. The reaction chamber temperature was then controlled at 800-900℃, while maintaining constant pressure. NH3 was introduced as the N source, N2 and H2 as the carrier gases, and TEGa as the Ga source to grow a GaN quantum barrier layer. The InGaN quantum well layer and GaN quantum barrier layer were then repeatedly stacked and periodically grown.

[0055] S106 grows the insertion layer, specifically, in one embodiment, including the following steps:

[0056] AlN layers grown on S106a:

[0057] MOCVD growth was employed, with the reaction chamber temperature controlled at 950-1000℃ and the pressure at 50-100 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, and TMAl was introduced as the Al source.

[0058] S106b grows Al layer:

[0059] MOCVD growth was employed, with the reaction chamber temperature controlled at 800-900℃ and the pressure at 100-300 Torr. N2 and H2 were used as carrier gases, and TMAl was introduced as the Al source.

[0060] S106c growth of WS2 layer:

[0061] CVD growth was employed, with the temperature controlled at 700-1000℃. Sodium thiosulfate solid powder and tungsten disulfide solid powder were placed in a quartz tube for chemical vapor deposition. The molar ratio of sodium thiosulfate solid powder to tungsten disulfide solid powder was 1:(1-3). Ar and H2 were used as carrier gases, with a volume ratio of Ar to H2 of 1:(1-5). The tube was then cooled and removed.

[0062] S107 grows an electron blocking layer:

[0063] MOCVD growth was employed, with the reaction chamber temperature controlled at 900-1000℃ and the pressure at 100-500 Torr. NH3 was introduced as the N source, N2 and H2 as the carrier gases, TMGa was introduced as the Ga source, and TMAl was introduced as the Al source to grow the AlGaN layer. The Al source was then turned off, and the Ga source was introduced again, along with TMIn as the In source, to grow the InGaN layer. The AlGaN and InGaN layers were then stacked and periodically grown.

[0064] S108 growth of P-type GaN layers:

[0065] MOCVD growth was employed, with the reaction chamber temperature controlled at 800-1000℃ and the pressure at 100-300 Torr. NH3 was introduced as the N source, N2 and H2 as the carrier gas, TMGa as the Ga source, and CP2Mg as the doping source.

[0066] The present invention will be further illustrated below with specific embodiments.

[0067] Example 1

[0068] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a V-shaped pit layer, a multiple quantum well layer, an insertion layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate.

[0069] The substrate is a sapphire substrate.

[0070] The nucleation layer is an AlGaN nucleation layer with a thickness of 30 nm.

[0071] The thickness of the intrinsic GaN layer is 400 nm.

[0072] The Si doping concentration in the N-type GaN layer is 7 × 10⁻⁶. 18 cm -3 The thickness is 2μm.

[0073] The V-shaped pit layer consists of alternating layers of InGaN and GaN, with the InGaN layer having a thickness of 3 nm and the GaN layer having a thickness of 10 nm, and a stacking period of 5.

[0074] The multiple quantum well layer consists of alternating layers of InGaN quantum wells and GaN quantum barriers. The thickness of the InGaN quantum well layer is 3 nm, the thickness of the GaN quantum barrier layer is 10 nm, and the stacking period is 10.

[0075] The insertion layer includes an AlN layer, an Al layer, and a WS2 layer. The thickness of the AlN layer is 7 nm, the thickness of the Al layer is 7 nm, and the thickness of the WS2 layer is 7 nm.

[0076] The electron blocking layer consists of alternating AlGaN and InGaN layers, with the AlGaN layer having a thickness of 6 nm and the InGaN layer having a thickness of 6 nm, and a stacking period of 8.

[0077] The Mg doping concentration in the p-type GaN layer is 5 × 10⁻⁶. 18 cm -3 The thickness is 10nm.

[0078] The above-mentioned method for fabricating an epitaxial wafer of a light-emitting diode includes the following steps:

[0079] S100 provides a substrate:

[0080] A sapphire substrate was selected and loaded into the MOCVD chamber. The reaction chamber temperature was controlled at 1100℃ and the pressure at 250 Torr. The sapphire substrate was subjected to high-temperature annealing for 6 minutes in an H2 atmosphere to clean the particles and oxides on the surface of the sapphire substrate.

[0081] S101 nucleation layer:

[0082] MOCVD growth was employed, with the reaction chamber temperature controlled at 600℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 and H2 as the carrier gas, TMGa as the Ga source, and TMAl as the Al source.

[0083] S102 grows intrinsic GaN layers:

[0084] MOCVD growth was employed, with the reaction chamber temperature controlled at 1120℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, and TMGa was introduced as the Ga source.

[0085] S103 grows N-type GaN layers:

[0086] MOCVD growth was employed, with the reaction chamber temperature controlled at 1120℃ and the pressure at 300 Torr. NH3 was introduced as the N source, N2 and H2 as the carrier gas, TMGa as the Ga source, and SiH4 as the doping source.

[0087] S104 growth V-shaped pit layer:

[0088] MOCVD growth was employed, with the reaction chamber temperature controlled at 850℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 as the carrier gas, TEGa as the Ga source, and TMIn as the In source to grow the InGaN layer. The In source was then turned off, and the Ga source was introduced again to grow the GaN layer. The InGaN and GaN layers were then stacked and grown periodically.

[0089] S105 multi-quantum-well layer growth:

[0090] MOCVD growth was employed, with the reaction chamber temperature controlled at 750℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 as the carrier gas, TEGa as the Ga source, and TMIn as the In source to grow an InGaN quantum well layer. The reaction chamber temperature was then controlled at 850℃, while maintaining constant pressure. NH3 was introduced as the N source, N2 and H2 as the carrier gases, and TEGa as the Ga source to grow a GaN quantum barrier layer. The InGaN quantum well layer and GaN quantum barrier layer were then repeatedly stacked and periodically grown.

[0091] The S106 growth insertion layer specifically includes the following steps:

[0092] AlN layer grown on S106a:

[0093] MOCVD growth was employed, with the reaction chamber temperature controlled at 960℃ and the pressure at 800 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, and TMAl was introduced as the Al source.

[0094] S106b grows Al layer:

[0095] MOCVD growth was employed, with the reaction chamber temperature controlled at 850℃ and the pressure at 150 Torr. N2 and H2 were used as carrier gases, and TMAl was introduced as the Al source.

[0096] S106c growth of WS2 layer:

[0097] CVD growth was employed at a controlled temperature of 800℃. Sodium thiosulfate solid powder and tungsten disulfide solid powder were placed in a quartz tube for chemical vapor deposition. The molar ratio of sodium thiosulfate solid powder to tungsten disulfide solid powder was 1:2. Ar and H2 were used as carrier gases, with a volume ratio of Ar to H2 of 1:4. The tube was then cooled and removed.

[0098] S107 grows an electron blocking layer:

[0099] MOCVD growth was employed, with the reaction chamber temperature controlled at 950℃ and the pressure at 150 Torr. NH3 was introduced as the N source, N2 and H2 as the carrier gases, TMGa was introduced as the Ga source, and TMAl was introduced as the Al source to grow the AlGaN layer. The Al source was then turned off, and the Ga source was introduced again, along with TMIn as the In source, to grow the InGaN layer. The AlGaN and InGaN layers were then stacked and periodically grown.

[0100] S108 growth of P-type GaN layers:

[0101] MOCVD growth was employed, with the reaction chamber temperature controlled at 900℃ and the pressure at 120 Torr. NH3 was introduced as the N source, N2 and H2 as the carrier gas, TMGa as the Ga source, and CP2Mg as the doping source.

[0102] Example 2

[0103] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the insertion layer includes an AlN layer, an Al layer, and a WS2 layer. The thickness of the AlN layer is 10 nm, the thickness of the Al layer is 3 nm, and the thickness of the WS2 layer is 8 nm. All other aspects are the same as in Embodiment 1.

[0104] Comparative Example 1

[0105] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that it does not include an insertion layer. Correspondingly, the fabrication method also excludes the step of preparing the insertion layer. Everything else is the same as in Example 1.

[0106] Comparative Example 2

[0107] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that the insertion layer is a WS2 layer. Correspondingly, in the fabrication method, the fabrication of the insertion layer only includes the fabrication step of the WS2 layer. All other steps are the same as in Example 1.

[0108] Comparative Example 3

[0109] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that the intercalation layer is an AlN layer. Correspondingly, in the fabrication method, the preparation of the intercalation layer only includes the AlN layer preparation step. All other steps are the same as in Example 1.

[0110] Performance testing:

[0111] The LED epitaxial wafers obtained in Examples 1 and 2 and Comparative Examples 1-3 were fabricated into 10mil × 24mil chips, and their photoelectric performance was tested. The testing methods are as follows:

[0112] (1) Brightness: The brightness of the chip was tested under a driving current of 120mA.

[0113] (2) Antistatic capability: The antistatic performance of the chip was tested using an electrostatic meter under the HBM model (human body discharge model) to test the percentage of reverse 8kV static electricity that the chip could withstand.

[0114] The test results are shown in Table 1.

[0115] Table 1. Photoelectric performance test results of LED epitaxial wafers

[0116] Example 1 198 97.2 Example 2 201 98.9 Comparative Example 1 191 90.1 Comparative Example 2 192.3 92.2 Comparative Example 3 193.1 92.8

[0117] As shown in Table 1, the brightness and antistatic capability of the chip are significantly improved by adopting the insertion layer structure of the present invention.

[0118] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that, It includes a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a V-shaped pit layer, a multiple quantum well layer, an insertion layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate; The insertion layer comprises an AlN layer, an Al layer, and a WS2 layer stacked sequentially; The thickness of the AlN layer is 5-20 nm; the thickness of the Al layer is 1-10 nm; the thickness of the WS2 layer is 5-20 nm; The V-shaped pit layer comprises periodically stacked InGaN and GaN layers, with a period number of 3-10. The thickness of the InGaN layer is 1-5 nm, and the thickness of the GaN layer is 3-20 nm.

2. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The growth temperature of the Al layer is less than the growth temperature of the AlN layer.

3. A method for fabricating a light-emitting diode epitaxial wafer, used to fabricate the light-emitting diode epitaxial wafer as described in claim 1 or 2, characterized in that, Includes the following steps: A substrate is provided on which a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a V-shaped pit layer, a multiple quantum well layer, an insertion layer, an electron blocking layer and a P-type GaN layer are sequentially grown. The insertion layer comprises an AlN layer, an Al layer, and a WS2 layer stacked sequentially.

4. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 3, characterized in that, The AlN layer is grown by MOCVD at a growth temperature of 950-1000℃ and a growth pressure of 50-100 Torr, using a mixture of N2 and H2 as the carrier gas.

5. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 3, characterized in that, The Al layer is grown by MOCVD at a growth temperature of 800-900℃ and a growth pressure of 100-300 Torr, with a carrier gas of N2 and H2.

6. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 3, characterized in that, The WS2 layer is grown by CVD at a growth temperature of 700-1000℃. Sodium thiosulfate and tungsten disulfide are used as precursors, with a molar ratio of 1:(1-3). The carrier gas is a mixture of Ar and H2.

7. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 3, characterized in that, The V-shaped pit layer comprises periodically stacked InGaN and GaN layers. The V-shaped pit layer is grown using MOCVD. The growth temperature of the V-shaped pit layer is 800-900℃, the growth pressure is 100-500 Torr, and the carrier gas is N2.

8. A light-emitting diode, characterized in that, The light-emitting diode includes the light-emitting diode epitaxial wafer as described in claim 1 or 2.

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