Red light micro-led chip and preparation method thereof

Abstract

The application discloses a red light Micro-LED chip and a preparation method thereof. The red light Micro-LED chip is prepared on the basis of an existing red light Micro-LED chip preparation method, the structure of a P electrode and an N electrode is changed, the purpose of reducing contact ohmic resistance and lowering voltage is achieved, the problem that the voltage of the red light Micro-LED chip is higher than 2.0 V under the application of a conventional working current 2 mA is solved, and after the outermost metal structure of the first N electrode or the second N electrode is PT, the thickness of AU in the electrode structure can be reduced, and the chip cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of Micro-LED chip technology, and more particularly to a red Micro-LED chip and its fabrication method. Background Technology

[0002] Micro-LED, also known as micro-light-emitting diode or μLED, generally refers to the technology of using LED light-emitting units with a size of 1 to 60 μm to form a display array. Its size is equivalent to 1 / 10 of a human hair. It has the characteristics of not requiring backlight, high photoelectric conversion efficiency, and response time in the nanosecond range. It is a technology that makes LEDs thin, miniaturized and arrayed, so that its volume is only 1% of that of mainstream LEDs and the pixel distance is from millimeters to micrometers.

[0003] Red Micro-LEDs can be fabricated using AlInGaP materials. Currently, the conventional N-electrode metal structure is AU / AUGE / AU. However, the voltage of existing electrode structures often exceeds 2.0V during bare die testing at a typical application current of 2mA. Furthermore, current P-electrode or N-electrode structures are primarily made of pure gold. During fabrication, to prevent leakage during PSV etching, the AU layer in the P-electrode or N-electrode structure is designed to be relatively thick as a sacrificial layer, resulting in higher chip costs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for fabricating a red Micro-LED chip, which can reduce the voltage by reducing the contact ohmic resistance and has a low chip cost.

[0005] The technical problem to be solved by this invention is to provide a red Micro-LED chip with low operating voltage and low production cost.

[0006] To address the aforementioned technical problems, this invention provides a method for fabricating a red Micro-LED chip, comprising the following steps:

[0007] S1. Prepare a red LED epitaxial wafer, wherein the red LED epitaxial wafer includes a GaAs substrate, and an N-GaAs layer, an N-AlGaInP layer, a multiple quantum well layer and a P-GaP layer are epitaxially grown sequentially from bottom to top on the GaAs substrate.

[0008] S2. A SiO2 layer is deposited on the surface of the P-GaP layer to obtain a first epitaxial wafer. The surface of the first epitaxial wafer with the SiO2 layer is bonded to a sapphire substrate. After bonding, the GaAs substrate is etched away to obtain a second epitaxial wafer with sapphire as the substrate and an N-GaAs layer as the surface.

[0009] S3. Etch away part of the N-GaAs layer, N-AlGainP layer and multiple quantum well layer to expose the P-GaP layer;

[0010] S4. Deposit a P electrode and a first N electrode on the exposed P-GaP layer surface, and deposit a second N electrode on the N-GaAs layer surface.

[0011] S5. Etch a dicing path in the epitaxial layer of the second epitaxial wafer to cut the second epitaxial wafer into individual core particles;

[0012] S6. Deposit a passivation layer on the surface of the N-GaAs layer, then etch a P-type conductive hole above the first N electrode and an N-type conductive hole above the second N electrode;

[0013] S7. Deposit pad electrodes into the P-type conductive holes and the N-type conductive holes by vapor deposition;

[0014] S8. The second epitaxial wafer is cut into individual core particles through the cutting channel to obtain a red Micro-LED chip;

[0015] The outermost metal structure of the first N electrode or the second N electrode is PT.

[0016] In one embodiment, the structure of the first N electrode is AU / AUGE / AU / PT;

[0017] The structure of the second N electrode is AU / AUGE / AU / PT.

[0018] In one embodiment, when etching a P-type conductive hole above the first N electrode, the PT layer etched up to the first N electrode is also etched.

[0019] When etching an N-type conductive hole above the second N electrode, the PT layer etched to the first N electrode is also etched.

[0020] In one embodiment, when a dicing channel is etched into the epitaxial layer of the second epitaxial wafer, the dicing channel penetrates the P-GaP layer to cut the second epitaxial wafer into individual cores.

[0021] In one embodiment, the passivation layer is a low-refractive-index material layer and / or a distributed Bragg reflector.

[0022] In one embodiment, the P electrode has an AU / AUBE structure.

[0023] In one embodiment, the pad electrode has a structure of TI / AL / AU.

[0024] To solve the above-mentioned technical problems, the present invention provides a red light Micro-LED chip, which is prepared by the aforementioned method for preparing a red light Micro-LED chip.

[0025] In one embodiment, the chip includes a sapphire substrate, a P-GaP layer, a multiple quantum well layer, an N-AlGaNP layer and an N-GaAs layer connected sequentially from bottom to top. A P electrode, a first N electrode and a pad electrode are sequentially disposed on the P-GaP layer, and a second N electrode and a pad electrode are sequentially disposed on the N-GaAs layer.

[0026] The outermost metal structure of the first N electrode or the second N electrode is PT.

[0027] In one embodiment, the structure of the first N electrode is AU / AUGE / AU / PT;

[0028] The structure of the second N electrode is AU / AUGE / AU / PT.

[0029] Implementing this invention has the following beneficial effects:

[0030] The method for fabricating a red Micro-LED chip provided by this invention involves depositing a P electrode and a first N electrode on the exposed P-GaP layer surface, and depositing a second N electrode on the N-GaAs layer surface. The outermost metal structure of the first or second N electrode is PT. By changing the structure of the P-point electrode and the N electrode based on the original process, the contact ohmic resistance is reduced, thereby lowering the voltage. This improves the problem that the voltage of the red Micro-LED chip is higher than 2.0V under the normal operating current of 2mA. Furthermore, by making the outermost metal structure of the first or second N electrode PT, the thickness of AU in the electrode structure can be reduced, thus reducing the chip cost. Attached Figure Description

[0031] Figure 1 A flowchart illustrating the fabrication method of the red Micro-LED chip provided by this invention;

[0032] Figure 2 This is a schematic diagram of the structure of the red Micro-LED chip provided by the present invention;

[0033] Among them, sapphire substrate 1, P-GaP layer 2, multiple quantum well layer 3, N-AlGaNP layer 4, N-GaAs layer 5, P electrode 6, first N electrode 71, second N electrode 72, pad electrode 8, and passivation layer 9. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below.

[0035] Unless otherwise stated or in case of contradiction, the terms or phrases used herein shall have the following meanings:

[0036] In this invention, "preferred" is merely a description of a more effective implementation method or embodiment, and should be understood as not constituting a limitation on the scope of protection of this invention.

[0037] In this invention, the technical features described in an open-ended manner include both closed-ended technical solutions composed of the listed features and open-ended technical solutions that include the listed features.

[0038] In this invention, numerical ranges are involved, and unless otherwise specified, they include the two endpoints of the numerical range.

[0039] To address the above problems, this invention provides a method for fabricating a red Micro-LED chip, such as... Figure 1 and Figure 2 As shown, it includes the following steps:

[0040] S1. Prepare a red LED epitaxial wafer, wherein the red LED epitaxial wafer includes a GaAs substrate, and an N-GaAs layer 5, an N-AlGaInP layer 4, a multiple quantum well layer 3 and a P-GaP layer 2 are epitaxially grown sequentially from bottom to top on the GaAs substrate.

[0041] S2. A SiO2 layer is deposited on the surface of the P-GaP layer 2 to obtain a first epitaxial wafer. The surface of the first epitaxial wafer with the SiO2 layer is bonded to the sapphire substrate 1. After bonding, the GaAs substrate is etched away to obtain a second epitaxial wafer with sapphire as the substrate and N-GaAs layer 5 as the surface.

[0042] In one embodiment, after growing a red LED chip epitaxial structure on a GaAs substrate using an MOCVD machine, a wet anisotropic roughening process is performed on the surface of the P-GaP layer 2 to roughen the surface. Then, a SiO2 layer is deposited using a PECVD machine. This SiO2 layer is then annealed, polished, cleaned, and activated before being bonded to a specially treated sapphire substrate. After bonding, a high-temperature, high-pressure bonding process is performed. After bonding, the bonded wafer is wet-removed from the original GaAs substrate (and the cutoff layer). After removal, a second epitaxial wafer with a sapphire substrate and an N-GaAs layer 5 as its surface is obtained.

[0043] S3. Etch away part of the N-GaAs layer 5, N-AlGaInP layer 4 and multiple quantum well layer 3 to expose the P-GaP layer 2.

[0044] In one embodiment, mask deposition, homogenization, exposure, development, dry etching, and resist removal are performed on the surface of the N-GaAs layer 5 to etch away part of the N-GaAs layer 5, the N-AlGaInP layer 4, and the multi-quantum well layer 3, exposing the P-GaP layer 2 to form the smallest unit of LED light-emitting structure.

[0045] S4. A P-electrode 6 and a first N-electrode 71 are deposited on the exposed P-GaP layer 2, and a second N-electrode 72 is deposited on the N-GaAs layer 5; the outermost metal structure of the first N-electrode 71 or the second N-electrode 72 is PT. Preferably, the structure of the first N-electrode 71 is AU / AUGE / AU / PT; the structure of the second N-electrode 72 is AU / AUGE / AU / PT. The method for fabricating a red Micro-LED chip provided by the present invention involves depositing a P-electrode and a first N-electrode on the exposed P-GaP layer surface, and depositing a second N-electrode on the N-GaAs layer surface. The outermost metal structure of the first N-electrode or the second N-electrode is PT. By changing the structure of the P-point electrode and the N-electrode based on the original process, the purpose of reducing contact ohmic resistance and thus reducing voltage is achieved, improving the problem that the voltage of the red Micro-LED chip is higher than 2.0V under the normal operating current of 2mA.

[0046] In one embodiment, after performing spin coating, exposure, development, coating, cleaning, evaporation, stripping, and resist removal on the exposed P-GaP layer 2, a P electrode 6 is formed on the P-GaP layer 2. The contact resistance between the P electrode 6 and the P-GaP layer 2 is reduced after RTA annealing. Then, a first N electrode 71 is deposited on the P electrode 6. In one embodiment, the structure of the P electrode 6 is AU / AUBE.

[0047] In one embodiment, after performing spin coating, exposure, development, coating, cleaning, vapor deposition, stripping, and resist removal on the unetched N-GaAs layer 5, a second N electrode 72 is formed on the N-GaAs layer 5, and the contact resistance between the second N electrode 72 and the N-GaAs layer 5 is reduced after RTA annealing and fusion.

[0048] S5. Etch a dicing path in the epitaxial layer of the second epitaxial wafer to cut the second epitaxial wafer into individual core particles;

[0049] In one embodiment, mask deposition, photoresist coating, exposure, development, dry etching, and photoresist removal are performed at the dicing location. When the dicing is etched into the epitaxial layer of the second epitaxial wafer, the dicing penetrates the P-GaP layer 2 to cut the second epitaxial wafer into individual cores.

[0050] S6. Deposit a passivation layer 9 on the surface of the N-GaAs layer 5, and then etch a P-type conductive hole above the first N electrode 71 and an N-type conductive hole above the second N electrode 72.

[0051] In one embodiment, the passivation layer 9 is a low-refractive-index material layer and / or a distributed Bragg reflector. Preferably, the passivation layer 9 is a distributed Bragg reflector.

[0052] In one embodiment, when etching a P-type conductive hole above the first N electrode 71, the PT layer extending to the first N electrode 71 is also etched; when etching an N-type conductive hole above the second N electrode 72, the PT layer extending to the first N electrode 71 is also etched. The P-type and N-type conductive holes facilitate electrode connection via the pads.

[0053] It should be noted that the conventional N-electrode metal structure is currently AU / AUGE / AU, and the photolithographic pattern of the N-electrode generally only exists in the mesa region. After the N-electrode is fabricated, GaAs etching is generally performed. The GaAs etching method is as follows: N-electrode resist removal, GaAs etching photolithography (photoresist mask), resist application, wet etching, resist removal, RTA annealing, ISO (i.e., step S5 in this invention), after ISO, PSV-DBR evaporation is performed (i.e., depositing a passivation layer 9 on the surface of N-GaAs layer 5 in step S6 of this invention), after evaporation, photolithography is performed, after photolithography masking, dry etching is performed, and the PSV hole will be over-etched to the AU layer of the N-electrode. After etching, resist removal is performed, and after resist removal, the bonding electrode is fabricated. The fabrication method of the bonding electrode is generally photolithography, resist application, cleaning, evaporation, and resist removal.

[0054] This invention improves the N-electrode structure to AU / AUGE / AU / PT, and simultaneously exists in the mesa region of the N-electrode and the PSV hole region of the P-region. Specifically, in this invention, the P-electrode 6 and the first N-electrode 71 are deposited on the exposed P-GaP layer 2, and the second N-electrode 72 is deposited on the N-GaAs layer 5. After electrode fabrication, the GaAs etching method is improved as follows: N-electrode resist removal, RTA annealing, wet etching of the GaAs electrode mask, ISO, ISO passes, and after PSV-DBR evaporation photolithography, dry etching of the PSV holes is performed up to the PT layer. After resist removal, the bonding electrode fabrication method is improved to photolithography, resist application, evaporation, and resist removal. This invention simplifies the original fabrication steps, and because the outermost metal structure of the first N-electrode 71 or the second N-electrode 72 is changed to PT, the thickness of the AU layer in the electrode structure can be reduced, and the AU layer is no longer used as a sacrificial layer, greatly reducing the chip manufacturing cost.

[0055] S7. Deposit pad electrodes 8 into the P-type conductive holes and the N-type conductive holes by vapor deposition;

[0056] In one embodiment, the pad electrode 8 has a structure of TI / AL / AU.

[0057] S8. The second epitaxial wafer is cut into individual core particles through the cutting channel to obtain a red Micro-LED chip.

[0058] Accordingly, the present invention provides a red Micro-LED chip, which is fabricated using the aforementioned method for preparing a red Micro-LED chip. For example... Figure 2 As shown, in one embodiment, the chip includes a sapphire substrate 1, a P-GaP layer 2, a multiple quantum well layer 3, an N-AlGaNP layer 4, and an N-GaAs layer 5 connected sequentially from bottom to top. A P-electrode 6, a first N-electrode 71, and a pad electrode 8 are sequentially disposed on the P-GaP layer 2. A second N-electrode 72 and a pad electrode 8 are sequentially disposed on the N-GaAs layer 5. The outermost metal structure of the first N-electrode 71 or the second N-electrode 72 is PT. Preferably, the structure of the first N-electrode 71 is AU / AUGE / AU / PT; and the structure of the second N-electrode 72 is AU / AUGE / AU / PT.

[0059] The present invention is further illustrated below with specific embodiments:

[0060] Example 1

[0061] This invention provides a method for fabricating a red Micro-LED chip, comprising the following steps:

[0062] S1. Prepare a red LED epitaxial wafer, wherein the red LED epitaxial wafer includes a GaAs substrate, and an N-GaAs layer, an N-AlGaInP layer, a multiple quantum well layer and a P-GaP layer are epitaxially grown sequentially from bottom to top on the GaAs substrate.

[0063] S2. A SiO2 layer is deposited on the surface of the P-GaP layer to obtain a first epitaxial wafer. The surface of the first epitaxial wafer with the SiO2 layer is bonded to a sapphire substrate. After bonding, the GaAs substrate is etched away to obtain a second epitaxial wafer with sapphire as the substrate and an N-GaAs layer as the surface.

[0064] S3. Etch away part of the N-GaAs layer, N-AlGainP layer and multiple quantum well layer to expose the P-GaP layer;

[0065] S4. A P-electrode and a first N-electrode are deposited on the exposed P-GaP layer surface, and a second N-electrode is deposited on the N-GaAs layer surface. The structure of the first N-electrode is AU / AUGE / AU / PT; the structure of the second N-electrode is AU / AUGE / AU / PT. The structure of the P-electrode is AU / AUBE.

[0066] S5. Etch a dicing path in the epitaxial layer of the second epitaxial wafer to cut the second epitaxial wafer into individual core particles;

[0067] S6. A passivation layer is deposited on the surface of the N-GaAs layer, and then a P-type conductive hole is etched above the first N electrode, and the PT layer etched to the first N electrode is etched; an N-type conductive hole is etched above the second N electrode, and the PT layer etched to the first N electrode is etched.

[0068] S7. Deposit pad electrodes into the P-type conductive holes and the N-type conductive holes by vapor deposition;

[0069] S8. The second epitaxial wafer is cut into individual core particles through the cutting channel to obtain a red Micro-LED chip;

[0070] Comparative Example 1

[0071] This comparative example differs from Example 1 in that, in step S4: a P-electrode is deposited on the exposed P-GaP layer surface, and an N-electrode is deposited on the N-GaAs layer surface, wherein the N-electrode has a structure of AU / AUGE / AU; and the P-electrode has a structure of AU / AUBE / AU. Furthermore, in step S6, a passivation layer is deposited on the N-GaAs layer surface, and then a P-type conductive via is etched above the P-electrode, etching over the AU layer down to the P-electrode; an N-type conductive via is etched above the N-electrode, etching over the AU layer down to the N-electrode. All other steps are the same as in Example 1.

[0072] The operating voltage, brightness, and luminous efficacy improvement rate relative to Comparative Example 1 of the red Micro-LED chips prepared in Example 1 and Comparative Example 1 were tested at a conventional operating current of 2mA. The specific test results are shown in Table 1.

[0073] Table 1. Performance test results of LEDs prepared in Examples 1-3 and Comparative Examples 1-3

[0074]

[0075] In summary, the method for fabricating a red Micro-LED chip provided by this invention involves depositing a P electrode and a first N electrode on the exposed P-GaP layer surface, and depositing a second N electrode on the N-GaAs layer surface. The outermost metal structure of the first or second N electrode is PT. By changing the structure of the P-point electrode and the N electrode based on the original process, the method achieves the purpose of reducing contact ohmic resistance and thus lowering the voltage. This improves the problem of the red Micro-LED chip having a voltage higher than 2.0V under a normal operating current of 2mA. Furthermore, by using PT as the outermost metal structure of the first or second N electrode, the thickness of AU in the electrode structure can be reduced, thereby reducing the chip cost.

[0076] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A method for fabricating a red Micro-LED chip, characterized in that, Includes the following steps: S1. Prepare a red LED epitaxial wafer, wherein the red LED epitaxial wafer includes a GaAs substrate, and an N-GaAs layer, an N-AlGaInP layer, a multiple quantum well layer and a P-GaP layer are epitaxially grown sequentially from bottom to top on the GaAs substrate. S2. A SiO2 layer is deposited on the surface of the P-GaP layer to obtain a first epitaxial wafer. The surface of the first epitaxial wafer with the SiO2 layer is bonded to a sapphire substrate. After bonding, the GaAs substrate is etched away to obtain a second epitaxial wafer with sapphire as the substrate and an N-GaAs layer as the surface. S3. Etch away part of the N-GaAs layer, N-AlGainP layer and multiple quantum well layer to expose the P-GaP layer; S4. Deposit a P electrode and a first N electrode on the exposed P-GaP layer surface, and deposit a second N electrode on the N-GaAs layer surface. S5. Etch a dicing path in the epitaxial layer of the second epitaxial wafer to cut the second epitaxial wafer into individual core particles; S6. Deposit a passivation layer on the surface of the N-GaAs layer, then etch a P-type conductive hole above the first N electrode and an N-type conductive hole above the second N electrode; S7. Deposit pad electrodes into the P-type conductive holes and the N-type conductive holes by vapor deposition; S8. The second epitaxial wafer is cut into individual core particles through the cutting channel to obtain a red Micro-LED chip; The outermost metal structure of the first N electrode or the second N electrode is PT.

2. The method for fabricating a red Micro-LED chip as described in claim 1, characterized in that, The structure of the first N electrode is AU / AUGE / AU / PT; The structure of the second N electrode is AU / AUGE / AU / PT.

3. The method for fabricating a red Micro-LED chip as described in claim 2, characterized in that, When etching a P-type conductive hole above the first N electrode, the PT layer etched to the first N electrode is also etched. When etching an N-type conductive hole above the second N electrode, the PT layer etched to the first N electrode is also etched.

4. The method for fabricating a red Micro-LED chip as described in claim 1, characterized in that, When dicing is etched into the epitaxial layer of the second epitaxial wafer, the dicing penetrates the P-GaP layer to cut the second epitaxial wafer into individual cores.

5. The method for fabricating a red Micro-LED chip as described in claim 1, characterized in that, The passivation layer is a low-refractive-index material layer and / or a distributed Bragg reflector.

6. The method for fabricating a red Micro-LED chip as described in claim 1, characterized in that, The structure of the P electrode is AU / AUBE.

7. The method for fabricating a red Micro-LED chip as described in claim 1, characterized in that, The structure of the pad electrode is TI / AL / AU.

8. A red Micro-LED chip, characterized in that, It is prepared using the method for preparing a red Micro-LED chip as described in any one of claims 1 to 7.

9. The red Micro-LED chip as described in claim 8, characterized in that, The chip includes a sapphire substrate, a P-GaP layer, a multiple quantum well layer, an N-AlGaNP layer and an N-GaAs layer connected in sequence from bottom to top. A P electrode, a first N electrode and a pad electrode are sequentially disposed on the P-GaP layer, and a second N electrode and a pad electrode are sequentially disposed on the N-GaAs layer. The outermost metal structure of the first N electrode or the second N electrode is PT.

10. The red Micro-LED chip as described in claim 9, characterized in that, The structure of the first N electrode is AU / AUGE / AU / PT; The structure of the second N electrode is AU / AUGE / AU / PT.

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