Stacked chip coupler and method of manufacturing the same

Abstract

The application provides a laminated chip coupling device and a manufacturing method thereof. The laminated chip coupling device comprises a device main body and a mark. The mark is arranged in the interior of the device main body, and at least part of the mark is visible outside the device main body. The mark is arranged in the interior of the device main body, so that the mark can be prevented from falling off, and defects caused by scratching of the mark can be avoided. In addition, the problem of poor color development caused by electroplating corrosion can be avoided.

Description

Technical Field

[0001] This application relates to the field of coupling, specifically to a multilayer chip coupling device and its manufacturing method. Background Technology

[0002] With the rapid development of 5G communication technology, the number of communication frequency bands has increased, and the frequencies are gradually trending towards higher frequencies. Furthermore, different applications require different characteristics from coupling devices, such as filters. The modern communication market has become an arena for various coupling devices. In the industry, product orientation markers used in coupling devices are typically made of metal or ceramic materials, with the markers exposed on the magnet surface. The disadvantages of metal markers are high manufacturing costs and susceptibility to scratches during handling, which can create circuits between adjacent pads, leading to poor electrical properties. For some coupling devices, the surface metal marker can form parasitic capacitance with the internal electrodes, degrading electrical performance. The disadvantages of ceramic markers are poor bonding between the ceramic and magnet materials after co-firing, causing the markers to easily detach or corrode during electroplating, resulting in poor color rendering and thus incorrect product orientation identification. Summary of the Invention

[0003] In view of this, this application provides a multilayer chip coupling device and its manufacturing method to improve the problems of markings on the surface of the coupling device being easily scratched and damaged, and poor color rendering caused by electroplating corrosion.

[0004] This application provides a multilayer chip coupling device, including a device body and a label, wherein the label is disposed inside the device body and outside the device body, and the label is at least partially visible.

[0005] Optionally, the device body includes:

[0006] First outer dielectric layer;

[0007] The second outer dielectric layer is disposed opposite to the first outer dielectric layer along the second direction;

[0008] Multiple inner dielectric layers;

[0009] The multilayer inner electrode and the plurality of inner dielectric layers are disposed between the first outer dielectric layer and the second outer dielectric layer, and are stacked alternately along the second direction. Adjacent inner electrodes are insulated by the inner dielectric layer disposed between them.

[0010] The identifier is located between the first outer dielectric layer and the second outer dielectric layer.

[0011] Optionally, the identifier includes at least one sub-part and / or at least one planar part; the sub-part is disposed in a via formed in the corresponding inner dielectric layer; the planar part is disposed on any adjacent inner dielectric layer, and along the second direction, the orthographic projection of the planar part covers the orthographic projection of the nearest sub-part.

[0012] Optionally, the planar portion is disposed on the side of the first outer dielectric layer facing the plurality of inner dielectric layers.

[0013] Optionally, a sub-part is provided in the via formed by the first outer dielectric layer.

[0014] Optionally, the identifier includes multiple layers of the sub-parts, which are connected end-to-end along the second direction.

[0015] Optionally, the color rendering intensity of the identifier is higher than that of the plurality of inner dielectric layers.

[0016] This application provides a method for manufacturing a multilayer chip coupling device, comprising:

[0017] A device body is formed, the device body comprising a plurality of dielectric layers and multiple internal electrodes stacked alternately along a second direction, wherein adjacent internal electrodes are insulated by a dielectric layer disposed between them;

[0018] An identifier is formed between the two outermost dielectric layers and is at least partially visible on the exterior of the device body.

[0019] Optionally, forming the identifier between the two outermost dielectric layers includes at least one of the following:

[0020] A via is formed in at least one of the dielectric layers between the two outermost dielectric layers, and a sub-part is formed in the via;

[0021] A planar portion is formed on at least one of the dielectric layers;

[0022] A planar portion is formed on at least one of the dielectric layers between the two outermost dielectric layers, and a via is formed in the dielectric layer adjacent to the planar portion, and a sub-portion is formed in the via, wherein the orthographic projection of the planar portion overlaps the orthographic projection of the sub-portion along the second direction.

[0023] Optionally, forming the identifier between the two outermost dielectric layers includes at least one of the following:

[0024] A planar portion is formed on a dielectric layer adjacent to the outermost dielectric layer, and a via is formed in the outermost dielectric layer, and a sub-portion is formed in the via, and along the second direction, the orthographic projection of the planar portion covers the orthographic projection of the sub-portion;

[0025] The marking is formed using a material with a color rendering index higher than that of the dielectric layer.

[0026] As described above, this application places the marking inside the main body of the device, thereby avoiding the marking from falling off or being damaged by scratches, and also avoiding problems such as poor color rendering caused by electroplating corrosion. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the overall structure of a stacked chip coupling device provided in an embodiment of this application;

[0028] Figure 2 This is a side view of a stacked chip coupling device provided in an embodiment of this application;

[0029] Figure 3 This is a partial exploded view of a multilayer chip coupling device provided in an embodiment of this application;

[0030] Figure 4 This is a schematic flowchart of a method for manufacturing a multilayer chip coupling device provided in an embodiment of this application;

[0031] Figure 5 This is a schematic flowchart of another method for manufacturing a multilayer chip coupling device provided in the embodiments of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, and not all of them. Unless otherwise specified, the following embodiments and their technical features can be combined with each other, and also belong to the technical solutions of this application.

[0033] In the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the technical solutions of the corresponding embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0034] This application provides a multilayer chip coupling device, including a device body and a label. The label is located inside the device body and outside the device body, and is at least partially visible. By embedding the label inside the device body, damage caused by the label being detached or scratched can be avoided, as well as problems such as poor color rendering caused by electroplating corrosion.

[0035] In practical applications, multilayer chip coupling devices (hereinafter referred to as coupling devices) also include other necessary structural components, such as terminal electrodes. Coupling devices include, but are not limited to, filters, capacitors, inductors, and thermistors. The function of the markings includes, but is not limited to, orientation identification, such as indicating the placement of the coupling device; or, marking the current input and current output terminals of the coupling device, for example, marking the current input or current output terminals adjacent to them, so that operators can intuitively know the location of the current input or current output terminals, thereby quickly determining the current direction of the coupling device. Of course, this is not limited to these uses.

[0036] The specific structure of the device body should be determined according to the specific type of coupling device, and correspondingly, the way the markings are set inside the device body should also be determined accordingly. The following is an example... Figures 1 to 3 Taking the device body shown as an example, the method of setting the mark is introduced.

[0037] Please refer to the following: Figures 1 to 3 This is a schematic diagram of the overall and partial structure of a multilayer chip coupling device provided in an embodiment of this application. The coupling device 1 includes a first outer dielectric layer 111, a second outer dielectric layer 112, multiple inner electrodes 12, end electrodes 13, multiple inner dielectric layers 14, and a marker 15.

[0038] The first outer dielectric layer 111, the second outer dielectric layer 112, the multilayer inner electrodes 12, and the multiple inner dielectric layers 14 form the device body of the coupling device 1. The shape and size of the device body are not limited in this embodiment; for example, the shape can be... Figures 1 to 3 The examples shown are cuboids, rectangles, or other similar tetrahedral shapes. It should be noted that... Figure 1 and Figure 2 The image shows a portion of the outer surface of the coupling device 1. Specifically, the inner electrode 12 and inner dielectric layer 14 are not shown, nor is the structural design of the identifier 15 inside the coupling device 1. Figure 3 The stacking relationship of the inner electrode 12 and the inner dielectric layer 14, and their respective structural designs for adapting to the identifier 15, are shown, but the portion of the identifier 15 at the corresponding location is not shown. The number of inner electrodes 12 and inner dielectric layers 14 can be the same; the specific number can be determined according to the actual required adaptability, and this application does not limit it. For example... Figure 3The diagram shows six inner dielectric layers 14 and six inner electrodes 12. The relative positions and overlapping patterns of these inner electrodes 12 are also shown as examples.

[0039] The length direction of coupling device 1 (and its main body) is the first direction x, the height direction is the second direction y, and the width direction is the third direction z. The first direction x, the second direction y, and the third direction z are all perpendicular to each other, and can be regarded as the three coordinate axes of a three-dimensional rectangular coordinate system. It should be understood that the term "perpendicular" in this application does not require that the angle between the two directions must be 90°, but allows for deviations of, for example, ±10°. That is, "perpendicular" can be understood as the angle between any two directions being 80° to 100°.

[0040] The first outer dielectric layer 111 and the second outer dielectric layer 112, also referred to as the upper outer dielectric layer and the lower outer dielectric layer respectively, are the outer dielectric layers of the coupling device 1. Both can be used to form the housing of the coupling device 1. Their shapes and dimensions are adapted to the shape and dimensions of the coupling device 1, which not only limits the appearance of the coupling device 1 but also protects its internal structural components, such as the internal electrodes 12 and the inner dielectric layer 14. The thickness of the first outer dielectric layer 111 and the second outer dielectric layer 112 (along the second direction y) can be equal, and the material can be the same, for example, ceramic. Either the first outer dielectric layer 111 or the second outer dielectric layer 112 can be a single-layer structure or a multi-layer structure.

[0041] The inner electrode 12 and the inner dielectric layer 14 form the main part of the magnet of the coupling device 1. They are disposed between the first outer dielectric layer 111 and the second outer dielectric layer 112, and are alternately stacked along the second direction y. Figure 3 As shown in the example, a first inner dielectric layer 14 is disposed on the second outer dielectric layer 112, a first inner electrode 12 is disposed on the first inner dielectric layer 14, a second inner dielectric layer 14 is disposed on the first inner electrode 12, a second inner electrode 12 is disposed on the second inner dielectric layer 14, and so on.

[0042] The inner dielectric layer 14 can be made of the same material as the first outer dielectric layer 111 and the second outer dielectric layer 112. For example, it can be formed by stacking multiple cast ceramic films, with zinc oxide (ZnO) as the main component and secondary components including, but not limited to, oxides of at least one of bismuth (Bi), cobalt (Co), titanium (Ti), nickel (Ni), manganese (Mn), chromium (Cr), and antimony (Sb), such as Bi2O3, Co2O3, MnO2, Sb2O3, TiO2, Cr2O3, Ni2O3, and other additives.

[0043] Each inner electrode 12 can be arranged in a sheet or a planar shape, for example, made of a metal or alloy material with high conductivity such as copper or silver. The width, length, and overlapping area of ​​the inner electrode 12 can be adaptively set according to actual needs. The figures shown are only illustrative examples and are not limited in the embodiments of this application.

[0044] The terminal electrode 13 is connected to each of the inner electrodes 12. The arrangement of the terminal electrode 13 (e.g., shape and position) can be adapted to actual needs; for example, it can be located on the side of the coupling device 1. Figure 1 The two opposing sides are shown, and connected to the inner electrode 12 extending to the corresponding sides. For example, in Figure 1 and Figure 2 In the scenario shown, a portion of the internal electrode 12 extends to one side of the coupling device 1, while another portion of the internal electrode 12 extends to the other side of the coupling device 1 along the third direction z. For example, in... Figure 3 In the scenario shown, one end of each inner electrode 12 extends to the side of the coupling device 1, thereby connecting to the end electrode 13 located on that side.

[0045] The mark 15 is located between the first outer dielectric layer 111 and the second outer dielectric layer 112. That is, the mark 15 is built into the inside of the coupling device 1, which can prevent the mark 15 from falling off and being damaged by scratches, and can also avoid problems such as poor color rendering caused by electroplating corrosion.

[0046] In practical scenarios, the color rendering index of identifier 15 is higher than that of the multiple inner dielectric layers 14, making the color of identifier 15 relatively more vivid and easier for operators to see. This can be understood as the color density value (i.e., RGB three primary color value) of identifier 15 being greater than the color density value of the main body of the device.

[0047] Please continue reading. Figure 3 The arrangement of identifier 15 in the multilayer chip coupling device 1 may optionally include a multilayer sub-part 151 and a planar part 152.

[0048] Each sub-part 151 is disposed in a via 141 formed in the inner dielectric layer 14 of the corresponding layer. The via 141 is formed by means including but not limited to etching and development, and the paste for preparing each sub-part 151 is poured into the via 141. Each sub-part 151 is spaced apart from the inner electrode 12 of the corresponding layer (i.e., they are not in contact). The material of each sub-part 151 can be a metal material or a ceramic material. For the sub-part 151 made of metal material, the inner electrode 12 and the sub-part 151 of the same layer can be formed in the same process.

[0049] Along the second direction y, the multi-layered sub-parts 151 are connected end to end in sequence, or they can be described as being connected top to bottom in sequence, thereby forming a columnar structure, such as a columnar structure that completely overlaps in orthographic projection. This columnar structure is inserted into the coupling device 1 along the second direction, making it easier to see.

[0050] Optionally, the first outer dielectric layer 111 may also be provided with a through-hole 141 and a corresponding sub-part 151, which together with the plurality of sub-parts 151 below form a columnar structure. Here, the marking 15 is exposed on the surface of the device body, which is convenient for operators to see.

[0051] Please continue reading. Figure 3 The planar portion 152 is disposed on the side of the first outer dielectric layer 111 facing the plurality of inner dielectric layers 14. Specifically, it can be disposed on the upper surface of the inner dielectric layer 14 closest to the first outer dielectric layer 111. The planar portion 152, which is sheet-like or planar, has an area larger than that of the sub-portion 151 and can be seen from above when operating the coupling device 1.

[0052] Optionally, along the second direction y, the orthographic projection of the sub-part 151 of the nearest planar part 152 is located within the orthographic projection of the planar part 152. For example, the orthographic projection of the columnar structure falls within the planar part 152. While achieving the aforementioned easily observable effect, the area occupied by the mark 15 can be saved.

[0053] The planar portion 152 can be circular, elliptical, square, polygonal, etc., and its area can optionally account for 0.125% to 95% of the surface area of ​​the coupling device 1. The height of the planar portion 152 from the surface of the coupling device 1 is H, and the value of H can range from 2μm to 50μm. The sub-portion 151 can be at least one of cylinder, cuboid, cone, sphere, etc. Correspondingly, the orthographic projection shape of the through hole 141 along the second direction y-sight includes at least one of circular, rectangular, rhomboid, etc. The opening area of ​​the through hole 141 is L, and the value of L can range from 25μm. 2 ≤L≤A2, where A2 is the area of ​​the planar portion 152. It should be understood that... Figure 2 L is not the length of the through hole 141 along the third direction z.

[0054] In other scenarios, the identifier 15 may only have one of the sub-part 151 and the planar part 152. For example, it may only have... Figure 1 and Figure 2 The planar portion 152 is disposed on the side of the first outer dielectric layer 111 facing the plurality of inner dielectric layers 14, that is, on the inner side of the first outer dielectric layer 111, or disposed on the inner dielectric layer 14 closest to the first outer dielectric layer 111. Alternatively, for example, only such a planar portion 152 may be disposed. Figure 1 and Figure 2 The sub-part 151 is disposed in the via 141 formed in the first outer dielectric layer 111.

[0055] Further, alternatively, the number of either sub-parts 151 or planar parts 152 can be determined according to the adaptability of the actual scenario. For example, multiple layers of sub-parts 151 and / or multiple layers of planar parts 152 can be provided.

[0056] This application also provides a method for manufacturing a multilayer chip coupling device, which can be used to manufacture the coupling device 1 of any of the foregoing embodiments. For example... Figure 4 As shown, the method includes the following steps S11 and S12.

[0057] S11: Form a device body, the device body comprising a plurality of dielectric layers and multiple internal electrodes stacked alternately along a second direction, with adjacent internal electrodes insulated by a dielectric layer disposed between them.

[0058] S12: A mark is formed between the two outermost dielectric layers, and the mark is at least partially visible on the outside of the device body.

[0059] Given that the coupling device in a real-world scenario also includes other necessary structural elements, such as end electrodes, the manufacturing method may also include other necessary steps, and is not limited to those described above.

[0060] The following is based on Figures 1 to 3 Taking the device body shown as an example, the manufacturing method is described. In step S12, the two outermost dielectric layers can be referred to as the aforementioned first outer dielectric layer and second outer dielectric layer, and each dielectric layer between the two outermost dielectric layers can be referred to as each inner dielectric layer.

[0061] like Figure 5 As shown, the method includes the following steps S21 to S24.

[0062] S21, Provides the first outer dielectric layer.

[0063] S22. A plurality of inner dielectric layers and multiple inner electrodes are formed on the first outer dielectric layer in a second direction and are alternately stacked in sequence. Adjacent inner electrodes are insulated by an inner dielectric layer disposed between them. A planar portion is formed on an inner dielectric layer that is closest to the first outer dielectric layer, and a through-hole is opened in the first outer dielectric layer. A sub-portion is formed in the through-hole, and the orthographic projection of the planar portion covers the orthographic projection of the sub-portion along the second direction.

[0064] S23. A second outer dielectric layer is formed on an electrode layer formed by multiple inner dielectric layers and multiple inner electrodes.

[0065] S24. An end electrode is formed on the side of the stacked chip coupling device and connected to multiple internal electrodes.

[0066] Figure 5 The method shown can be considered as... Figure 4 In step S12 shown, a planar portion is formed on a dielectric layer adjacent to the outermost dielectric layer, and a via is opened in the outermost dielectric layer, and a sub-portion is formed in the via. Along the second direction, the orthographic projection of the planar portion covers the orthographic projection of the sub-portion. Here, the surface of the marking (the sub-portion) is exposed on the surface of the device body, which is beneficial for the operator to see.

[0067] In other scenarios, step S12 can use a material with a higher color rendering index than the dielectric layer to form the marking. The higher color rendering index of the marking compared to the multiple inner dielectric layers makes the marking's color more vibrant and easier for operators to see.

[0068] Additionally, in step S12, forming a marker between the two outermost dielectric layers may include at least one of the following: 1. forming a via in at least one dielectric layer and forming a sub-part in the via; 2. forming a planar portion on at least one dielectric layer between the two outermost dielectric layers. That is, only the sub-part or only the planar portion may be provided.

[0069] Alternatively, the number of either sub-parts or planar parts can be determined based on the specific scenario. For example, multiple layers of sub-parts and / or multiple layers of planar parts can be configured.

[0070] Of course, the sub-parts and planar parts of any implementation scenario can be formed using materials with a higher color rendering index than the dielectric layer.

[0071] Although step designations such as S21 and S22 are used, their purpose is to more clearly and concisely describe the corresponding content, and they do not constitute a substantial restriction on the order. In specific implementation, those skilled in the art may, for example, execute S23 first and then S22, etc., and these should all be within the scope of protection of this application.

[0072] The manufacturing process described above is only a general overview. In actual manufacturing scenarios, the specific implementation details of each step can be found in existing technologies. For example, the entire multilayer chip coupling device can be manufactured using processes such as molding, cutting, debinding and sintering, chamfering, and electroplating.

[0073] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. For those skilled in the art, any equivalent structural transformations made using the content of this specification and drawings are similarly included within the patent protection scope of this application.

[0074] Although this document uses terms such as "first," "second," etc., to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. Furthermore, the singular forms "a," "an," and "the" are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only arise when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

Claims

1. A multilayer chip coupling device, characterized in that, Including the main body of the device and its markings; The main body of the device includes: First outer dielectric layer; The second outer dielectric layer is disposed opposite to the first outer dielectric layer along the height direction of the stacked chip coupling device; Multiple inner dielectric layers; The multilayer internal electrode and the plurality of internal dielectric layers are disposed between the first external dielectric layer and the second external dielectric layer, and are alternately stacked along the height direction of the stacked chip coupling device. Adjacent internal electrodes are insulated by the internal dielectric layer disposed between them. The identifier is located inside the device body, between the first outer dielectric layer and the second outer dielectric layer, and outside the device body, and is at least partially visible. The identifier includes at least one sub-part and / or at least one planar part. The sub-part is disposed in a via opened in the corresponding inner dielectric layer, and the planar part is disposed on any of the inner dielectric layers. Along the height direction of the stacked chip coupling device, the orthographic projection of the planar part covers the orthographic projection of the nearest sub-part.

2. The stacked chip coupling device according to claim 1, characterized in that, The planar portion is disposed on the side of the first outer dielectric layer facing the plurality of inner dielectric layers.

3. The stacked chip coupling device according to claim 1 or 2, characterized in that, A sub-part is provided in the via formed in the first outer dielectric layer.

4. The stacked chip coupling device according to claim 1 or 2, characterized in that, The identifier comprises multiple sub-parts, which are sequentially connected end-to-end along the height direction of the stacked chip coupling device.

5. The stacked chip coupling device according to claim 1, characterized in that, The color rendering intensity of the identifier is higher than that of the plurality of inner dielectric layers.

6. A method for manufacturing a multilayer chip coupling device, characterized in that, include: A device body is formed, the device body comprising a plurality of dielectric layers and multiple internal electrodes that are alternately stacked along the height direction of the stacked chip coupling device, and adjacent internal electrodes are insulated by a dielectric layer disposed between them; A marking is formed between the two outermost dielectric layers and is at least partially visible on the exterior of the device body. The marking includes at least one of the following: A via is formed in at least one of the dielectric layers, and a sub-part is formed in the via; A planar portion is formed on at least one of the dielectric layers between the two outermost dielectric layers; A planar portion is formed on at least one of the dielectric layers between the two outermost dielectric layers, and a via is formed in the dielectric layer adjacent to the planar portion, and a sub-portion is formed in the via, wherein the orthographic projection of the planar portion overlaps the orthographic projection of the sub-portion along the height direction of the stacked chip coupling device.

7. The method according to claim 6, characterized in that, The formation of the identifier between the two outermost dielectric layers includes at least one of the following: A planar portion is formed on a dielectric layer adjacent to the outermost dielectric layer, and a via is formed in the outermost dielectric layer, and a sub-portion is formed in the via, and the orthographic projection of the planar portion covers the orthographic projection of the sub-portion along the height direction of the stacked chip coupling device. The marking is formed using a material with a color rendering index higher than that of the dielectric layer.

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