System and method for clock resynchronization

Abstract

The present disclosure relates to systems and methods for clock resynchronization. A method of processing a data stream includes acquiring a first number of samples of the data stream using a sampling clock within a first observation window, and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A number of measured periods of the sampling clock is determined from the first number of samples. An error between an expected number of periods of the sampling clock in the observation window and the number of measured periods of the sampling clock is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.

Description

Technical Field

[0001] The present invention generally relates to a system and method for clock resynchronization, and in a particular embodiment, to an error correction system and method for an internal clock used in asynchronous communication. Background Technology

[0002] Clock synchronization is a topic in computer science and engineering, aiming to harmonize otherwise independent clocks. Even if initially set accurately, actual clocks will differ over time. This clock drift is caused by the clock counting time at slightly different rates. Communication that relies on counting a fixed number of samples to achieve synchronization can fail due to clock drift.

[0003] In asynchronous transmission between the transmitter and receiver, the receiver clock may drift and lose synchronization with the transmitter clock. Clock drift causes communication between the receiver and transmitter to become out of sync, leading to communication failure. When the receiver applies oversampling to the data received from the transmitter, the receiver's internal clock is used to evaluate the number of samples acquired for each input symbol. However, errors in the internal clock indicate that the evaluation is incorrect. Over time, the accumulated errors in the internal clock can lead to a loss of synchronization. Summary of the Invention

[0004] According to one embodiment, a method for processing a data stream includes: acquiring a first number of samples of the data stream using a sampling clock within a first observation window, and storing a stored data stream including the first number of samples in a data buffer, wherein the length of the first observation window is determined by a reference clock; determining a measurement cycle number of the sampling clock based on the first number of samples; measuring an error between an expected number of cycles of the sampling clock and the measurement cycle number of the sampling clock within the observation window; updating the stored data stream corresponding to the first observation window to include a second number of samples by correcting the first number of samples for the error; and decoding the data stream based on processing the second number of samples.

[0005] According to another embodiment, a method for resynchronizing a data stream includes: oversampling the data stream to form a sampled dataset, wherein the oversampling sampling rate is determined by a sampling clock, and the sampled dataset is stored in a data buffer; counting the number of measurement cycles of the sampling clock within an observation window, wherein the length of the observation window is determined by a reference clock; indicating the end of the observation window by sending a trigger to a data stream recovery method; executing the data stream recovery method, which includes: determining a difference between the number of measurement cycles of the sampling clock within the observation window and an expected number of cycles of the sampling clock within the observation window; adding or subtracting a number of samples equal to the difference from the sampled dataset in the data buffer; and decoding the sampled dataset after executing the data stream recovery method.

[0006] According to another embodiment, a system for processing a data stream includes: a sampling clock having a first frequency; a reference clock having a second frequency less than the first frequency, the reference clock being more accurate than the sampling clock, the reference clock being configured to measure the length of an observation window; a plurality of processors; and a non-transitory memory storing program instructions to be executed in the plurality of processors, the program instructions including instructions for: measuring the difference between an expected number of cycles of the sampling clock in the observation window and a measured number of cycles of the sampling clock in the observation window; and correcting a first number of samples acquired from a transmission within the observation window using the measured difference, wherein the samples are acquired using the sampling clock.

[0007] It should be understood that both the above general description and the following detailed description are exemplary and interpretive only, and not a limitation on the claimed disclosure. Attached Figure Description

[0008] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 An example system including a receiver and a transmitter according to some embodiments is shown;

[0010] Figure 2 This is a block diagram of a method for clock resynchronization according to some embodiments;

[0011] Figure 3 An operational example of a clock error measurement method according to some embodiments is shown;

[0012] Figure 4 An operational example of a data stream recovery method according to some embodiments is shown;

[0013] Figures 5-7Example methods for oversampling and slicing a received data stream according to some embodiments are shown;

[0014] Figures 8-13 The diagram illustrates waveforms sampled at different rates according to some embodiments, the resulting desynchronization, and examples of correcting desynchronization by resynchronization;

[0015] Figure 14 Waveform diagrams according to some embodiments are shown, illustrating a clock recovery algorithm applied to data acquired using a sampling clock with a positive offset;

[0016] Figure 15 Waveform diagrams according to some embodiments are shown, illustrating a clock recovery algorithm applied to data acquired using a sampling clock with a negative offset;

[0017] Figure 16 The implementation of a clock recovery algorithm in an RTL according to some embodiments is illustrated; and

[0018] Figure 17 A block diagram illustrating an example implementation of a clock recovery algorithm on a semiconductor chip according to some embodiments is shown.

[0019] Unless otherwise stated, corresponding numbers and symbols in the various figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the embodiments, and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the termination of the feature range. Detailed Implementation

[0020] The various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein are applicable to a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using the various embodiments and should not be interpreted in a limited manner.

[0021] Within the framework of this specification, references to "embodiment" or "an embodiment" are intended to indicate that a particular configuration, structure, or feature described in connection with that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment," which may appear in one or more places in this specification, do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any suitable manner.

[0022] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments. According to one or more embodiments of this disclosure, this application relates to an error correction system and method for a sampling clock used in asynchronous communication. The asynchronous transmission is received and oversampled by a receiver. The receiver's sampling clock is used to accept samples from the received transmission at a desired frequency to achieve a desired data rate. The clock drift of the sampling clock is measured using a slower and more accurate reference clock. The clock drift measurement provides the clock cycle difference between the current sampling frequency and the desired sampling frequency based on the sampling clock. This clock drift measurement is then used to add or subtract samples from the incoming sample stream to achieve the desired data rate. Embodiments of this disclosure offer advantages by achieving the desired data rate without excessively increased power consumption, excessively increased area consumption (e.g., area on a computer chip), excessively increased design complexity, or excessively reduced processing speed. These advantages can save costs while still providing the desired data rate.

[0023] Embodiments of this disclosure are described in the context of the accompanying drawings. Figure 1 An example system including a receiver and a transmitter is shown. Figure 2 This is a block diagram of the clock resynchronization method. Figure 3 and Figure 4 Operational examples of the clock error measurement method and the data stream recovery method, which are performed as part of the clock resynchronization method, are shown respectively. Figures 5-7 An example of a clock resynchronization method is shown in the context of oversampling and slicing the received data stream. Figures 8-13 The waveforms sampled at different rates are shown, the resulting desynchronization is shown, and the correction of desynchronization is shown by resynchronization. Figure 14 and Figure 15 Examples of clock recovery algorithms applied to data acquired using sampling clocks with positive and negative offsets are shown respectively. Figure 16 The implementation of the clock recovery algorithm in RTL is shown. Figure 17 An example implementation of a clock recovery algorithm on a semiconductor chip is shown.

[0024] Figure 1An example system 50 including a receiver 100 and a transmitter 200 according to some embodiments is shown. The receiver 100 includes an antenna 102, a sampling clock 110 (also referred to as an internal clock), a reference clock 120, a clock error measurement method 130, and a data stream recovery method 140. The transmitter 200 includes an antenna 202. The transmitter 200 utilizes the antenna 202 to propagate a data transmission 210. In some embodiments, the transmission 210 is an asynchronous transmission, such as on-off keying (OOK) modulation of an IEEE 802.11.ba standard carrier. The preamble of the transmission 210 may lack timing information (e.g., Manchester encoding), so the correct detection of incoming data may depend on the accuracy of the receiver 100's internal clock. The receiver 100 may expect a fixed data rate from the transmission 210 and uses its internal clock to count the fixed data rate to select from the oversamples of the transmission 210. Adding and subtracting samples at fixed intervals can reduce or prevent communication loss due to frequency offset of sampling clock 110, thus allowing communication to continue smoothly even when the timing of sampling clock 130 is offset.

[0025] Transmission 210 is received by receiver 100 via antenna 102, and oversampled data streams from transmission 210 are provided to data stream recovery method 140. Next, data stream recovery method 140 uses feedback from reference clock 120 and clock error measurement method 130 to compensate for clock drift of sampling clock 110.

[0026] It should be understood that Figure 1 System 50 is a non-limiting example, and the following embodiments can be implemented in any suitable system, including hardware, software (e.g., Matlab, RTL, etc.), and firmware. In some embodiments, receiver 100 is a wake-up radio using the IEEE 802.11ba standard. However, receiver 100 can be any suitable receiver that uses any protocol such as WiFi, Bluetooth, Bluetooth Low Energy (BLE), ZeegBee, etc.

[0027] Figure 2 This is a block diagram illustrating the operational flow of a clock resynchronization method in receiver 100 according to some embodiments. A sampling clock 110 and a reference clock 120 provide time signals to a clock error measurement method 130. An input data stream 150 is oversampled from a source data stream (such as transmission 210) (see above). Figure 1The input data stream 150 is stored for subsequent processing (e.g., in a data buffer in a non-transitory computer-readable storage medium such as random access memory). After being stored, the input data stream 150 is also referred to as the stored data stream. The data stream recovery method 140 receives a measurement error 132 of the sampling clock 110 and a trigger 134 from the clock error measurement method 130, the trigger 134 being used to determine the desired sampling rate based on the input data stream 150. Even when the sampling clock 110 has an offset from the desired sampling frequency, adding or subtracting samples can achieve the desired data rate. The appropriately sampled data is then output by the data stream recovery block as an output data stream 160 and stored as a stored data stream for subsequent processing (e.g., in a data buffer). Subsequent processing may include decoding the output data stream.

[0028] Sampling clock 110 is used to provide a sampling signal for the rate at which the input data stream 150 is sampled. In an embodiment, the sampling signal is 4 MHz or greater, such as in the range of 4 MHz to 64 MHz, depending on the desired oversampling rate. The sampling signal can be a square wave, sine wave, sawtooth wave, etc. The sampling signal can have an error rate of up to 8%. In some embodiments, sampling clock 110 is an internal clock of receiver 100, such as a clock directly derived from the carrier frequency itself. However, any clock suitable for providing the sampling rate can be used.

[0029] Reference clock 120 is used to correct accumulated errors in the sampling clock 110 rate and provides a slower, more accurate reference signal at a frequency lower than that of sampling clock 110 (e.g., in the range of 1 kHz to 64 kHz). The reference signal can be a square wave, sine wave, sawtooth wave, etc. The reference signal can have an error rate in the range of 20 ppm to 40 ppm. In some embodiments, reference clock 120 is internal to receiver 100 and is a crystal oscillator, etc. However, any clock suitable for providing an accurate reference signal can be used. In some embodiments, reference clock 120 and sampling clock 110 reside on the same semiconductor chip.

[0030] Clock error measurement method 130 receives a sampled signal from sampling clock 110 and a reference signal from reference clock 120. Clock error measurement method 130 then calculates the measurement error 132 of the sampled signal relative to the reference signal within an observation window of fixed length (such as one to sixteen cycles of the reference clock 120). However, any suitable number of cycles can be selected based on the desired accuracy of clock error measurement method 130. Next, clock error measurement method 130 provides the measurement error 132 for the observation window and a trigger 134 indicating the end of the observation window to data stream recovery method 140. Clock error measurement method 130 can be implemented in hardware (e.g., as an application-specific integrated circuit (ASIC)) or in software (e.g., a program stored in a non-transitory computer-readable storage medium for execution by a microprocessor such as a CPU).

[0031] In some embodiments, clock error measurement method 130 continuously calculates measurement error 132 during operation of receiver 100. For example, clock error measurement method 130 may calculate measurement error 132 every cycle of reference clock 120 or every two to sixteen cycles. In this case, the error of sampling clock 110 is continuously corrected and therefore does not accumulate. Clock error measurement method 130 then provides continuous and effective correction of the sampling rate relative to the incoming data (e.g., transmission 210; see above). Figure 1 The length of ) is irrelevant.

[0032] In some embodiments, the clock error measurement method 130 calculates the measurement error 132 only once, such as at the start of operation of the receiver 100. Calculating the measurement error 132 only once reduces the power consumption used in the calculations of the clock error measurement method 130. This can be advantageous for shorter data streams, for which correcting the error of the sampling clock 110 once is sufficient. These shorter data streams can have a length of 2048 samples with an oversampling factor of 16 to 8192 samples with an oversampling factor of 16 within a total time interval of 128 μs to 512 μs. Due to the short length of the data stream, correction of the single measurement error 132 is effective because errors exceeding the single measurement error 132 do not have sufficient time to accumulate significantly.

[0033] Data stream recovery method 140 receives oversampled data from input data stream 150. Using measurement error 132 and trigger 134 provided by clock error measurement method 130, data stream recovery method 140 adds or subtracts samples from input data stream 150 at fixed intervals to achieve the desired data rate in output data stream 160, which can then be stored in a data buffer. Output data stream 160 can be provided to other components of receiver 100. The desired data rate can be matched to the expected data rate of transmission 210 (see above). Figure 1 This allows communication to continue smoothly even when the sampling clock 110 has an offset, and reduces or prevents communication loss.

[0034] The data stream recovery method 140 can be implemented in hardware (e.g., as an application-specific integrated circuit (ASIC)) or software (e.g., a program stored in a non-transitory computer-readable storage medium for execution by a microprocessor such as a CPU), and can be performed during or after runtime. In some embodiments, the data rate is lower than the frequency of the sampling clock 110, and the correction of the data stream recovery method 140 is performed during active runtime (e.g., when the receiver 100 is receiving transmission 210). In some embodiments, the fully oversampled input data stream 150 and the measurement error 132 are saved (e.g., to a computer-readable storage medium), and the algorithm of the data stream recovery method 140 is run offline (e.g., after transmission 210 has been completed) on the saved data.

[0035] Figure 3 An operational example of a clock error measurement method 130 according to some embodiments is shown. An observation window 142 is measured using a reference signal from a reference clock 120. In the illustrated example, the observation window 142 is equivalent to one cycle of the reference clock 120. However, any suitable number of cycles of the reference clock 120 can be used. When the observation window 142 completes, the clock error measurement method 130 marks it with a trigger 134. In some embodiments, the trigger 134 is a pulse, such as a square wave pulse, sent to the data stream recovery method 140. However, any suitable trigger 134 can be used to mark the end of the observation window 142. For example, in some embodiments where subsequent processing of the data stream recovery method 140 is performed offline, the trigger 134 can be the end of a data block stored in the observation window 142.

[0036] Clock error measurement method 130 determines the measurement error 132 of observation window 142. Observation window 142 has a sample N of expected data number determined based on the length of observation window 142 and the expected data sampling rate. expected .exist Figure 3 In the example, N expectedThe value is 5. Clock error measurement method 130 then measures the number of cycles N of the sampled clock 110 in the observation window 142. measured Perform a count. Figure 3 In the example shown, observe window 142's N. measured The measurement error 132 of observation window 142 is 1. measured With N expected The difference between them, Figure 3 In the example, it is 1. Clock error measurement method 130 then provides the measurement error 132 and trigger 134 to data stream recovery method 140.

[0037] The length of the observation window 142 can range from 1 μs to 250 μs and can include 8 to 2000 samples. A longer observation window 142 allows for more accurate detection of frequency errors in the sampling clock 110. However, since subsequent corrections to a number of samples extracted from the input data stream 150 are performed after the end of the observation window 142, a longer observation window may introduce a longer delay for the correction of measurement error 132.

[0038] Figure 4 An operational example of a data stream recovery method 140 according to some embodiments is shown. The data stream recovery method 140 receives a measurement error 132 and a trigger 134 from a clock error measurement method 130. The trigger 134 determines the end of an observation window 142. The measurement error 132 is used by the data stream recovery method 140 to determine how many samples to add or subtract from the input data stream 150 in the observation window 142. The input data stream 150, which may be stored in a data buffer, includes data samples A, B, C, D, E, F, G, H, I, L, and M, of which six samples AF are in the observation window 142.

[0039] exist Figure 4 In the example shown, the measurement error is 1, and the input data stream 150 contains 6 samples A, B, C, D, E, and F counted by the sampling clock 110 in the observation window 143. Since the measurement error 132 is 1, the data stream recovery method 140 subtracts 1 sample from the observation window 142 to realign the output data stream 160 with the desired data rate. This updates the output data stream 160 to have the desired number of samples in the portion of the output data stream 160 corresponding to the observation window 142. As a result, the output data stream 160 contains data samples A, B, C, D, E, F, H, I, L, and M, with five samples AE in the observation window 142. This is the correct expected number N of data samples. expected (See above) Figure 3 ).

[0040] In some embodiments, the data stream recovery method 140 removes redundant samples from the observation window 142 by pushing the last sample (e.g., sample F) into the next observation window and removing subsequent samples (e.g., sample G) from the output data stream 160. In other embodiments, the data stream recovery method 140 removes redundant samples from the observation window 142 in the output data stream 160 by removing redundant samples at the beginning of the observation window 142. Data samples can be removed by deleting samples from the data buffer or by forcing the valid bits of the data samples to zero, such that samples with valid bits set to zero are not processed by subsequent steps of the algorithm (e.g., receiver 100).

[0041] Figures 5-7 Example methods for oversampling and slicing a received data stream according to some embodiments are shown. Figure 5 An example of oversampling and slicing the received data stream is shown when the sampling clock is ideal (in other words, there is no timing error). Figure 6 An example of oversampling and slicing the received data stream is shown when the sampling clock is faster than the ideal rate. Figure 7 An example of oversampling and slicing the received data stream is shown when the sampling clock is slower than the ideal rate.

[0042] exist Figure 5 The system receives an input data stream 150 containing a first symbol 152, a second symbol 154, and a third symbol 156. The symbols can be, for example, pulses in digital baseband transmission, where each symbol has a direct correspondence with a small data unit. For example, a symbol can be a digital bit represented by a pulse of approximately 2 μs in length. However, any suitable symbol used for data transmission can be used.

[0043] The input data stream 150 is expected to be sampled at five times the data rate. It should be understood that five times the data rate is a non-limiting example, and the sampling rate can be any suitable rate, such as eight to sixteen times the data rate. Figure 5In the example, the sampling clock operates at an ideal frequency without error. Thus, the first symbol 152, the second symbol 154, and the third symbol 156 are each sampled five times in the sampled dataset 151. The sampled dataset 151 is then sliced ​​by a processor (e.g., CPU) into a sliced ​​dataset 155 with three data slices. The first data slice contains five samples of the first symbol 152, the second data slice contains five samples of the second symbol 154, and the third data slice contains five samples of the third symbol 156. Algorithms for subsequent processing of the sliced ​​dataset 155 (such as decoding the symbols of the sliced ​​dataset 155) can be implemented in hardware or software. For example, when decoding a transmission with an on / off keying (OOK) format, the processing algorithm can use the desired sampling rate and symbol rate to convert the received data signal into binary values. The decoded binary values ​​can then be further processed to extract, for example, instructions from the data. The processing algorithm is configured to expect five samples for each consecutive symbol in the sliced ​​dataset 155, and for each symbol in which the sampling clock operates at an ideal frequency... Figure 5 For example, five samples of each of the first symbol 152, the second symbol 154, and the third symbol 156 exist in the slice dataset 155.

[0044] exist Figure 6 In the example, the sampling clock was faster than the ideal rate. As a result, the first symbol 152 was sampled five times, the second symbol 154 was sampled six times, and the third symbol 156 was sampled six times to produce a sampled dataset 151'. Subsequently, the sampled dataset 151' was sliced ​​into sliced ​​datasets 155', resulting in a first data slice containing five samples of the first symbol 152, a second data slice containing five samples of the second symbol 154, and a third data slice containing one sample of the second symbol 154 and four samples of the third symbol 156, with two additional samples of the third symbol. This differs from the expected processing algorithm of five samples for each consecutive symbol and may lead to errors.

[0045] To reduce or prevent these errors, data stream recovery method 140 (see above) Figure 4 The measurement error 132 from clock error measurement method 130 is used to determine the correct number of samples to be subtracted from the sampled dataset 151'. Figure 6 In the example, two samples were removed: the second symbol 154 and the third symbol 156. This produces a corrected slice dataset for the output data stream 160, which contains the expected five samples for each of the first symbol 152, the second symbol 154, and the third symbol 156, correcting for errors caused by the faster sampling clock rate.

[0046] exist Figure 7In the example, the sampling clock was slower than the ideal rate. As a result, the first symbol 152 was sampled five times, the second symbol 154 was sampled four times, and the third symbol 156 was sampled five times to produce a sampled dataset 151". Subsequently, the sampled dataset 151 was sliced ​​into sliced ​​datasets 155, resulting in a first data slice containing five samples of the first symbol 152, a second data slice containing four samples of the second symbol 154 and one sample of the third symbol 156, and a third data slice containing four samples of the third symbol 156. This differs from the expected processing algorithm of five samples for each consecutive symbol and may lead to errors.

[0047] To reduce or prevent these errors, data stream recovery method 140 (see above) Figure 4 The measurement error 132 from clock error measurement method 130 is used to determine the correct number of samples to be added to the sampling dataset 151. Figure 7 In the example, an additional sample is added: an additional second symbol 154, which can be done by copying one of the second symbols in the sampled second symbol 154. The resulting corrected slice dataset of the output data stream 160 then contains the expected five samples for each of the first symbol 152, the second symbol 154, and the third symbol 156, thereby correcting for errors caused by the slower sampling clock rate.

[0048] Figures 8 to 13 Examples of waveform 300 sampled at an ideal rate, a rate faster than the ideal rate, and a rate slower than the desired rate according to some embodiments are shown, as well as desynchronization obtained based on the difference from the ideal rate and desynchronization correction by resynchronization. Figure 8 Waveform 300 is shown sampled at an ideal sampling rate (e.g., 16 MHz, shown by dashed lines). In region 300F on the left, waveform 300 is also sampled at an actual sampling rate (shown by solid lines) that is faster than the ideal sampling rate, and in region 300S on the right, waveform 300 is also sampled at an actual sampling rate that is slower than the ideal sampling rate. Region 302 shows a detailed view of the actual sampling rate compared to the ideal sampling rate, and region 304 shows a detailed view of the actual sampling rate compared to the ideal sampling rate.

[0049] Figure 9 An example of desynchronization between the ideal sampling rate (shown as a dashed line) and the actual sampling rate (shown as a solid line) is shown, where the actual sampling rate is slower than the ideal sampling rate in region 300S of waveform 300. The ideal sampling rate and the slower sampling rate are synchronized to the left of region 300S where waveform 300 intersects with the midline, but in circled region 306, the slower sampling rate lags behind the ideal sampling rate by one full sample. Figure 9The example illustrates a significant error between the ideal and actual sampling rates. For clarity, the actual sampling rate is slower than the ideal rate by a greater extent than is possible in a real system. However, even small differences between the actual and ideal sampling clock rates can accumulate over many cycles, significantly increasing the error and leading to desynchronization. For instance, a 1% error between the actual and ideal sampling rates will result in an increase or decrease of one sample every 100 cycles.

[0050] Figure 10 Another example of desynchronization is shown in region 300S of waveform 300, between an ideal clock (sampling time shown as a dot) with an ideal sampling rate (shown as a dashed line) and an actual sampling clock (sampling time shown as a triangle) with a slower sampling rate (shown as a solid line). Waveform 300 is oversampled by the ideal clock to form data slice 307, and waveform 300 is oversampled by the actual clock to form data slice 305. Each data slice in data slice 305 and data slice 307 contains three samples. However, a data slice can contain any suitable number of samples.

[0051] like Figure 10 As shown, data slice 305' and data slice 307' lose synchronization in region 308. This is because the sampling rate of the actual sampling clock is slower than the ideal clock, causing data slice 305' to lag behind data slice 307' by a full clock cycle. This can lead to a difference in the number of symbols expected by the algorithm used for subsequent data processing, resulting in errors.

[0052] Figure 11 This illustrates the resynchronization of data slice 305” and data slice 305' in region 308'. Data slice 305” is generated by forward shifting data slice 305' forward by a suitable number of cycles (e.g., one cycle) of the actual clock. This forward shift can be achieved, for example, through the methods described above. Figures 2-7 The described clock recovery algorithm is used for execution. Resynchronization can reduce or prevent errors in subsequent data processing.

[0053] Figure 12An example of desynchronization between an ideal clock (sampling time shown as a dot) with an ideal sampling rate (shown as a dashed line) and an actual sampling clock (sampling time shown as a triangle) with a faster sampling rate (shown as a solid line) in region 300F of waveform 300 is shown. Waveform 300 is oversampled by the ideal clock to form data slice 307, and waveform 300 is oversampled by the actual clock to form data slice 305. However, data slice 305' and data slice 307' lose synchronization in region 310. This is because the sampling rate of the actual sampling clock is faster than the ideal clock, causing data slice 305' to lead the ideal clock by one full cycle. Since the data slices contain a different number of symbols than expected, this can introduce errors in algorithms used for subsequent data processing.

[0054] Figure 13 This illustrates the resynchronization of data slice 305” and data slice 305' in region 310'. Data slice 305” is generated by shifting data slice 305' backward by a suitable number of cycles (e.g., one cycle) of the actual clock. This backward shift can be achieved, for example, as described above regarding... Figures 2-7 The described clock recovery algorithm is used to reduce subsequent errors in data processing.

[0055] Figure 14 A waveform diagram 400 according to some embodiments is shown, illustrating a clock recovery algorithm applied to data acquired using a sampling clock with a positive offset (in other words, a sampling clock faster than the desired data rate). Diagram 400 includes a sampling clock 402, a trigger 404, a sampled data stream 406, and a corrected data stream 408. The trigger 404 is a pulse indicating the end of the observation window and the start of the clock recovery correction phase. After the trigger 404, samples in the sampled data stream 406 are suppressed in the corrected data stream 408 by forcing the sample values ​​from 1 to 0. This is applied until the correct number of samples have been suppressed to compensate for the positive offset of the sampling clock 402.

[0056] Figure 15 A waveform diagram 500 according to some embodiments is shown, illustrating a clock recovery algorithm applied to data acquired using a sampling clock with a negative offset (in other words, a sampling clock slower than the desired data rate). Diagram 400 includes a sampling clock 502, a trigger 504, a sampled data stream 506, and a corrected data stream 508. After the trigger 504, indicating the start of the clock recovery correction phase, samples are added to the sampled data stream 506 within the corrected data stream 508. This is achieved by setting the value of the trough between samples in the corrected data stream 508 from 0 to 1. This is applied until the correct number of samples has been added to compensate for sample loss due to the negative offset from the sampling clock 502.

[0057] Figure 16 An implementation of a clock recovery algorithm in an RTL according to some embodiments is shown. Figure 16 The clock recovery algorithm will address the above regarding Figure 2 and Figure 4 The described data stream recovery method 140 is implemented as a hardware algorithm. However, Figure 16 The clock recovery algorithm described in the paper can also be implemented in software.

[0058] Figure 17 A clock recovery algorithm on a semiconductor chip 1000 according to some embodiments is shown (e.g., the one mentioned above). Figures 2-4 A block diagram illustrating an example implementation of the described clock recovery algorithm. Semiconductor chip 1000 includes circuitry for waking a radio using the IEEE 802.11ba standard. As shown, the clock recovery algorithm is applied to the data stream from an ADC coupled to an antenna. However, the clock recovery algorithm can be implemented using any suitable circuitry or software stored in a computer-readable storage medium for execution by a microprocessor and integrated into any suitable chip, die, storage medium, or device.

[0059] The exemplary embodiments of this disclosure are summarized herein. Other embodiments may also be understood from the entire specification and the claims set forth herein.

[0060] Example 1. A method for processing a data stream, the method comprising: acquiring a first number of samples of the data stream using a sampling clock within a first observation window, and storing a stored data stream including the first number of samples in a data buffer, wherein the length of the first observation window is determined by a reference clock; determining a number of measurement cycles of the sampling clock based on the first number of samples; measuring an error between an expected number of cycles of the sampling clock and the number of measurement cycles of the sampling clock within the observation window; updating the stored data stream corresponding to the first observation window to include a second number of samples by correcting the first number of samples with the error; and decoding the data stream based on processing the second number of samples.

[0061] Example 2. According to the method of Example 1, wherein the data stream comprises multiple frames, the method further comprises: acquiring a third number of samples of the data stream using the sampling clock within a second observation window, the stored data stream comprising the third number of samples, wherein the length of the second observation window is determined by the reference clock; and updating the stored data stream corresponding to the second observation window to include a fourth number of samples by correcting the third number of samples with the error, wherein the decoding of the data stream is further based on processing the fourth number of samples.

[0062] Example 3. The method according to Example 1 or 2, wherein the reference clock has a frequency slower than the sampling clock.

[0063] Example 4. The method according to any one of Examples 1 to 3, wherein the reference clock has higher accuracy than the sampling clock.

[0064] Example 5. The method according to any one of Examples 1 to 4, wherein the data stream is an on / off keyed modulation of a carrier.

[0065] Example 6. The method according to any one of Examples 1 to 5, wherein the data stream has no timing information.

[0066] Example 7. The method according to any one of Examples 1 to 6, wherein the sampling clock and the reference clock are on the same semiconductor chip.

[0067] Example 8. The method according to Example 7, wherein the semiconductor chip is part of a wake-up radio.

[0068] Example 9. A method for resynchronizing a data stream, the method comprising: oversampling the data stream to form a sampled dataset, wherein the oversampling sampling rate is determined by a sampling clock, the sampled dataset being stored in a data buffer; counting the number of measurement cycles of the sampling clock within an observation window, wherein the length of the observation window is determined by a reference clock; indicating the end of the observation window by sending a trigger to a data stream recovery method; performing the data stream recovery method; and decoding the sampled dataset after performing the data stream recovery method. The data stream recovery method includes: determining a difference between the number of measurement cycles of the sampling clock within the observation window and an expected number of cycles of the sampling clock within the observation window; and adding or subtracting a number of samples equal to the difference from the sampled dataset in the data buffer.

[0069] Example 10. The method described in Example 9, wherein the data stream is an asynchronous transmission.

[0070] Example 11. The method according to Example 9 or 10, wherein the sampling clock and the reference clock are components of a semiconductor chip.

[0071] Example 12. The method according to Example 11, wherein the semiconductor chip is a component of the receiver.

[0072] Example 13. The method according to any one of Examples 9 to 12, wherein subtracting a sample from the sampled dataset comprises: forcing the valid bits of the sample to zero in the data buffer.

[0073] Example 14. A system for processing a data stream, the system comprising: a sampling clock having a first frequency; a reference clock having a second frequency less than the first frequency, the reference clock being more accurate than the sampling clock, the reference clock being configured to measure the length of an observation window; a plurality of processors; and a non-transitory memory storing program instructions to be executed in the plurality of processors, the program instructions including instructions for: measuring a difference between an expected number of cycles of the sampling clock in the observation window and a measured number of cycles of the sampling clock in the observation window; and correcting a first number of samples acquired from a transmission within the observation window using the measured difference, wherein the samples are acquired using the sampling clock.

[0074] Example 15. The system according to Example 14, wherein the sampling clock and the reference clock are part of the receiver.

[0075] Example 16. The system according to Example 15, wherein the receiver is a wake-up radio.

[0076] Example 17. The system according to Example 16, wherein the program instructions are configured to correct the number of samples while the receiver receives the transmission.

[0077] Example 18. The system according to Example 16, wherein the program instructions are configured to: correct the number of samples after the receiver receives the transmission.

[0078] Example 19. The system according to any one of Examples 16 to 18, wherein the program instructions further include instructions for forcing a corresponding valid bit of a second number of samples to zero when the number of measurement periods is greater than the expected number of periods, the second number of samples being equal to the measured difference.

[0079] Example 20. The system according to any one of Examples 16 to 19, wherein the program instructions further include instructions for replicating a second number of samples when the number of measurement cycles is less than the expected number of cycles, the second number of samples being equal to the measured difference.

[0080] Although the specification has been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. In different drawings, the same elements are indicated by the same reference numerals. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, and as will be readily understood by those skilled in the art from this disclosure, existing or future processes, machines, manufactures, compositions of matter, means, methods, or steps may perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. A method for processing a data stream, the method comprising: Within a first observation window, a first number of samples of the data stream are acquired using a sampling clock, and a storage data stream including the first number of samples is stored in a data buffer, wherein the length of the first observation window is determined by a reference clock. The number of measurement cycles of the sampling clock is determined based on the first number of samples; In the first observation window, the error between the expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock is measured; The stored data stream, comprising the first number of samples, is updated to include a second number of samples by correcting the first number of samples with the error; and The data stream is decoded based on the processing of the second number of samples.

2. The method of claim 1, wherein the data stream comprises a plurality of frames, and the method further comprises: Within a second observation window, a third number of samples of the data stream are acquired using the sampling clock, and another stored data stream including the third number of samples is stored in the data buffer, wherein the length of the second observation window is determined by the reference clock; and The other stored data stream, which includes the third number of samples, is updated by correcting the third number of samples with the error to include a fourth number of samples, and the decoding of the data stream is also based on the processing of the fourth number of samples.

3. The method of claim 1, wherein the reference clock has a frequency slower than the sampling clock.

4. The method of claim 1, wherein the reference clock has higher accuracy than the sampling clock.

5. The method according to claim 1, wherein the data stream is a carrier on / off keyed modulation.

6. The method according to claim 1, wherein the data stream has no timing information.

7. The method according to claim 1, wherein the sampling clock and the reference clock are on the same semiconductor chip.

8. The method of claim 7, wherein the semiconductor chip is part of a wake-up radio.

9. The method of claim 1, wherein the sampling clock provides a sampling signal in the range of 4MHz to 64MHz.

10. A method for resynchronizing a data stream, the method comprising: The data stream is oversampled to form a sampled dataset, wherein the oversampling rate is determined by a sampling clock, and the sampled dataset is stored in a data buffer. The number of measurement cycles of the sampling clock within the observation window is counted, wherein the length of the observation window is determined by the reference clock; The end of the observation window is indicated by sending a trigger to the data stream recovery method; After sending the trigger to the data stream recovery method, in response to receiving the trigger, the data stream recovery method is executed, the data stream recovery method comprising: Determine the difference between the number of measurement cycles of the sampling clock within the observation window and the expected number of cycles of the sampling clock within the observation window; and Add or subtract a number of samples equal to the difference from the sampled dataset in the data buffer; and After executing the data stream recovery method, the sampled dataset is decoded.

11. The method of claim 10, wherein the data stream is an asynchronous transmission.

12. The method of claim 10, wherein the sampling clock and the reference clock are components of a semiconductor chip.

13. The method of claim 12, wherein the semiconductor chip is a component of the receiver.

14. The method of claim 10, wherein subtracting a sample from the sampled dataset comprises forcing the valid bits of the sample to zero in the data buffer.

15. A system for processing data streams, the system comprising: A sampling clock, the sampling clock having a first frequency; A reference clock having a second frequency less than the first frequency, and a frequency smaller than the sampling clock, wherein the length of the observation window is determined by the reference clock; Multiple processors; as well as Non-transitory memory stores program instructions to be executed in the plurality of processors, the program instructions including instructions for the following: Measure the difference between the expected number of cycles of the sampling clock in the observation window and the measured number of cycles of the sampling clock in the observation window; as well as The number of samples of a first number of samples acquired from the transmission within the observation window is corrected by the measured difference, wherein the samples are acquired using the sampling clock.

16. The system of claim 15, wherein the sampling clock and the reference clock are part of the receiver.

17. The system of claim 16, wherein the receiver is a wake-up radio.

18. The system of claim 16, wherein the program instructions include: While the receiver receives the transmission, the number of samples of the first number of samples is corrected.

19. The system of claim 16, wherein the program instructions include: After the receiver receives the transmission, the number of samples of the first number of samples is corrected.

20. The system of claim 15, wherein correcting the number of samples of the first number of samples includes forcing the corresponding valid bits of the second number of samples to zero when the number of measurement periods is greater than the expected number of periods, the number of samples of the second number of samples being equal to the measured difference.

21. The system of claim 15, wherein correcting the number of samples of the first number of samples further comprises replicating a second number of samples when the number of measurement periods is less than the expected number of periods, the number of samples of the second number of samples being equal to the measured difference.

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