Running smaller memory address width program code in larger memory address width address spaces

Abstract

Methods and systems are provided for running a smaller memory address width program in a larger memory address width address space. The method includes dividing the smaller memory address width program executable code into a set of sections, reserving a first virtual storage area in a portion of the address space that uses smaller memory address width address accesses, and reserving a set of second virtual storage areas in a portion of the address space that uses larger memory address width address accesses to accommodate the program executable code. The method provides a relocation mechanism to relocate a processor thread by using a relocation factor to convert from an address in the reserved first virtual storage area to a second virtual storage area in the set of second virtual storage areas that contains executable code.

Description

Background Technology

[0001] This invention relates to computer addressing modes, and more specifically, to running a program with a smaller memory address width in a larger memory address width address space.

[0002] Addressing mode (AMODE) is used to identify the number of bits a program uses to store addresses. AMODE-31 programs use 31-bit memory addresses; they use four-byte fields and four-byte registers to contain them. AMODE-64 programs use 64-bit memory addresses; they use eight-byte fields and eight-byte registers to contain them.

[0003] RMODE describes where a program must reside in memory. An RMODE-31 program must reside in memory that can be accessed using 31-bit addresses, i.e., within the first 2GB of the address space, also known as "below the bar." An RMODE-64 program must reside in memory that can be accessed using 64-bit addresses, i.e., anywhere within the 64-bit architecture address space. An RMODE-64 program can and preferably resides in memory above the first 2GB, also known as "above the bar."

[0004] Modern computer architectures typically support 64-bit virtual memory addresses, but older versions of these same architectures often support smaller addresses, such as 8-bit, 16-bit, 24-bit, 31-bit, or 32-bit. 64-bit architectures are designed to run AMODE-64 programs, but many can also run older versions of programs from that architecture. Techniques that allow this include emulation and bimodal or trimodal operation. Other useful techniques for this include form-to-reality conversion programs to provide interoperability between software modules whose routines cannot call each other, and in which code is inserted into the calling process (and possibly into the return process).

[0005] Dual-mode operation allows programs to execute in two addressing modes. Application servers widely utilize this capability; it allows users to continue leveraging applications developed over decades by running them unchanged on the most modern processors. Furthermore, users continue to develop new AMODE-31 programs for various reasons. In an installation, the amount of under-strip memory occupied by RMODE-31 programs can be substantial and continuously increasing. Users of such installations may wish to "free up" under-strip memory with RMODE-31 programs so that more storage can be available for data, or more programs can be loaded into the address space, or both.

[0006] This issue also applies in other cases where applications need to be built for a memory address width smaller than the memory address width that the runtime can support. Summary of the Invention

[0007] According to one aspect of the present invention, a computer-implemented method for running a program with a smaller memory address width in a larger memory address width address space is provided, comprising: dividing the executable code of the smaller memory address width program into a partial set; reserving a first virtual memory region in the portion of the address space accessed using addresses with a smaller memory address width; reserving a second set of virtual memory regions in the portion of the address space accessed using addresses with a larger memory address width to accommodate the executable code; and providing a relocation factor for a processor thread to translate from an address in the reserved first virtual memory region to a second virtual memory region containing the executable code in the reserved second virtual memory region.

[0008] According to another aspect of the invention, a computer program product is provided for running a program with a smaller memory address width in a larger memory address width address space, wherein, during program execution, the method includes: receiving an access request for executable code of the program on a processor thread; searching for a first storage region reserved for the processor thread in a portion of the address space accessed using a smaller memory address width address; searching for a relocation factor for the processor thread to obtain a relocation factor; and using the relocation factor to translate an address in the reserved first storage region to a second virtual storage region in a set of second virtual storage regions accessed using a larger memory address width address in a portion of the address space containing the executable code of the program, wherein the reserved second storage region contains code being executed in the reserved first storage region.

[0009] According to another aspect of the present invention, a computer system for running a smaller memory address width program in a larger memory address width address space is provided, comprising: a processor and a memory configured to provide computer program instructions to the processor to perform functions of various components; and an address reservation component comprising: a partitioning component for partitioning smaller memory address width program executable code into a set of portions; a first storage region reservation component for reserving a first virtual storage region in a portion of the address space accessed using smaller memory address width addresses; a second storage region reservation component for reserving a second set of virtual storage regions in a portion of the address space accessed using larger memory address width addresses to accommodate the program executable code; and a relocation factor providing component for providing a relocation factor for a processor thread to translate from an address in the reserved first virtual storage region to a second virtual storage region in the reserved second virtual storage region containing the executable code.

[0010] The system may further include a runtime relocation component, comprising: an access request receiving component for receiving an access request for executable code of the program on a processor thread; a first memory region lookup component for looking up a relocation region register for the processor thread to identify a reserved first memory region; a relocation factor lookup component for looking up a relocation factor register for the processor thread to obtain a relocation factor; and an address translation component for using the relocation factor to translate an address in the reserved first memory region to a second memory region containing code executed in the reserved first memory region.

[0011] According to another aspect of the present invention, a computer program product for running a smaller memory address width program in a larger memory address width address space is provided, the computer program product comprising a computer-readable storage medium having program instructions implemented therewith, the program instructions being executable by a processor to cause the processor to: divide the smaller memory address width program executable code into a partial set; reserve a first virtual memory region in the portion of the address space accessed using smaller memory address width addresses; reserve a second set of virtual memory regions in the portion of the address space accessed using larger memory address width addresses to accommodate the program executable code; and provide a relocation factor for a processor thread to translate from an address in the reserved first virtual memory region to a second virtual memory region containing the executable code in the reserved second virtual memory region.

[0012] According to another aspect of the invention, a computer program product is provided for running a program with a smaller memory address width in a larger memory address width address space, the computer program product comprising a computer-readable storage medium having program instructions implemented therewith, the program instructions being executable by a processor to cause the processor to: receive, on a processor thread, an access request for executable code of the program; locate a first storage region reserved for the processor thread in a portion of the address space accessed using a smaller memory address width address; locate a relocation factor for the processor thread to obtain a relocation factor; and use the relocation factor to translate from an address in the reserved first storage region to a second virtual storage region in a set of second virtual storage regions accessed using a larger memory address width address that contains the executable code of the program, wherein the reserved second storage region contains code being executed in the reserved first storage region.

[0013] Computer-readable storage media may be non-transitory computer-readable storage media, and computer-readable program code may be executed by processing circuitry. Attached Figure Description

[0014] The subject matter of the invention is specifically pointed out and clearly claimed in the conclusion section of the specification. The organization and operation of the invention, as well as its objects, features, and advantages, can be best understood by referring to the following detailed description when read in conjunction with the accompanying drawings.

[0015] Preferred embodiments of the invention will now be described by way of example only with reference to the following figures, wherein:

[0016] Figure 1 This is a flowchart of an example embodiment of the method according to the present invention;

[0017] Figure 2 This is a flowchart of an example embodiment of one aspect of the method according to the present invention;

[0018] Figure 3 This is a flowchart illustrating an example embodiment of another aspect of the method according to the present invention;

[0019] Figure 4 This is a schematic diagram illustrating the method according to the present invention;

[0020] Figure 5 This is a block diagram of an example embodiment of the system according to the present invention; and

[0021] Figure 6 This is a block diagram of an embodiment of a computer system or cloud server in which the present invention can be implemented.

[0022] It should be understood that, for the sake of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, for clarity, the dimensions of some elements may be enlarged relative to others. Furthermore, where deemed appropriate, reference numerals may be repeated in the figures to indicate corresponding or similar features. Detailed Implementation

[0023] The method and system allow smaller memory address width programs to reside outside the smaller memory address width addressable portion of the address space and run in a smaller memory address width addressing mode. This enables smaller memory address width programs to run on larger memory address width architectures while freeing up space in the smaller memory address width portion of the address space and utilizing the larger available space in the larger memory address width portion of the address space.

[0024] The terms "smaller memory address width" and "larger memory address width" are used to describe any suitable pair of smaller memory address width addresses and larger memory address width addresses. In the example described, the smaller memory address width address is a 31-bit address, while the larger memory address width address is a 64-bit address.

[0025] In the method described, for any given program, when it executes, there are two virtual memory regions in the same address space. The first region is located in a portion of the address space where the smaller address width is sufficient, and the second region is one of a set of regions located in a much larger portion of the address space that requires a larger address width. A relocation mechanism is provided that allows a thread to access executable code located in the second region using an address within the first region.

[0026] refer to Figure 1 Flowchart 100 illustrates an example embodiment of the described method.

[0027] The application in the executable code with a smaller memory address width is divided into a set of 101 parts. This division takes into account the links between them to ensure that no part contains pointers to another part. A single executable object of the static linker works as a part because any pointers it contains do not point to any other such object. This observation simplifies the process of dividing the application code. Furthermore, the division can include more than one object in the same part, and an existing object can be divided into two objects, as long as the code in one object is not statically linked to the code in the other object.

[0028] Reserve 102 for a first virtual memory region accessed by addresses with smaller memory address widths, whose size is at least large enough to contain the largest code portion in the code portion set. Reserve 103 for a second set of memory regions that must be accessed by addresses with larger memory address widths. Each second memory region in the second set of memory regions may be the same size as the first region. Alternatively, the second memory regions may be allocated such that each second memory region matches the size of the application portion it contains.

[0029] The method provides a 104 relocation region register for the processor thread to identify a reserved first memory region, and a 105 relocation factor register with a relocation factor for the processor thread to access a second set of memory regions based on address translations within the first memory region.

[0030] The software needs to provide these values ​​to the hardware, which then makes them available for its own use. The term "register" is used as a common, general term for memory locations used in this way. In an exemplary implementation, this can be done using fields from a z / Architecture (z / Architecture is a trademark of IBM) schedulable unit control table (DUCT), which can also be described as a register.

[0031] At runtime, the method running the application uses a relocation mechanism to look up the relocation region register associated with the processor thread to identify addresses within a reserved first memory region. The relocation mechanism also looks up a relocation factor register for the processor thread to provide address translation within the first memory region, thereby allowing access to a second memory region within a second memory region set. This allows threads to access executable code within a second memory region within a second memory region set using smaller memory address widths. Different relocation factors are provided for different threads and for the same thread at different times to access different sets of second memory regions, thus allowing different executable code to be obtained using the same first memory region.

[0032] Using examples of 31-bit addressing mode (AMODE-31) and 64-bit addressing mode (64-AMODE), the method can access AMODE-31 executable code in on-strip virtual memory using under-strip virtual memory addresses. This allows the executable code to use a 31-bit address to reference itself (e.g., when branching or accessing constants). The executable code can also still use 31-bit addresses to access data and other programs in under-strip memory. Thus, the executable code can run in AMODE-31 even if it resides in on-strip memory (RMODE-31).

[0033] When a 31-bit address is used to access on-strip virtual memory containing executable code, the relocation mechanism adds a 64-bit offset or relocation factor associated with the thread to the 31-bit address to calculate the 64-bit address. This addition process is transparent to the executable code.

[0034] Different relocation factors can be used so that different threads (or the same thread at different times) can access different barcode on-site storage containing different executable code. In this way, the same range of bar-side virtual addresses can be used for different portions of executable AMODE-31 code residing in different ranges of bar-side virtual addresses.

[0035] refer to Figure 2 Flowchart 200 illustrates a more detailed example embodiment of the described method. In this example embodiment, the smaller memory address width is a 31-bit address, where the first virtual memory space is "under-strip" and occupies the first 2GB of the address space, and the larger memory address width is a 64-bit address, where the second virtual memory space is "on-strip". About Figure 2 The described method can be used for other pairs of smaller memory address widths and larger memory address widths.

[0036] This method divides the entire application executable code in 31-bit addressing mode into several parts. Further details of this division, and its adaptation to the linking between programs, will be described below.

[0037] This method reserves a region in the memory stored under instruction 202, which is at least large enough to contain the largest of these portions. The method uses a relocation region register associated with the processor thread to identify the reserved region in the memory stored under instruction 203. For example, the relocation region register may contain the address and length of the region, or the start and end addresses of the region. The relocation region register can be provided in almost the same way that the instruction address register is associated with the processor thread.

[0038] This method preserves a set of 204 regions stored on the upper edge of the strip, each region being the same size as the reserved region stored below the strip. The number of regions in this set is at least equal to the number of parts obtained by partitioning the executable code. The method calculates a relocation factor for each of the 205 reserved regions on the upper edge of the strip, where the address at the displacement within the lower edge region is given by adding the relocation factor to the address at the same displacement within the upper edge region.

[0039] This method uses a relocation factor register to associate the calculated relocation factor with the processor thread, which is roughly the same as the way the instruction address register is associated with the processor thread.

[0040] This method uses a 207 relocation mechanism to access the on-strip storage, where relocation is performed from the under-strip address in the under-strip storage.

[0041] refer to Figure 3 Flowchart 300 illustrates an example embodiment of a method for accessing instructions or data stored using the described storage method. A relocation mechanism can perform the described access method.

[0042] For any executing program, there are two virtual memory regions within the same address space. The first memory region is located in the portion of the address space where the smaller address width is sufficient, while the second memory region is one of a set of regions located in a much larger portion of the address space that requires a larger address width. A relocation mechanism is provided that allows a thread to access executable code located in the second memory region using an address within the first memory region.

[0043] The processor thread receives a 301 access request using a smaller memory address width addressing mode and performs a 302 lookup on the relocation region register so that the processor thread can identify any access to memory in the first memory region that has sufficient address space for the smaller address width.

[0044] This method looks up the 303 relocation factor register to obtain the relocation factor associated with the processor thread. The obtained relocation factor is applied to the smaller memory address width address using 304, and the address obtained using 305 is used to access memory in a second memory region that requires a larger address width. This method is used for both instruction and data access.

[0045] refer to Figure 4 Schematic diagram 400 illustrates the described method. Application 410 is divided into n parts 411, with the largest part 412 having a size X. Virtual address space 420 has a partition 425 between a smaller memory address width address space 423 and the remainder of address space 424. In the case where the smaller memory address width address is a 31-bit address, partition 425 is a "bar" at 2GB.

[0046] A first region A421 of size x is reserved in the smaller memory address width address space 423, and a set of n regions (regions B, C, ..., M) 422 of size x is reserved in the remainder of the address space 424. A relocation region register 430 is provided to identify the reserved region A 421 431 for use by the processor thread, and a relocation factor register 440 is provided to provide a relocation factor 441 for the processor thread to translate the address of the first region into one of the regions 422 in the remainder of the address space 424.

[0047] The method described allows a portion of application code to reside in one of the reserved areas of the on-strip storage and run with AMODE-31. Any code running in this processor thread uses 31-bit addresses within the reserved under-strip storage area to access all storage within the on-strip area. References to storage outside the on-strip area, such as calls to services provided by the runtime or operating system, and references to data owned by the runtime or operating system, are unaffected by the relocation process. Code within the application, as well as runtime code invoked by the application, functions in the same way as when the application code resided in the under-strip area.

[0048] This method uses the aforementioned capability to reduce the under-strip storage required by AMODE-31 application code. To achieve this, the runtime uses different on-strip storage regions for different parts of the application code, but relocates the same range of under-strip addresses of the reserved under-strip regions to these different on-strip storage regions.

[0049] The runtime ensures that the correct relocation factor is in the relocation factor register of the processor thread using the application code in that section. Since the relocation factor register is a hardware component, the runtime should likely invoke an operating system service to set its contents.

[0050] Divide the application code into parts

[0051] The above embodiments do not allow a smaller memory address width application code section to access storage in different smaller memory address width application code sections. Equivalently, when one application accesses storage in another application, both applications must be in the same section. The following discussion of aspects of dividing application code into sections addresses this problem.

[0052] When one application calls another, it typically uses one of the following linking mechanisms for the entry point address and return point address.

[0053] In the first mechanism, static linking is provided. The calling program "knows" the memory address of the entry point of the called program. It branches to that address and passes the return address (within itself) as an argument. The called program returns by branching to that return address. It uses a linker or a similar mechanism to combine this group of interconnected programs into a single executable object using static libraries, which can be referred to as a load module in z / Architecture (z / Architecture is a trademark of IBM). This means that static linking calls and returns must access memory within the same load module.

[0054] In the described method, the application code is divided into multiple parts, each containing a single object of an executable static linker. In other words, when the code is divided, the loaded module is in one part.

[0055] In the second mechanism, dynamic linking can be provided. In this case, the calling program is unaware of the storage address of the called program; in some cases, the runtime loads the called program into memory only after the call is made. The calling program invokes the runtime service, passing the name or other token identifying the target program's entry point and the return address. If applicable, the runtime service invokes the target program after it has been loaded into memory. This is a form of dynamic linking that allows interconnected programs to reside in different executable objects.

[0056] In the method described, dynamic linking calls and returns are handled by the runtime, which can therefore modify the relocation factor register if necessary. This allows different loaded modules to reside in different parts.

[0057] When one code section is dynamically linked to another, the relocation value used in the `from` code section must be replaced by the value required by that code section. This is because the two code sections each use the same "first region" sequentially, but use different "second regions." Because the dynamic linking mechanism uses code that is not part of the application, that code is in a position to change the value in the relocation register during the linking process.

[0058] The variation in dynamic linking includes the case where the program loading the application's loading module constructs a table containing entry point addresses. Applications in other loading modules can load the required entry point addresses from the table and branch directly to the target program (somewhat similar to static linking calls). One or more programs that construct the table in this way can be modified to store the address of the "glue" program instead of the target entry point itself. The glue program can then call traditional dynamic linking, allowing the loading module containing the target entry point to reside in a separate section.

[0059] The calling program typically passes data as arguments to the called program. The called program receives the arguments as parameters. Typically, the arguments are either the address of the data (accessed by reference) or the value of the data (accessed by value).

[0060] When invoked according to the reference example, the data itself can be within the calling program's section. If so, the calling program must be in the same section as the called program, or it must be completely excluded from the relocation process.

[0061] In either case, the data can be an address. If it is a storage address within the calling program's section, then the calling program must be in the same section as the called program, or it must be completely excluded from the relocation process.

[0062] Alternatively, the call can be modified so that it copies the referenced data to dynamic storage and instead passes the address of that dynamic storage. This can be achieved by having the compiler generate different calling logic or by having the "conversion" code statically included at runtime or by a runtime linker service call.

[0063] If the application is reentrant, any data within the application remains unchanged.

[0064] In short, loading modules are a natural choice for a part, since direct references from one program to another are usually mediated by a linker (or the like) and restricted to loading modules.

[0065] Links between different loaded modules do not necessarily prevent loaded modules from being in separate sections. When they do prevent it, the called and invoked programs can be included in the same section.

[0066] In some cases, when the target is widely used, a copy of the target program may be included in multiple parts, or the target may be completely excluded from the relocation process and treated as a regular RMODE program with a smaller memory address width.

[0067] refer to Figure 5 The computing system 500 is shown to include at least one processor 501, a hardware module, or circuitry for performing the functions of the described components, which may be software units executing on at least one processor. Multiple processors running parallel processor threads may be provided to enable parallel processing of some or all of the components' functions.

[0068] Memory 502 can be configured to provide computer instructions to at least one processor 501 to perform the functions of the component. Virtual memory space 520 is provided to access the stored executable code 503 with associated relocation region registers 530 and relocation factor registers 540.

[0069] Computer system 500 includes address reservation component 550 for providing code address translation as described herein to provide address relocation, which allows a smaller memory address width program to reside outside the smaller memory address width addressable portion of a larger memory address width address space and to run in a smaller memory address width addressing mode.

[0070] Computer system 500 also includes runtime relocation component 560 for providing address relocation to smaller memory address width programs residing outside the smaller memory address width addressable portion during runtime, while running in smaller memory address width addressing mode.

[0071] Because the relocation factor register 540 is a hardware component, the runtime relocation component 560 can call operating system services to set its contents. The operating system can restrict which programs can set the relocation factor register, and typically, this is done by allowing only operating system code to issue instructions to set the value. Therefore, other code may need to call operating system services on its behalf to set the required value.

[0072] Address reservation component 550 may include partitioning component 551 for partitioning application executable code with smaller memory address widths into sets of portions. Partitioning component 551 may include linking processing component 552 for adapting to linking requirements during partitioning, including providing a single executable object of a statically linked program within a portion.

[0073] Address reservation component 550 may include: a first memory region reservation component 553 for reserving a first virtual memory region in a portion of the address space accessed using a smaller memory address width address; and a second memory region reservation component 554 for reserving a second set of memory regions in a portion of the address space accessed using a larger memory address width address, to accommodate program executable code.

[0074] Address reservation component 550 may include relocation factor calculation component 557 for calculating the relocation factor of the processor thread for each of the second memory region set based on the address of the first memory region, such that adding the relocation factor to the address at the offset in the first memory region gives the address at the same offset in the second memory region.

[0075] Address reservation component 550 may include: relocation region providing component 555 for providing relocation region register 530 to allow processor threads to identify the reserved first memory region; and relocation factor providing component 556 for providing relocation factors to relocation factor register 540 so that processor threads can access a second set of memory regions based on address translations within the first memory region.

[0076] Runtime relocation component 560 may include access request receiving component 561 for receiving access requests for executable code of an application on a processor thread. Runtime relocation component 560 may include first storage region lookup component 563 for looking up relocation region register 530 for a processor thread to identify a reserved first storage region, and relocation factor lookup component 564 for looking up relocation factor register 540 for a processor thread to obtain a relocation factor.

[0077] The runtime relocation component 560 may include a relocation mechanism 565 with an address translation component 566 for translating addresses from a reserved first storage region to a second storage region set using a relocation factor to access executable code in the second storage region set.

[0078] The runtime relocation component 560 may include a dynamic linking component 567 for modifying the relocation factor register during runtime to accommodate dynamic linking calls and returns.

[0079] Figure 6 A block diagram depicting the components of a computing system 500 according to an embodiment of the present invention is provided. It should be understood that... Figure 6 This is merely an illustration of an implementation and does not imply any limitation on the environments in which different embodiments may be implemented. Many modifications can be made to the described environment.

[0080] The computing system may include one or more processors 602, one or more computer-readable RAMs 604, one or more computer-readable ROMs 606, one or more computer-readable storage media 608, device drivers 612, read / write drivers or interfaces 614, and network adapters or interfaces 616, all of which are interconnected via a communication structure 618. The communication structure 618 can be implemented using any architecture designed to transfer data and / or control information between processors (e.g., microprocessors, communication and network processors, etc.), system memory, peripheral devices, and any other hardware components within the system.

[0081] One or more operating systems 610 and applications 611, such as executable code address reservation component 550 and executable code runtime relocation component 560, are stored on one or more computer-readable storage media 608 for execution by one or more processors 602 via one or more corresponding RAMs 604 (typically including cache memory). In the illustrated embodiment, according to embodiments of the invention, each computer-readable storage medium 608 may be a disk storage device such as an internal hard disk drive, CD-ROM, DVD, Memory Stick, magnetic tape, magnetic disk, optical disk, semiconductor storage device such as RAM, ROM, EPROM, flash memory, or any other computer-readable storage medium capable of storing computer programs and digital information.

[0082] The computing system may also include a R / W drive or interface 614 for reading from and writing to one or more portable computer-readable storage media 626. An application program 611 on the computing system may be stored on one or more portable computer-readable storage media 626, read via the corresponding R / W drive or interface 614, and loaded into the corresponding computer-readable storage medium 608.

[0083] The computing system may also include a network adapter or interface 616, such as a TCP / IP adapter card or a wireless communication adapter. Applications 611 on the computing system can be downloaded to the computing device from an external computer or external storage device via a network (e.g., the Internet, a local area network, or other wide area networks or wireless networks) and the network adapter or interface 616. Programs can be loaded from the network adapter or interface 616 into a computer-readable storage medium 608. The network may include copper wire, fiber optic, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers.

[0084] The computing system may also include a display screen 620, a keyboard or keypad 622, and a computer mouse or touchpad 624. Device driver 612 interfaces with the display screen 620 for imaging, the keyboard or keypad 622, the computer mouse or touchpad 624, and / or the pressure-sensing display screen 620 for alphanumeric character input and user selection. Device driver 612, R / W driver or interface 614, and network adapter or interface 616 may include hardware and software stored in computer-readable storage medium 608 and / or ROM 606.

[0085] This invention can be a system, method, and / or computer program product at any possible level of technical detail integration. The computer program product may include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0086] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0087] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or via a network, such as the Internet, a local area network (LAN), a wide area network (WAN), and / or a wireless network, to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the respective computing / processing device.

[0088] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing the status information of the computer-readable program instructions.

[0089] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0090] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0091] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0092] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a different order than indicated in the figures. For example, two blocks shown consecutively may actually be implemented as a single step, executed simultaneously, substantially simultaneously, with partial or complete time overlap, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0093] The computer program product of the present invention includes one or more computer-readable hardware storage devices storing computer-readable program code that can be executed by one or more processors to implement the method of the present invention.

[0094] The computer system of the present invention includes one or more processors, one or more memories, and one or more computer-readable hardware storage devices, wherein the one or more hardware storage devices contain program code executable by the one or more processors via the one or more memories to implement the methods of the present invention.

[0095] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0096] Without departing from the scope of this invention, improvements and modifications may be made to the foregoing.

Claims

1. A computer-implemented method for running a program with a smaller memory address width in a larger memory address width address space, comprising: Divide executable code with a smaller memory address width into partial sets; Reserve a first virtual memory region in the portion of the address space accessed using addresses with smaller memory address widths; A set of second virtual memory regions is reserved in the portion of the address space accessed using larger memory address widths to accommodate the program's executable code; as well as A relocation factor is provided for the processor thread to translate from an address in a reserved first virtual memory region to a reserved second virtual memory region containing the executable code; The first virtual memory region is reserved to be large enough to contain the largest portion of the set of executable code; and different relocation factors are provided to different threads and the same thread at different times to access different sets of second virtual memory regions that use the same first virtual memory region to obtain different executable code.

2. The method of claim 1, comprising: Provide a relocation region register to allow the processor thread to identify a reserved first virtual memory region; as well as Provides relocation factors for processor threads to the relocation factor register.

3. The method of claim 1, further comprising: Based on the address of the first virtual memory region, a relocation factor for the processor thread is calculated for each of the second virtual memory regions in the set of second virtual memory regions, wherein the address at the displacement in the first virtual memory region is given by adding the relocation factor to the address at the same displacement in the second virtual memory region.

4. The method of claim 1, wherein the relocation factor adds a displacement to the smaller memory address width address in the first virtual memory region to calculate the larger memory address width address in one of the second virtual memory regions.

5. The method of claim 1, wherein dividing the smaller memory address width program executable code into a set of portions includes providing a single object of an executable statically linked program within one portion.

6. The method of claim 1, wherein the smaller memory address width program executable code is divided into a set of portions and included in the same portion as the called program, and the calling program is provided therein.

7. The method of claim 1, wherein the smaller memory address width address is one of the group consisting of an 8-bit address, a 16-bit address, a 24-bit address, a 31-bit address, or a 32-bit address, and the larger memory address width address is a 32-bit address or a 64-bit address.

8. The method of claim 1, wherein, The smaller memory address width is a 31-bit address, while the larger memory address width is a 64-bit address, wherein the first virtual memory region is within the first 2GB address space, and the second virtual memory region is located outside the first 2GB address space.

9. A computer program product for running a program with a smaller memory address width in a larger memory address width address space, wherein, during program execution, the computer program product includes program instructions executable by a processing unit to cause the processing unit to perform a method comprising: Receive an access request for the executable code of the program on the processor thread; Locate the first virtual memory region reserved for the processor thread in the portion of the address space accessed using smaller memory address widths; Find the relocation factor for the processor thread to obtain the relocation factor; as well as The relocation factor is used to convert the address in the reserved first virtual memory region to a second virtual memory region in a set of second virtual memory regions in a portion of the address space accessed using a larger memory address width address that accommodates the executable code of the program, wherein the reserved second virtual memory region contains the code being executed in the reserved first virtual memory region; The first virtual memory region is reserved to be large enough to contain the largest portion of the set of executable code; and different relocation factors are provided to different threads and the same thread at different times to access different sets of second virtual memory regions that use the same first virtual memory region to obtain different executable code.

10. The computer program product of claim 9, wherein a first virtual memory region is searched to locate a relocation region register for the processor thread; and The process involves searching the relocation factor register for the processor thread to obtain the relocation factor for that processor thread.

11. The computer program product of claim 9, wherein the relocation factor is used to add a displacement to the smaller memory address width address in the first virtual memory region to calculate the larger memory address width address in one or the second virtual memory region.

12. The computer program product of claim 9, comprising modifying the relocation factor register during runtime to accommodate dynamic linking calls and returns.

13. A computer system for running programs with a smaller memory address width in a larger memory address width address space, comprising: A processor and a memory, wherein the memory is configured to provide computer program instructions to the processor to perform the functions of the components; as well as Address reservation components include: Partitioning is used to divide executable code with a smaller memory address width into partial sets; A first memory region reservation component is used to reserve a first virtual memory region in a portion of the address space accessed using addresses with a smaller memory address width. A second memory region reservation component is used to reserve a set of second virtual memory regions in portions of the address space accessed using larger memory address widths to accommodate executable program code; and A relocation factor providing component is used to provide a relocation factor for a processor thread to translate from an address in a reserved first virtual memory region to a reserved second virtual memory region containing the executable code; The first virtual memory region is reserved to be large enough to contain the largest portion of the set of executable code; and different relocation factors are provided to different threads and the same thread at different times to access different sets of second virtual memory regions that use the same first virtual memory region to obtain different executable code.

14. The computer system of claim 13, wherein, The address reservation component includes: A relocation region providing component is used to provide a relocation region register to allow processor threads to identify a reserved first virtual memory region; and The relocation factor providing component provides a relocation factor for the processor thread to the relocation factor register.

15. The computer system of claim 13, wherein the partitioning component includes a linking processing component for adapting linking requirements at the time of partitioning to provide a single object of executable static linker within a partition.

16. The computer system of claim 14, further comprising a runtime relocation component, the runtime relocation component comprising: An access request receiving component is used to receive access requests for the executable code of the program on a processor thread; The first memory region lookup component is used to look up the relocation region register for the processor thread to identify the reserved first virtual memory region; A relocation factor lookup component is used to look up the relocation factor register for the processor thread to obtain the relocation factor; as well as An address translation component is used to translate addresses in a reserved first virtual memory region to a reserved second virtual memory region containing code executed in the reserved first virtual memory region, using the relocation factor.

17. The computer system of claim 16, wherein the runtime relocation component includes a dynamic linking component, the dynamic linking component being configured to modify the relocation factor register during runtime to accommodate dynamic link calls and returns.

18. The computer system of claim 16, wherein the runtime relocation component invokes an operating system service to set the relocation factor register.

19. The computer system of claim 13, wherein, The address reservation component includes: A relocation factor calculation component is used to calculate a relocation factor for a processor thread for each of the second virtual memory regions in the set of second virtual memory regions based on the address of the first virtual memory region, wherein the address at the displacement in the first virtual memory region is given by adding the relocation factor to the address at the same displacement in the second virtual memory region.

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