Searchable array circuit with load-matched signals having reduced hit signal timing margin and related methods

Abstract

A CAM array of compare memory cell circuits includes a decode column corresponding to each set, and each set includes at least one row of compare memory cell circuits. Each decode column receives a set clock signal that addresses the corresponding set and generates a set match signal in each row of the corresponding set. A column compare circuit generates compare data that indicates bits of a compare tag. A row match circuit generates a row match signal for each row indicating that the compare tag matches a binary tag stored in the row in response to the set match signal. Circuitry and loading in the decode column to generate the set clock signal corresponds to circuitry to generate the row match signal in each column of the CAM array to reduce timing margins of match indications and to reduce access times of the CAM array.

Description

Technical Field

[0001] The technology disclosed herein relates to memory arrays, and more specifically to content addressable random access memory (CAM-RAM) arrays. Background Technology

[0002] Computers and electronic devices process information stored in binary form. Many different technologies exist for storing binary data. The technology chosen for storing binary data in a given situation depends on several factors, including the amount of time the binary data must be stored, the frequency of access to the binary data, whether the data must be preserved in the absence of power, and the speed at which the processing element must access the binary data. Binary data can be stored in an array of memory cell circuits on an integrated circuit (IC). The array consists of rows and columns of memory cell circuits efficiently arranged on a semiconductor substrate. If the desired storage location of the binary data in random access memory (RAM) is known, the processor can access the binary information by identifying the rows and columns.

[0003] In some cases, the location of binary data can be tracked using identifiers (often called tags) based on the binary data itself, rather than tracking row and column information. The location of the desired binary data can be found by locating the corresponding identifier. The identifier can consist of some bits of the binary data, or the binary pattern can be generated using an algorithm that takes the binary data as input. The identifier is stored in a location corresponding to the binary data, so that if the identifier is found, the location of the binary data can be determined. In an exhaustive random access method, each identifier in the array can be read and compared with a known identifier of the desired binary data. However, this method significantly increases the time required for the processor to access the desired binary file. Alternatively, a Content Addressable Memory (CAM) has the ability to compare a known identifier of the desired binary data with all identifiers stored in the array. When a matching identifier is found, the location of the desired binary data can be determined. While this method is faster than the exhaustive method, it is desirable to minimize the time required to compare a known identifier with identifiers (tags) within the array, in order to further minimize the data access time of the CAM array. Summary of the Invention

[0004] Exemplary aspects disclosed herein include searchable array circuitry with a load match signal having reduced timing margin for the hit signal. The content-addressable memory (CAM) includes comparison memory cell circuitry in columns and rows storing binary tag bits. Triggered by a clock signal, a comparison tag is compared with binary tags stored in each row of the CAM array to determine in which row (if any) a binary tag matching the comparison tag is stored. A comparison bit signal indicating the comparison tag's comparison bits is provided to each column of the comparison memory cell circuitry for comparison with the corresponding bits of the binary tags stored in each row. The hit signal (also referred to herein as the row match signal) is an indication of the comparison tag that matches the binary tags in the row based on the comparisons in each column.

[0005] In an exemplary aspect, the CAM array includes at least one decoded column, each decoded column corresponding to a set, wherein each set includes at least one row of comparison memory cell circuitry. Each decoded column receives a set clock signal for addressing the corresponding set and generates a set match signal in each row of the corresponding set. Column comparison circuitry generates comparison truth data and comparison complement data in each column, indicating bits of the comparison tag. Row match circuitry generates a row match signal for each row in response to the set match signal, indicating that the comparison tag matches a binary tag stored in the row. In one example, each row may include a row match line, and the row match circuitry may generate a row match signal for that row in response to a row match line indicating that the comparison tag matches a binary tag in the row. Thus, the row match signal is generated in response to a set clock signal triggered by a clock signal and a row match line. The difference between the activation timing of the set clock signal and the indication of a comparison tag match on the row match line depends on the difference in propagation delay, which is affected by variations in the manufacturing process in the corresponding circuitry and the number of loads on the corresponding circuitry. In an exemplary aspect, the circuitry for generating a set clock signal in the decoded column and loading it corresponds to the circuitry for generating a row match signal in each column of the CAM array. This correspondence reduces the timing margin of the match indication and thus reduces the access time of the CAM array.

[0006] In an exemplary aspect, an array of comparison memory cell circuits is disclosed. The array of comparison memory cell circuits includes at least one set, each set including at least one row of a plurality of rows of comparison memory cell circuits, and each row of the plurality of rows is configured to store binary tags. The array of comparison memory cell circuits includes a plurality of columns of comparison memory cell circuits, each column including comparison memory cell circuits in each of the plurality of rows. The array of comparison memory cell circuits includes at least one decoding column, each decoding column corresponding to a set in at least one set, the at least one decoding column being configured to receive a set clock signal for the corresponding set and generate a set matching signal on a set matching line in each row of the corresponding set. The array of comparison memory cell circuits includes a dynamic comparator circuit, the dynamic comparator circuit including a set clock circuit, a column comparison circuit, and a row matching circuit. The set clock circuit is configured to generate a set clock signal to each decoding column in the at least one decoding column for addressing the corresponding set. The column comparison circuit is configured to generate comparison truth data for each column of the plurality of columns, indicating comparison truth bits of the comparison tag. The row matching circuit is configured to generate a row matching signal for each of the multiple rows in response to a set matching signal generated in the row, indicating that the comparison tag matches the binary tag stored in the row.

[0007] In other exemplary aspects, an integrated circuit including an array of comparison memory cell circuits is disclosed. The array of comparison memory cell circuits includes at least one set, each set including at least one row of a plurality of rows of comparison memory cell circuits, and each row of the plurality of rows is configured to store binary tags. The array of comparison memory cell circuits includes a plurality of columns of comparison memory cell circuits, each column of the plurality of columns including comparison memory cell circuits in each row of the plurality of rows. The array of comparison memory cell circuits includes at least one decoding column, each decoding column corresponding to a set in at least one set, the at least one decoding column being configured to receive a set clock signal for the corresponding set and generate a set match signal on a set match line in each row of the corresponding set. The array of comparison memory cell circuits includes a dynamic comparator circuit, the dynamic comparator circuit including a set clock circuit, a column comparison circuit, and a row match circuit. The set clock circuit is configured to generate a set clock signal to each decoding column of the at least one decoding column for addressing the corresponding set. The column comparison circuit is configured to generate comparison truth data for each column of the plurality of columns, indicating comparison truth bits of the comparison tag. The row matching circuit is configured to generate a row matching signal for each of the multiple rows in response to a set matching signal generated in the row, indicating that the comparison label matches the binary label stored in the column. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0009] Figure 1 This is a schematic diagram of a comparator memory cell circuit, which includes a six (6) transistor (6T) static random access memory (SRAM) cell circuit, as well as a truth comparison circuit and a two's complement comparison circuit coupled to the matching line, as used in a content addressable memory (CAM) array;

[0010] Figure 2 This is a schematic diagram of a CAM array, which includes rows of memory cell circuits. Figure 1 The 6TSRAM cell circuit shown;

[0011] Figure 3 This is a timing diagram of the timing margin of the clock used to generate a hit signal, which indicates the comparison tag is stored in... Figure 2 The binary tags in the rows of the CAM array are matched, where the timing margin depends on process variations;

[0012] Figure 4 It is similar to Figure 2 The schematic diagram of the CAM array in the diagram shows that the clock signal has a programmable delay to accommodate process variations, thereby reducing timing margin.

[0013] Figure 5 This is a schematic diagram of an exemplary CAM array, which includes a decoding column corresponding to each set for receiving a set clock signal and generating a set matching signal and generating a hit signal indicating a match with a reduced timing margin.

[0014] Figure 6 This is a schematic diagram of a non-comparison memory cell circuit in a CAM array used to store data of objects that are not being compared.

[0015] Figure 7 This is a schematic diagram of an exemplary modified non-comparison memory cell circuit used to form a non-comparison memory cell circuit with... Figure 5 The circuitry for each row of the comparison memory cell circuitry in the CAM array, corresponding to the decoding column;

[0016] Figure 8 This is a schematic diagram of a CAM array, which includes an alternative example of a non-comparison memory cell circuit in a decoding column, which is further modified to fine-tune the delay between the set match signal and the row match line.

[0017] Figure 9This is a schematic diagram of a CAM array, in which the decoding column is separated from the non-comparison memory cell circuitry; and

[0018] Figure 10 This is a block diagram of an exemplary processor-based system that includes multiple devices coupled to a system bus, wherein any CAM array in the processor-based system can be... Figure 5 , Figure 8 and Figure 9 CAM array in any one of them. Detailed Implementation

[0019] Exemplary aspects disclosed herein include searchable array circuitry with a load match signal having reduced timing margin for the hit signal. The content-addressable memory (CAM) includes comparison memory cell circuitry in columns and rows storing binary tag bits. Triggered by a clock signal, a comparison tag is compared with binary tags stored in each row of the CAM array to determine in which row (if any) a binary tag matching the comparison tag is stored. A comparison bit signal indicating the comparison tag's comparison bits is provided to each column of the comparison memory cell circuitry for comparison with the corresponding bits of the binary tags stored in each row. The hit signal (also referred to herein as the row match signal) is an indication of the comparison tag that matches the binary tags in the row based on the comparisons in each column.

[0020] In an exemplary aspect, the CAM array includes at least one decoded column, each decoded column corresponding to a set, wherein each set includes at least one row of comparison memory cell circuitry. Each decoded column receives a set clock signal for addressing the corresponding set and generates a set match signal in each row of the corresponding set. Column comparison circuitry generates comparison truth data and comparison complement data in each column, indicating bits of the comparison tag. Row match circuitry generates a row match signal for each row in response to the set match signal, indicating that the comparison tag matches a binary tag stored in the row. In one example, each row may include a row match line, and the row match circuitry may generate a row match signal for that row in response to a row match line indicating that the comparison tag matches a binary tag in the row. Thus, the row match signal is generated in response to a set clock signal triggered by a clock signal and a row match line. The difference between the activation timing of the set clock signal and the indication of a comparison tag match on the row match line depends on the difference in propagation delay, which is affected by variations in the manufacturing process in the corresponding circuitry and the number of loads on the corresponding circuitry. In an exemplary aspect, the circuitry for generating a set clock signal in the decoded column and loading it corresponds to the circuitry for generating a row match signal in each column of the CAM array. This correspondence reduces the timing margin of the match indication and thus reduces the access time of the CAM array.

[0021] In description Figures 5-9 Before showing exemplary aspects of content-addressable memory (CAM) arrays, first refer to Figures 1-4 This paper discusses an existing CAM array circuit and its operation. The CAM array is configured to compare, for example, a comparison bit pattern (comparison tag) known to the processor with a bit pattern (binary tag) stored in the CAM array. The location of the binary tag that matches the comparison tag indicates the location where the expected data corresponding to the comparison tag is stored. To minimize the time to access the expected binary data in the CAM array, the time to compare the comparison tag with all binary tags and generate a match indication must be minimized.

[0022] Figure 1 This is a schematic diagram of a comparator memory cell circuit 100 that can be used to store bits of binary tags in a CAM array (not shown). The comparator memory cell circuit 100 includes a six (6) transistor (6T) static random access memory cell circuit 102. The comparator memory cell circuit 100 also includes a truth comparison circuit 104T and a two's complement comparison circuit 104C coupled to a match line 106. The truth comparison circuit 104T and the two's complement comparison circuit 104C are used to compare the truth data 108T in the truth data node 110T and the two's complement data 108C in the two's complement data node 110C with the comparison truth data 112T and the comparison two's complement data 112C, respectively. The two's complement data 108C is complementary to (e.g., opposite to) the truth data 108T. The result of the comparison is indicated on the match line 106.

[0023] During operation, the matching line 106 is pre-charged to the power supply voltage (V) via a pre-charging circuit (not shown). DD Transistor 114A in the truth comparison circuit 104T is coupled to the truth data node 110T, and is supplied with voltage (V) through the truth data node 110T. DD This is achieved when, for example, the truth data 108T is binary "1". In this example, the truth data 108T being binary "0" corresponds to the truth data node 110T being at ground voltage (V). SS (For example, 0 volts). Transistor 114B in the truth comparison circuit compares the two's complement data 112C to binary "1" (voltage V). DD Therefore, if the true data 108T does not match the comparison true data 112T, making both the true data 108T and the comparison complement data 112C binary "1", then transistors 114A and 114B will be turned on and the matching line 106 will be discharged to the ground voltage V. SS This is to indicate a mismatch. Matching line 106 is a wire or conductive element coupled to transistors 114A and 116A.

[0024] Similarly, transistor 116A in the two's complement comparator circuit 104C is coupled to the two's complement data node 110C and is turned on by the two's complement data 108C, which is a binary "1". Transistor 116B in the two's complement comparator circuit is turned on by the comparison truth data 112T, which is a binary "1". Therefore, if the truth data 108T does not match the comparison truth data 112T, such that both the two's complement data 108C and the comparison truth data 112T are binary "1", then transistors 116A and 116B will be turned on and the matching line 106 will be discharged to the ground voltage V. SS Therefore, a discharge state (e.g., 0 volts) of the matching line 106 indicates a mismatch between the true data 108T and the comparison true data 112T, regardless of the polarity of the true data 108T. In a CAM array (not shown), the matching line 106 can be shared among multiple comparison memory cell circuits 100 storing bits of a binary tag. The matching line 106 will remain charged to indicate that all bits of the binary tag stored in the CAM array match the corresponding bits of the comparison tag. The duration for which the matching line 106 discharges depends on the capacitance C of the matching line 106. 106 And the current flowing through the truth comparison circuit 104T or the two's complement comparison circuit 104C. Capacitor C 106 It is determined in part by the length of the matching line 106 and the number of loads (such as transistors to which the matching line 106 is coupled or electrically connected).

[0025] Figure 2 This is a schematic diagram of a CAM array 200, which includes rows 202 of comparator memory cell circuits 204, each comparator memory cell circuit 204 corresponding to... Figure 1 The comparison memory cell circuit 100 in the middle. Figure 2 The CAM array 200 in the diagram includes only one set 206, and set 206 includes only rows 202, but the CAM array 200 may include multiple rows 202 and / or multiple sets 206 (each set having at least one row 202). Row 202 includes six (6) compare memory cell circuits 204, but depending on the number of bits in the binary tag BT stored in row 202, row 202 may include more or fewer compare memory cell circuits 204. Details of one of the compare memory cell circuits 204 are shown for reference. Each compare memory cell circuit 204 corresponds to a column 208 of the CAM array 200. Therefore, any additional row 202 in the CAM array 200 will include a compare memory cell circuit 204 in each of the columns 208.

[0026] The comparison memory cell circuit 204 includes a memory cell circuit 210, which can be... Figure 1 The 6T SRAM cell circuit 102 or other types of memory cell circuits. The comparator memory cell circuit 204 includes... Figure 1 The true value comparison circuit 104T corresponds to the true value comparison circuit 212T, and the two's complement comparison circuit 212C corresponds to the two's complement comparison circuit 104C. The true value comparison circuit 212T and the two's complement comparison circuit 212C compare the true value data 214T stored in the comparison memory unit circuit 204 with the comparison true value data 216T, and compare the two's complement data 214C stored in the comparison memory unit circuit 204 with the comparison two's complement data 216C. The true value data 214T and the two's complement data 214C indicate a bit of the binary tag BT stored in row 202. The comparison true value data 216T and the comparison two's complement data 216C indicate a bit of the comparison tag CT corresponding to the data being accessed by the processor. If the comparison tag CT matches one of the binary tags BT stored in the binary tags BT in the CAM array 200, the data corresponding to the binary tag BT can be accessed in the CAM array 200.

[0027] Each compare memory cell circuit 204 is coupled to a match line 218. Match lines 218 are precharged via a precharge circuit 220 controlled by a match line precharge signal MLP. If a mismatch is detected in any compare memory cell circuit 204 in row 202, match lines 218 are discharged (i.e., pulled down). Match lines 218 and a set clock signal 222 are received in row match circuit 224. The set clock signal 222 indicates that row 202 in set 206 (and any other row 202 in set 206) is the target for comparison with the compare tag CT. If the set clock signal 222 is active, the state of match lines 218 determines whether a hit signal 226 is activated to indicate that the compare tag CT matches the binary tag BT stored in row 202. Each row in row 202 of the CAM array 200 includes one row match circuit in row match circuit 224.

[0028] Returning to the comparator memory cell circuit 204, transistor 228A of the truth comparison circuit 212T is coupled to the truth data node 230T, which stores the truth data 214T in the memory cell circuit 210. Transistor 228B of the truth comparison circuit 212T receives the comparison complement data 216C. If both the truth data node 230T and the comparison complement data 216C are at the power supply voltage V... DDTo indicate a mismatch, transistors 228A and 228B are both turned on, and the truth comparison circuit 212T discharges the matching line 218. Alternatively, if the complement data node 230C of the memory cell circuit 210 and the comparison truth data 216T are both at the power supply voltage V... DD Then the two's complement comparator circuit 212C causes the matching line 218 to discharge.

[0029] The column comparator circuit 232 receives the comparison truth bit 234T and comparison complement bit 234C, which are the truth and complement values ​​of the corresponding bits of the comparison tag CT. The column comparator circuit 232 generates comparison truth data 216T and comparison complement data 216C based on the comparison truth bit 234T and comparison complement bit 234C, respectively. The comparison truth data 216T and comparison complement data 216C are held at the ground voltage V. SS This continues until activated by the clock signal CLK. When the clock signal CLK is activated, one of the comparison data 216T and the comparison complement data 216C is driven to the power supply voltage V based on the values ​​of the comparison truth bit 234T and the comparison complement bit 234C. DD If the true value data 214T does not match the comparison true value data 216T, one of the true value comparison circuit 212T and the two's complement comparison circuit 212C discharges the matching line 218. Similar comparisons are performed in the other comparison memory cell circuits 204 in each column 208 of row 202, and any one of the comparison memory cell circuits 204 can discharge the matching line 218.

[0030] The set clock signal 222 is generated by the set address circuit 236 and activated by the clock signal CLK to address the corresponding set 206. The set address circuit 236 receives the set address signal 238, which is in an active state, to indicate that set 206 is being addressed. When the set address signal 238 is activated and the clock signal CLK is activated, the set address circuit 236 activates the set clock signal 222.

[0031] Since both the set clock signal 222 and the matching line 218 contribute to the hit signal 226 and are both activated in response to the CLK signal, the state of the hit signal 226 is indicated within a timing margin after the activation of the CLK signal. The timing margin depends on the propagation delay of the set address signal 238 through the set address circuit 238 in response to the clock signal CLK, before reaching the set address circuit 236. The timing margin also depends on the time required to discharge the matching line 218 through one or more comparator memory cell circuits 204 in row 202. The time required to discharge the matching line 218 after the activation of the clock signal CLK depends on the propagation delay through the column comparator circuit 232 and the number of loads on the comparison true data 216T and the comparison two's complement data 216C. The number of loads on the comparison true data 216T and the comparison two's complement data 216C depends on the number of rows 202 in the CAM array 200. Furthermore, the time required to discharge the matching line 218 depends on the total capacitance C of the matching line 218. 218 Total capacitance C 218 It depends on the number of compare memory cell circuits 204 (i.e., bits in binary tag BT) to which the match line 218 in row 202 is coupled.

[0032] It is evident that the duration of the propagation delay through the aggregate address circuit 236 is typically much shorter than the time required to discharge the match line 218. The circuit path from the column comparator circuit 232 to the match line 218 is more complex than the path through the aggregate address circuit 236. Furthermore, this propagation timing can be affected by variations in manufacturing processes, resulting in timing uncertainties, which increases the timing margin used to generate an indication of match or mismatch on the hit signal 226.

[0033] The desired outcome is to reduce any propagation timing difference between the circuit path from the set clock signal 222 to the hit signal 226 and the circuit path from the comparison truth bit 234T and the comparison complement bit 234C to the hit signal 224. Reducing such a difference will make it possible to reduce the timing margin of the hit signal 226, which in turn reduces the access time of the CAM array 200.

[0034] Figure 3 This is a timing diagram 300 showing the signals in the CAM array 200, including those for responding to the comparison of the tag CT with the match line 218. Figure 2 The timing margin of the clock signal 222 is generated by indicating whether the binary tag BT in the CAM array matches or does not match.

[0035] In this example, the clock signal CLK is a square wave with a 50% duty cycle, but the duty cycle can be longer or shorter. The low-activity match line precharge signal MLP controlling the precharge circuit 220 is deactivated at time T1 in response to the activation of the clock signal CLK. The comparison truth bit 234T and the comparison complement bit 234C are provided to the column comparator circuit 232 at time T2. In the case of mismatch, the match line 218 is discharged within the timing margin between time T3 and time T4. The hit signal 226 is valid after time T4. At time T5, the clock signal CLK is activated again, and the comparison truth bit 234T and the comparison complement bit 234C are again provided to the column comparator circuit 232 at time T6. In the case of match, the match line 218 does not discharge; however, since the match line 218 can be discharged at any time during the timing margin between time T7 and time T8 in the event of mismatch, the match line 218 in the charging state does not reliably indicate a match until after time T8. Therefore, it is desirable to reduce the timing margin in order to reduce Figure 2 The access time of the CAM array 200 is reduced because reducing the time required for the processor to access the CAM array 200 can increase the processor speed, thereby improving the performance of electronic devices or applications.

[0036] Figure 4 It is similar to Figure 2 A schematic diagram of CAM array 400 in CAM array 200 is shown. In an example of a technique for reducing timing margin, CAM array 400 includes a programmable delay PD in the clock signal CLK to better synchronize the timing of the aggregate clock signal 222 with the discharge time of the matching line 218. The programmable delay PD can add a delay to the clock signal CLK to delay the aggregate clock signal 222 to adjust for manufacturing process variations. Employing a programmable delay PD requires a calibration step in each integrated circuit in which CAM array 400 is fabricated. A CAM array where the circuit paths from aggregate address signal 238 to hit signal 226 and from comparison truth bit 234T (or comparison complement bit 234C) to hit signal 226 are more tightly synchronized (e.g., with a smaller timing margin) without a calibration step would be desirable.

[0037] Figure 5 This is a schematic diagram of an exemplary CAM array 500, which includes a decoded column 502 corresponding to each set 504. Figure 5The CAM array 500 in the diagram includes only one set 504 and therefore includes one decoder column 502, but may include multiple sets 504. The decoder column 502 receives set address signals 506 and generates set match signals 508 in each row 510 of each set 504, such that set match signals 508 and match indications on row match lines 512 are generated within a reduced timing margin. Figure 5 The decoded column 502 corresponding to a single row 510 in set 504 is shown. Before explaining how the decoded column 502 reduces timing margin, a detailed explanation of the comparator memory cell circuit 514 is first provided.

[0038] The CAM array 500 is functionally similar to Figure 2 Corresponding to CAM array 200 in the diagram. Row 510 includes multiple arrays corresponding to... Figure 2 The comparison memory cell circuit 514 corresponds to the comparison memory cell circuit 204 in row 202. The CAM array 500 may include additional sets 504, each additional set including one or more rows 510. Each comparison memory cell circuit 514 includes a truth comparison circuit 516T and a two's complement comparison circuit 516C, which discharge the row matching line 512 in response to a mismatch between the truth data 518T stored in the comparison memory cell circuit 514 and the comparison truth data 520T provided to the CAM array 500. The two's complement comparison circuit 516C is coupled to the row matching line 512 and discharges the row matching line 512 in response to a mismatch between the two's complement data 518C stored in the comparison memory cell circuit 514 and the comparison two's complement data 520C provided to the CAM array 500.

[0039] The CAM array 500 receives comparison truth data 520T and comparison two's complement data 520C on the true comparison bit line 521T and the two's complement comparison bit line 521C, respectively. The truth comparison circuit 516T in the comparison memory cell circuit 514 is coupled to the row matching line 512 of the row 510 including the comparison memory cell circuit 514, and the row matching line 512 is coupled to a fixed voltage, such as the ground voltage V. SS The truth comparison circuit 516T is controlled by the stored truth data 518T and the comparison complement data 520C on the complement comparison bit line 521T. The row matching line 512 is a wire, metal trace, or other conductive element coupled to the truth comparison circuit 516T and the complement comparison circuit 516C. The truth comparison circuit 516T couples the row matching line 512 to the ground voltage V. SSThis indicates that the comparison truth data 520T received on the true comparison bit line 521T does not match the truth data 518T stored in the comparison memory cell circuit 514 (e.g., opposite binary polarity). The time for discharging the row matching line 512 depends on the capacitance C of the row matching line 512. 512 The current capacity of the 516T true value comparison circuit or the 516C two's complement comparison circuit. Capacitor C 512 It is determined in part by the length of the row match line 512 and the number of loads (such as the transistors to which the row match line 512 is coupled or electrically connected).

[0040] The stored truth data 518T is one bit of the binary tag BT stored in row 510. The comparison truth data 520T is a bit of the comparison tag CT provided for comparison with the binary tag BT stored in the CAM array 500. In other words, each of the binary tags BT is stored in multiple comparison memory cell circuits 514 in row 510. The number of bits of the binary tag BT may correspond to the number of columns 522 of the comparison memory cell circuits 514 of the CAM array 500. The true comparison bit line 521T receives the comparison truth data 520T from column 522, and the two's complement comparison bit line 521C receives the two's complement data 520C, which is complementary to the comparison truth data 520T.

[0041] The comparison of the comparison tag CT with the binary tag BT in row 510, and the generation of the indication that the comparison tag CT matches the binary tag BT, are performed by a dynamic comparator circuit 524. The dynamic comparator circuit 524 includes a column comparison circuit 526 that generates comparison truth data 520T on the true comparison bit line 521T for each column 522 and comparison complement data 520C, complementary to the comparison truth data 520T, on the complement comparison bit line 521C of the comparison memory cell circuit 514 in each row 510. The comparison truth data 520T and the comparison complement data 520C are generated based on the comparison truth bit 528T and the comparison complement bit 528C, respectively, in response to the activation of the clock signal CLK. The comparison truth bit 528T and the comparison complement bit 528C indicate the bits of the comparison tag CT.

[0042] As described above, the CAM array 500 includes a decoded column 502 for each set 504. The dynamic comparator circuit 524 includes a set clock circuit 530 that generates a set clock signal 532 for addressing the corresponding set 504 (i.e., the set 504 corresponding to the decoded column 502) to each decoded column 502. The set clock signal 532 is generated based on the set address signal 506 in response to the clock signal CLK. The set clock signal 532 controls the matching in the set 504. Specifically, the set clock signal 532 provided to each row 510 of the set 504 is used to generate a set matching signal 508. The dynamic comparator circuit 524 includes a row matching circuit 534 that receives the set matching signal 508 and the row matching line 512. The row matching circuit 534 generates a row matching signal 536 for each row 510 in response to the set matching signal 508 in row 510, indicating that the comparison tag CT matches the binary tag BT stored in row 510. The row matching signal 536 corresponds to... Figure 2 The hit signal is 226.

[0043] The row match signal 536 is generated based on the row match line 512 and the set match signal 508. The match indication on the row match line 512 and the activation of the set match signal 508 are both triggered by the clock signal CLK. The difference in the corresponding delays of these signals after the activation of the clock signal CLK determines the timing margin. Therefore, these delays are discussed separately below to explain the reduction in timing margin in the row match signal 536. The delay from the activation of the clock signal CLK to the match indication on the row match line 512 depends on several factors.

[0044] Regarding the first factor, the comparison complement data 520C is generated by the column comparator circuit 526 in response to the clock signal CLK based on the comparison complement bit 528C. The comparison complement data 520C and the stored true value data 518T are coupled to the truth comparison circuit 516T in each row 510. The truth comparison circuit 516T includes a storage data transistor 537T1 controlled by the stored true value data 518T and a comparison data transistor 537T2 controlled by the comparison complement data 520C. If the stored true value data 518T and the comparison complement data 520C are both at the same voltage (e.g., power supply voltage V),... DDIf both the stored two's complement data 518C and the comparison data 520T are "1", indicating a mismatch, then both the stored data transistor 537T1 and the comparison data transistor 537T2 are turned on and the row matching line 512 is discharged. Additionally, the two's complement comparator circuit 516C includes a stored data transistor 537C1 controlled by the stored two's complement data 518C and a comparison data transistor 537C2 controlled by the comparison truth data 520T. If both the stored two's complement data 518C and the comparison truth data 520T are "1", indicating a mismatch, then the two's complement comparator circuit 516C is turned on to discharge the row matching line 512.

[0045] Regarding the second factor, the propagation time of the comparison true data 520T is partly determined by the number of rows 510 in the CAM array 500, which corresponds to the number of loads on the wires and the wire length. The comparison true data 520T of each column 522 of the comparison memory cell circuit 514 is coupled to the truth comparison circuit 516T in each row 510. The comparison complement data 520C has the same number of loads as the comparison true data 520T.

[0046] Regarding the third factor, the time required for the line matching line 512 to discharge to indicate mismatch depends on the capacitance C. 512 The capacitor C 512 The discharge time depends on the length and the number of loads on the row match line 512, both of which depend on the number of compare memory cell circuits 514 in row 510 (i.e., the number of columns 522 in row 510). The discharge time also depends on the number of bits in row 510 where the corresponding bits of the binary tag BT stored in row 510 do not match the corresponding bits of the compare tag CT. The number of mismatched bits determines the number of truth comparison circuits 516T and two's complement comparison circuits 516C that discharge the row match line 512 in parallel. The time to discharge the row match line 512 decreases with increasing number of mismatched bits because more truth comparison circuits 516T or two's complement comparison circuits 516C are turned on to discharge the row match line 512 in parallel.

[0047] Decoding column 502 improves the synchronization between the set match signal 508 and the match indication on the row match line 512. The three factors regarding the delay of the row match line 512 described above are compared here with their corresponding factors regarding the set match signal 508.

[0048] First, the pool clock signal 532 is generated by the pool clock circuit 530 in response to the activation of the clock signal CLK, based on the pool address signal 506. The decoded column 502 includes pull-down circuits 538 corresponding to each row 510 of the CAM array 500. The pool clock signal 532 controls the first transistor 540 of the pull-down circuit 538 to be turned on or off (e.g., conducted or not conducted), depending on the state of the pool clock signal 532. The pull-down circuit 538 includes a constant voltage source (e.g., power supply voltage V). DD or ground voltage V SS The second transistor 542 is controlled so that it is always on or always off.

[0049] Specifically, in row 510 of set 504 corresponding to decoded column 502, the second transistor 542 is coupled to the power supply voltage V. DD This keeps the second transistor 542 on (i.e., conducting). In row 510 of set 504 that does not correspond to decode column 502, the second transistor 542 is coupled to ground voltage V. SS To keep the second transistor 542 off (i.e., not conducting). Therefore, the pull-down circuit 538 in row 510 of set 504 corresponding to decode column 502 is controlled by set clock signal 532. The pull-down circuit 538 in row 510 of other sets 504 not corresponding to decode column 502 is always off, regardless of the state of set clock signal 532 coupled to the first transistor 540.

[0050] Secondly, the propagation time of the set clock signal 532 is partially determined by the set clock signal 532 provided to the load (i.e., the first transistor 540) in each of the rows 510. When the set clock signal 532 for set 504 is activated, the set matching line 544 for each row 510 in set 504 is discharged. The set matching signal 508 is generated on the set matching line 544.

[0051] Third, the time required for the set match line 544 to discharge in order to select the row match line 512 in the same row 510 depends on the number of decoding columns 502. This is because the set match line 544 is coupled to the pull-down circuit 538 in each decoding column to increase the number of loads on the set match line 544, even if only one pull-down circuit 538 in the decoding column 502 actually discharges the set match line. Comparing the set match line 544 to the row match line 512, the number of loads on the set match line 544 can be less than the number of columns 522 to which the row match line 512 is coupled, but this difference can be offset by the fact that the length of the set match line 544 is greater than that of the row match line 512, which increases the capacitance of the set match line 544.

[0052] The set-match line 544 extends along row 504 and passes through the decoding column 502 located at the opposite end of the row match circuit 534 in the CAM array 500. Delay circuitry 546 may be included in the row match circuit 534 to further increase the delay of the set-match line 532. On the other hand, row match line 512 is coupled to pre-charge circuit 548, while set-match line 544 is coupled to pre-charge circuit 550.

[0053] As shown above, the delay factors of the matching indications on row matching line 512 and set matching line 544 become very similar due to the addition of decoding column 502. Because of the similarity between the corresponding circuits, manufacturing and process variations tend to affect these two delays to a similar degree. Therefore, the difference between the corresponding delays decreases, which reduces the timing margin of the row matching signal 536.

[0054] Figure 5 The decoded column 502 shown is implemented in a non-comparison memory cell circuit 552 corresponding to row 510. In a CAM array 500 including multiple rows 510, the decoded column 502 will include multiple non-comparison memory cell circuits 552, one corresponding to each row 510. A CAM array 500 including multiple sets 504 will include a decoded column 502 corresponding to each set 504, and each of these decoded columns 502 will include a non-comparison memory cell circuit 552 corresponding to each row 510. Each decoded column 502 will include a set clock circuit 530.

[0055] The non-comparison memory cell circuit 552 is capable of storing stored data (e.g., one bit) that can be read by the read bit circuit 554 in response to the read word line RWL. Typically, information such as process IDs and / or parity bits are stored in the non-comparison memory cell circuit 552 because they are not objects of comparison. The non-comparison memory cell circuit 552 is not included in the truth comparison circuit 516T and the two's complement comparison circuit 516C included in the comparison memory cell circuit 514. Therefore, the decoding column 502 can actually be implemented in the non-comparison memory cell circuit 552 of the CAM array 500. By adding a pull-down circuit 538, a set clock signal 532, and a set match line 544, the decoding column 502 can be incorporated into the existing columns of the non-comparison memory cell circuit 552, as shown in the reference. Figure 6 and Figure 7 As discussed. In this way, the decoding column 502 can be implemented in the CAM array 500 to reduce the timing margin of the row matching signal 536 without increasing its size (i.e., area).

[0056] For example, the first transistor 540 and the second transistor 542 in each of the pull-down circuits 538 can be metal-oxide-semiconductor (MOS) field-effect transistors (FETs). A pool clock signal 532 is coupled to the gate terminal of the first transistor 540 to control conductivity via the pull-down circuit 538. The pool clock circuit 530 can perform a logical AND operation on the pool address signal 506 and the clock signal CLK.

[0057] Figure 6 This is a schematic diagram illustrating details of a non-comparison memory cell circuit 600, including an example of a 6T SRAM cell circuit 602. The 6T SRAM cell circuit 602 includes inverters 604T and 604C that provide cross-coupled real memory node 606T and two's complement memory node 606C. Real memory node 606T and two's complement memory node 606C are written to via pass-through gate 608. Figure 6 In the process, the two's complement storage node 606C is read via the bit read circuit 610, similar to... Figure 5 The read bit circuit 554 is shown. Further details of the 6TSRAM memory cell circuit 602 are beyond the scope of this disclosure and are not presented here. Comparing the compare memory cell circuit 514 with the non-compare memory cell circuit 600, the read bit circuit 610 occupies the area of ​​the non-compare memory cell circuit 600 that would have been occupied by the two's complement compare circuit 516C in the compare memory cell circuit 514. The non-compare memory cell circuit 600 does not include another circuit coupled to the true memory node 606T, wherein the truth compare circuit 516T is located in the compare memory cell circuit 514.

[0058] Figure 7 It includes Figure 6 The non-comparison memory cell circuit 600 and Figure 5 A schematic diagram of the non-compare memory cell circuit 700 of the pull-down circuit 538. At this point, implementation... Figure 5 The decoder column 502 shown only includes the addition of pull-down circuit 538 to the non-comparison memory cell circuit 600 of the CAM array, which reduces timing margin and does not increase area.

[0059] Figure 8 This is an example of a decoding column 800, which includes a non-comparison memory cell circuit 802 corresponding to the non-comparison memory cell circuit 700, and pull-down circuits 804A and 804B coupled to a set match line 806. The set match line 806 corresponds to... Figure 5 The set-matching line 544 is in the middle. Pull-down circuits 804A and 804B load the set-matching line 806 to connect with... Figure 5The loads of the row matching line 512 are matched. These additional loads provide a means to fine-tune the capacitance increase of the set matching line 806 so that the propagation delay of the set matching line 804 better corresponds to the propagation delay of the row matching line 512, thereby further reducing the timing margin of the row matching signal (not shown).

[0060] Figure 9 This is a schematic diagram of a CAM array 900, which includes sets 902A and 902B, each of which includes two rows of 904. Although Figure 9 Not shown in the diagram, but each of line 904 includes multiple compare memory cell circuits for storing bits of the binary tag BT, similar to... Figure 5 The CAM array 900 includes a comparator memory cell circuit 514. The CAM array 900 includes a decoder column 906A corresponding to set 902A and a decoder column 906B corresponding to set 902B. A set clock circuit (not shown) generates a set clock signal 908A for set 902A and a set clock signal 909A for set 902B. Pull-down circuits 910 corresponding to each of rows 904 in decoder columns 906A and 906B receive set matching signals 908A and 908B, respectively. The pull-down circuits 910 can be included in the non-comparator memory cell circuitry, similar to... Figure 5 The non-comparison memory cell circuit 552 (not shown) is included. Alternatively, the decoding columns 906A and 906B may consist only of the pull-down circuit 910 in the CAM array 900, which is separate from the comparison memory cell circuit and the non-comparison memory cell circuit (not shown).

[0061] In each of the pull-down circuits 910 in decoder column 906A, the first transistor 912 receives a set clock signal 908A indicating that set 902A is addressed. In each of the pull-down circuits 910 in decoder column 906B, the first transistor 912 receives a set clock signal 908B indicating that set 902B is addressed. The second transistor 916 in each of the pull-down circuits 910 is coupled to a fixed voltage source. In row 904 of set 902A, the second transistor 916 in decoder column 906A is coupled to the power supply voltage V. DD This causes the pull-down circuit 910 in row 904 of set 902A to be controlled by the set clock signal 908A. Similarly, in row 904 of set 902B, the second transistor 916 in decoder column 906B is coupled to the power supply voltage V. DD Therefore, the pull-down circuit 910 in row 904 of set 902B is controlled by set clock signal 908B.

[0062] However, in row 904 of set 902A, the second transistor 916 in decoder column 906B is coupled to ground voltage V.SS This ensures that the pull-down circuit 910 in row 904 of set 902A in decoder column 906B is always off. In row 904 of set 902B, the second transistor 916 in decoder column 906A is also coupled to the ground voltage V. SS The pull-down circuit 910 in row 904 of set 902B in decoded column 906A is kept off at all times. That is, in decoded column 906A, each pull-down circuit 910 corresponding to each row 904 in set 902A activates the set matching line 918A or 920A in row 904 in response to receiving the set clock signal 908A corresponding to the set 902A. In decoded column 906B, each pull-down circuit 910 corresponding to row 904 in set 902B activates the set matching signal 918B or 920B corresponding to row 904 in response to receiving the set clock signal 908B corresponding to the set 902B. In decoded column 906A, each pull-down circuit 910 corresponding to row 904 in set 902B does not activate set matching signal 918A or 918B, and in decoded column 906B, the pull-down circuit 910 in each row 904 of set 902A does not activate set matching signal 918B or 920B.

[0063] Even if the clock signals 908A and 908B do not control some of the pull-down circuits 910, the first transistor 912 to which they are coupled still provides a load on the capacitors of the clock signals 908A and 908B to better replicate them. Figure 5 The comparison of truth data 520T and complement data 520C in the middle helps reduce the load. Figure 5 Timing margin of the set matching signal 508 and the line matching line 512 in the dataset.

[0064] Figure 10This is an exemplary block diagram of a processor-based system 1000, which includes a processor 1002 (e.g., a microprocessor) that includes instruction processing circuitry 1004. The processor-based system 1000 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing board, mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based system 1000 includes a processor 1002. The processor 1002 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc. More specifically, the processor 1002 can be an EDGE instruction set microprocessor or other processor implementing an instruction set that supports explicit consumer naming for transmitting produced values ​​generated by the execution of producer instructions. The processor 1002 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, processor 1002 includes instruction cache 1006, which serves as temporary fast-access memory for storing instructions accessible to instruction processing circuitry 1004. Instructions fetched or prefetched from memory (such as main memory 1008) via system bus 1010 are stored in instruction cache 1006. Data may be stored in cache memory 1012 coupled to system bus 1010 for low-latency access by processor 1002. Instruction processing circuitry 1004 is configured to process instructions fetched into instruction cache 1006 and process these instructions for execution.

[0065] Processor 1002 and main memory 1008 are coupled to system bus 1010 and can be coupled to peripheral devices included in the processor-based system 1000. It is known that processor 1000 communicates with these other devices by exchanging address, control, and data information on system bus 1010. For example, processor 1002 can transmit bus transaction requests to memory controller 1014 in main memory 1008, which is an example of a slave device. Although... Figure 10 Not shown, but multiple system buses 1010 may be provided, each forming a different architecture. In this example, memory controller 1014 is configured to provide memory access requests to memory array 1016 in main memory 1008. Memory array 1020 includes an array of storage bit cells for storing data. As a non-limiting example, main memory 1008 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0066] Other devices can be connected to system bus 1010. For example... Figure 10 As shown, as an example, these devices may include main memory 1008, one or more input devices 1018, one or more output devices 1020, modem 1022, and one or more display controllers 1024. The input devices 1018 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 1020 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 1022 may be any device configured to allow data exchange with network 1026. Network 1026 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth, etc. TM Networks and the Internet. Modem 1022 can be configured to support any type of desired communication protocol. Processor 1002 can also be configured to access multiple display controllers 1024 via system bus 1010 to control information sent to one or more displays 1028. The multiple displays 1028 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0067] Figure 10 The processor-based system 1000 may include a set of instructions 1030 to be executed by the processor 1002 to implement any desired application according to the instructions. The instructions 1030 may be stored in main memory 1008, the processor 1002, and / or the instruction cache 1006, as an example of a non-transitory computer-readable medium 1032. The instructions 1030 may also reside wholly or at least partially in main memory 1008 and / or the processor 1002 during execution. The instructions 1030 may also be transmitted or received on a network 1026 via a modem 1022, such that the network 1026 includes the computer-readable medium 1032.

[0068] Although computer-readable medium 1036 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processing device and causing the processing device to perform one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0069] Any IC in the processor-based system 1000 can include a CAM array, which includes a decoding column corresponding to each set, each in the decoding column receiving a set address signal, and generating a set match signal in each row of the set, such that the set match signal and the match indication on the row match line are generated within a reduced timing margin, such as... Figure 5 As shown.

[0070] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed using those instructions to perform these steps. Alternatively, these steps may be performed by a combination of hardware and software.

[0071] The embodiments disclosed herein can be provided as a computer program product or software that may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include: machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.); and so on.

[0072] Unless otherwise specified and as can be clearly seen from the preceding discussion, it should be understood that throughout the description, the use of terms such as “processing,” “computing,” “determining,” and “displaying” refers to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data and memory representing physical (electronic) quantities in the registers of the computer system into other data representing physical quantities similarly represented in the memory or registers of the computer system or other such information storage, transmission, or display devices.

[0073] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will become apparent from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It will be understood that the teachings of the embodiments described herein can be implemented using various programming languages.

[0074] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. Components of the distributed antenna system described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip, as an example. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this embodiment.

[0075] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0076] The embodiments disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0077] It should also be noted that the operational steps described in any exemplary embodiments herein are for illustrative and discussion purposes only. The described operations can be performed in many different sequences besides the sequences shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips (which can be referenced throughout the description) can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0078] Unless otherwise expressly stated, no method described herein shall be construed as requiring its steps to be performed in a particular order. Therefore, no particular order is intended to be inferred if a method claim does not actually state the order in which its steps are followed, or if the steps are not otherwise specified in the claim or description as being limited to a particular order.

[0079] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments in conjunction with the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be construed as including everything within the scope of the appended claims and their equivalents.

Claims

1. An array of comparison memory cell circuits, comprising: At least one set, each set including at least one row of a plurality of rows of comparison memory cell circuitry, each of the plurality of rows being configured to store binary tags; The comparison memory cell circuit comprises multiple columns, each of the multiple columns including the comparison memory cell circuit in each of the multiple rows; At least one decoded column, each decoded column corresponding to a set in the at least one set, the at least one decoded column being configured as follows: Receive the set clock signal for the corresponding set; as well as A set matching signal is generated on the set matching line in each row of the corresponding set; as well as Dynamic comparator circuit, including: A set clock circuit is configured to generate a set clock signal for addressing the corresponding set for each of the at least one decoded column; A column comparison circuit is configured to generate comparison truth data for each of the plurality of columns, indicating comparison truth bits of a comparison tag; and A row matching circuit is configured to generate, in response to the set matching signal generated in the rows, a row matching signal for each of the plurality of rows indicating that the comparison tag matches the binary tag stored in the row. Each of the at least one decoded column includes a pull-down circuit in each of the plurality of rows of the comparison memory cell circuitry, each pull-down circuit being coupled to the set matching line in the corresponding row; and In the decoding column corresponding to the set in the at least one set: Each pull-down circuit corresponding to a row in the set is configured to activate the set match line in the row in response to receiving a set clock signal for the corresponding set; and Each dropdown circuit corresponding to a row in another set of the at least one set is configured to not activate the set matching line in that row.

2. The array of comparison memory cell circuits according to claim 1, wherein each of the plurality of rows further includes a row matching line, wherein the row matching circuit is further configured to generate the row matching signal for the row in response to the row matching line indicating that the comparison tag matches the binary tag stored in the row.

3. The array of comparison memory cell circuits according to claim 2, wherein each comparison memory cell circuit is configured to store stored truth data corresponding to the comparison truth bits of the binary tag and stored complement data complementary to the stored truth data.

4. The array of comparator memory cell circuits according to claim 3, wherein each comparator memory cell circuit further comprises a truth comparison circuit, the truth comparison circuit being coupled to: The row matching line, including the row of the comparison memory cell circuit; as well as A truth comparison bit line, the truth comparison bit line being configured to receive the comparison truth data for the column including the comparison memory cell circuitry; The truth comparison circuit is configured to couple the row match line to a first voltage to indicate that the comparison truth data received on the truth comparison bit line does not match the truth data stored in the comparison memory cell circuit.

5. The array of comparator memory cell circuits according to claim 4, wherein: The column comparison circuit is further configured to: generate, for each of the plurality of columns, comparison complement data that is complementary to the comparison truth data of the binary tag and indicates the comparison complement bits of the comparison tag; and Each comparator memory cell circuit also includes a two's complement comparator circuit configured to couple the row match line of the row including the memory cell circuit to the first voltage to indicate that the comparator two's complement data of the column including the comparator memory cell circuit does not match the stored two's complement data stored in the comparator memory cell circuit.

6. The array of comparison memory cell circuits according to claim 5, wherein the two's complement comparison circuit further comprises a third transistor controlled by stored two's complement data stored in the comparison memory cell circuit and a fourth transistor controlled by the comparison truth data for the column including the comparison memory cell circuit.

7. The array of comparison memory cell circuits according to claim 5, wherein the truth comparison circuit further comprises a first transistor controlled by stored truth data stored in the comparison memory cell circuit, and a second transistor controlled by the comparison complement data for the column including the comparison memory cell circuit.

8. The array of comparator memory cell circuits according to claim 3, wherein each comparator memory cell circuit in the array comprises a static random access memory (SRAM) cell circuit.

9. The array of comparator memory cell circuits according to claim 1, wherein the set clock circuit is further configured to generate the set clock signal to each of the at least one decoded column in response to a clock signal and a set address signal corresponding to the set.

10. The array of comparison memory cell circuits according to claim 1, wherein the column comparison circuit is further configured to generate comparison truth data for each of the plurality of columns based on the comparison truth bits of the binary tag in response to the clock signal.

11. The array of comparator memory cell circuits according to claim 1, wherein: Each decoded column is configured to receive the set clock signal for the corresponding set generated by the set clock circuit; and Each pull-down circuit includes a first transistor controlled by the set clock signal and a second transistor coupled to a fixed voltage source.

12. The array of comparator memory cell circuits according to claim 11, wherein: In each row of the corresponding set, the voltage source includes a power supply voltage V. DD ;and In each row that is not in the corresponding set, the voltage source includes the ground voltage V. SS .

13. The array of comparator memory cell circuits according to claim 11, wherein: Each decoded column also includes a non-comparison memory cell circuit coupled to the read bit line in each row, the non-comparison memory cell circuit comprising: Memory cell circuitry; and A read transistor circuit is configured to read stored data stored in the non-comparison memory cell circuit in response to activation of a read word signal.

14. An integrated circuit comprising an array of comparator memory cell circuits, the array of comparator memory cell circuits comprising: At least one set, each set including at least one row of a plurality of rows of comparison memory cell circuitry, each of the plurality of rows being configured to store binary tags; The comparison memory cell circuit comprises multiple columns, each of the multiple columns including the comparison memory cell circuit in each of the multiple rows; At least one decoded column, each decoded column corresponding to a set in the at least one set, the at least one decoded column being configured as follows: Receive the set clock signal for the corresponding set; as well as A set matching signal is generated on the set matching line in each row of the corresponding set; as well as Dynamic comparator circuit, including: A set clock circuit is configured to generate a set clock signal for addressing the corresponding set for each of the at least one decoded column; A column comparison circuit is configured to generate comparison truth data for each of the plurality of columns, indicating comparison truth bits of a comparison tag; and A row matching circuit is configured to generate, in response to the set matching signal generated in the rows, a row matching signal for each of the plurality of rows indicating that the comparison label matches the binary label stored in the column. Each of the at least one decoded column includes a pull-down circuit in each of the plurality of rows of the comparison memory cell circuitry, each pull-down circuit being coupled to the set matching line in the corresponding row; and In the decoding column corresponding to the set in the at least one set: Each pull-down circuit corresponding to a row in the set is configured to activate the set match line in the row in response to receiving a set clock signal for the corresponding set; and Each dropdown circuit corresponding to a row in another set of the at least one set is configured to not activate the set matching line in that row.

15. The integrated circuit of claim 14, wherein each of the plurality of rows further includes a row matching line, wherein the row matching circuit is further configured to generate the row matching signal for the row in response to the row matching line indicating that the comparison tag matches the binary tag stored in the row.

16. The integrated circuit of claim 15, wherein each comparison memory cell circuit is configured to store stored truth data corresponding to the comparison truth bits of the binary tag and stored complement data complementary to the stored truth data.

17. The integrated circuit of claim 16, wherein each comparator memory cell circuit further comprises a truth comparison circuit coupled to: The row matching line, including the row of the comparison memory cell circuit; as well as A truth comparison bit line, the truth comparison bit line being configured to receive the comparison truth data for the column including the comparison memory cell circuitry; The truth comparison circuit is configured to couple the row match line to a first voltage to indicate that the comparison truth data received on the truth comparison bit line does not match the truth data stored in the comparison memory cell circuit.

18. The integrated circuit according to claim 17, wherein: The column comparison circuit is further configured to: generate, for each of the plurality of columns, comparison complement data that is complementary to the comparison truth data of the binary tag and indicates the comparison complement bits of the comparison tag; and Each comparator memory cell circuit also includes a two's complement comparator circuit configured to couple the row match line of the row including the memory cell circuit to the first voltage to indicate that the comparator two's complement data of the column including the comparator memory cell circuit does not match the stored two's complement data stored in the comparator memory cell circuit.

19. The integrated circuit of claim 18, wherein the truth comparison circuit further comprises a first transistor controlled by stored truth data stored in the comparison memory cell circuit, and a second transistor controlled by the comparison complement data for the column including the comparison memory cell circuit.

20. The integrated circuit of claim 19, wherein the two's complement comparison circuit further comprises a third transistor controlled by stored two's complement data stored in the comparison memory cell circuit and a fourth transistor controlled by the comparison truth data for the column including the comparison memory cell circuit.

21. An array of comparison memory cell circuits, comprising: At least one set, each set including at least one row of a plurality of rows of comparison memory cell circuitry, each of the plurality of rows being configured to store binary tags; The comparison memory cell circuit comprises multiple columns, each of the multiple columns including the comparison memory cell circuit in each of the multiple rows; At least one decoded column, each decoded column corresponding to a set in the at least one set, the at least one decoded column being configured as follows: Receive the set clock signal for the corresponding set; as well as A set matching signal is generated on the set matching line in each row of the corresponding set; as well as Dynamic comparator circuit, including: A set clock circuit is configured to generate a set clock signal for addressing the corresponding set for each of the at least one decoded column; A column comparison circuit is configured to generate comparison truth data for each of the plurality of columns, indicating comparison truth bits of a comparison tag; and A row matching circuit is configured to generate, in response to the set matching signal generated in the rows, a row matching signal for each of the plurality of rows indicating that the comparison tag matches the binary tag stored in the row. In each of the at least one decoded columns: The clock signal of the set is coupled to the load in each row of each set of the array; and The load corresponding to the decoded column in each row of the set includes circuitry for controlling the set matching signal.

22. The array of comparison memory cell circuits of claim 21, wherein each of the plurality of rows further includes a row matching line, wherein the row matching circuit is further configured to generate the row matching signal for the row in response to the row matching line indicating that the comparison tag matches the binary tag stored in the row.

23. The array of comparison memory cell circuits according to claim 22, wherein each comparison memory cell circuit is configured to store stored truth data corresponding to the comparison truth bits of the binary tag and stored complement data complementary to the stored truth data.

24. The array of comparator memory cell circuits according to claim 23, wherein each comparator memory cell circuit further comprises a truth comparison circuit coupled to: The row matching line, including the row of the comparison memory cell circuit; as well as A truth comparison bit line, the truth comparison bit line being configured to receive the comparison truth data for the column including the comparison memory cell circuitry; The truth comparison circuit is configured to couple the row match line to a first voltage to indicate that the comparison truth data received on the truth comparison bit line does not match the truth data stored in the comparison memory cell circuit.

25. The array of comparator memory cell circuits according to claim 24, wherein: The column comparison circuit is further configured to: generate, for each of the plurality of columns, comparison complement data that is complementary to the comparison truth data of the binary tag and indicates the comparison complement bits of the comparison tag; and Each comparator memory cell circuit also includes a two's complement comparator circuit configured to couple the row match line of the row including the memory cell circuit to the first voltage to indicate that the comparator two's complement data of the column including the comparator memory cell circuit does not match the stored two's complement data stored in the comparator memory cell circuit.

26. The array of comparator memory cell circuits according to claim 25, wherein the two's complement comparator circuit further comprises a third transistor controlled by stored two's complement data stored in the comparator memory cell circuit and a fourth transistor controlled by the comparison truth data for the column including the comparator memory cell circuit.

27. The array of comparator memory cell circuits according to claim 25, wherein the truth comparison circuit further comprises a first transistor controlled by stored truth data stored in the comparator memory cell circuit, and a second transistor controlled by the comparator complement data for the column including the comparator memory cell circuit.

28. The array of comparator memory cell circuits according to claim 21, wherein the set clock circuit is further configured to generate the set clock signal to each of the at least one decoded column in response to a clock signal and a set address signal corresponding to the set.

29. The array of comparison memory cell circuits according to claim 21, wherein the column comparison circuit is further configured to generate comparison truth data for each of the plurality of columns based on the comparison truth bits of the binary tag in response to the clock signal.

30. An array of comparison memory cell circuits, comprising: At least one set, each set including at least one row of a plurality of rows of comparison memory cell circuitry, each of the plurality of rows being configured to store binary tags; The comparison memory cell circuit comprises multiple columns, each of the multiple columns including the comparison memory cell circuit in each of the multiple rows; At least one decoded column, each decoded column corresponding to a set in the at least one set, the at least one decoded column being configured as follows: Receive the set clock signal for the corresponding set; as well as A set matching signal is generated on the set matching line in each row of the corresponding set; as well as Dynamic comparator circuit, including: A set clock circuit is configured to generate a set clock signal for addressing the corresponding set for each of the at least one decoded column; A column comparison circuit is configured to generate comparison truth data for each of the plurality of columns, indicating comparison truth bits of a comparison tag; and A row matching circuit is configured to generate a delayed set matching signal based on the set matching signal generated in the row, wherein the row matching circuit is configured to generate a row matching signal for each of the plurality of rows in response to the delayed set matching signal, indicating that the comparison tag matches the binary tag stored in the row.

31. The array of comparison memory cell circuits of claim 30, wherein each of the plurality of rows further includes a row matching line, wherein the row matching circuit is further configured to generate the row matching signal for the row in response to the row matching line indicating that the comparison tag matches the binary tag stored in the row.

32. The array of comparison memory cell circuits according to claim 31, wherein each comparison memory cell circuit is configured to store stored truth data corresponding to the comparison truth bits of the binary tag and stored complement data complementary to the stored truth data.

33. The array of comparator memory cell circuits according to claim 32, wherein each comparator memory cell circuit further includes a truth comparison circuit coupled to: The row matching line, including the row of the comparison memory cell circuit; as well as A truth comparison bit line, the truth comparison bit line being configured to receive the comparison truth data for the column including the comparison memory cell circuitry; The truth comparison circuit is configured to couple the row match line to a first voltage to indicate that the comparison truth data received on the truth comparison bit line does not match the truth data stored in the comparison memory cell circuit.

34. The array of comparator memory cell circuits according to claim 33, wherein: The column comparison circuit is further configured to: generate, for each of the plurality of columns, comparison complement data that is complementary to the comparison truth data of the binary tag and indicates the comparison complement bits of the comparison tag; and Each comparator memory cell circuit also includes a two's complement comparator circuit configured to couple the row match line of the row including the memory cell circuit to the first voltage to indicate that the comparator two's complement data of the column including the comparator memory cell circuit does not match the stored two's complement data stored in the comparator memory cell circuit.

35. The array of comparator memory cell circuits according to claim 34, wherein the two's complement comparator circuit further comprises a third transistor controlled by stored two's complement data stored in the comparator memory cell circuit and a fourth transistor controlled by the comparison truth data for the column including the comparator memory cell circuit.

36. The array of comparator memory cell circuits according to claim 34, wherein the truth comparison circuit further comprises a first transistor controlled by stored truth data stored in the comparator memory cell circuit, and a second transistor controlled by the comparator complement data for the column including the comparator memory cell circuit.

37. The array of comparator memory cell circuits according to claim 30, wherein the set clock circuit is further configured to generate the set clock signal to each of the at least one decoded column in response to a clock signal and a set address signal corresponding to the set.

38. The array of compare memory cell circuits according to claim 30, wherein the column compare circuit is further configured to generate the compare truth data for each of the plurality of columns based on the compare truth bits of the binary tag in response to the clock signal.

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