Discharge circuit for NAND flash memory

Abstract

The present disclosure provides a method for discharging a memory device after an erase operation. The method includes grounding a source line of the memory device; and turning on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. The method also includes comparing a potential of the source line to a first predetermined value; and floating the gate terminal of the discharge transistor when the potential of the source line is lower than the first predetermined value.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more particularly to a discharge circuit for NAND flash memory. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges attributed to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0003] In 3D NAND flash memory, the memory array can include multiple memory strings arranged vertically on a substrate, each memory string having multiple memory cells stacked vertically. This can significantly increase the storage density per unit area.

[0004] While programming and reading operations can be performed on all memory cells within a word line of a shared memory page, erase operations are typically performed on all memory cells within a memory block sharing a common source line. During the erase operation, an erase voltage (approximately 20V) can be applied to the common source line or an n-well in the substrate, while the word line can be grounded. The potential of the channel layer in the memory string can be gradually increased from bottom to top.

[0005] As the number of vertically stacked memory cells increases, an erase voltage can be applied to the bit line at the top of the memory string to improve erase speed. Furthermore, gate-induced drain-leakage (GIDL) current can be introduced to assist the erase operation, allowing the channel layer potential in the memory string to quickly reach the erase voltage. After the erase operation, the GIDL current needs to be removed, and the high potentials of the common source line and the bit line need to be discharged. Although the discharge can be performed using a discharge transistor connected between the common source line and the corresponding bit line, the timing of the discharge operation is critical. Summary of the Invention

[0006] This disclosure describes an embodiment of a discharge circuit and method for discharging NAND flash memory.

[0007] One aspect of this disclosure provides a discharge circuit for discharging a memory device after an erase operation. The discharge circuit includes a discharge transistor connected to a bit line and a source line of the memory device. The discharge circuit also includes a source line detection circuit connected to the source line and configured to compare the potential of the source line with a predetermined value. The discharge circuit further includes a gate discharge circuit configured to maintain a constant voltage difference between the discharge transistor and the source line, wherein the constant voltage difference applied to the discharge transistor and the source line turns on the discharge transistor.

[0008] In some embodiments, the discharge transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). The gate terminal of the MOSFET is connected to the gate discharge circuit. The source terminal of the MOSFET is connected to the source line, and the drain terminal of the MOSFET is connected to the bit line.

[0009] In some embodiments, the gate discharge circuit includes a group of diodes connected in series.

[0010] In some embodiments, the gate discharge circuit further includes a switching transistor connected in series with a set of diodes.

[0011] In some embodiments, the gate discharge circuit further includes a voltage level shifter configured to provide a switching voltage to turn on the switching transistor.

[0012] In some embodiments, a set of diodes includes a MOSFET configured as an effective diode, wherein the gate terminal of the MOSFET is connected to the drain terminal of the MOSFET. In some embodiments, the MOSFET is a p-channel MOSFET.

[0013] In some embodiments, the source line detection circuit includes an operational amplifier, a resistor divider, and a capacitor connected in parallel with the resistor divider. The capacitor and the first terminal of the resistor divider are connected together. The second terminal of the capacitor and the resistor divider is grounded.

[0014] In some embodiments, the source line detection circuit further includes a pull-up transistor that connects the first terminal of a capacitor and a resistor divider to a power supply. The pull-up transistor is controlled by the output of an operational amplifier.

[0015] In some embodiments, the resistive voltage divider includes a first resistor connected in series with a second resistor. The second resistor has an adjustable resistance.

[0016] In some embodiments, the operational amplifier is configured to have a predetermined value set by the potential of a capacitor and a first terminal of a resistor divider. The negative input terminal of the operational amplifier is connected to a reference voltage, and the positive input terminal of the operational amplifier is connected to the midpoint of the resistor divider.

[0017] In some embodiments, the operational amplifier is configured to compare the potential of the source line with a predetermined value. The negative input of the operational amplifier is connected to the source line, and the positive input of the operational amplifier is connected to the first terminal of a capacitor and resistor divider.

[0018] In some embodiments, the source line is grounded.

[0019] In some embodiments, the discharge circuit further includes a current source configured to regulate the discharge current flowing through the source line.

[0020] Another aspect of this disclosure provides a method for discharging a memory device after an erase operation. The method includes grounding the source line of the memory device; and turning on the discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between the gate terminal of the discharge transistor and the source line. The method further includes comparing the potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the potential of the source line is lower than the first predetermined value.

[0021] In some embodiments, the method further includes comparing the potential of the source line with a second predetermined value, wherein the second predetermined value is less than the first predetermined value.

[0022] In some embodiments, the method further includes grounding the gate terminal of the discharge transistor when the potential of the source line is lower than a second predetermined value.

[0023] In some embodiments, the method further includes adjusting the discharge current flowing through the source wire using a current source.

[0024] In some embodiments, the method further includes setting a first predetermined value less than the source / drain junction breakdown voltage of the discharge transistor.

[0025] Another aspect of this disclosure provides a memory device having a memory block and peripheral circuitry. The memory block includes multiple memory strings connected to source lines and multiple bit lines. The peripheral circuitry includes a discharge circuit configured to discharge the memory block after an erase operation. The discharge circuit includes multiple discharge transistors. Each discharge transistor is configured to connect a source line to a corresponding bit line. The discharge circuit also includes a source line detection circuit connected to a source line and configured to compare the potential of the source line with a predetermined value. The discharge circuit also includes a gate discharge circuit configured to maintain a constant voltage difference between the gate terminals of the multiple discharge transistors and the source lines.

[0026] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims and drawings of this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0028] Figures 1A-1C A memory system with NAND flash memory is shown according to some embodiments of the present disclosure.

[0029] Figure 2A A schematic circuit diagram of a NAND flash memory according to some embodiments of the present disclosure is shown.

[0030] Figure 2B A perspective view of a three-dimensional (3D) NAND flash memory according to some embodiments of the present disclosure is shown.

[0031] Figure 3 A 3D NAND flash memory and a first discharge circuit according to some embodiments of the present disclosure are shown.

[0032] Figure 4A and Figure 4B Waveforms used during erasure and discharge operations according to some embodiments of this disclosure are shown.

[0033] Figure 5 A 3D NAND flash memory and a second discharge circuit according to some embodiments of the present disclosure are shown.

[0034] Figure 6 Waveforms used during erasure and discharge operations according to some embodiments of this disclosure are shown.

[0035] Figure 7Methods for discharging 3D NAND flash memory according to some embodiments of the present disclosure are shown.

[0036] Figure 8A and Figure 8B A schematic diagram of a gate discharge circuit according to some embodiments of the present disclosure is shown.

[0037] Figure 9 A schematic diagram of a source line (SL) detection circuit according to some embodiments of the present disclosure is shown.

[0038] Figure 10 A method for setting predetermined values ​​for an SL detection circuit according to some embodiments of the present disclosure is shown.

[0039] Figure 11 A method for comparing an input voltage with a predetermined value is shown according to some embodiments of the present disclosure.

[0040] The features and advantages of the invention will become more apparent when viewed in conjunction with the accompanying drawings, in which similar reference numerals consistently identify corresponding elements. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0041] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0042] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used for a variety of other applications.

[0043] Note that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., in this specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge scope of those skilled in the art.

[0044] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0045] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may arise due to minor variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "approximately" can indicate a value of a given quantity that varies.

[0046] Figure 1A A block diagram of an exemplary system S1 having a memory system 10 according to some embodiments of this disclosure is shown. System S1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage means therein. Memory system 10 (also referred to as NAND memory system) includes NAND flash memory 100 and host controller 20 (also referred to as memory controller). Memory system 10 can communicate with host computer 15 via memory controller 20, wherein memory controller 20 can be connected to NAND flash memory 100 via memory channel 30. In some embodiments, memory system 10 may have more than one NAND flash memory 100, and each NAND flash memory 100 may be managed by memory controller 20.

[0047] In some embodiments, host computer 15 may include a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). Host computer 15 sends data to be stored in NAND memory system or memory system 10, or retrieves data by reading memory system 10.

[0048] The memory controller 20 can process I / O requests received from the host computer 15, ensure data integrity and effective storage, and manage the NAND flash memory 100. The memory channel 30 can provide data via the data bus and control communication between the memory controller 20 and the NAND flash memory 100.

[0049] The memory controller 20 and one or more NAND flash memory units 100 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 10 can be implemented and packaged into different types of end electronic products. Figure 1B In one example shown, the memory controller 20 and a single NAND flash memory 100 can be integrated into a memory card 26. The memory card 26 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may also include a memory card connector 24 that couples the memory card 26 to a host computer (e.g., host computer 15 in Figure 16). Figure 1C In another example shown, the memory controller 20 and multiple NAND flash memory units 100 can be integrated into a solid-state drive (SSD) 27. The SSD 27 may also include a connection between the SSD 27 and a host computer (e.g., Figure 1A The host computer 15) is coupled to the SSD connector 28.

[0050] refer to Figure 1AThe NAND flash memory 100 (i.e., "flash memory", "NAND flash", or "NAND") can be any part of a memory chip (package), memory die, or memory die, and may include one or more memory surfaces 101, each memory surface may include multiple memory blocks 103. The same and concurrent operations can occur at each memory surface 101. The size of the memory block 103 may be megabytes (MB), and the memory block 103 is the minimum size for performing an erase operation. Figure 1A As shown, the exemplary NAND flash memory 100 includes four memory surfaces 101, and each memory surface 101 includes six memory blocks 103. Each memory block 103 may include a plurality of memory cells, wherein each memory cell can be addressed by interconnects such as bit lines and word lines. The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The orientation of the bit lines and word lines is... Figure 1A The blocks 103 are labeled "BL" and "WL" respectively. In this disclosure, one or more memory blocks 103 may also be referred to as a "memory array" or "array". A memory array is the core area of ​​a memory device that performs storage functions.

[0051] The NAND flash memory 100 also includes a peripheral circuitry region 105, which is the region surrounding the memory surface 101. The peripheral circuitry region 105 (also referred to as peripheral circuitry) contains a number of digital, analog, and / or mixed-signal circuits (e.g., page buffer / sensor amplifier 50, row decoder / word line driver 40, column decoder / bit line driver 60, and control circuitry 70) to support the functionality of the memory array. The control circuitry 70 includes registers, active and / or passive semiconductor devices such as transistors, diodes, capacitors, resistors, etc., which will be apparent to those skilled in the art. The control circuitry 70 of the peripheral circuitry region 105 can be configured to initiate a programming operation on a selected memory cell in the NAND memory string within the memory block 103. In some embodiments, the control circuitry 70 receives a programming command via an interface from a memory controller (e.g., memory controller 20) and, in response, sends control signals to at least a row decoder / word line driver, a column decoder / bit line driver, and a voltage generator disposed in the peripheral circuitry region 105 to initiate a programming operation on the selected memory cell.

[0052] Notice, Figure 1AThe layout of the electronic components in the memory system 10 and NAND flash memory 100 is shown as an example. The memory system 10 and NAND flash memory 100 may have other layouts and may include additional components. For example, the NAND flash memory 100 may also have a high-voltage charge pump, I / O circuitry, etc. The memory system 10 may also include firmware, a data scrambler, etc. In some embodiments, the peripheral circuitry region 105 and the memory array may be formed independently on separate wafers and then interconnected by wafer bonding.

[0053] Figure 2A A schematic diagram of a NAND flash memory 100 according to some embodiments of the present disclosure is shown. The NAND flash memory 100 includes one or more memory blocks 103. Each memory block 103 includes a memory string 212. Each memory string 212 includes memory cells 340. Memory cells 340 sharing the same word line form memory pages 448. The memory string 212 may also include at least one field-effect transistor (e.g., MOSFET) at each end, the field-effect transistor being controlled by a bottom select gate (BSG) 332 and a top select gate (TSG) 334, respectively. The drain terminal of the top select transistor 334-T may be connected to a bit line 341, and the source terminal of the bottom select transistor 332-T may be connected to an array common source (ACS) 446. The ACS 446 may be shared by the memory strings 212 throughout the memory block and is also referred to as the common source line.

[0054] The NAND flash memory 100 may also include peripheral circuitry, comprising a number of digital, analog, and / or mixed-signal circuits (e.g., page buffer / sensor amplifier 50, row decoder / word line driver 40, column decoder / bit line driver 60, control circuitry 70, voltage generator 65, and input / output buffer 55) to support the functionality of the memory block 103. This circuitry may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art. In some embodiments, the peripheral circuitry may support erase operations assisted by gate-induced drain leakage (GIDL) current.

[0055] Memory block 103 can be coupled to row decoder / word line driver 40 via word line (“WL”) 333, bottom select gate (“BSG”) 332, and top select gate (“TSG”) 334. Memory block 103 can be coupled to page buffer / sensor amplifier 50 via bit line (“BL”) 341. Row decoder / word line driver 40 can select one memory block from memory blocks 103 on NAND flash memory 100 in response to an X-path control signal provided by control circuitry 70. Row decoder / word line driver 40 can pass voltage from voltage generator 65 to word line according to X-path control signal. During read and program operations, row decoder / word line driver 40 can pass read voltage V according to X-path control signal received from control circuitry 70. read and programming voltage V pgm It is passed to the selected word line and will be transmitted through voltage V. pass Passed to unselected word lines.

[0056] The column decoder / bit line driver 60 can disable the voltage V according to the Y-path control signal received from the control circuit 70. inhibit The signal is passed to the non-selectable positioning line, and the selectable positioning line is connected to ground. That is, the column decoder / bit line driver 60 can be configured to select or deselect one or more memory strings 212 according to the Y-path control signal from the control circuit 70. The page buffer / sensor amplifier 50 can be configured to read data from memory block 103 and program (write) data to memory block 10 according to the Y-path control signal from the control circuit 70. For example, the page buffer / sensor amplifier 50 can store a page of data to be programmed into a memory page 448. In another example, the page buffer / sensor amplifier 50 can perform a verification operation to ensure that data has been correctly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer / sensor amplifier 50 can sense the current flowing through bit line 341 reflecting the logic state (i.e., data) of memory cell 340 and amplify the small signal to a measurable amplification.

[0057] The input / output buffer 55 can pass I / O data from / to the page buffer / sensor amplifier 50, and pass address ADDR or command CMD to the control circuitry 70. In some embodiments, the input / output buffer 55 can be used as a memory controller 20. Figure 1A The interface between the NAND flash memory 100 and the NAND flash memory 100.

[0058] Control circuitry 70 can control page buffer / sensor amplifier 50 and row decoder / word line driver 40 in response to command CMD passed from input / output buffer 55. During programming operations, control circuitry 70 can control row decoder / word line driver 40 and page buffer / sensor amplifier 50 to program selected memory cells. During read operations, control circuitry 70 can control row decoder / word line driver 40 and page buffer / sensor amplifier 50 to read selected memory cells. X-path control signals and Y-path control signals include row address X-ADDR and column address Y-ADDR, which can be used to locate selected memory cells in memory block 103. Row address X-ADDR can include page index, block index, and face index to identify memory page 448, memory block 103, and memory face 101, respectively. Figure 1A (In the middle). The column address Y-ADDR can identify a byte or word in the data of memory page 448.

[0059] In some implementations, control circuitry 70 may include one or more control logic units. Each control logic unit described herein may be a software module and / or firmware module running on a processor, such as a microcontroller unit (MCU) as part of control circuitry 70, or a hardware module of a finite-state machine (FSM), such as an integrated circuit (IC, such as an application-specific IC (ASIC), a field-programmable gate array (FPGA), etc.), or a combination of software modules, firmware modules, and hardware modules.

[0060] Voltage generator 65, under the control of control circuit 70, generates the voltage to be supplied to the word lines and bit lines. The voltage generated by voltage generator 65 includes the read voltage V. read Programming voltage V pgm Through voltage V pass Prohibited voltage V inhibit wait.

[0061] In some embodiments, the NAND flash memory 100 can be formed based on floating gate technology. In some embodiments, the NAND flash memory 100 can be formed based on charge trapping technology. Charge trapping-based NAND flash memory can provide high storage density and high intrinsic reliability. It stores data or logic states (e.g., the threshold voltage V of memory cell 340). thThe amount of charge trapped in the storage layer depends on the amount of charge trapped. In some embodiments, the NAND flash memory 100 may be a three-dimensional (3D) memory device, wherein memory cells 340 may be stacked vertically on top of each other.

[0062] Figure 2B A perspective view of a portion of a 3D NAND flash memory 200 according to some embodiments of the present disclosure is shown. The 3D NAND flash memory 200 includes a substrate 330, an insulating film 331 above the substrate 330, a bottom select gate (BSG) 332 above the insulating film 331, and a control gate 333 (also referred to as a "word line (WL)") stacked on top of the BSG 332 to form an alternating conductive and dielectric layer stack 335. For clarity, in Figure 2B The dielectric layer adjacent to the control gate is not shown.

[0063] Each layer's control gate is separated by slot structures 216-1 and 216-2 through the film stack 335. The 3D NAND flash memory 200 also includes a layer of top select gate (TSG) 334 above the stack of control gates 333. The stack of TSG 334, control gate 333, and BSG 332 is also referred to as a "gate electrode". The 3D NAND flash memory 200 also includes memory strings 212 and doped source line regions 344 in portions of the substrate 330 between adjacent BSGs 332. Each memory string 212 includes a channel via 336 extending through the film stack 335 of insulating film 331 and alternating conductive and dielectric layers. The memory string 212 also includes a memory film 337 on the sidewall of the channel via 336, a channel layer 338 above the memory film 337, and a core filler 339 surrounded by the channel layer 338. Memory cells 340 (e.g., 340-1, 340-2, 340-3) may be formed at the intersection of control gates 333 (e.g., 333-1, 333-2, 333-3) and memory strings 212. A portion of the channel layer 338, responsive to the respective control gate, is also referred to as the channel layer 338 of the memory cell. The 3D NAND flash memory 200 also includes bit lines (BLs) 341 connected to the memory strings 212 above the TSG 334. The 3D NAND flash memory 200 also includes metal interconnects 343 connected to the gate electrode via contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connections to each level of the gate electrode.

[0064] exist Figure 2BFor illustrative purposes, three levels of control gates 333-1, 333-2, and 333-3 are shown together with one level of TSG 334 and one level of BSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3, which correspond to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The 3D NAND flash memory 200 may also include other structures, such as TSG notches, common source contacts, array common source, and dummy memory strings. For simplicity, these structures are not shown. Figure 2B As shown in the image.

[0065] In NAND flash memory, read and program operations can be performed in memory pages 448, which include all memory cells 340 sharing the same word line. In NAND memory, memory cells 340 can be in an erase state (ER) or a programmable state (P1). To further increase storage density, memory cells can store n bits of data and have 2... n There are 3 states, where n is an integer. For example, for SLC, MLC, TLC, and QLC modes, n is equal to 1, 2, 3, and 4, respectively.

[0066] During the erase operation, a negative voltage difference is applied between the control gate 333 of the memory cell and the source terminal (e.g., the array common source 446) to remove all trapped electron charges in the storage layer of the memory cell 340, allowing all memory cells 340 in the same memory block 103 to be reset to the erase state ER as logic "1". For example, the negative voltage difference can be induced by setting the control gate 333 of the memory cell 340 to ground and applying a high positive voltage to the array common source 446. In some embodiments, an incremental step pulse erase (ISPE) scheme can be used for the erase operation. In this example, a voltage pulse can be applied to the memory cell in the erase cycle, wherein an erase step voltage V can be applied in subsequent erase cycles. step_ers Incrementally increase the voltage pulse (i.e., erase voltage V) erase The amplitude of ).

[0067] After the erase operation, an erase verification operation can be performed to determine whether the memory cell is in state ER or whether the erase operation was successfully completed. An erase verification voltage EV can be applied to the word line of the memory cell and compared to a threshold voltage for the memory cell. If the erase verification voltage EV is higher than the threshold voltage of the memory cell, the memory cell is considered to be in state ER. If all memory cells in the memory block are in state ER, the memory block is considered to have passed the erase verification. If a predetermined number of memory cells are not in state ER, the memory block is considered to have failed the erase verification. The erase and erase verification operations can be performed again on the memory cells in the next erase cycle, where the erase voltage EV can be applied. erase Increase the erase step voltage V step_ers .

[0068] To perform the erase operation, the erase voltage V can be... erase An n-well is applied to a substrate shared by all memory cells in the same memory block. In some embodiments, the erase voltage V erase It can be applied to ACS 446, such as Figure 2A As shown in the figure. In some embodiments, the NAND flash memory 100 may have a three-dimensional structure, for example, as shown in the figure. Figure 2B The 3D NAND flash memory 200 is shown. In this example, the NAND flash memory may also include additional transistors at each end of the memory string, wherein the additional transistors introduce gate-induced drain leakage (GIDL) to assist the erase operation.

[0069] Figure 3 A 3D NAND flash memory 300 according to some embodiments of the present disclosure is shown. The 3D NAND flash memory 300 may be Figure 1A It is part of memory block 103. Similar to... Figure 2B The 3D NAND flash memory 200 and 300 also include a film stack 335 with alternating conductive and dielectric layers, and multiple memory strings 212 having multiple vertically stacked memory cells 340. During an erase operation, the word lines 333 of all memory cells 340 in the same memory block can be grounded, and the erase voltage V erase Bit lines 341 at the top of memory string 212 and source lines (SL) 342 at the bottom of memory string 212 can be applied. SL 342 can be shared by all memory strings 212 and all memory cells 340 in the same memory block. In one example, SL 342 can be connected to ACS 446.

[0070] SL 342 can be coupled to the channel layer 338 of the memory string 212 via SL contact 350. Bit line (BL) 341 can be coupled to the channel layer 338 via BL contact 352. In some embodiments, SL contact 350 and BL contact 352 comprise polysilicon. In some embodiments, SL contact 350 and BL contact 352 may be doped with an n-type dopant, such as phosphine or arsenic.

[0071] The 3D NAND flash memory 300 also includes multiple select gates, such as BSG 332-1, BSG 332-2, TSG 334-1, and TSG 334-2, wherein at least one select gate (e.g., BSG 332-2 and TSG 334-2) at each end of the memory string 212 can be controlled to generate a GIDL current and to inject charge carriers (e.g., holes) from SL 342 and BL 341 into the channel layer 338 during an erase operation. Therefore, the potential of the channel layer 338 along the memory string 212 can be raised to near or equal to the erase voltage V applied to SL 342 and BL 341. erase The voltage. As previously described, the negative voltage bias between word line 333 and the corresponding channel layer 338 can remove charge carriers (e.g., electrons) trapped in memory film 337, and thereby reduce the threshold voltage of the corresponding memory cell 340. After the erase and erase verification operations are completed, i.e., after the memory cell is reset to the erase state ER, the stored data in the memory cell is erased accordingly. In this example, the erase operation can be assisted by gate-induced drain leakage (GIDL) current flowing through the bit lines and source lines of the memory device.

[0072] Figure 3 A first discharge circuit 302 for a 3D NAND flash memory according to some embodiments of the present disclosure is also shown. The first discharge circuit 302 may be... Figure 2A This is a portion of the peripheral circuitry shown and can be fabricated in the peripheral region. The first discharge circuit 302 can be coupled to the 3D NAND flash memory 300 to discharge the 3D NAND flash memory 300 (e.g., bit lines 341 and SL 342) after an erase operation.

[0073] The first discharge circuit 302 includes a discharge transistor 354. The discharge transistor 354 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the discharge transistor 354 may be an n-channel MOSFET. The drain terminal (DS_D) of the discharge transistor 354 may be connected to BL341, which may be connected to its corresponding page buffer / sensor amplifier 50. The source terminal (DS_S) of the discharge transistor 354 may be connected to SL342, which may be connected to ACS 446 and current source 360 ​​via a first switch 356. The current source 360 ​​may be used to regulate the discharge current flowing to ground. In some embodiments, the current source 360 ​​may be a flexible confined current source. The gate terminal (DS_GT) of the discharge transistor 354 may be grounded via a second switch 358.

[0074] In some embodiments, the discharge transistor 354 may be included as a component in the page buffer / sensor amplifier 50. In this example, each BL 341 is connected to the discharge transistor 354 at its drain terminal DS_D. All discharge transistors 354 in the entire memory block may be connected to a shared SL 342 at their source terminals DS_S. The gate terminals DS_GT of all discharge transistors 354 in the same memory block may also be connected together to a second switch 358.

[0075] Figure 4A and Figure 4B Waveforms 400A and 400B are shown for erase and discharge operations for a 3D NAND flash memory according to some embodiments of this disclosure. Each erase operation is followed by a discharge operation. During the erase operation, the first switch 356 can be turned off, and the erase voltage V can be applied. erase An erase voltage V is applied to SL 342. The gate terminal DS_GT of the discharge transistor 354 can be supplied with an on-state voltage VGG to turn on the discharge transistor 354, electrically connecting the source terminal DS_S and the drain terminal DS_D of the discharge transistor 354. BL 341 is connected to the drain terminal DS_D of the discharge transistor 354, and thus also connected to the source terminal DS_S and SL 342, and is supplied with an erase voltage V. erase In some embodiments, the erase voltage V erase It can be in the range of approximately 18V to approximately 22V. For an n-type MOSFET, in order to turn on the discharge transistor 354, the turn-on voltage VGG is higher than the erase voltage V applied to the source terminal DS_S. erase The on-state voltage VGG can be in the range of approximately 22V to approximately 27V. During erase and discharge operations, word line 333 ( Figure 4A and Figure 4B(Not shown in the image) can be grounded. In the example where each BL 341 is connected to a discharge transistor 354, multiple discharge transistors 354 can be turned on during the erase operation, such that multiple bit lines 341 can be connected to the source line 342 during the erase operation, wherein the multiple bit lines 341 and the source line 342 can be subjected to an erase voltage V during the erase operation. erase Gate-induced drain leakage (GIDL) current can flow through each bit line and source line into the channel layer of each memory string to assist in the erase operation.

[0076] During the discharge operation, the first switch 356 can be turned on, allowing the source terminal DS_S of the discharge transistor 354 to be grounded via a current source 360 ​​(e.g., a flexible confined current source). The current source 360 ​​can regulate the discharge current flowing through it, and thereby regulate the discharge rate of SL 342. As shown in waveforms 400A and 400B, at the end of the discharge operation, the potential V of SL 342... SL It can be reduced to 0V.

[0077] During the discharge operation, when the discharge transistor 354 is turned on, BL 341 can be connected to SL 342 and ground. That is, BL 341 can discharge simultaneously with SL 342 through the discharge transistor 354.

[0078] At the end of the discharge operation, the discharge transistor 354 can be turned off by turning on the second switch 358 to connect the gate terminal DS_GT to ground. However, the timing of turning off the discharge transistor 354 during the discharge operation may affect the performance and reliability of the discharge transistor 354.

[0079] exist Figure 4A In this example, the second switch 358 is turned on simultaneously with the first switch 356. Because the gate terminal DS_GT is grounded when the second switch 358 is on, the discharge transistor 354 can be turned off. In this example, when the discharge transistor 354 is off, the potential V of BL 341 is... BL Still at a high level (e.g., close to the erase voltage V) erase Because the fast discharge path through discharge transistor 354 is turned off, the potential V of BL 341 is... BL It remains at a high level, as shown in waveform 400A. Because the drain terminal DS_D of discharge transistor 354 is connected to BL 341, the drain terminals DS_D of discharge transistor 354 and BL 341 are at the same potential V. BLTherefore, after SL 342 drops to 0V, a high potential difference exists between the drain terminal DS_D and the source terminal DS_S of the discharge transistor 354, which may lead to breakdown of the source / drain junction. As the discharge transistor 354 is scaled down to a smaller size, the source / drain breakdown voltage of the discharge transistor 354 decreases. Therefore, if the discharge transistor 354 is turned off prematurely, the high potential difference between the source and drain terminals may lead to breakdown of the source / drain junction of the discharge transistor 354.

[0080] exist Figure 4B In this example, when SL 342 drops to 0V, the second switch 358 turns on. When the potential V of SL 342... SL From the erase voltage V erase When the voltage drops to 0V, the discharge transistor 354 remains on. Because BL 341 is electrically connected to SL 342 through the discharge transistor 354 when it is on, the potential V of BL 341... BL Following the potential V of SL 342 SL The discharge voltage drops to 0V at the same discharge rate. Although the source and drain of the discharge transistor 354 are at the same potential in this example, there is a large voltage difference between the gate terminal DS_GT and the source terminal DS_S / drain terminal DS_D, which may cause Fowler-Nordheim (FN) stress on the gate dielectric of the discharge transistor 354. The threshold voltage of the discharge transistor 354 can be increased accordingly, and therefore the performance and reliability of the discharge transistor 354 may be reduced.

[0081] Figure 5 A 3D NAND flash memory and a second discharge circuit 504 according to some embodiments of the present disclosure are shown. The second discharge circuit 504 is similar to the first discharge circuit 302 and can be coupled to the 3D NAND flash memory 300. The differences and improvements of the second discharge circuit 504 relative to the first discharge circuit 302 will be described in detail below.

[0082] Unlike the first discharge circuit 302, the second discharge circuit 504 also includes an SL detection circuit 564, which is connected to the source terminal DS_S of the SL 342 and the discharge transistor 354. The SL detection circuit 564 is also connected to a current source 360 ​​(e.g., a flexible confined current source) via a first switch 356.

[0083] The second discharge circuit 504 also includes a gate discharge circuit 566, which is connected to the gate terminal DS_GT of the discharge transistor 354. The gate discharge circuit 566 is also connected to the SL detection circuit 564 via a third switch 562.

[0084] Figure 6 Waveform 600 for a second discharge circuit 504 according to some embodiments of this disclosure is shown. Waveform 600 illustrates erase and discharge operations performed on a 3D NAND flash memory 300 with the support of the second discharge circuit 504. The erase operation represented by waveform 600 is followed by a discharge operation. The erase operation of waveform 600 is similar to waveforms 400A and 400B, as per [reference to...]. Figure 4A and Figure 4B As described.

[0085] During the discharge operation, the timing of discharging the gate terminal DS_GT of the discharge transistor 354 can be controlled by the second discharge circuit 504, so that the discharge transistor 354 will not suffer from FN stress or source / drain junction breakdown.

[0086] Figure 7 A method 700 for discharging a 3D NAND flash memory after an erase operation, according to some embodiments of this disclosure, is illustrated. It should be understood that method 700 is not exhaustive, and other operation steps may be performed before, after, or between any of the illustrated operation steps. In some embodiments, some operation steps of method 700 may be omitted, or other operation steps may be included, which are not described herein for simplicity. In some embodiments, the operation steps of method 700 may be performed in different orders and / or variations.

[0087] refer to Figures 5-7 The following steps can be implemented as an example of discharging the 3D NAND flash memory 300 via the second discharge circuit 504 after an erase operation.

[0088] First, during the erasure operation and before the discharge operation, all switches are turned off, specifically the first switch 356, the second switch 358, and the third switch 562 of the second discharge circuit 504. The erasure voltage V can then be applied. erase The power-on voltage VGG can be applied to the gate terminal DS_GT of the discharge transistor 354 to turn it on. Therefore, BL 341 can be connected to SL 342 and can also be applied with an erase voltage V. erase At the end of the erase operation, the erase voltage V can be removed from SL342 and the gate terminal DS_GT, respectively. erase And the on-state voltage VGG.

[0089] At the start of the discharge operation (i.e. Figure 6At time T0, as shown in operation step 710, SL 342 can be grounded by turning on the first switch 356. That is, zero volts (0V) can be applied to SL 342. The source terminal DS_S of the discharge transistor 354 is connected to SL 342, and thus the source terminal DS_S of the discharge transistor 354 is maintained at the same potential V. SL It discharges simultaneously with SL342. A current source 360 ​​connected between the first switch 356 and ground can regulate the discharge current flowing through it, thereby regulating the discharge rate of SL 342. In some embodiments, the current source 360 ​​may be a flexible, confined current source. Figure 6 As shown, the potential V of SL 342 SL The erase voltage V at time T0 at the end of the discharge operation erase It drops to 0V, where the slope represents the discharge rate of the SL 342.

[0090] The third switch 562 can be turned on simultaneously with the first switch 356, i.e., turned on at time T0, to form an electrical connection from the gate terminal DS_GT of the discharge transistor 354 through the gate discharge circuit 566 to SL 342. As shown in operation step S720, the gate discharge circuit 566 can provide and maintain a constant voltage difference Vg_Vs between the gate terminal DS_GT of the discharge transistor 354 and SL 342. In some embodiments, the constant voltage difference Vg_Vs can be higher than the threshold voltage of the discharge transistor 354, allowing the discharge transistor 354 to be turned on. In some embodiments, the constant voltage difference Vg_Vs can be in the range of about 3V to about 10V. In some embodiments, the constant voltage difference Vg_Vs is 5V. To avoid causing FN stress on the discharge transistor 354, the constant voltage difference Vg_Vs can be selected to maintain a small FN stress voltage, for example, 15V.

[0091] Therefore, in operation step S720, BL 341 and gate terminal DS_GT can discharge at the same discharge rate as SL 342. Figure 6 As shown, the potential V of the gate terminal DS_GT GT The potential V of BL 341 BL The on-state voltage VGG and the erase voltage V at time T0 are respectively... erase It descends at the same slope as SL 342. Because BL 341 is electrically connected to SL 342 at approximately the same potential, source / drain junction breakdown can also be avoided during this period.

[0092] In operation step S730, the SL detection circuit 564 detects the potential V of SL 342. SLThe value is compared with a first predetermined value VF1. In some embodiments, in order to reduce damage to the gate dielectric of the discharge transistor 354, the first predetermined value VF1 may be selected in a range, for example, between 3V and 5V.

[0093] In operation step S740, the potential V of SL 342 is determined. SL Is it less than or lower than the first predetermined value VF1? If the potential V of SL 342 is... SL If the value is not lower than the first predetermined value VF1, then operation steps S720 and S730 can be repeated.

[0094] When the potential V of SL 342 SL When the voltage drops below a first predetermined value VF1, for example at time T1, the third switch 562 can be turned off according to operation step S750. As a result, the gate terminal DS_GT of the discharge transistor 354 can be floating. That is, no external bias is applied to the gate terminal DS_GT. Due to the capacitive coupling effect, the potential V of the gate terminal DS_GT... GT Following the potential V of SL342 SL The gate terminal DS_GT continues to discharge, but at a slower rate than SL 342. Meanwhile, discharge transistor 354 remains on, allowing BL 341 to continue discharging through it.

[0095] In operation step S760, the SL detection circuit 564 detects the potential V of SL342. SL Compare with the second predetermined value VF2.

[0096] In operation step S770, the potential V of SL 342 is determined. SL Is it less than or lower than the second predetermined value VF2? If the potential V of SL 342 is... SL If the value is not lower than the second predetermined value VF2, then operation steps S750 and S760 can be repeated.

[0097] When the potential V of SL 342 SL When the voltage drops below the second predetermined value VF2, for example at time T2, the second switch 358 can be turned on according to operation step S780. As a result, the gate terminal DS_GT is grounded, i.e., 0V is applied. Therefore, the gate terminal DS_GT can be quickly discharged to 0V. The discharge transistor 354 is turned off accordingly.

[0098] The second predetermined value VF2 can be less than the first predetermined value VF1. In some embodiments, to avoid source / drain junction breakdown, the second predetermined value VF2 can be selected to be lower than the source / drain junction breakdown voltage. In some embodiments, the second predetermined value VF2 can be between 0.5V and 3V, for example, the second predetermined value VF2 can be 1V or 2V. Therefore, even after the discharge transistor 354 is turned off, in the absence of a fast discharge path, the potential V of BL 341 is... BL It can also be controlled to be lower than the source / drain junction breakdown voltage.

[0099] When the discharge operation is finished, the first switch 356, the second switch 358 and the third switch 562 in the second discharge circuit 504 can be turned off.

[0100] Figure 8A and Figure 8B Schematic diagrams 800A and 800B are shown of a gate discharge circuit 566 according to some embodiments of the present disclosure. As previously described, the gate discharge circuit 566 can... Figure 5 The potential V of the gate terminal DS_GT shown GT With respect to the potential V of SL342 SL A constant voltage difference Vg_Vs is maintained between them. The gate discharge circuit 566 can be designed into the peripheral circuitry of a 3D NAND flash memory.

[0101] exist Figure 8A and Figure 8B In the circuit, the gate discharge circuit 566 includes a switching transistor 872 and a voltage level shifter 874. The source terminal of the switching transistor 872 can be connected to a voltage level V. SL SL 342 ( Figure 8A (Not shown in the image). For example... Figure 5 As shown, a third switch 562 can be inserted between SL 342 and the gate discharge circuit 566. In some embodiments, a switching transistor 872 can be implemented as the third switch 562. In some embodiments, a switching transistor 872 can be implemented in addition to the third switch 562. The switching transistor 872 can be turned on or off by a voltage level shifter 874 connected to the gate terminal of the switching transistor 872. The voltage level shifter 874 can adjust the potential V at the gate terminal DS_GT of the discharge transistor 354. GT Converted to the switching voltage V used to turn on the switching transistor 872 SW The voltage level shifter 874 can also be controlled by the enable signal dis_en to determine when the switching voltage V can be shifted. SW The switching current I flowing through the switching transistor 872 is supplied to the switching transistor 872. SW It can be determined by the switching voltage V SW Sure.

[0102] exist Figure 8A In the circuit, the gate discharge circuit 566 also includes a set of MOSFETs 870 connected in series. The first terminal of the set of MOSFETs 870 can be connected to the drain terminal of the switching transistor 872, and the second terminal of the set of MOSFETs 870 can be connected to a voltage V. GT The gate terminal DS_GT of the discharge transistor 354. Each MOSFET in the set of MOSFETs 870 can be configured as an effective diode—the gate terminal can be connected to the drain terminal. Thus, each MOSFET in the set can operate in its saturation mode. The voltage drop across each MOSFET in the set of MOSFETs 870 depends on the switching current I controlled by the switching transistor 872. SW The total voltage drop across a set of MOSFETs 870 from the first terminal to the second terminal can determine the potential V. GT With V SL A constant voltage difference Vg_Vs exists between them. Additionally, each MOSFET in the group of MOSFETs 870 can be bypassed by parallel switches (e.g., switches S1, S2, ...), allowing adjustment of the potential V. GT With V SL The constant voltage difference Vg_Vs between them.

[0103] A set of MOSFET 870s can include either p-channel MOSFETs or n-channel MOSFETs. Figure 8A The diagram illustrates a p-channel MOSFET as an example. To reduce body bias effects, preferably, the body of each MOSFET can be connected to the source terminal of the MOSFET. Since the body of the p-channel MOSFET is in an n-well and can be easily connected to its source terminal, preferably, a p-channel MOSFET can replace an n-channel MOSFET in a set of MOSFETs 870.

[0104] exist Figure 8B In the circuit, the gate discharge circuit 566 may further include a set of diodes 876 connected in series. The first terminal of the set of diodes 876 may be connected to the drain terminal of the switching transistor 872, and the second terminal of the set of diodes 876 may be connected to a diode at a potential V. GT The gate terminal DS_GT of the discharge transistor 354. The voltage drop across each diode in the group of diodes 876 depends on the switching current I controlled by the switching transistor 872. SW The total voltage drop across a set of diodes 876, from the first terminal to the second terminal, determines the potential V. GT With V SLThe constant voltage difference Vg_Vs between them. Additionally, each diode in the group of diodes 876 can be bypassed by parallel switches (e.g., switches S1, S2, ...), allowing the potential V to be adjusted. GT With V SL A constant voltage difference Vg_Vs exists between them. However, since diodes typically occupy a larger area than MOSFETs, to reduce costs, a p-channel MOSFET can preferably replace the diode in the gate discharge circuit 566.

[0105] Figure 9 A schematic diagram 900 of an SL detection circuit 564 according to some embodiments of the present disclosure is shown. As previously described, the SL detection circuit 564 can detect the potential V of the SL 342. SL Compare with a predetermined value (e.g., a first predetermined value VF1 or a second predetermined value VF2).

[0106] The SL detection circuit 564 includes an operational amplifier 980, which has a negative input and a positive input. The negative input of the operational amplifier 980 can be connected to a reference voltage V. REF Or input voltage V IN Switches SS0 and SS1 can be used to select the reference voltage V. REF Or input voltage V IN In some embodiments, operational amplifier 980 is a comparator.

[0107] The SL detection circuit 564 also includes a resistor divider 982 having a first resistor 984 connected in series with a second resistor 986. The first resistor 984 has a resistance R0, and the second resistor 986 has an adjustable resistance R1. In some embodiments, the second resistor 986 is a potentiometer. The resistor divider 982 is connected in parallel with a capacitor 988, wherein the first terminal 983 of the resistor divider 982 and the capacitor 988 are connected together to the positive input terminal of the operational amplifier 980 via a switch SS4. The second terminals of both the resistor divider 982 and the capacitor 988 are grounded. The capacitor 988 has a capacitance C0. The midpoint 985 between the first resistor 984 and the second resistor 986 is connected to the positive input terminal of the operational amplifier 980 via a switch SS2.

[0108] like Figure 9 As shown, the SL detection circuit 564 also includes a pull-up transistor 990. In some embodiments, the pull-up transistor 990 is a p-channel MOSFET, wherein the drain terminal of the pull-up transistor 990 is connected to the first terminal of the resistor divider 982 and the capacitor 988 via switch SS3, and the source terminal of the pull-up transistor 990 is connected to the power supply V. DDThe gate terminal of the pull-up transistor 990 is connected to a circuit with an output voltage V. OUT The output of the comparator.

[0109] Initially, predetermined values ​​(e.g., a first predetermined value VF1 and a second predetermined value VF2) used for the discharge operation in method 700 can be set to the SL detection circuit 564. Then, the input voltage V... IN (e.g., the potential V of SL 342) SL It is compared with a first predetermined value VF1, and then with a second predetermined value VF2.

[0110] Figure 10 A method 1000 for setting a predetermined value (e.g., a first predetermined value VF1 or a second predetermined value VF2) to an SL detection circuit 564, according to some embodiments of this disclosure, is illustrated. It should be understood that method 1000 is not exhaustive, and other operational steps may be performed before, after, or between any of the illustrated operational steps. In some embodiments, some operational steps of method 1000 may be omitted, or other operational steps may be included, which are not described herein for simplicity. In some embodiments, the operational steps of method 1000 may be performed in different orders and / or variations.

[0111] refer to Figure 9 and Figure 10 In operation step 1010, switch SS0 can be turned on and switch SS1 can be turned off. As a result, the negative input terminal of operational amplifier 980 is at the reference voltage V. REF .

[0112] In operation step 1020, switches SS2 and SS3 can be turned on, and switch SS4 can be turned off. As a result, the positive input terminal of operational amplifier 980 is connected to the midpoint 985 of resistor divider 982, where the midpoint 985 is at potential V0. An external feedback loop is formed from the output terminal of operational amplifier 980 to the positive input terminal through pull-up transistor 990 and resistor divider 982. Due to the high gain of the operational amplifier, the voltage difference between the positive and negative input terminals can be approximately zero. Therefore, the potential V0 at midpoint 985 can be set as the reference voltage V. REF That is, V0 = V REF .

[0113] In operation step 1030, through the resistor divider 982 and the pull-down transistor 990, the potential V1 at the first terminal 983 of the resistor divider 982 and capacitor 988 can be determined as follows: Thus, by adjusting the resistance R1 of the second resistor 986, or the resistance ratio between resistor R1 and R0, the potential V1 can be set to a predetermined value, such as a first predetermined value VF1 or a second predetermined value VF2.

[0114] In operation step 1040, capacitor 988, connected in parallel with resistor divider 982, is connected to power supply V via pull-up transistor 990. DD Charged to potential V1. Therefore, once the power supply V is disconnected... DD The potential V1, i.e., the first predetermined value VF1 or the second predetermined value VF2, can be maintained by capacitor 988.

[0115] As described above, in method 1000, operational amplifier 980 is configured as a voltage buffer, wherein the input voltage can be mirrored or followed at the output.

[0116] Figure 11 Some embodiments of the present disclosure are shown for converting input voltage V IN (For example, the potential V of SL 342) SL Method 1100 compares a potential V1 with a predetermined value (i.e., a potential V1, for example, a first predetermined value VF1 or a second predetermined value VF2). It should be understood that method 1100 is not exhaustive, and other operational steps may be performed before, after, or between any of the operational steps shown. In some embodiments, some operational steps of method 1100 may be omitted, or other operational steps may be included, which are not described herein for simplicity. In some embodiments, the operational steps of method 1100 may be performed in different orders and / or variations.

[0117] refer to Figure 9 and Figure 11 In operation step 1110, switches SS2 and SS3 can be turned off, and switch SS4 can be turned on. At power supply V... DD After the resistor divider 982 and capacitor 988 are disconnected, the potential V1 held by capacitor 988 (e.g., a first predetermined value VF1 or a second predetermined value VF2) can be connected to the positive input terminal of operational amplifier 980.

[0118] In operation step 1120, switch SS0 can be turned off and switch SS1 can be turned on. Therefore, the input voltage V IN It can be connected to the negative input terminal of operational amplifier 980.

[0119] In operation step 1130, the operational amplifier 980 can convert the input voltage V IN It is compared with potential V1. Here, operational amplifier 980 is configured as a comparator, in which the voltages at its two input terminals can be compared.

[0120] In operation step 1140, determine the input voltage V. IN Is it below potential V1?

[0121] In operation step 1150, when the input voltage V IN When the voltage is below potential V1 (e.g., a first predetermined value VF1 or a second predetermined value VF2), the output voltage V OUT It can be positive or logical "1".

[0122] In operation step 1160, when the input voltage V IN When the voltage is higher than the potential V1 (e.g., the first predetermined value VF1 or the second predetermined value VF2), the output voltage can be negative or logic "0".

[0123] As described above, a constant voltage difference Vg_Vs is provided between the gate terminal DS_GT of the discharge transistor 354 and SL342 by adding a gate discharge circuit 566, and a potential Vg_Vs of SL342 is detected by introducing an SL detection circuit 564. SL By comparing the first predetermined value VF1 and the second predetermined value VF2, the discharge operation of the 3D NAND flash memory can be optimized. First, the discharge transistor 354 remains on to discharge BL 342. By maintaining a constant voltage difference Vg_Vs between the gate terminal DS_GT and SL 342 of the discharge transistor 354, a high voltage difference between the source terminal DS_S and the drain terminal DS_D can be avoided. Therefore, source / drain junction breakdown of the discharge transistor 354 can be avoided. The constant voltage difference Vg_Vs can also be used to avoid FN stress that would cause damage to the gate dielectric of the discharge transistor 354. Then, when discharging the gate terminal DS_S of the discharge transistor 354, the potential V of SL 342 is adjusted... SL Comparing with the first predetermined value VF1 and the second predetermined value VF2 can also prevent source / drain junction breakdown or FN stress.

[0124] Note that the discharge methods and circuits described in this disclosure are not limited to three-dimensional NAND flash memory or NAND flash memory. Any system with discharge operation can employ the above methods and circuits to achieve improved performance and reliability.

[0125] In summary, this disclosure provides a discharge circuit for discharging a memory device after an erase operation. The discharge circuit includes a discharge transistor connected to a bit line and a source line of the memory device. The discharge circuit also includes a source line detection circuit connected to the source line and configured to compare the potential of the source line with a predetermined value. The discharge circuit further includes a gate discharge circuit configured to maintain a constant voltage difference between the discharge transistor and the source line, wherein the constant voltage difference applied to the discharge transistor and the source line turns on the discharge transistor.

[0126] This disclosure also provides a method for discharging a memory device after an erase operation. The method includes grounding the source line of the memory device; and turning on the discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between the gate terminal of the discharge transistor and the source line. The method further includes comparing the potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the potential of the source line is lower than the first predetermined value.

[0127] This disclosure also provides a memory device having a memory block and peripheral circuitry. The memory block includes multiple memory strings connected to source lines and multiple bit lines. The peripheral circuitry includes a discharge circuit configured to discharge the memory block after an erase operation. The discharge circuit includes multiple discharge transistors. Each discharge transistor is configured to connect a source line to a corresponding bit line. The discharge circuit also includes a source line detection circuit connected to a source line and configured to compare the potential of the source line with a predetermined value. The discharge circuit also includes a gate discharge circuit configured to maintain a constant voltage difference between the gate terminals of the multiple discharge transistors and the source lines.

[0128] The foregoing description of the specific embodiments so fully reveals the general nature of this disclosure that others can readily modify and / or adapt these specific embodiments for various applications by applying knowledge of the art without excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the disclosure and guidance presented herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive rather than limiting purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on the disclosure and guidance.

[0129] Embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0130] The summary and abstract section may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and therefore is not intended to limit this disclosure and the appended claims in any way.

[0131] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A discharge circuit for discharging a memory device after an erase operation, comprising: A discharge transistor that connects the bit line and source line of the memory device; A source line detection circuit is connected to the source line and configured to compare the potential of the source line with a predetermined value. as well as A gate discharge circuit is connected to the source line and the gate terminal of the discharge transistor and is configured to maintain a constant voltage difference between the discharge transistor and the source line, wherein the constant voltage difference applied to the discharge transistor and the source line turns on the discharge transistor, and wherein the gate discharge circuit includes a set of diodes connected in series.

2. The discharge circuit according to claim 1, wherein, The discharge transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). The gate terminal of the MOSFET is connected to the gate discharge circuit, the source terminal of the MOSFET is connected to the source line, and the drain terminal of the MOSFET is connected to the bit line.

3. The discharge circuit according to claim 1, wherein, Each of the diodes in the group is connected in parallel with the switch, making the constant voltage difference adjustable.

4. The discharge circuit according to claim 1, wherein, The gate discharge circuit also includes a switching transistor connected in series with the set of diodes.

5. The discharge circuit according to claim 4, wherein, The gate discharge circuit further includes a voltage level shifter configured to provide a switching voltage to turn on the switching transistor.

6. The discharge circuit according to claim 1, wherein, The set of diodes includes a MOSFET configured as an effective diode, wherein the gate terminal of the MOSFET is connected to the drain terminal of the MOSFET.

7. The discharge circuit according to claim 6, wherein, The MOSFET is a p-channel MOSFET.

8. The discharge circuit according to claim 1, wherein, The source line detection circuit includes: Operational amplifier; Resistor voltage divider; and A capacitor is connected in parallel with the resistive voltage divider, wherein: The capacitor is connected to the first terminal of the resistor divider; and The second terminal of the capacitor and the resistor divider is grounded.

9. The discharge circuit according to claim 8, wherein, The source line detection circuit further includes a pull-up transistor that connects the first terminal of the capacitor and the resistor divider to the power supply, wherein the pull-up transistor is controlled by the output of the operational amplifier.

10. The discharge circuit according to claim 8, wherein, The voltage divider includes a first resistor connected in series with a second resistor, the second resistor including an adjustable resistor.

11. The discharge circuit according to claim 8, wherein, The operational amplifier is configured to set the predetermined value via the potential of the capacitor and the first terminal of the resistor divider, wherein: The negative input terminal of the operational amplifier is connected to a reference voltage; and The positive input terminal of the operational amplifier is connected to the midpoint of the resistor divider.

12. The discharge circuit according to claim 8, wherein, The operational amplifier is configured to compare the potential of the source line with the predetermined value, wherein: The negative input terminal of the operational amplifier is connected to the source line; and The positive input terminal of the operational amplifier is connected to the capacitor and the first terminal of the resistor divider.

13. The discharge circuit according to claim 1, wherein, The source line is grounded.

14. The discharge circuit according to claim 13, further comprising: A current source is configured to regulate the discharge current flowing through the source line.

15. A method for discharging a memory device after an erase operation, comprising: Ground the source line of the memory device; The memory device bit line is connected to the source line by turning on the discharge transistor by maintaining a constant voltage difference between the gate terminal of the discharge transistor and the source line by a gate discharge circuit, wherein the gate discharge circuit includes a group of diodes connected in series and the gate discharge circuit is connected to the gate terminal of the discharge transistor and the source line. Compare the potential of the source line with a first predetermined value; and When the potential of the source line is lower than the first predetermined value, the gate terminal of the discharge transistor is floated.

16. The method of claim 15, further comprising: The potential of the source line is compared with a second predetermined value, wherein the second predetermined value is less than the first predetermined value.

17. The method of claim 16, further comprising: When the potential of the source line is lower than the second predetermined value, the gate terminal of the discharge transistor is grounded.

18. The method according to claim 16, wherein, The first predetermined value is in the range of 3V to 5V.

19. The method of claim 16, wherein, The second predetermined value is in the range of 0.5V to 3V.

20. The method of claim 15, further comprising: The discharge current flowing through the source wire is adjusted by a current source.

21. The method of claim 15, further comprising: The first predetermined value is set to be less than the source / drain junction breakdown voltage of the discharge transistor.

22. The method according to claim 15, wherein, The erase operation is assisted by a gate-induced drain leakage (GIDL) current flowing through the bit line and the source line of the memory device.

23. A memory device, comprising: A memory block comprises multiple memory strings connected to source lines and multiple bit lines; as well as Peripheral circuitry, including: A discharge circuit, configured to discharge the memory block after an erase operation, includes: A plurality of discharge transistors, wherein each of the plurality of discharge transistors is configured to connect the source line to a corresponding bit line; A source line detection circuit, connected to the source line and configured to compare the potential of the source line with a predetermined value; and A gate discharge circuit is connected to the source line and the gate terminal of the discharge transistor, and is configured to maintain a constant voltage difference between the gate terminal of the plurality of discharge transistors and the source line, wherein the gate discharge circuit includes a group of diodes connected in series.

24. The memory device of claim 23, wherein, The plurality of discharge transistors are turned on during the erase operation, such that the plurality of bit lines are connected to the source lines.

25. The memory device of claim 24, wherein, The multiple bit lines and the source lines are subjected to an erase voltage during the erase operation.

26. The memory device of claim 24, wherein, Gate-induced drain leakage (GIDL) current flows through each of the multiple bit lines and the source line to assist the erase operation.

27. A memory system comprising: Memory devices, including: A memory block includes multiple memory strings connected to source lines and multiple bit lines; and Peripheral circuitry, including: A discharge circuit, configured to discharge the memory block after an erase operation, includes: A plurality of discharge transistors, wherein each of the plurality of discharge transistors is configured to connect the source line to a corresponding bit line; A source line detection circuit, connected to the source line and configured to compare the potential of the source line with a predetermined value; and A gate discharge circuit, connected to the source line and the gate terminal of the discharge transistors, and configured to maintain a constant voltage difference between the gate terminals of the plurality of discharge transistors and the source line, wherein the gate discharge circuit includes a group of diodes connected in series; and A memory controller is configured to manage the memory device via a memory channel.

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