Method for operating a drive system and drive system for carrying out the method

Abstract

The invention relates to a method for operating a drive system having a plurality of inverters, wherein the respective electric motor is fed from a connection on the AC voltage side of the respective inverter, wherein the connections on the DC voltage side of the respective inverters are connected in parallel to one another and this parallel circuit is connected to a connection on the DC voltage side of a rectifier, wherein each inverter has semiconductor switches which are operated in accordance with a respective pulse width modulation, wherein the inverters are configured as bus users of a data bus, to which a module configured as a master device is also connected, wherein the master device assigns a bus address to the inverters and subsequently assigns to each inverter the polarity of its pulse width modulation.

Description

Technical Field

[0001] The present invention relates to a method for operating a drive system and a drive system for performing the method. Background Technology

[0002] As is well known, drive systems enable the operation of electric motors through speed regulation or torque regulation.

[0003] As the closest prior art, a method for operating an electric drive system is known from DE 102018 210 244 A1.

[0004] A method for regulating an intermediate voltage circuit is known from DE 102016 008 951 A1. Summary of the Invention

[0005] Therefore, the object of the present invention is to develop a drive system that increases service life.

[0006] According to the present invention, this objective is achieved by a drive system and method having the following features.

[0007] An important feature of the method for operating a drive system with multiple, particularly more than two, inverters is that the corresponding motors are powered by the AC voltage side terminals of the corresponding inverters.

[0008] The DC voltage side terminals of the respective inverters are connected in parallel to each other, and this parallel circuit is connected to the DC voltage side terminals of the rectifier, especially the feedback rectifier, particularly via a busbar.

[0009] Each inverter has a semiconductor switch controlled according to a corresponding pulse width modulation.

[0010] The inverter is configured as a bus user of the data bus, and the module configured as the master device is also connected to this data bus.

[0011] In particular, one of the modules includes the rectifier.

[0012] The master device, in particular, assigns bus addresses to the inverters during the initial operation of the drive system, and subsequently specifies the polarity of the pulse width modulation for each inverter, especially its pulse width modulation method.

[0013] The pulse width modulation polarity of the first inverter is different from that of the second inverter.

[0014] In particular, the pulse width modulation of the drive signal for the controllable semiconductor switch of the first inverter and the pulse width modulation of the drive signal for the controllable semiconductor switch of the second inverter are configured to be performed in reverse synchronization on the clock.

[0015] The advantage of doing this is that the compensation current, especially the leakage current, is reduced, and the grid filter on the grid side of the rectifier therefore has a longer service life.

[0016] In a favorable design, each inverter has a DC-fed half-bridge connected in parallel with each other, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches.

[0017] In this process, the semiconductor switches of the corresponding inverter are controlled based on the pulse width modulation (PWM) drive signal and the inverter's PWM and polarity. The advantage of this is that different inverters can have different polarities. Therefore, the compensation current in or through the intermediate circuit can be reduced, and components can withstand lower loads, especially the grid filter located at the AC voltage side of the rectifier.

[0018] In a favorable design, at the start of the corresponding pulse width modulation cycle, the upper switch of the first half-bridge of the first inverter is opened, and the lower switch of the first half-bridge of the first inverter is closed.

[0019] Specifically, the upper switch is connected to the high potential of the voltage present at the DC voltage side terminal of the inverter, and the lower switch is connected to the low potential of the voltage present at the DC voltage side terminal of the inverter. The advantage of this is that the first inverter has a positive polarity and can therefore assign the reverse (i.e., negative) polarity to the next adjacent inverter.

[0020] In a favorable design, starting with the main unit, the inverters are arranged in series along the data bus.

[0021] In the first method step, starting with the master device, and particularly sequentially, each inverter assigns a bus address to the inverter downstream of it in the series structure, until it is identified as the last in the series structure because it is no longer possible to assign bus addresses, and subsequently...

[0022] In the second method step, a default value is determined for the polarity of its pulse width modulation, and then, starting from the last inverter and sequentially, each inverter passes on a polarity reversed with its own to the inverter upstream in the series structure.

[0023] The upstream inverter determines the polarity of the polarity reversal as the polarity of its pulse width modulation.

[0024] Especially when it is not constructed as a dual inverter, particularly a dual-axis inverter, and continues to transmit its power to an inverter located upstream of it,

[0025] In particular, the dual-inverter configuration features a single bus address and two independent inverters arranged in a common housing, with their pulse width modulations having polarities that are reversed relative to each other. The advantage of this is that it allows for decentralized, automatic allocation of addresses and polarities, rather than centralized allocation.

[0026] In a favorable design, the data bus has a forward channel and a reverse channel, such that each inverter has both forward channel input and output, as well as reverse channel input and output. The master device is connected to the forward channel input of the first inverter and to the reverse channel output of the first inverter.

[0027] For address allocation, the master device sends a first bus address to the first inverter via the forward channel, and the first inverter uses this first bus address as its own bus address.

[0028] The first inverter generates a second bus address from a first bus address, specifically by incrementing it, and sends it to the second inverter via a forward channel. The second inverter uses the second bus address and generates a third bus address from it, specifically by incrementing it, and forwards it via its forward channel.

[0029] Each additional inverter uses the bus address received via its positive channel input as its own bus address, and generates another bus address from the received bus address, specifically by incrementing it, and sends it to the downstream inverter via the positive channel.

[0030] The last inverter is identified as the last inverter because further transmission of its generated bus address fails. The advantage of this approach is that it provides high security because the forward and reverse channels are separate, and each bus user can first check the received data to determine if it is valid for them or if they should continue forwarding it.

[0031] In a favorable design, especially during initial operation, the master device repeatedly / periodically sends broadcast messages via the data bus to assign addresses, particularly during startup. These broadcast messages assign polarity information to the corresponding address information, specifically assigning a first polarity to the first inverter and a second polarity, distinct from the first, to the second inverter. The advantage of this approach is that only one inverter is always in standby mode, using the address transmitted with the broadcast message, allowing the inverters to sequentially obtain addresses.

[0032] In a favorable design, the voltage signal can be fed from the main inverter to the first inverter, and the voltage signal can be fed from the corresponding inverter to the corresponding next inverter.

[0033] The corresponding inverter receiving the voltage signal then extracts the address and / or polarity information contained in the broadcast message from the master device at the next available time. The advantage of this is that only one inverter is always ready to extract the address contained in the broadcast message, and after the inverter extracts the address, it forwards the voltage signal to switch the next inverter into a ready state.

[0034] In a favorable design, regarding the forwarding of voltage signals and / or the data bus, the inverters are arranged in series in a row, particularly such that in this series structure, from the first inverter to the penultimate inverter, another inverter is arranged after each inverter. The advantage of this is that the inverters can be connected to a serial data bus.

[0035] In a favorable design, the last inverter, especially one from which no downstream inverter can feed a voltage signal, assigns a polarity opposite to that used by its upstream inverter in pulse width modulation.

[0036] The upstream inverter then assigns a polarity opposite to that used by its upstream inverter in pulse width modulation. The advantage of this is that address allocation within the inverter row proceeds forward, while polarity allocation proceeds backward within the series configuration.

[0037] In a favorable design, after address assignment to the inverters, the master device will transmit the polarity to be used in the pulse width modulation of each inverter to these inverters.

[0038] The polarities are allocated in such a way that the sum of the products of the rated / nominal power of each inverter and its corresponding polarity is minimized.

[0039] Especially when adjacent inverters are preferably arranged with different polarities. The advantage of this is that the different polarities, based on the inverters' respective nominal power, result in the smallest possible load through compensation current, particularly leakage current, and especially in the intermediate circuit. The sum of the products of nominal power and polarity is preferably as small as possible.

[0040] In a favorable design, for address allocation, the corresponding inverter inputs a voltage signal to the inverter positioned downstream, using this voltage signal to notify the corresponding downstream inverter. It then uses the address contained in the next broadcast message from the master device (which is later in time) as its own bus address and inputs another voltage signal to the other inverter (if that other inverter exists). Otherwise, it adjusts the polarity of its pulse width modulation based on the polarity information contained in the broadcast message. The advantage of this approach is that it allows for distributed polarity allocation.

[0041] In a favorable design, the drive system has a first inverter and a second inverter, wherein the first motor is fed by the AC voltage side connector of the first inverter.

[0042] The second motor is powered by the AC voltage side connector of the second inverter.

[0043] The DC voltage side terminals of the first inverter and the second inverter are connected in parallel, and this parallel connection is powered by DC voltage, particularly intermediate circuit voltage, especially via a bus.

[0044] The first inverter has two DC-fed half-bridges connected in parallel with each other, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches.

[0045] The second inverter has two parallel half-bridges fed by DC voltage, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches.

[0046] The semiconductor switches of the first inverter are controlled by pulse-width modulated drive signals.

[0047] The semiconductor switches of the second inverter are controlled by pulse-width modulated drive signals.

[0048] The pulse width modulation (PWM) configuration of the drive signal for the controllable semiconductor switch used in the first inverter is configured to be timed / beat / pulsed in reverse synchronization with the PWM configuration of the drive signal for the controllable semiconductor switch used in the second inverter.

[0049] The advantage of this approach is that it reduces or prevents leakage current on the DC voltage side, especially the compensation current. This also reduces the load on the mains filter and consequently increases its lifespan, thus extending the lifespan of the entire drive system.

[0050] In a favorable design, the drive system has a first inverter and a second inverter, wherein the first motor is fed by the AC voltage side connector of the first inverter.

[0051] The second motor is powered by the AC voltage side connector of the second inverter.

[0052] The DC voltage side terminals of the first inverter and the second inverter are connected in parallel, and this parallel circuit is powered by DC voltage, particularly intermediate circuit voltage, especially by means of a bus.

[0053] The first inverter has two DC-fed half-bridges connected in parallel with each other, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches.

[0054] The second inverter has two parallel half-bridges fed by DC voltage, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches.

[0055] The semiconductor switches of the first inverter are controlled by pulse-width modulated drive signals.

[0056] The semiconductor switches of the second inverter are controlled by pulse-width modulated drive signals.

[0057] in

[0058] - As long as the quotient of the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is less than a threshold, especially 1, then at the beginning of the corresponding pulse width modulation period,

[0059] The upper switch of the first half-bridge of the first inverter is opened, and the lower switch of the first half-bridge of the first inverter is closed.

[0060] This closes the upper switch of the second half-bridge of the second inverter and opens the lower switch of the second half-bridge of the second inverter.

[0061] - And, as long as the quotient of the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is greater than a threshold, especially 1, then at the beginning of the corresponding pulse width modulation period,

[0062] The upper switch of the first half-bridge of the first inverter is opened, and the lower switch of the first half-bridge of the first inverter is closed.

[0063] The upper switch of the second half-bridge of the second inverter is opened, and the lower switch of the second half-bridge of the second inverter is closed.

[0064] The advantage of doing this is that the compensation current is reduced, which in turn reduces the load on the grid filter and thus increases its lifespan.

[0065] In a favorable design, the drive system has a first inverter and a second inverter, wherein the first motor is fed by the AC voltage side connector of the first inverter.

[0066] The second motor is powered by the AC voltage side connector of the second inverter.

[0067] The DC voltage side terminals of the first inverter and the second inverter are connected in parallel, and this parallel connection is powered by DC voltage, particularly intermediate circuit voltage, especially via a bus.

[0068] The first inverter has two DC-fed half-bridges connected in parallel with each other, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches.

[0069] The second inverter has two parallel half-bridges fed by DC voltage, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches.

[0070] The semiconductor switches of the first inverter are controlled by pulse-width modulated drive signals.

[0071] The semiconductor switches of the second inverter are controlled by pulse-width modulated drive signals.

[0072] in

[0073] - As long as the difference between the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is less than a threshold, especially 50%, then at the beginning of the corresponding pulse width modulation period,

[0074] The upper switch of the first half-bridge of the first inverter is opened, and the lower switch of the first half-bridge of the first inverter is closed, and...

[0075] This closes the upper switch of the second half-bridge of the second inverter and opens the lower switch of the same second half-bridge.

[0076] - And, as long as the difference between the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is greater than a threshold, especially 50%, then at the beginning of the corresponding pulse width modulation period,

[0077] The upper switch of the first half-bridge of the first inverter is opened, and the lower switch of the first half-bridge of the first inverter is closed, and...

[0078] The upper switch of the second half-bridge of the second inverter is opened, and the lower switch of the second half-bridge of the second inverter is closed.

[0079] The advantage of doing this is that the compensation current is reduced, which in turn reduces the load on the grid filter and thus increases its lifespan.

[0080] In a favorable design, DC voltage is supplied for use at the DC voltage side connector of the grid-fed rectifier.

[0081] In particular, the rectifier, especially at its AC voltage side terminals, is powered by an AC voltage network, particularly utilizing three-phase voltage.

[0082] Specifically, the DC-side connectors of the rectifier are connected in parallel with the DC voltage side connectors of the first inverter and the second inverter. This reduces the compensation current, thereby reducing the load on the grid filter and increasing its lifespan.

[0083] In a favorable design, the pulse width modulation (PWM) signals of the first inverter and the second inverter are modulated simultaneously, particularly synchronously. This reduces the compensation current, thereby reducing the load on the grid filter and thus increasing its lifespan.

[0084] In a favorable design, the pulse width modulation cycles of the first and second inverters start synchronously and / or simultaneously. This reduces the compensation current, thereby reducing the load on the grid filter and thus increasing its lifespan.

[0085] In a favorable design, within each pulse width modulation cycle, the first switching edge of the drive signal for the upper semiconductor switch of the first inverter extends in reverse and / or opposite directions to the first switching edge of the drive signal for the upper semiconductor switch of the second inverter. This reduces the compensation current, and consequently reduces the load on the grid filter, thereby increasing its lifespan.

[0086] In a favorable design, one of the controllable semiconductor switches in the corresponding half-bridge, namely the upper semiconductor switch, is connected to the high potential of the DC voltage.

[0087] In a favorable design, one of the controllable semiconductor switches in the corresponding half-bridge, namely the lower semiconductor switch, is connected to a low potential DC voltage. The advantage of doing so is that the half-bridge (i.e., the bridge branch) can be powered by a DC voltage, and the half-bridge can be constructed as a series circuit of two semiconductor switches (especially IGBTs or MODFETs).

[0088] In a favorable design, at the start of the corresponding pulse width modulation period...

[0089] The upper switch of the first half-bridge of the first inverter is open, and the lower switch of the first half-bridge of the first inverter is closed.

[0090] The upper switch of the second half-bridge of the second inverter is closed, and the lower switch of the second half-bridge of the second inverter is open. The advantage of doing this is that the compensation current is minimized by using two pulse-width modulated clocks that are relatively opposite to each other for the two inverters.

[0091] In a favorable design scheme,

[0092] - As long as the quotient of the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is less than a threshold, especially 1,

[0093] Then at the beginning of the corresponding pulse width modulation period,

[0094] The upper switch of the first half-bridge of the first inverter is open, and the lower switch of the first half-bridge of the first inverter is closed, and

[0095] The upper switch of the second half-bridge of the second inverter is closed, and the lower switch of the second half-bridge of the second inverter is open.

[0096] - And, provided that the quotient of the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is greater than a threshold, especially 1,

[0097] Then at the beginning of the corresponding pulse width modulation period,

[0098] The upper switch of the first half-bridge of the first inverter is open, and the lower switch of the first half-bridge of the first inverter is closed, and

[0099] The upper switch of the second half-bridge of the second inverter is open, and the lower switch of the second half-bridge of the second inverter is closed.

[0100] The advantage of this approach is that the clock reversal is only executed if the threshold is not exceeded. Therefore, the compensation current is minimized as much as possible.

[0101] In a favorable design scheme

[0102] - Provided that the difference between the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is less than a threshold value, specifically 50%,

[0103] Then at the beginning of the corresponding pulse width modulation period,

[0104] The upper switch of the first half-bridge of the first inverter is open, and the lower switch of the first half-bridge of the first inverter is closed, and

[0105] The upper switch of the second half-bridge of the second inverter is closed, and the lower switch of the second half-bridge of the second inverter is open.

[0106] - And, provided that the difference between the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is greater than a threshold value, specifically 50%,

[0107] Then at the beginning of the corresponding pulse width modulation period,

[0108] The upper switch of the first half-bridge of the first inverter is open, and the lower switch of the first half-bridge of the first inverter is closed, and

[0109] The upper switch of the second half-bridge of the second inverter is open, and the lower switch of the second half-bridge of the second inverter is closed.

[0110] The advantage of this approach is that the clock reversal is only executed if the threshold is not exceeded. Therefore, the compensation current is minimized as much as possible.

[0111] In a favorable design, a synchronization signal, particularly a synchronization signal with a synchronization pulse, is modulated onto a bus that connects the DC voltage side terminals of the inverters to each other and to the DC voltage side terminals of the rectifier. This has the advantage that the pulse width modulation frequency of the first inverter is synchronized with the pulse width modulation frequency of the second inverter, and thus, opposite clocks can be executed synchronously. The synchronization signal can be transmitted via a data bus connection connecting the signal electronics of the two inverters. Alternatively, modulation can be performed on the bus, thus eliminating the need for an additional communication connection between the inverters.

[0112] In a drive system used to perform one of the aforementioned methods, an important feature is that the terminals on the DC voltage side of the inverter are connected to each other via busbars and are connected to the terminals on the DC voltage side of the rectifier.

[0113] The advantage of doing this is that it enables simple and inexpensive connections. Attached Figure Description

[0114] The invention will be explained in more detail here with reference to the schematic diagram:

[0115] Figure 1 The diagram shows the phase voltage at the first terminal on the AC voltage side of the first inverter 1 and the phase voltage at the first terminal on the AC voltage side of the first inverter 2.

[0116] Figure 2The diagram shows the phase voltage relative to the ground potential.

[0117] Figure 3 The diagram shows a drive system with more than two inverters according to the present invention. Detailed Implementation

[0118] like Figure 1 and Figure 2 As shown, the first drive system according to the present invention has a first inverter 1 and a second inverter 2, which are powered by DC voltage in parallel using their DC voltage side terminals.

[0119] The DC voltage is preferably supplied by a rectifier fed from the power grid.

[0120] Each of the two inverters (1, 2) preferably has a smoothing capacitor, especially a multi-plate smoothing capacitor, at the junction on its DC voltage side.

[0121] Each of the two inverters (1, 2) has three parallel series circuits, each series circuit having two controllable semiconductor switches. Therefore, the corresponding phase voltage is supplied to the motor at the connection node of the two controllable semiconductor switches in the respective series circuit.

[0122] The AC voltage side terminals of the inverter are preferably constructed as three-phase, that is, each inverter (1, 2) has three such series circuits, and thus provides three-phase voltage for the motor.

[0123] Each inverter (1, 2) has an electronic circuit configured as a signal electronics device, which generates a pulse-width modulated drive signal for the controllable semiconductor switches of the inverter (1, 2).

[0124] like Figure 1 As shown, in order to generate the corresponding value of the phase voltage, the pulse width modulation ratio is specified within the pulse width modulation period. Figure 1 The diagram shows a 50% pulse width modulation ratio. In this case, at the beginning of the pulse width modulation period, the lower semiconductor switch of the series circuit is closed and the upper semiconductor switch of the series circuit is open. That is, in this case, the connector for the phase voltage is connected to the low potential of the DC voltage—that is, the intermediate circuit voltage U_z. After one-quarter of the pulse width modulation period has elapsed, the lower semiconductor switch is open and the upper semiconductor switch is closed, so that the connector for the phase voltage is now connected to the high potential of the DC voltage, which continues for half the period duration.

[0125] According to the invention, the second inverter 2 operates on a switching edge opposite to that of the first inverter. Figure 1In this example, a 50% pulse width modulation ratio is again selected. However, in this case, in the series circuit of the second inverter 2, at the beginning of the pulse width modulation cycle, the upper semiconductor switch of the series circuit is closed and the lower semiconductor switch of the series circuit is open. That is, in this case, the terminal for the phase voltage of the second inverter 2 associated with this series circuit is connected to the high potential of the DC voltage, i.e., the intermediate circuit voltage U_z. After one-quarter of the pulse width modulation cycle duration has passed, the upper semiconductor switch is open and the lower semiconductor switch is closed, so that the terminal for the phase voltage is connected to the low potential of the DC voltage at this time, which lasts for half of the cycle duration.

[0126] If the pulse width modulation ratio is controlled to be other than 50% in the series circuit, the corresponding switch moves towards positive (Plus+) or negative (Minus-), as if from... Figure 1 This can be seen from the diagram. Therefore, the semiconductor switches of the half-bridge of the first inverter 1 do not switch precisely and simultaneously with the half-bridge of the second inverter 2.

[0127] In this way, the compensation current between the terminals on the DC voltage side of the inverters (1, 2) in the intermediate circuit is reduced or even completely eliminated.

[0128] This advantage according to the invention is particularly important if the cable used from the AC voltage side connector of the respective inverter (1, 2) to the corresponding motor is long. This is because there is a high grounding capacitance in the cable and the motor, which causes the common grid filter arranged on the voltage feeder that provides the DC voltage to be subjected to high leakage current.

[0129] If the first switching edge jumps to a high potential within the pulse width modulation period, the pulse width modulation is positive. If the first switching edge jumps to a low potential within the pulse width modulation period, the pulse width modulation is negative.

[0130] To synchronize the pulse width modulation of the two inverters (1, 2), a synchronization signal is repeatedly transmitted in time. For this purpose, it is preferable to connect the signal electronics of the first inverter 1 to the signal electronics of the second inverter 2 via a data bus. In the simplest case, this data bus connection is constructed as a wired connection, particularly in a shielded cable.

[0131] Alternatively, the synchronization signal is modulated onto the DC voltage side connection of the inverters (1, 2). Since the high potential of the DC voltage side connection of the first inverter 1 is preferably connected to the high potential of the DC voltage side connection of the second inverter 1 via a bus to allow for strong current flow, the synchronization signal is modulated onto the current present in the bus. Coupling of the intermediate frequency or high frequency synchronization signal to the bus in the first inverter 1 is achieved via a capacitor; decoupling of the signal in the second inverter 2 is also achieved via a capacitor. Alternatively, although inductive and thus reliable, potential-free coupling and decoupling can also be achieved, this results in higher costs.

[0132] In another embodiment of the invention, the inversion of the pulse width modulation signal in the second inverter 2 is performed / operated only when the absolute value of the difference between the two pulse width modulation ratios is less than 50%. When it exceeds 50%, the inversion is canceled and a pulse width modulation signal with the same synchronized clock is used.

[0133] Alternatively, the quotient of the two pulse width modulation ratios can be used as a standard. If the quotient exceeds 1, the above inversion is applied; otherwise, it is not.

[0134] In this way, a reduction in the compensation current is achieved even when the operating points of the two inverters (1, 2) are significantly different. This is the case, for example, when the first inverter 1 generates a high-phase voltage, i.e., a high potential close to the DC voltage, and the second inverter 2 generates a low-phase voltage, i.e., a low potential close to the DC voltage. An example of the high-phase voltage is 0.9 U_z, and an example of the low-phase voltage is 0.1 * U_z.

[0135] like Figure 3 As shown, the second drive system has a data bus 35, through which the power supply module of the master device 3 is connected to the inverters (31, 32, 33, 34) for data exchange.

[0136] The power supply module has a grid-fed rectifier that supplies power to the inverters (31, 32, 33, 34) from its DC voltage side connector. For this purpose, the DC voltage side connectors of the inverters (31, 32, 33, 34) are connected in parallel to the DC voltage side connectors of the rectifier.

[0137] Preferably, the rectifier is configured to provide feedback, specifically as an AC / DC converter. When the drive system primarily powers the motor, this AC / DC converter rectifies the power from the AC voltage supply network and provides it as an intermediate circuit voltage to the inverter at the DC voltage side terminal. When the drive system primarily powers the generator, the power is fed back from the DC voltage side terminal of the rectifier to the AC voltage network. Furthermore, when the drive system starts operating, the power supply module configured as the master device 30 first assigns a bus address to the inverters (31, 32, 33, 34) configured as bus users and arranged in series with respect to the data bus.

[0138] For this purpose, the master device 30 assigns a first bus address to the first inverter 31, which is arranged serially from the master device's perspective. This is accomplished by the master device 30 generating a voltage signal that is communicated to the first inverter 1, which is directly connected by wires. The first inverter adopts the bus address contained in the next broadcast message sent by the master device as its own bus address. Then, the first inverter 31 similarly generates a voltage signal for the second inverter 32, so that the bus address contained in the next broadcast message is adopted by the second inverter 32. This method of address allocation continues until the last inverter 34 is configured as a bus user.

[0139] After or upon address allocation, the master device sends the specified polarity of the pulse width modulation (PWM) to the last bus user, or the last bus user uses the default value for its polarity. Therefore, the PWM is determined for the last inverter, specifically the direction of the first (time-first) switching edge within each PWM cycle. For example, the direction of this first switching edge is specified as a rising edge rather than a falling edge.

[0140] Subsequently, the last inverter 34 generates a voltage signal on the wire or another wire, thereby specifying the inverted edge direction of the first switching edge of the pulse width modulation for the preceding inverter 33. This can also be easily achieved by the last inverter 34 transmitting a polarity reversed with its own to the preceding inverter 33. This method continues up to the first inverter 31, so that the corresponding next adjacent bus user has its respective first switching edge with a relatively reversed edge direction in the corresponding pulse width modulation cycle.

[0141] Advantageously, the main equipment does not need to pre-calculate which inverter gets which polarity, and thus does not perform any centralized allocation, but rather distributes the polarity in a decentralized manner.

[0142] In another embodiment of the invention, after an address is assigned to a bus user, the nominal power is determined by the corresponding inverter and then polarity is assigned based on that nominal power, such that approximately half of the nominal power of the drive system has a first polarity, and the remaining inverters have the opposite polarity. Here, the polarity is preferably additionally assigned such that the next adjacent inverter in the series connection has as different polarities as possible.

[0143] Therefore, the allocation of polarity is based on these two optimization criteria.

[0144] The second inverter 32 has two AC voltage side terminals, so that the second motor M2 and the third motor M3 can be supplied with pulse-width modulated voltages respectively. Here, the same polarity is used in the two pulse-width modulations because the two pulse-width modulations are performed in the same device, that is, in the same housing.

[0145] Equally important in the drive system is the placement of a grid filter between the AC voltage supply network, preferably configured as a three-phase voltage network, and the AC voltage side connector of the rectifier in the power supply module.

[0146] The power grid filter has three capacitors that are electrically connected to each other at their first terminals and connected at their other terminals to the corresponding phases of the AC voltage side terminals of the rectifier in the power supply module. This forms a star point at the respective first terminals. This star point is connected to a protective conductor and / or to an electrical grounding current.

[0147] At the junction of the DC voltage side of the rectifier, a voltage divider is formed by two capacitors connected in series. The connection node, i.e., the potential generated by the voltage division of the intermediate circuit voltage, is connected to the star point, i.e., also to the protective conductor and / or to the grounding current.

[0148] In addition, three additional capacitors are provided, which are electrically connected to each other at their first terminals and connected to the corresponding motors at their other terminals. Therefore, a star-shaped point is also formed at its first terminal, which is electrically connected to the aforementioned star-shaped point.

[0149] The inverter has three half-bridges, which are powered in parallel by DC voltages present at the terminals on the DC voltage side of the inverter. The connection nodes of the half-bridges, i.e., the bridge branches, are connected to the motor phases. Each half-bridge has a series circuit consisting of upper and lower controllable semiconductor switches.

[0150] In other embodiments of the invention, such as Figure 3 As shown, each inverter is connected to its adjacent inverter or master unit via a forward channel and a reverse channel.

[0151] At the start of operation or initialization, each inverter first reports to the master device 30 by sending a message on its reverse channel. The message is then forwarded from the upstream inverter through its reverse channel until it reaches the master device 30.

[0152] For address allocation, the master device 30 sends a bus address to the first inverter 31 on the forward channel, which the first inverter 31 uses itself. The first inverter 31 then adds a value to or increments the bus address, passing this resulting bus address to the second inverter 32 on the forward channel. The second inverter 32 does this in exactly the same way, and so does the third inverter 33. If the fourth inverter 33 sends its incremented bus address on its forward channel and subsequently does not receive a response at its reverse channel input for a period of time, it determines that it is the last inverter in the drive system. Therefore, it reads the default value of the parameter describing its pulse width modulation polarity from its data memory and activates that default value in its inverter's pulse width modulation signal electronics.

[0153] Subsequently, the last inverter 34 sends information about its polarity to the upstream inverter 33 via a reverse channel. Inverter 33 receives this information and activates a polarity that is reversed relative to the polarity of the last inverter 34 in its pulse width modulation. This process continues until the first inverter 31.

[0154] However, if an inverter, also configured as a bus user and thus having only a single bus address, is configured as a multi-component inverter—that is, consisting of two separate inverters arranged in a common housing—the information received from the downstream inverter is forwarded unchanged to the upstream inverter via a reverse channel, since the two separate inverters anyway acquire polarities that are reversed relative to each other. This reversed polarity is preferably permanently fixed by means of hardware.

[0155] An inverter consisting of two separate inverters, or independent inverters, is also called a dual inverter or dual-axis inverter.

[0156] List of reference numerals in the attached diagram:

[0157] 1 First Inverter

[0158] 2 Second Inverter

[0159] 30 Main Equipment

[0160] 31 serves as the first inverter of the first slave unit.

[0161] 32 serves as the second inverter, acting as the second slave unit.

[0162] 33 is the third inverter as the third slave unit.

[0163] 34 is the fourth inverter, serving as the last slave unit.

[0164] 35 Data Bus

[0165] M1 First Electric Motor

[0166] M2 Second Motor

[0167] M3 Third Motor

[0168] M4 Fourth Electric Motor

[0169] Mn, the last motor

Claims

1. A method for operating a drive system having multiple inverters and a data bus, wherein a corresponding motor is fed by a terminal on the AC voltage side of a corresponding inverter. The DC voltage side terminals of the respective inverters are connected in parallel to each other, and this parallel circuit is connected to the DC voltage side terminals of the rectifier via a busbar. The corresponding inverter has corresponding semiconductor switches controlled according to the corresponding pulse width modulation. The inverter is configured as a bus user of the data bus, and the module configured as the master device is also connected to this data bus. The module includes the rectifier. In the first method step, a corresponding bus address is assigned to each inverter during drive system initialization or startup, and subsequently in the second method step, the polarity of its pulse width modulation is specified for each inverter. The pulse width modulation polarity of the first inverter is different from that of the second inverter. This ensures that the pulse width modulation of the drive signal for the controllable semiconductor switch of the first inverter and the pulse width modulation of the drive signal for the controllable semiconductor switch of the second inverter are configured to be inversely synchronous. in, For address allocation, the corresponding inverter inputs a voltage signal to the downstream inverter, uses this voltage signal to notify the corresponding downstream inverter, adopts the address contained in the next broadcast message of the master device in time as its own bus address, and inputs another voltage signal to the other inverter if another inverter exists, and if the other inverter does not exist, adapts its pulse width modulation polarity to the polarity information contained in the broadcast message.

2. The method according to claim 1, characterized in that, Each inverter has a DC-fed half-bridge connected in parallel with each other, and each half-bridge is configured as a series circuit of at least two controllable semiconductor switches. The drive signal uses pulse width modulation to control the semiconductor switches of the inverter according to the pulse width modulation and polarity of the inverter.

3. The method according to claim 1 or 2, characterized in that, At the beginning of the corresponding pulse width modulation period The upper switch of the first half-bridge of the first inverter is open, and the lower switch of the first half-bridge of the first inverter is closed. The upper switch is connected to the high potential of the DC voltage side connector of the inverter, and the lower switch is connected to the low potential of the DC voltage side connector of the inverter.

4. The method according to claim 1 or 2, characterized in that, Starting with the main unit, the inverters are arranged in series along the data bus in a series configuration. In the first method step, starting with the master device, each inverter assigns a bus address to the inverter downstream of it in the series structure, until it is identified as the last in the series structure because it is impossible to continue assigning bus addresses, and then... In the second method step, a default value is determined as the polarity of the pulse width modulation of the last inverter. Then, starting from the last inverter, each inverter passes on the polarity reversed with its own to the inverter upstream in the series structure. The upstream inverter determines the polarity of the polarity reversal as the polarity of its pulse width modulation. The dual-inverter configuration has a single bus address and two independent inverters arranged in a common housing. The pulse width modulation of these two independent inverters has polarities that are opposite to each other.

5. The method according to claim 1 or 2, characterized in that, The data bus has a forward channel and a reverse channel, enabling each inverter to have both forward channel input and output, as well as reverse channel input and output. The master device is connected to the forward channel input of the first inverter and to the reverse channel output of the first inverter. For address allocation, the master device sends a first bus address to the first inverter via the forward channel, and the first inverter uses this first bus address as its own bus address. The first inverter generates a second bus address from a first bus address and sends the second bus address to the second inverter via a forward channel. The second inverter uses the second bus address and generates a third bus address from it, and forwards the third bus address via its forward channel. Each additional inverter uses the bus address received via its positive channel input as its own bus address, generates another bus address from the received bus address, and sends the generated other bus address to the downstream inverter via the positive channel. The last inverter identified itself as the last inverter because further transmission of the bus address it generated failed.

6. The method according to claim 1 or 2, characterized in that, In order to assign addresses, the master device repeatedly sends broadcast messages via the data bus over time. These broadcast messages are associated with the corresponding address information and the corresponding polarity information, so that a first polarity is assigned to the first inverter and a second polarity different from the first polarity is assigned to the second inverter.

7. The method according to claim 6, characterized in that, A voltage signal can be fed from the master equipment to the first inverter, and a voltage signal can be fed from the corresponding inverter to the corresponding next inverter. The corresponding inverter that receives the voltage signal then extracts the address and / or polarity information contained in the subsequent broadcast message from the master device, and only then feeds the voltage signal to the corresponding next inverter. Regarding the forwarding of voltage signals and / or the data bus, the inverters are arranged in a series configuration such that, in the series configuration, from the first inverter to the penultimate inverter, another inverter is arranged downstream of each inverter.

8. The method according to claim 6, characterized in that, The last inverter assigns a polarity opposite to that used by its upstream inverter in pulse width modulation. The upstream inverter then assigns a polarity opposite to that used by its own inverter in pulse width modulation.

9. The method according to claim 1 or 2, characterized in that, After assigning addresses to the inverters, the master device will transmit the polarity used in the pulse width modulation of each inverter to these inverters. The polarities are allocated in such a way that the sum of the products of the nominal power of each inverter and its corresponding polarity is minimized. The inverters arranged adjacent to each other have different polarities.

10. The method according to claim 1 or 2, characterized in that, The first inverter has two DC-fed half-bridges connected in parallel with each other, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches. The second inverter has two parallel half-bridges fed by DC voltage, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches. The semiconductor switches of the first inverter are controlled by pulse-width modulated drive signals. The semiconductor switches of the second inverter are controlled by pulse-width modulated drive signals. in - As long as the quotient of the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is less than a threshold, then at the beginning of the corresponding pulse width modulation period: The upper switch of the first half-bridge of the first inverter is opened, and the lower switch of the first half-bridge of the first inverter is closed. This closes the upper switch of the second half-bridge of the second inverter and opens the lower switch of the second half-bridge of the second inverter. - And, as long as the quotient of the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is greater than a threshold, then at the beginning of the corresponding pulse width modulation period, The upper switch of the first half-bridge of the first inverter is opened, and the lower switch of the first half-bridge of the first inverter is closed. The upper switch of the second half-bridge of the second inverter is opened, and the lower switch of the second half-bridge of the second inverter is closed.

11. The method according to claim 1 or 2, characterized in that, The drive system has a first inverter and a second inverter, wherein the first motor is fed by the AC voltage side connector of the first inverter. The second motor is powered by the AC voltage side connector of the second inverter. The DC voltage side connectors of the first inverter and the second inverter are connected in parallel, and this parallel connection is powered by DC voltage. The first inverter has two DC-fed half-bridges connected in parallel with each other, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches. The second inverter has two DC-fed half-bridges connected in parallel with each other, each half-bridge being configured as a series circuit of at least two controllable semiconductor switches. The semiconductor switches of the first inverter are controlled by pulse-width modulated drive signals. The semiconductor switches of the second inverter are controlled by pulse-width modulated drive signals. Its features are, - As long as the difference between the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is less than a threshold, then at the beginning of the corresponding pulse width modulation period, The upper switch of the first half-bridge of the first inverter is opened, and the lower switch of the first half-bridge of the first inverter is closed, and... This closes the upper switch of the second half-bridge of the second inverter and opens the lower switch of the same second half-bridge. - And, as long as the difference between the pulse width modulation ratio of the drive signal for the first semiconductor bridge of the first inverter and the pulse width modulation ratio of the drive signal for the second semiconductor bridge of the second inverter is greater than a threshold, then at the beginning of the corresponding pulse width modulation period, The upper switch of the first half-bridge of the first inverter is opened, and the lower switch of the first half-bridge of the first inverter is closed, and... The upper switch of the second half-bridge of the second inverter is opened, and the lower switch of the second half-bridge of the second inverter is closed.

12. The method according to claim 1 or 2, characterized in that, A DC voltage is provided for use at the DC voltage side connector of the rectifier fed by the power grid. The rectifier is powered by a three-phase voltage network at its AC voltage side terminals. The DC side connector of the rectifier is connected in parallel with the DC voltage side connector of the first inverter and in parallel with the DC voltage side connector of the second inverter.

13. The method according to claim 1 or 2, characterized in that, The pulse width modulation signal of the first inverter is generated simultaneously with the pulse width modulation signal of the second inverter. and / or The pulse width modulation cycles of the first and second inverters start synchronously and / or simultaneously. and / or Within each pulse width modulation cycle, the first switching edge of the drive signal for the upper semiconductor switch of the first inverter is reversed and / or extended in the opposite direction compared to the first switching edge of the drive signal for the upper semiconductor switch of the second inverter. and / or One of the corresponding controllable semiconductor switches in the half-bridge, namely the upper semiconductor switch, is connected to the high potential of the DC voltage. and / or One of the controllable semiconductor switches in the corresponding half-bridge, namely the lower semiconductor switch, is connected to the low potential of the DC voltage. And / or at the beginning of the corresponding pulse width modulation period, The upper switch of the first half-bridge of the first inverter is open, and the lower switch of the first half-bridge of the first inverter is closed. The upper switch of the second half-bridge of the second inverter is closed, and the lower switch of the second half-bridge of the second inverter is open.

14. The method according to claim 1 or 2, characterized in that, The synchronization signal is modulated onto a bus that connects the DC voltage side terminals of the inverters to each other and to the DC voltage side terminals of the rectifiers. Alternatively, the synchronization signal can be broadcast as a message from the master device to all inverters in a time-repeated manner via a data bus. The pulse modulation of all inverters is synchronized based on the synchronization signal.

15. A drive system for performing the method according to any one of claims 1 to 14, characterized in that, The DC voltage side terminals of the inverter are connected to each other via busbars and are also connected to the DC voltage side terminals of the rectifier. The corresponding inverter is connected to at least one upstream or downstream inverter via at least one line to feed a voltage signal using at least one wire.

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